Instruction fusion segmentation method, processor core and processor

Abstract

The present invention discloses an instruction fusion and segmentation method, a processor core and a processor, comprising the following steps: obtaining two adjacent instructions in execution order; when a fusion condition is met, that is, a base-address-modified addressing memory access operation is implemented, the instructions are fused to obtain a fusion conditional load / store instruction; the fusion conditional load / store instruction is segmented according to fusion information to form a segmentation instruction; the indirect register of the second segmentation instruction is replaced with two source registers of the first segmentation instruction, and the write-after-read correlation of the two segmentation instructions is eliminated. The present invention fuses the addition and subtraction instructions and the load / store instructions generated by the base-address-modified addressing operation implemented during decoding to improve the bandwidth from the instruction fetch unit to the decoding unit, and the instructions are segmented in the decoding unit, and the source operands of the load / store instructions are replaced, eliminating the write-after-read correlation between the load / store instruction and the addition and subtraction instruction, thereby improving the performance of the RISC‑V processor.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to an instruction fusion and segmentation method, a processor core and a processor. Background Art

[0002] Modern general-purpose processor architectures are mainly divided into Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC). In the CISC instruction set, one instruction can complete many operations, but the processor design is relatively complex, which is prone to redundant or inefficient instructions. In the RISC instruction set, each instruction only performs a single simple operation, such as addition, subtraction, etc., but its instruction length is short and the format is regular, which greatly reduces the difficulty of decoding. At the same time, it is easy to design a pipeline structure and can execute instructions quickly. The current mainstream RISC-V instruction set is a reduced instruction set. Although the reduced instruction set has simple instructions, it may require more instructions to execute a program. If the number of instructions can be reduced, the RISC processor can have higher performance.

[0003] The instruction fusion method is to merge two or more adjacent instructions into one instruction, which can improve the bandwidth of the pipeline with less communication cost.

[0004] Instruction splitting is to split a complex instruction into multiple simple instructions, and implement the behavior of a complex instruction through multiple simple instructions. Therefore, only some simple execution units are needed, which can reduce the complexity of the execution units.

[0005] The processor interacts with the memory through load / store instructions. There are multiple addressing modes, including direct addressing, register indirect addressing, register relative addressing, and base address indexing addressing, as shown in Table 1:

[0006]

[0007]

[0008] Table 1 Load and store instruction addressing mode

[0009] In order to simplify the instruction set, the addressing mode of the basic load / store instructions of the RISC-V instruction set is only register relative addressing. The addressing address is calculated in the form of register plus offset. For example, ld rd, offset(rs1) means reading eight bytes from address x[rs1]+sign-extend(offset) and writing to x[rd]. The length of a RISC-V instruction is usually 32 bits or 16 bits. The width of the offset address is limited. The width of the offset address in a 32-bit instruction is 12 bits, while the width of the offset address in a 16-bit compressed instruction is only 6 bits. Due to the limited offset address, some memory addresses cannot be accessed through register relative addressing, but need to be accessed through base address displacement. The memory address is calculated using two registers through addition and subtraction instructions, and the calculated memory address is assigned to the indirect register of the load / store instruction. Since there is no base address displacement addressing instruction in the basic RISC-V instruction set, the following will be generated when the program is compiled:

[0010] add x1,x2,x3

[0011] ld x4,0(x1)

[0012] Such an instruction sequence is used to complete the memory access of the base-indexed addressing mode. Compared with directly using the base-indexed addressing instruction, an additional instruction is required. And in such an instruction sequence, the load / store instruction is related to the addition and subtraction instructions in a write-after-read manner. The load / store instruction needs to wait for the addition and subtraction instructions to be executed to obtain the indirect register result before it can be issued. In contrast, the base-indexed addressing instruction can be issued when the two source operands are ready. Therefore, in order to complete the base-indexed addressing operation, the RISC-V processor needs to execute more instructions and takes a longer execution time. Summary of the invention

[0013] The purpose of the present invention is to provide an instruction fusion and segmentation method, a processor core and a technical solution of a processor to address the deficiencies in the prior art, to fuse the addition and subtraction instructions and load / store instructions generated for the base address displacement addressing operation implemented during decoding, so as to improve the bandwidth from the instruction fetch unit to the decoding unit, and to segment the instructions in the decoding unit, and replace the source operands of the load and store instructions, eliminate the write-after-read correlation between the load / store instructions and the addition and subtraction instructions, and speed up the emission of the load / store instructions, thereby improving the performance of the RISC-V processor.

[0014] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0015] An instruction fusion segmentation method, characterized by comprising the following steps:

[0016] S1, obtaining two adjacent instructions in execution order, namely the first instruction and the second instruction, and detecting the first instruction and the second instruction;

[0017] S2, when the first instruction and the second instruction meet the fusion condition, that is, the base address indexing addressing memory access operation is implemented, the first instruction and the second instruction are fused to obtain a fusion conditional load / store instruction including fusion information;

[0018] S3, splitting the fused conditional load / store instruction according to the fusion information to form two split instructions, namely a first split instruction and a second split instruction;

[0019] S4. Replace the indirect register of the second split instruction with the two source registers of the first split instruction, thereby eliminating the read-after-write dependency between the two split instructions.

[0020] The method fuses and compresses the addition and subtraction instructions and the load / store instructions generated for the base-address-modified addressing operation during decoding to improve the bandwidth from the instruction fetch unit to the decoding unit, splits the instructions in the decoding unit, replaces the source operands of the load and store instructions, eliminates the write-after-read dependency between the load / store instructions and the addition and subtraction instructions, speeds up the emission of the load / store instructions, and improves the performance of the RISC-V processor.

[0021] Furthermore, the fusion conditions specifically include:

[0022] The instruction type of the first instruction is an addition or subtraction instruction, and the second instruction is a load / store instruction. The source register and the destination register of the first instruction are different, and the destination register of the first instruction is the same as the indirect register of the second instruction, and the offset address of the second instruction is 0.

[0023] Furthermore, the fusion information includes instruction valid encoding information of the first instruction and the second instruction.

[0024] Furthermore, the first instruction and the first split instruction are both addition and subtraction instructions.

[0025] Further, the second instruction and the second split instruction are both load / store instructions.

[0026] A processor core, characterized in that the processor core supports the above-mentioned instruction fusion segmentation method, including:

[0027] 1) Instruction fetch unit: used to fetch two instructions that are adjacent in execution order;

[0028] 2) Instruction decoding unit: The instruction decoding unit includes an instruction segmentation unit, which is used to decode and segment the fused instruction, obtain decoding information of the fused instruction through decoding, segment the fused instruction into a first segmentation instruction and a second segmentation instruction, and replace the source register of the second segmentation instruction;

[0029] 3) Instruction issuing unit: used to obtain the corresponding source operand according to the source register of the instruction and give it to the load storage unit;

[0030] 4) Load storage unit: used to calculate the address of the load / store instruction access memory and access the memory according to the address;

[0031] 5) Execution unit: used to execute instruction-related operations.

[0032] Further, the instruction fetch unit includes:

[0033] Pre-decoding unit: used to provide necessary information for instruction fusion;

[0034] and fusion detection unit: used to determine whether two adjacent instructions implement base address displacement addressing memory access operations based on information of the first instruction and the second instruction.

[0035] Furthermore, the necessary information is the instruction type and register information for decoding the first instruction and the second instruction.

[0036] A processor, characterized by comprising at least one processor core as described above.

[0037] The present invention has the following beneficial effects due to the adoption of the above technical solution:

[0038] 1. The present invention fuses and compresses the addition and subtraction instructions and the load / store instructions generated for the base-address-modified addressing operation implemented during decoding, so as to improve the bandwidth from the instruction fetch unit to the decoding unit, and splits the instructions in the decoding unit, and replaces the source operands of the load and store instructions, eliminates the write-after-read dependency between the load / store instructions and the addition and subtraction instructions, and speeds up the emission of the load / store instructions, thereby improving the performance of the RISC-V processor.

[0039] 2. This method does not require changes to the instruction set and has good compatibility with compilers and software systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention will be further described below in conjunction with the accompanying drawings:

[0041] Figure 1 A flowchart of an instruction fusion segmentation method, a processor core, and an instruction fusion method in a processor according to the present invention;

[0042] Figure 2 is a block diagram of a processor core in the present invention;

[0043] Figure 3 is an execution flow chart of the conditional operation fusion instruction in the present invention;

[0044] Figure 4 It is a flowchart of the instruction sequence fusion in the present invention. DETAILED DESCRIPTION

[0045] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0046] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0048] Definitions of professional terms used in this invention:

[0049] 1. Processor: the computing and control core of a computer system.

[0050] 2. Processor core: The core computing engine in a processor used to process and execute instructions. A processor can include one processor core or multiple processor cores.

[0051] 3. Pipeline structure: refers to breaking down the instruction processing process into multiple stages, and executing each stage independently to form an instruction pipeline. Each stage performs different operations, such as instruction fetch, decoding, execution, memory access, write back, etc. This allows the processor to process multiple instructions at the same time and improve the execution efficiency of the processor.

[0052] 4. The life cycle of an instruction: refers to the time from when the computer fetches an instruction to when the instruction is executed and retired.

[0053] 5. Operand: The operand of an instruction refers to the data used to perform the operation in the instruction. It is divided into source operand and destination operand. The source operand refers to the data to be operated, and the destination operand refers to the result data of the operation. The operand can be in the form of an immediate number, register, memory address, etc. The type and number of operands depend on the type and function of the instruction.

[0054] 6. Source register and destination register: If the operands are all in register form, then the instruction gets the source operand from the source register and writes the destination operand to the destination register after execution.

[0055] 7. Read-after-write dependency: For instructions A and B that are executed sequentially, if the source register of instruction B is the destination register of instruction A, then instructions A and B have a read-after-write dependency.

[0056] 8. Indirect register: RISC-V instruction set load / store instructions are all addressed in register relative addressing mode, and the address of the operand = indirect register + offset.

[0057] 9. Load instruction: An instruction that loads data from memory to a register.

[0058] 10. Store instruction: An instruction that stores data in the processor register into the memory.

[0059] like Figure 1 As shown, an instruction fusion segmentation method of the present invention includes the following steps:

[0060] S1, obtaining two adjacent instructions in execution order, namely the first instruction and the second instruction, and detecting the first instruction and the second instruction;

[0061] The instructions in this application include addition and subtraction instructions and load / store instructions. The specific addition and subtraction instructions are shown in Table 2, and the specific load / store instructions are shown in Table 3.

[0062]

[0063] Table 2 Addition and subtraction instructions

[0064]

[0065] Table 3 Load / Store Instructions

[0066] S2, when the first instruction and the second instruction meet the fusion condition, that is, the base address indexing addressing memory access operation is implemented, the first instruction and the second instruction are fused to obtain a fusion conditional load / store instruction including fusion information;

[0067] The fusion information includes instruction valid encoding information of the first instruction and the second instruction.

[0068] The fusion conditions include:

[0069] The instruction type of the first instruction is an addition or subtraction instruction, and the second instruction is a load / store instruction. The source register and the destination register of the first instruction are different, and the destination register of the first instruction is the same as the indirect register of the second instruction, and the offset address of the second instruction is 0.

[0070] S3, splitting the fused conditional load / store instruction according to the fusion information to form two split instructions, namely a first split instruction and a second split instruction;

[0071] The first instruction and the first split instruction are both addition and subtraction instructions.

[0072] The second instruction and the second split instruction are both load / store instructions.

[0073] S4. Replace the indirect register of the second split instruction with the two source registers of the first split instruction, thereby eliminating the read-after-write dependency between the two split instructions.

[0074] The method fuses and compresses the addition and subtraction instructions and the load / store instructions generated for the base-address-modified addressing operation during decoding to improve the bandwidth from the instruction fetch unit to the decoding unit, splits the instructions in the decoding unit, replaces the source operands of the load and store instructions, eliminates the write-after-read dependency between the load / store instructions and the addition and subtraction instructions, speeds up the emission of the load / store instructions, and improves the performance of the RISC-V processor.

[0075] A processor core, such as Figure 2 As shown, the processor core supports the above-mentioned instruction fusion segmentation method, including:

[0076] 1) Instruction fetch unit: used to fetch two instructions in adjacent execution order from the memory, and pre-decode and merge the instructions for subsequent instruction decoding and instruction execution;

[0077] The instruction fetch unit includes:

[0078] Pre-decoding unit: used to provide necessary information for instruction fusion; the necessary information is the instruction type and register information for decoding the first instruction and the second instruction.

[0079] and fusion detection unit: used to determine whether two adjacent instructions implement base address displacement addressing memory access operations based on information of the first instruction and the second instruction.

[0080] The execution process of instruction fusion is as follows: Figure 3 As shown, the execution process of the fusion instruction in its life cycle:

[0081] The instruction fetch unit fetches multiple instructions in sequence, and pre-decodes them according to the opcode of the instruction. The pre-decoding can tell the instruction type and register number, and then send them to the fusion detection unit. The fusion detection unit checks the instruction type and register number of two adjacent instructions. If the fusion condition is met, the second instruction is identified as a fusion instruction, and the instruction information of the first instruction is generated with an additional code. This code will enter the instruction decoding unit along with the instruction. The instruction decoding unit will split the fused instruction according to the additional code, and split the instruction into addition and subtraction instructions and load / store instructions. The addition and subtraction instructions are the same as the first instruction, and the indirect registers of the load / store instructions will be replaced by the two source registers of the first instruction. The two instructions are decoded separately to obtain control information. The control signal is mainly a signal for the emission unit and the execution unit to distinguish the instruction and operation type. After decoding, the instruction enters the instruction emission unit. When the operand is ready, the source operand is obtained by reading the register or bypassing, and the source operand is handed over to the load storage unit together with the control information to implement memory access. The addition and subtraction instructions are the same as normal instructions. The source operand is obtained and emitted into the execution unit to implement the operation. The indirect registers of the load / store instruction are replaced by the two source registers of the first instruction, requiring an additional register read port or bypass port to obtain all source operands. After the instruction is issued, it enters the load-store unit, which calculates the address of the memory access based on the source operand and accesses the memory based on the address, thus realizing the interaction between the processor and the memory.

[0082] Decoding of pre-decoding unit:

[0083] In order to perform fusion detection, some information about the instruction needs to be known in advance, including the instruction type, register number, and offset address of the load / store instruction. The pre-decoding unit can obtain this information through simple decoding based on the instruction opcode.

[0084] Fusion detection unit detection content:

[0085] If the instruction types of two adjacent instructions meet the fusion condition, that is, the first instruction is an addition or subtraction instruction, and the second instruction is a load / store instruction, then the register numbers are compared. If the source register and the destination register of the first instruction are different, and the indirect register of the load / store instruction and the destination register of the second instruction are the same register, and the offset address of the load / store instruction is 0, then the two instructions meet the fusion condition, and the second instruction is marked as a fusion instruction.

[0086] In addition, the first instruction cannot be completely lost. Additional coding must be generated based on the instruction information obtained through pre-decoding and appended to the instruction information of the fused instruction to prepare for decoding by the subsequent decoding unit.

[0087] Examples of pre-decoding and fusion detection:

[0088] like Figure 4 As shown, it is assumed that the instruction fetch unit fetches four instructions, and the four instructions are sent to the fusion detection unit after pre-decoding, and two adjacent instructions are subjected to fusion detection, that is, the first and second instructions, the second and third instructions, and the third and fourth instructions. The four instructions must be fused every two. Assuming that the fusion detection unit detects that the first instruction is a conditional transfer instruction, the second instruction is an addition instruction, and the registers of the two instructions also meet the fusion conditions, then the first and second instructions can be fused into a conditional operation instruction. Assuming that the third and fourth instructions do not meet the fusion conditions, then the four instructions fetched by the instruction fetch unit can obtain three instructions after passing through the fusion detection unit, namely, one fusion instruction and two ordinary instructions, that is, the fused instruction sequence shown in the figure.

[0089] These three instructions will enter the decoding unit for decoding in sequence. The control signals obtained by decoding the ordinary instructions are prepared for the subsequent pipeline use. The fused instructions have fused instruction identifiers. According to the additional encoding in the instruction information, the instructions need to be split into instructions that are the same as the first and second instructions, and the source operands of the second instruction are replaced, and additional decoding information is obtained according to the additional encoding. After the instructions are split, they will be restored to 4 instructions, and the instruction order before the instruction fusion will be maintained after the instructions are split.

[0090] After instruction fusion, the bandwidth between the instruction fetch unit and the decoding unit is increased, which can improve the utilization rate of the decoding unit. After instruction segmentation, the source register of the load / store instruction is replaced, eliminating the write-after-read data dependency of the addition and subtraction instructions and the load / store instructions, which can speed up the issuance of the load / store instruction and improve the processor's memory access performance.

[0091] 2) Instruction decoding unit: The instruction decoding unit includes an instruction segmentation unit, which is used to decode and segment the fused instruction, obtain decoding information of the fused instruction through decoding, identify information such as instruction type, operand and function code, segment the fused instruction into a first segmentation instruction and a second segmentation instruction, replace the source register of the second segmentation instruction, and pass it to the instruction emission unit;

[0092] The decoding functions of the pre-decoding unit and the instruction decoding unit are different. In this fusion method, the pre-decoding unit is mainly used to provide some necessary instruction information to the fusion detection unit to facilitate the fusion detection unit to identify instructions. It is local decoding, while the instruction decoding unit will split complex instructions and obtain the information required for instruction execution according to the instruction encoding information, including opcodes, source registers, destination registers, additional encodings and other information. It is a complete decoding.

[0093] The instruction segmentation unit will segment complex instructions into multiple simple instructions. For fused load / store instructions, the instruction segmentation unit will determine whether the instruction is a fused instruction based on the additional encoding generated when the instruction is fused, and restore the addition and subtraction instructions deleted after the merger. The fused instruction is segmented into two instructions, addition and subtraction and load / store, and the source operand of the load / store instruction is replaced, and additional decoding information is generated to indicate whether the operation on the source operand is addition, subtraction, or shift addition when calculating the address.

[0094] According to add x1,x2,x3

[0095] ld x4,0(x1)

[0096] These two instructions are fused and split into

[0097] add x1,x2,x3

[0098] ld x4,x3(x2) form

[0099] The function of sh1add, sh2add, and sh3add is to shift the source operand 1 of the instruction and add the source operand 2. Therefore, when sh1add, sh2add, and sh3add are fused with load / store instructions, the number of shifts needs to be saved in the additional decoding information when the instructions are split. For example, the shift number for sh1add is 1, the shift number for sh2add is 2, and the shift number for sh3add is 3. For ordinary add and sub instructions, the shift number is 0, indicating that no shift is required.

[0100] 3) Instruction issuing unit: used to obtain the corresponding source operand according to the source register of the instruction, distribute the instruction to the corresponding execution unit, and give it to the load storage unit;

[0101] Dependencies of the instruction issuing unit:

[0102] In the instruction issuing unit, the instruction must wait for the operand to be ready, that is, it must read the register to obtain the latest data. If the operand of this instruction comes from the result of the previous instruction, then this instruction cannot be executed until the result of the previous instruction is obtained. There is a read after write (Read After Write, RAW) dependency between the two instructions. This type of dependency will affect the efficiency of parallel execution of the processor.

[0103] The two instructions described in this fusion method originally had a read-after-write dependency. The indirect registers of the load / store instructions depended on the addition and subtraction instructions. The load / store instructions needed to wait for the addition and subtraction instructions to finish executing and return results before they could be issued. However, this paper replaces the indirect registers of the load / store instructions with the two source registers of the addition and subtraction instructions. Therefore, after the source registers of the addition and subtraction instructions are ready, the addition and subtraction instructions and the load / store instructions can be issued at the same time, eliminating the read-after-write dependency between the two instructions.

[0104] Since the indirect register of the load / store instruction is replaced by the two source registers of the first instruction, an additional register read port or bypass port is required to obtain all source operands, which increases but eliminates the correlation between the two instructions, speeds up the issuance of the load / store instruction, and can improve the performance of the processor.

[0105] 4) Load / store unit: used to calculate the address of the load / store instruction, access the memory according to the address, perform load / store operations, and enable the processor to interact with the memory;

[0106] The load storage unit calculates the address of the instruction memory access based on the two source operands and the additional decoding information. If the additional decoding information is not 0, the source operand 1 is shifted and added to the source operand 2 to obtain the address, otherwise the memory access address is obtained by directly adding and subtracting the two source operands. And according to the memory access address and the type of instruction, data is loaded from the memory or stored in the memory.

[0107] 5) Execution unit: used to execute instruction-related operations, such as addition, subtraction, logical OR, logical XOR, etc.

[0108] A processor comprises at least one processor core as described above.

[0109] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent replacements or modifications made based on the present invention to achieve basically the same technical effects are all included in the protection scope of the present invention.

Claims

1. A method for instruction fusion segmentation, characterized in that The steps include: S1, obtaining two adjacent instructions in execution order, namely a first instruction and a second instruction, and detecting the first instruction and the second instruction; S2. When the first instruction and the second instruction meet a fusion condition, that is, a base-address-modified addressing memory access operation is implemented, the first instruction and the second instruction are fused to obtain a fusion condition load / store instruction including fusion information; the fusion condition specifically includes that the instruction type of the first instruction is an addition / subtraction instruction, the second instruction is a load / store instruction, the source register and the destination register of the first instruction are different, and the destination register of the first instruction and the indirect register of the second instruction are the same, and the offset address of the second instruction is 0; S3, splitting the fused conditional load / store instruction according to the fusion information to form two split instructions, namely a first split instruction and a second split instruction; S4. Replace the indirect register of the second split instruction with the two source registers of the first split instruction, thereby eliminating the read-after-write dependency between the two split instructions.

2. The instruction fusion segmentation method according to claim 1, characterized in that: The fusion information includes instruction valid encoding information of the first instruction and the second instruction.

3. The instruction fusion segmentation method according to claim 1, characterized in that: The first instruction and the first segmentation instruction are both addition and subtraction instructions.

4. The instruction fusion segmentation method according to claim 3, characterized in that: The second instruction and the second split instruction are both load / store instructions.

5. A processor core, characterized in that: The processor core supports the instruction fusion segmentation method according to any one of claims 1 to 4, including: 1) Instruction fetch unit: used to fetch two instructions that are adjacent in execution order; 2) Instruction decoding unit: the instruction decoding unit includes an instruction segmentation unit, which is used to decode and segment the fused instruction, obtain decoding information of the fused instruction through decoding, segment the fused instruction into a first segmentation instruction and a second segmentation instruction, and replace the source register of the second segmentation instruction; 3) Instruction issuing unit: used to obtain the corresponding source operand according to the source register of the instruction and give it to the load storage unit; 4) Load storage unit: used to calculate the address of the load / store instruction access memory and access the memory according to the address; 5) Execution unit: used to execute instruction-related operations.

6. The processor core according to claim 5, characterized in that: The instruction fetch unit comprises: Pre-decoding unit: used to provide necessary information for instruction fusion; and fusion detection unit: used to determine whether two adjacent instructions implement base address displacement addressing memory access operations based on information of the first instruction and the second instruction.

7. The processor core according to claim 6, characterized in that: The necessary information is the instruction type and register information for decoding the first instruction and the second instruction.

8. A processor, characterized in that: Comprising at least one processor core as claimed in claim 5.

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