T-shaped gate preparation method based on electron beam exposure

Abstract

The application discloses a T-shaped gate preparation method based on electron beam exposure, which comprises the following steps: covering two layers of photoresists with different sensitivities on a substrate, exposing and developing to obtain a gate leg photoetching mask structure; depositing metal on the substrate with the gate leg photoetching mask structure; stripping the gate leg metal structure formed by the two layers of photoresist masks to obtain the gate leg attached to the substrate; spin-coating three layers of photoresists on the substrate with the gate leg; forming a gate cap photoetching mask structure for forming a gate cap through the second upper layer of photoresist and the middle layer of photoresist, and forming a gate cap support layer through the second lower layer of photoresist; depositing metal on the substrate with the gate cap photoetching mask and the gate cap support layer mask to obtain a gate cap metal structure; and stripping the gate cap metal structure to obtain a complete T-shaped gate attached to the substrate. The application reduces process damage, avoids the problem that the foot cap dose influences each other when the T-shaped gate is prepared, and is beneficial to the preparation of a T-shaped gate with a shorter gate length.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more specifically to a method for fabricating a T-gate based on electron beam exposure. Background Technology

[0002] High electron mobility transistors (HEMTs) and heterojunction field-effect transistors (HFETs) possess characteristics such as high two-dimensional electron gas concentration and high mobility, making them core components of microwave, millimeter-wave, and terahertz power amplifiers. With the development of information technology, increasingly more high-frequency applications are placing new demands on the frequency characteristics of HEMTs (including HFETs). The cutoff frequency f is a key indicator reflecting the frequency characteristics of HEMTs. T This makes it all the more important. The smaller the gate length, the lower the cutoff frequency f of the device. T Higher frequency response (RF) values ​​are generally achieved by reducing the gate length of the HEMT to obtain better frequency characteristics. However, shortening the gate length increases the gate parasitic resistance R of the HEMT. g Increased parasitic capacitance can negatively impact device performance. Therefore, gate electrodes are often made into T-shaped gates (including but not limited to Γ-shaped gates, τ-shaped gates, Y-shaped gates, and mushroom-shaped gates, etc.) with a narrow gate foot and a wide gate cap at the top, in order to reduce the gate-source and gate-drain parasitic capacitances without severely deteriorating the gate parasitic resistance.

[0003] Generally, there are several technical approaches to T-gate fabrication in HEMTs: 1. Multilayer photoresist approach: This approach utilizes the different exposure sensitivities of various photoresists to fabricate the T-gate. It achieves a floating T-gate below the gate cap (excluding the gate feet), minimizing the parasitic capacitance introduced by the gate cap. However, multilayer photoresist inevitably suffers from large photoresist thickness, numerous interfaces, severe particle scattering during exposure, difficulty in minimizing the gate length, and poor process repeatability. 2. Dielectric-supported gate approach: This approach involves first depositing a layer of Si on the surface. x N y (Including but not limited to SiO2, Al2O3, the same below) are used as passivation support layers, and holes are opened by photolithography and Si is etched. x N y A gate foot mask is formed, and a gate cap is fabricated using a second photolithography process. The T-shaped gate is then fabricated through metal deposition and lift-off. However, this method results in the non-gate foot portion below the gate cap being filled with Si. x N y The increased parasitic capacitance from the gate cap to the channel leads to larger gate-source and gate-drain parasitic capacitances, negatively impacting the frequency characteristics of HEMTs. Thirdly, the dielectric release gate technique requires multiple passivation and low-damage etching processes. For self-aligned methods, chemical mechanical polishing (CMP) is also necessary, making the process extremely complex. Most importantly, it is difficult to achieve the same gentle dielectric release process as removing a photoresist mask, resulting in some damage to the T-gate.

[0004] To address the above issues, a T-type gate fabrication method is proposed, which avoids the introduction of Si. x N y The dielectric support layer can be used to separately fabricate gate feet with high precision requirements. Summary of the Invention

[0005] Based on this, the present invention proposes a method for fabricating a high electron mobility transistor T-gate using electron beam lithography, which avoids the introduction of Si. x N y The dielectric support layer can be used to separately fabricate gate feet with high precision requirements.

[0006] According to one aspect of the present invention, a method for fabricating a T-gate based on electron beam exposure is provided, comprising:

[0007] By covering the above substrate with two layers of photoresist with different sensitivities, exposing and developing, a gate foot photolithography mask structure is obtained;

[0008] Deposit metal on a substrate having the aforementioned gate foot photolithography mask structure;

[0009] The gate foot photolithographic mask structure formed by two layers of photoresist is peeled off to obtain the gate foot metal structure attached to the above substrate;

[0010] Three layers of photoresist are spin-coated on the substrate having the aforementioned gate feet; a gate cap photomask structure is formed by the second upper layer of photoresist and the middle layer of photoresist, and a gate cap support layer is formed by the second lower layer of photoresist.

[0011] A metal is deposited on the substrate having the above-described gate cap photolithography mask structure and gate cap support layer to obtain a gate cap;

[0012] Peel off the metal structure of the gate cap to obtain a complete T-shaped gate attached to the substrate.

[0013] According to an embodiment of the present invention, the substrate material is a heteroepitaxial structure, which is formed by one or more combinations of (Al)(In)(Sc)GaN-based materials and (Al)(In)(P)GaAs-based materials.

[0014] According to an embodiment of the present invention, the surface of the above-mentioned heteroepitaxial structure has an in-situ passivation cap layer formed of silicide, and the thickness of the in-situ passivation cap layer includes 2nm to 200nm.

[0015] According to an embodiment of the present invention, the two photoresist layers include a first upper photoresist layer and a first lower photoresist layer, wherein the photolithographic sensitivity of the first upper photoresist layer is lower than that of the first lower photoresist layer.

[0016] According to an embodiment of the present invention, the height of the gate foot is 50 nm to 500 nm.

[0017] According to an embodiment of the present invention, the height of the gate foot is greater than the thickness of the gate cap support layer.

[0018] According to an embodiment of the present invention, the metal deposited on the gate foot or the gate cap includes one or more metal combinations of Ni, Ti, Pt, and Au.

[0019] According to an embodiment of the present invention, the photolithographic sensitivity of the middle layer photoresist, the second upper layer photoresist, and the second lower layer photoresist decreases sequentially.

[0020] According to an embodiment of the present invention, in the stripping process of the above-mentioned gate foot metal structure and gate cap metal structure, the stripping solution used includes one or more combinations of acetone, ethanol or a film remover, and the stripping temperature range is 20°C to 95°C.

[0021] According to an embodiment of the present invention, a substrate pretreatment step is further included to remove contaminants from the substrate surface.

[0022] As can be seen from the above technical solution, the T-gate fabrication method based on electron beam exposure provided by the present invention has the following beneficial effects:

[0023] 1. Compared with the method of simultaneously exposing the grid feet and grid cap in multilayer adhesive, the simultaneous exposure of the grid cap and grid feet in the multilayer adhesive technology route has the problem of mutual interference. This invention proposes to prioritize the preparation of the grid feet, so as to avoid the influence of grid cap exposure on the grid foot size, and can obtain short grid feet relatively easily and reliably.

[0024] 2. Compared with the dielectric-supported gate technology, this invention avoids the introduction of Si into the process. x N y Hard mask solves the problem of Si under the gate cap x N y The layer causes parasitic capacitance to increase, leading to a decrease in device performance.

[0025] 3. Compared with the technical approach of dielectric release gate (including self-alignment), this invention proposes to use a photoresist mask instead of Si. x N y Using a hard mask as a gate cap support layer simplifies the process steps. During the release of the under-gate dielectric, the photoresist mask allows for a gentler, less damaging release of the T-gate. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the substrate material according to an embodiment of the present invention;

[0027] Figure 2This is a schematic diagram of the structure of two layers of photoresist according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the gate foot photolithography mask structure according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the gate foot metal deposition structure according to an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the gate foot metal structure according to an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of the three-layer photoresist structure according to an embodiment of the present invention;

[0032] Figure 7 This is a schematic diagram of the photolithographic mask structure for the gate cap according to an embodiment of the present invention;

[0033] Figure 8 This is a schematic diagram of the gate cap metal deposition structure according to an embodiment of the present invention;

[0034] Figure 9 This is a schematic diagram of the complete T-shaped gate structure according to an embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0036] According to one aspect of the present invention, a method for fabricating a T-gate based on electron beam exposure is provided, comprising:

[0037] Step 1: By covering the substrate with two layers of photoresist with different sensitivities, exposure and development are performed to obtain the gate foot photolithography mask structure;

[0038] Step 2: Deposit metal on a substrate with a gate foot photolithographic mask structure;

[0039] Step 3: Remove the gate foot photomask structure formed by two layers of photoresist to obtain the gate foot metal structure attached to the substrate;

[0040] Step 4: Spin-coat three layers of photoresist onto the substrate with gate feet; form a gate cap photomask structure for forming the gate cap through the second upper layer of photoresist and the middle layer of photoresist, and form a gate cap support layer through the second lower layer of photoresist;

[0041] Step 5: Deposit metal on the substrate with the gate cap photolithography mask structure and the gate cap support layer to obtain the gate cap;

[0042] Step 6: Peel off the metal structure of the gate cap to obtain a complete T-shaped gate attached to the substrate.

[0043] By using photoresist, a soft mask that is easy to remove, gate feet and gate caps are fabricated separately. Since the gate feet are already fixed in shape, the problem of simultaneous exposure of the gate cap and gate feet and mutual interference is avoided. The process is simple and process damage is reduced.

[0044] Compared with the method of simultaneously exposing the gate feet and gate cap in multilayer adhesive, the simultaneous exposure of the gate cap and gate feet in the multilayer adhesive technology route has the problem of mutual interference. This invention proposes to prioritize the preparation of the gate feet, so as to avoid the influence of the gate cap exposure on the gate foot size, and can obtain short gate feet relatively easily and reliably.

[0045] Compared with the dielectric-supported gate technology, this invention avoids the introduction of Si into the process. x N y Hard mask solves the problem of Si under the gate cap x N y The layer causes parasitic capacitance to increase, leading to a decrease in device performance.

[0046] Compared with the dielectric release gate (including self-aligned) approach, this invention proposes to use a photoresist mask instead of Si. x N y Using a hard mask as a gate cap support layer simplifies the process steps. During the release of the under-gate dielectric, the photoresist mask allows for a gentler, less damaging release of the T-gate.

[0047] Figure 1 This is a schematic diagram of the structure of the substrate material according to an embodiment of the present invention.

[0048] Figure 2 This is a schematic diagram of the structure of two layers of photoresist according to an embodiment of the present invention.

[0049] Figure 3 This is a schematic diagram of the gate foot photolithography mask structure according to an embodiment of the present invention.

[0050] According to an embodiment of the present invention, step one specifically involves: preparing a substrate material, such as... Figure 1 As shown, the substrate material, from bottom to top, includes: a substrate, a buffer layer, an AlN insertion layer 1, an InAlN barrier layer 2, and a GaN cap layer 3.

[0051] like Figure 2 As shown, a single layer of electron beam photoresist is spin-coated onto a clean substrate material and baked at 170°C–220°C for 2–10 minutes to obtain the first upper photoresist layer 5. A single layer of electron beam photoresist is then spin-coated onto the first upper photoresist layer 5 and baked at 170°C–220°C for 2–10 minutes to obtain the first lower photoresist layer 6.

[0052] The gate foot size is defined by using double-layer adhesive exposure, resulting in small lateral expansion of the gate foot metal and precise and controllable dimensions.

[0053] At accelerating voltages of 30kV to 100kV, 100μC / cm 2 ~2000μC / cm 2 Exposure conditions were used to expose two layers of photoresist. Since both PMMA-MMA and PMMA electron beam photoresist can be dissolved in the developer, development was performed simultaneously for 30s to 60s.

[0054] Depending on the difference in photolithographic sensitivity between PMMA-MMA and PMMA, development yielded results such as Figure 4 The grating foot photolithography mask structure shown.

[0055] According to an embodiment of the present invention, in step one, the substrate material is a heteroepitaxial structure, which is formed by one or more combinations of (Al)(In)(Sc)GaN-based materials and (Al)(In)(P)GaAs-based materials.

[0056] According to an embodiment of the present invention, in step one, the surface of the heteroepitaxial structure may have an in-situ passivation cap layer formed by silicide, or a certain multi-component compound of the material of the heteroepitaxial structure may be used directly as the passivation cap layer, and the thickness of the in-situ passivation cap layer includes 2 nm to 200 nm.

[0057] According to an embodiment of the present invention, in step one, the substrate material may further include an insertion layer 1, a barrier layer 2, a cap layer 3, a buffer layer, and a substrate.

[0058] According to an embodiment of the present invention, in step one, the thickness of the buffer layer is 1 μm to 2 μm; the thickness of the insertion layer 1 is 1 nm to 2 nm; the thickness of the barrier layer 2 is 2 nm to 20 nm; and the thickness of the cap layer 3 is 2 nm to 200 nm.

[0059] According to an embodiment of the present invention, in step one, the substrate may be based on wafers of 2-inch, 3-inch, 4-inch, 6-inch, 8-inch, 12-inch, and 18-inch sizes.

[0060] According to an embodiment of the present invention, in step one, the substrate material includes, but is not limited to, sapphire, Si, SiC, diamond, GaAs, AlN and GaN.

[0061] According to an embodiment of the present invention, in step one, the developer is a mixture of MIBK and IPA.

[0062] MIBK stands for methyl isobutyl ketone, also known as methyl isobutyl ketone or 4-methyl-2-pentanone; IPA stands for isopropanol.

[0063] The mass ratio of MIBK to IPA is in the range of 1:1 to 1:3, such as 1:1, 1:2, 1:3, etc.

[0064] According to an embodiment of the present invention, step one further includes a substrate treatment step to remove contaminants from the substrate surface.

[0065] According to an embodiment of the present invention, in step one, the substrate treatment step specifically includes: placing the substrate material in acetone, bathing in a 55°C water bath for 10 minutes, bathing in an ethanol water bath at 55°C for 5 minutes, immersing in deionized water for 2 minutes, and drying with N2 to remove surface contaminants.

[0066] According to an embodiment of the present invention, in step one, the two photoresist layers include: a first upper photoresist layer and a first lower photoresist layer, wherein the photolithographic sensitivity of the first upper photoresist layer is lower than that of the first lower photoresist layer.

[0067] According to an embodiment of the present invention, in step one, the electron beam photoresist uses PMMA-MMA photoresist (photosensitivity of 617.06) and PMMA photoresist (photosensitivity of 679.02), with PMMA-MMA photoresist having higher photolithographic sensitivity than PMMA photoresist.

[0068] According to an embodiment of the present invention, the height of the gate foot is 50 nm to 500 nm.

[0069] Figure 4 This is a schematic diagram of the structure of the gate foot metal deposition according to an embodiment of the present invention.

[0070] According to embodiments of the present invention, such as Figure 4 As shown, in step two: a metal is deposited on a substrate with a gate foot photolithography mask structure. The gate foot metal 7 can be a Ni / Au system, including but not limited to one or more metal combinations such as Ni, Ti, Pt, and Au.

[0071] According to embodiments of the present invention, such as Figure 4 As shown, in step two, the metal can be deposited using methods such as electron beam physical vapor deposition (EB) or atomic layer deposition (ALD).

[0072] Figure 5 This is a schematic diagram of the gate foot metal structure according to an embodiment of the present invention.

[0073] According to embodiments of the present invention, such as Figure 5 As shown, step three specifically involves: the stripping of the gate metal 7 is achieved by soaking in a room temperature acetone solution for 2 to 4 hours. The acetone solution dissolves the electron beam photoresist and causes the gate metal 7 attached to the upper layer of the photoresist to fall off, thereby leaving the gate metal 7 on the material surface to form the gate.

[0074] Figure 6 This is a schematic diagram of the structure of the three-layer photoresist according to an embodiment of the present invention.

[0075] Figure 7This is a schematic diagram of the photolithographic mask structure of the gate cap according to an embodiment of the present invention.

[0076] According to an embodiment of the present invention, step four specifically includes: Figure 6 As shown, three layers of electron beam photoresist are spin-coated onto a substrate material with gate metal 7 and baked at high temperature to obtain a second upper photoresist 6, a second middle photoresist 5, and a second lower photoresist 4, respectively.

[0077] like Figure 7 As shown, the second lower photoresist 4 is a PMMA photoresist with low photolithographic sensitivity and a large thickness. By adjusting the exposure dose and development time, the second upper photoresist 6 and the middle photoresist 5 are effectively exposed / developed to open the aperture. The exposure and development process can be the same as in step three. Finally, the second lower photoresist 4 is left as the gate cap support layer.

[0078] According to an embodiment of the present invention, in step four, the photolithographic sensitivity of the second middle layer photoresist 5, the second upper layer photoresist 6, and the second lower layer photoresist 4 decreases sequentially.

[0079] According to an embodiment of the present invention, in step four, the height of the gate foot is greater than the thickness of the gate cap support layer.

[0080] According to an embodiment of the present invention, in step four, by adjusting the spin coating speed, the thickness of the underlying photoresist with lower sensitivity is made slightly lower than the gate foot metal height prepared in step S4.

[0081] According to an embodiment of the present invention, in step four, a certain thickness of the second lower layer photoresist 4 can be consumed by photolithography / development, and the remaining thickness of the second lower layer photoresist 4 is the actual gate height.

[0082] Figure 8 This is a schematic diagram of the structure of the gate cap metal deposition according to an embodiment of the present invention.

[0083] According to an embodiment of the present invention, step five specifically includes:

[0084] like Figure 8 As shown, the gate cap metal 8 is deposited using step four, and the second lower photoresist 4 is used as the gate cap support layer to achieve contact between the gate cap metal 8 and the gate foot that is higher than the second lower photoresist 4.

[0085] Figure 9 This is a schematic diagram of the complete T-shaped gate structure according to an embodiment of the present invention.

[0086] According to an embodiment of the present invention, step six specifically includes:

[0087] like Figure 9As shown, the gate cap metal stripping scheme involves soaking in acetone solution at room temperature for 2 to 4 hours. The acetone solution can dissolve the second upper layer photoresist 6 and the second middle layer photoresist 5, causing the metal attached to the photoresist surface to fall off. The second lower layer photoresist 4 is released, resulting in a complete T-shaped gate with the gate foot and gate cap combined, thus completing the T-shaped gate fabrication.

[0088] According to an embodiment of the present invention, during the stripping process of the gate foot metal structure and the gate cap metal structure, the stripping solution used includes one or more combinations of acetone, ethanol or a film remover, and the stripping temperature range is 20°C to 95°C.

[0089] The stripping solution used can be any one or more solutions that can strip photoresist without damaging the device.

[0090] According to embodiments of the present invention, the metal deposited on the gate foot or gate cap includes one or more metal combinations of Ni, Ti, Pt, and Au.

[0091] The gate foot and gate cap metal system can be selected according to the requirements of the device.

[0092] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a T-gate based on electron beam exposure, comprising: By covering a substrate with two layers of photoresist with different sensitivities, and then exposing and developing them, a gate foot photolithography mask structure is obtained. The two layers of photoresist include a first upper photoresist and a first lower photoresist, wherein the sensitivity of the first upper photoresist is lower than that of the first lower photoresist. Deposit metal on a substrate having the aforementioned gate foot photolithographic mask structure; The gate foot photolithographic mask structure formed by two layers of photoresist is peeled off to obtain the gate foot metal structure attached to the substrate; Three layers of photoresist are spin-coated onto the substrate having the gate feet; A gate cap photomask structure is formed by a second upper layer photoresist and a second middle layer photoresist, and a gate cap support layer is formed by a second lower layer photoresist. The sensitivity of the second middle layer photoresist, the second upper layer photoresist, and the second lower layer photoresist decreases sequentially. Metal is deposited on the substrate having the aforementioned gate cap photolithography mask structure and gate cap support layer mask to obtain a gate cap metal structure; The metal structure of the gate cap is peeled off to obtain a complete T-shaped gate attached to the substrate.

2. The method according to claim 1, wherein the substrate material is a heteroepitaxial structure, and the heteroepitaxial structure is formed by one or more combinations of (Al)(In)(Sc)GaN-based materials and (Al)(In)(P)GaAs-based materials.

3. The method according to claim 2, wherein the surface of the heteroepitaxial structure has an in-situ passivation cap layer formed of silicide, and the thickness of the in-situ passivation cap layer includes 2 nm to 200 nm.

4. The method according to claim 1, wherein the height of the gate foot is 50nm to 500nm.

5. The method according to claim 1, wherein the height of the gate foot is greater than the thickness of the gate cap support layer.

6. The method of claim 1, wherein the metal deposited on the gate foot or the gate cap comprises one or more metal combinations of Ni, Ti, Pt, and Au.

7. The method according to claim 1, wherein during the stripping process of the gate foot metal structure and the gate cap metal structure, the stripping solution used includes one or more combinations of acetone, ethanol or a film remover, and the stripping temperature range is 20°C to 95°C.

8. The method according to claim 1, further comprising a substrate pretreatment step to remove contaminants from the substrate surface.

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