Semiconductor integrated circuit and memory

Abstract

Embodiments of the present disclosure relate to a semiconductor integrated circuit and a memory. The semiconductor integrated circuit comprises a first node and a second node, the first node is coupled to a working power supply, and the second node is grounded; a detection circuit coupled between the first node and the second node, configured to detect an ESD pulse signal, and when the ESD pulse signal meets a preset condition, an output end of the detection circuit outputs an enable signal, and when the ESD pulse signal does not meet the preset condition, the output end of the detection circuit is coupled to the second node; and an electrostatic discharge circuit coupled between the first node and the second node, the electrostatic discharge circuit comprises a discharge NMOS tube, a substrate and a gate of the discharge NMOS tube are coupled to the output end of the detection circuit, and the discharge NMOS tube is configured to provide a discharge channel between the first node and the second node in response to the enable signal. Embodiments of the present disclosure are beneficial to reducing the risk of latch-up effect of the semiconductor integrated circuit while improving the electrostatic discharge protection capability of the semiconductor integrated circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor integrated circuit and a memory. Background Technology

[0002] Electrostatic discharge (ESD) is the process of charge transfer caused when objects with different electrostatic potentials approach or come into direct contact. When an ESD event occurs, the instantaneous overvoltage can potentially damage semiconductor devices, leading to device failure. Power-clamp circuits are typically used to mitigate ESD phenomena in semiconductor integrated circuits.

[0003] The latch-up effect refers to the low-impedance path created between power supply (VDD) and ground (GND) in CMOS circuits due to the interaction of parasitic PNP and NPN transistors, resulting in a large current between VDD and GND.

[0004] Currently, while reducing the latch-up risk of semiconductor integrated circuits, it may also reduce the ESD protection capability of semiconductor integrated circuits. Summary of the Invention

[0005] This disclosure provides a semiconductor integrated circuit and a memory, which at least helps to solve the problem that reducing the latch-up effect risk of semiconductor integrated circuits may reduce the ESD protection capability of semiconductor integrated circuits.

[0006] This disclosure provides a semiconductor integrated circuit, including: a first node and a second node, the first node being coupled to a power supply and the second node being grounded; a detection circuit coupled between the first node and the second node, configured to detect an ESD pulse signal, wherein when the ESD pulse signal meets a preset condition, the output terminal of the detection circuit outputs an enable signal, and when the ESD pulse signal does not meet the preset condition, the output terminal of the detection circuit is coupled to the second node; and an electrostatic discharge circuit coupled between the first node and the second node, the electrostatic discharge circuit including a discharge NMOS transistor, the substrate and gate of the discharge NMOS transistor being coupled to the output terminal of the detection circuit, and configured to provide a discharge channel between the first node and the second node in response to the enable signal.

[0007] In some embodiments, the detection circuit includes: a first detection circuit coupled between a first node and a second node, configured such that when the ESD pulse signal meets a preset condition, the output terminal of the first detection circuit outputs an enable signal; and a second detection circuit coupled between the first node and the second node, configured such that when the ESD pulse signal does not meet the preset condition, the output terminal of the first detection circuit is coupled to the second node; wherein the output terminal of the first detection circuit serves as the output terminal of the detection circuit.

[0008] In some embodiments, the first detection circuit includes: a first capacitor, a first end of which is coupled to a first node; and a first resistor, a first end of which is coupled to a second end of the first capacitor, wherein the first end of the first resistor serves as the output terminal of the first detection circuit, and the second end of the first resistor is coupled to a second node.

[0009] In some embodiments, the second detection circuit includes: a trigger circuit coupled between the first node and the second node, configured to detect an ESD pulse signal and output a trigger signal based on the ESD pulse signal; and a first switch circuit coupled between the output terminal of the first detection circuit and the second node, configured to turn on in response to a trigger signal corresponding to an ESD pulse signal not meeting a preset condition.

[0010] In some embodiments, the trigger circuit includes: a detection circuit coupled between the first node and the second node, configured to output a detection signal based on an ESD pulse signal, wherein the level of the detection signal corresponding to the ESD pulse signal meeting a preset condition is different from the level of the detection signal corresponding to the ESD pulse signal not meeting the preset condition; and an inverting circuit configured to output a trigger signal in response to the detection signal, wherein the trigger signal and the detection signal are signals with opposite phases.

[0011] In some embodiments, the inverting circuit includes: a second resistor, a first end of which is coupled to a first node; a first NMOS transistor, a first end of which is coupled to a second end of the second resistor and provides a trigger signal, a second end of which is coupled to a second node, and a gate of which receives a detection signal.

[0012] In some embodiments, the inverting circuit includes: a PMOS transistor, the first end of which is coupled to a first node, and the gate of the PMOS transistor receiving a detection signal; and a first NMOS transistor, the first end of which is coupled to the second end of the PMOS transistor and provides a trigger signal, the second end of which is coupled to a second node, and the gate of the first NMOS transistor receiving the detection signal.

[0013] In some embodiments, the detection circuit includes: a second switching circuit, the first terminal of which is coupled to a first node and configured to be turned on when the ESD pulse signal meets a preset condition and turned off when the ESD pulse signal does not meet the preset condition; and a third resistor, the first terminal of which is coupled to a second terminal of the second switching circuit and provides a detection signal, and the second terminal of which is coupled to a second node.

[0014] In some embodiments, the second switching circuit includes a plurality of diodes connected in series, wherein the anode of one of the diodes is coupled to the first node.

[0015] In some embodiments, the second switching circuit includes at least one second capacitor.

[0016] In some embodiments, the first switching circuit includes a second NMOS transistor, the gate of which receives a trigger signal, the first end of which is coupled to the output of the first detection circuit, and the second end of which is coupled to a second node.

[0017] In some embodiments, the first end of the bleeder NMOS transistor is coupled to the first node, and the second end of the bleeder NMOS transistor is coupled to the second node.

[0018] In some embodiments, the electrostatic discharge circuit further includes a fourth resistor coupled between the first node and the first terminal of the discharge NMOS transistor.

[0019] Accordingly, this disclosure also provides a memory, including: the semiconductor integrated circuit provided in any of the above embodiments.

[0020] The technical solution provided in this disclosure has the following advantages:

[0021] The semiconductor integrated circuit technical solution provided in this disclosure includes a detection circuit and an electrostatic discharge (ESD) circuit. Both the detection circuit and the ESD circuit are coupled between a first node and a second node. The ESD circuit includes a discharge NMOS transistor, the substrate and gate of which are coupled to the output terminal of the detection circuit. The first node is coupled to a power supply, and the second node is grounded. The detection circuit is configured to detect ESD pulse signals. When the ESD pulse signal meets a preset condition, the output terminal of the detection circuit outputs an enable signal, allowing the ESD circuit to provide a discharge channel between the first and second nodes in response to the enable signal, thereby improving ESD protection. When the ESD pulse signal does not meet the preset condition, the output terminal of the detection circuit is coupled to the second node, thereby turning off the parasitic NPN bipolar transistor (BJT) in the discharge NMOS transistor and reducing latch-up risk. Therefore, in the semiconductor integrated circuit provided in this embodiment, when the semiconductor integrated circuit is subjected to ESD impact, a discharge channel can be provided for the first node and the second node to improve the ESD protection capability; when it is not subjected to ESD impact, the latch-up risk of the semiconductor integrated circuit is reduced. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a circuit diagram of a semiconductor integrated circuit;

[0024] Figure 2 A circuit diagram of a semiconductor integrated circuit provided in an embodiment of this disclosure;

[0025] Figure 3 A circuit diagram of another semiconductor integrated circuit provided in an embodiment of this disclosure;

[0026] Figure 4 A circuit diagram of yet another semiconductor integrated circuit provided in this disclosure embodiment;

[0027] Figure 5 A circuit diagram of another semiconductor integrated circuit provided in an embodiment of this disclosure. Detailed Implementation

[0028] As the background technology indicates, there is a problem that reducing the gate-lock effect risk of semiconductor integrated circuits may simultaneously reduce their ESD protection capabilities. Analysis reveals that one reason for this problem is that, when reducing the gate-lock effect risk, the ESD protection capability of semiconductor integrated circuits is... Figure 1 Current power-clamp circuits typically include a gate-grounded NMOS1 as a discharge device. The principle is to utilize the turn-on of the parasitic NPN BJT within the NMOS to provide a low-impedance discharge path for charge dissipation. Gate grounding ensures that NMOS1 is not conducting and has no leakage current during normal operation of the semiconductor integrated circuit. However, the presence of the NPN BJT causes a latch-up effect. To mitigate this effect and ensure proper operation of the semiconductor integrated circuit, a detection circuit is usually added to receive the power-on signal during circuit operation. Specifically, the detection circuit includes NMOS2. When NMOS2 is turned on based on the power-on signal, the gate of NMOS1 is coupled to ground, causing NMOS1 to turn off, thereby shutting off the parasitic NPN BJT within NMOS1 and mitigating the latch-up effect. However, since NMOS1 is in a non-conducting state, it cannot provide a low-impedance discharge path when the circuit is subjected to ESD, thus reducing the protection effect of the semiconductor integrated circuit against ESD.

[0029] This disclosure provides a semiconductor integrated circuit and a memory, including a detection circuit and an electrostatic discharge (ESD) circuit. Both the detection circuit and the ESD circuit are coupled between a first node and a second node. The ESD circuit includes a discharge NMOS transistor, the substrate and gate of which are coupled to the output terminal of the detection circuit. The first node is coupled to a power supply, and the second node is grounded. The detection circuit is configured to detect ESD pulse signals. When the ESD pulse signal meets a preset condition, the output terminal of the detection circuit outputs an enable signal, allowing the ESD circuit to provide a discharge channel between the first and second nodes in response to the enable signal, thereby improving ESD protection. When the ESD pulse signal does not meet the preset condition, the output terminal of the detection circuit is coupled to the second node, thereby turning off the parasitic NPN BJT in the discharge NMOS transistor and reducing latch-up risk.

[0030] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0031] Figure 2 A circuit diagram of a semiconductor integrated circuit provided in an embodiment of this disclosure.

[0032] refer to Figure 2 The semiconductor integrated circuit includes: a first node A and a second node B, the first node A being coupled to a power supply VDD and the second node B being grounded; a detection circuit 10, coupled between the first node A and the second node B, configured to detect ESD pulse signals, and output an enable signal when the ESD pulse signal meets a preset condition, and output the second node B when the ESD pulse signal does not meet the preset condition; and an electrostatic discharge circuit 11, coupled between the first node A and the second node B, including a discharge NMOS transistor M1, the substrate and gate of the discharge NMOS transistor M1 being coupled to the output of the detection circuit 10, and configured to provide a discharge channel between the first node A and the second node B in response to the enable signal.

[0033] When an ESD event impacts the operating power supply VDD of the semiconductor integrated circuit, and the ESD pulse signal meets preset conditions, the bleeder NMOS transistor M1 is turned on based on the turn-on signal, providing a discharge channel for the first node A and the second node B, thus improving ESD protection capability. When the semiconductor integrated circuit is not subjected to ESD impact, or the ESD pulse signal does not meet the preset conditions, since the gate and substrate of the bleeder NMOS transistor M1 are electrically connected to the output terminal of the detection circuit 10, which is equivalent to the gate of the bleeder NMOS transistor M1 being electrically connected to the grounded second node B, the bleeder NMOS transistor M1 is turned off, thereby turning off the parasitic NPN BJT of the bleeder NMOS transistor M1, thereby reducing the latch-up risk of the semiconductor integrated circuit. In other words, a detection circuit 10 is set in the semiconductor integrated circuit to detect ESD signals. When the ESD impact is insufficient to break down the semiconductor device, the bleeder NMOS transistor M1 is kept off, thereby improving the latch-up risk; when the ESD signal meets the preset conditions, it may break down the semiconductor device. At this time, the bleeder NMOS transistor M1 is turned on, thereby providing ESD protection for the semiconductor integrated circuit.

[0034] In some embodiments, the first end of the discharge NMOS transistor M1 is coupled to the first node A, and the second end of the discharge NMOS transistor M1 is coupled to the second node B. Specifically, the discharge NMOS transistor M1 has a P-type substrate and an N-type doped region, with the N-type doped region serving as either the source or drain of the NMOS transistor. The drain of the discharge NMOS transistor M1 is coupled to the first node A, and the source of the discharge NMOS transistor M1 is coupled to the second node B. When the discharge NMOS transistor M1 is turned on, it provides a discharge channel between the first node A and the second node B, thereby rapidly discharging the electrostatic charge accumulated at the first node A to ground.

[0035] Specifically, in some embodiments, the principle by which the bleeder NMOS transistor M1 provides a discharge channel between the first node A and the second node B is as follows: When the ESD pulse signal meets a preset condition, the ESD pulse signal impacts the operating power supply VDD, causing the voltage of the first node A to rise rapidly. Simultaneously, the bleeder NMOS transistor M1 turns on in response to the turn-on signal, and a large amount of positive charge accumulates at the drain terminal of the bleeder NMOS transistor M1. Among them, a certain amount of positive charge is transferred to the P-type substrate through the reverse-biased PN junction between the drain and the P-type substrate. This portion of positive charge will accumulate at the ground terminal, which is also a P-type substrate. The positive charge accumulated at the ground terminal makes the PN junction between the drain and the source terminal conduct, thereby turning on the parasitic NPN BJT of the bleeder NMOS. After the parasitic NPN BJT of the bleeder NMOS is discharged, the large amount of positive charge accumulated at the drain terminal is rapidly transferred to the source terminal through the substrate below the gate in the bleeder NMOS transistor M1, thereby rapidly discharging the positive charge accumulated at the drain terminal to the ground terminal.

[0036] In some embodiments, the ESD pulse signal can be a voltage, and the preset condition can be a pre-set voltage for the ESD pulse signal. Specifically, in some embodiments, the preset condition can be determined based on whether the voltage of the ESD pulse signal reaches a voltage that can break down the semiconductor device. That is, when the ESD pulse signal reaches the pre-set voltage, the semiconductor device will be at risk of being broken down; when the ESD pulse signal does not reach the pre-set voltage, it is insufficient to break down the semiconductor device. In other words, a critical point is set; only when this critical point is exceeded will the discharge NMOS transistor turn on. This allows the discharge NMOS transistor M1 in the semiconductor integrated circuit to remain in a non-conducting state for a longer period, thereby maintaining a longer latch-up resistance for the semiconductor integrated circuit, enabling it to operate normally for a longer time and improving its efficiency.

[0037] In some embodiments, the detection circuit 10 includes: a first detection circuit 101, coupled between a first node A and a second node B, configured to output an enable signal when the ESD pulse signal meets a preset condition; and a second detection circuit 102, coupled between the first node A and the second node B, configured to couple the output of the first detection circuit 101 to the second node B when the ESD pulse signal does not meet the preset condition. The output of the first detection circuit 101 (refer to reference numeral D in the figure) serves as the output of the detection circuit 10. Specifically, when the voltage of the ESD pulse signal reaches a preset voltage, the enable signal output by the first detection circuit 101 triggers the conduction of the discharge NMOS transistor M1, forming a discharge channel to discharge the electrostatic charge generated by the ESD pulse signal. When the voltage of the ESD pulse signal does not reach the preset voltage, the output of the first detection circuit 101 is coupled to the second node B via the second detection circuit 102. Since the gate and substrate of the bleeder NMOS transistor M1 are electrically connected to the output of the detection circuit 10, and the second node B is grounded, when the voltage of the ESD pulse signal does not reach the preset voltage, the gate of the bleeder NMOS transistor M1 is grounded. Therefore, the bleeder NMOS transistor M1 is in a non-conducting state, thereby turning off the parasitic NPN BJT of the bleeder NMOS transistor M1 and reducing the latch-up risk of the semiconductor integrated circuit. Specifically, when the ESD pulse signal does not meet the preset condition, the substrate of the bleeder NMOS transistor M1 is directly grounded, which can prevent the P-type substrate and N-well in the NMOS transistor from forward conducting, further improving the latch-up effect.

[0038] In some embodiments, the first detection circuit 101 may include: a first capacitor C1, the first end of which is coupled to a first node A; a first resistor R1, the first end of which is coupled to a second end of the first capacitor C1, and the first end of the first resistor R1 serves as the output terminal of the first detection circuit 101, and the second end of the first resistor R1 is coupled to a second node B.

[0039] When the ESD pulse signal voltage reaches a preset voltage, the ESD pulse signal impacts the operating power supply VDD, causing the voltage at the first node A to rise rapidly. Since the first terminal of the first capacitor C1 is coupled to the first node A, and the voltage across the first capacitor C1 cannot change abruptly (i.e., the first capacitor C1 does not act as a voltage divider), the voltage output at the second terminal of the first capacitor C1 rises along with the increase in the operating power supply VDD, making the second terminal of the first capacitor C1 high-level, thereby turning on the discharge NMOS transistor M1. The first resistor R1 is coupled between the second terminal of the first capacitor C1 and the second node B, acting as a voltage divider to prevent the voltage across the capacitor from becoming too high, which would cause a sharp change in the operating power supply VDD input to the output terminal of the first detection circuit 101. This prevents the gate of the discharge NMOS transistor M1 from experiencing a severe latch-up effect due to a sharp change in the input voltage. It is understood that in some other embodiments, the first detection circuit 101 may also be other logic gate circuits.

[0040] In some embodiments, the second detection circuit 102 includes: a trigger circuit 103 coupled between the first node A and the second node B, configured to detect an ESD pulse signal and output a trigger signal based on the ESD pulse signal; and a first switch circuit 104 coupled between the output terminal of the first detection circuit 101 and the second node B, configured to turn on in response to a trigger signal corresponding to the ESD pulse signal not meeting a preset condition. In some embodiments, the trigger signal can be divided into a first trigger signal corresponding to the ESD pulse signal meeting a preset condition and a second trigger signal corresponding to the ESD pulse signal not meeting a preset condition. Specifically, when the ESD pulse signal reaches a preset voltage, the trigger circuit 103 outputs the first trigger signal to de-convert the second switch circuit, thereby allowing the gate and substrate of the discharge NMOS transistor M1 to be electrically connected to the output terminal of the first detection circuit 101, thus turning on in response to an on signal and providing a discharge channel for the first node A and the second node B. When the ESD pulse signal does not reach the preset voltage, the trigger circuit 103 outputs a second trigger signal to turn on the first switching circuit 104. This causes the gate of the discharge NMOS transistor M1 to be coupled between the output of the first detection circuit 101 and the second node B via the first switching circuit 104, grounding the gate of the discharge NMOS transistor M1. In other words, the discharge NMOS transistor M1 is not turned on, thus shutting down the parasitic NPN BJT in the discharge NMOS transistor M1 and reducing latch-up risk. In other words, by outputting two different trigger signals from the trigger circuit 103, the semiconductor integrated circuit, in its power-on state, can, on the one hand, keep the discharge NMOS transistor M1 off when the ESD pulse signal does not reach the preset voltage, improving latch-up risk; and on the other hand, turn on the discharge NMOS transistor M1 when the ESD pulse signal reaches the preset voltage, providing a discharge channel. This achieves both improved latch-up risk and enhanced ESD protection capability of the semiconductor integrated circuit in its power-on state.

[0041] In some embodiments, the trigger circuit 103 may include: a detection circuit 105 coupled between the first node A and the second node B, configured to output a detection signal based on an ESD pulse signal, wherein the level of the detection signal corresponding to the ESD pulse signal meeting a preset condition is different from the level of the detection signal corresponding to the ESD pulse signal not meeting the preset condition; and an inverting circuit 106 configured to output a trigger signal in response to the detection signal, wherein the trigger signal and the detection signal are signals with opposite phases. In some embodiments, when the ESD pulse signal meets the preset condition, the detection signal output by the detection circuit 105 is high-level, and when the ESD pulse signal does not meet the preset condition, the detection signal output by the detection circuit 105 is low-level. An inverting circuit 106 is configured so that the trigger signal and the detection signal are out of phase. This helps distinguish between different trigger signals that turn on and off the first switching circuit 104, thus maintaining the first switching circuit 104 in the power-on state. This improves the latch-up risk of the semiconductor integrated circuit under normal operating conditions. When the ESD pulse signal meets a preset condition, the first switching circuit 104 can be immediately turned off to enhance ESD protection. This is because, in some embodiments, the first switching circuit 104 is turned on based on a power-on signal, which can be generated internally and is consistent with the operating power supply VDD. The first switching circuit 104 turns on after the operating power supply VDD is input. In order for the first switching circuit 104 to turn off when the ESD pulse signal meets the preset condition, a trigger signal opposite to that used when the ESD pulse signal does not meet the preset condition needs to be input to the first switching circuit 104. When the ESD pulse signal meets the preset conditions, the operating power supply VDD will rise rapidly. If the first switching circuit 104 is configured to turn on in response to a high-level signal, then even when the ESD pulse signal does not meet the preset conditions, the operating power supply VDD will still provide a high-level signal. Therefore, if the inverting circuit 106 is not provided, the first switching circuit 104 may remain in the on state. Based on this, the inverting circuit 106 can accurately distinguish between the trigger signal when the ESD pulse signal does not meet the preset conditions and the trigger signal when the ESD pulse signal meets the preset conditions.

[0042] Specifically, in some embodiments, the first switching circuit 104 is turned on in response to a high level. When the ESD pulse signal does not meet the preset conditions, the detection signal output by the detection circuit 105 is low, and the inverting circuit 106 outputs a high-level trigger signal in response to the low-level detection signal, and the first switching circuit 104 is turned on; when the ESD pulse signal meets the preset conditions, the detection signal output by the detection circuit 105 is high, and the inverting circuit 106 outputs a low-level trigger signal in response to the high-level detection signal, and the first switching circuit 104 is turned off, so that the gate and substrate of the discharge NMOS transistor M1 can be electrically connected to the output terminal of the first detection circuit 101, thereby turning on in response to the turn-on signal and providing a discharge channel for the first node A and the second node B.

[0043] In some embodiments, the detection circuit 105 may include: a second switching circuit 107, the first terminal of which is coupled to the first node A, configured to turn on when the ESD pulse signal meets a preset condition and turn off when the ESD pulse signal does not meet the preset condition; and a third resistor R3, the first terminal of which is coupled to the second terminal of the second switching circuit 107 and provides a detection signal, and the second terminal of which is coupled to the second node B. The third resistor R3 acts as a voltage divider, preventing the second terminal of the second switching circuit 107 from outputting an excessively large detection signal voltage when the ESD pulse signal meets the preset condition, thereby reducing the transient current flowing through the inverting circuit 106. The second switching circuit 107 turns off when the ESD pulse signal does not meet the preset condition, thereby ensuring the normal conduction of the first switching circuit 104.

[0044] Specifically, in some embodiments, the second switching circuit 107 may include multiple diodes connected in series, with the anode of one diode coupled to the first node A. It is understood that the diode can only conduct when the voltage across its positive and negative terminals meets its forward voltage. Based on this, the number of diodes can be set according to the voltage at which the ESD pulse signal meets a preset condition, such that when the ESD pulse signal voltage meets the preset condition, the series-connected diodes conduct, generating a corresponding detection signal with a high level; when the ESD pulse signal voltage does not meet the preset condition, the series-connected diodes do not conduct, generating a low-level detection signal.

[0045] In some embodiments, the inverter circuit 106 may include: a second resistor R2, the first end of which is coupled to a first node A; a first NMOS transistor M2, the first end of which is coupled to the second end of the second resistor R2 and provides a trigger signal, the second end of which is coupled to a second node B, and the gate of the first NMOS transistor M2 receiving a detection signal. In some embodiments, the drain of the first NMOS transistor M2 is electrically connected to the first node A, and the source of the first NMOS transistor M2 is electrically connected to the second node B. The second resistor R2 acts as a voltage divider to prevent the drain input of the first NMOS transistor M2 from rapidly changing the operating power supply VDD when the first NMOS transistor M2 is turned on based on the detection signal. This can, on the one hand, improve the latch-up caused by the parasitic NPN BJT in the first NMOS transistor M2 due to the rapidly changing operating power supply VDD, and on the other hand, reduce the transient current flowing through the first NMOS transistor M2.

[0046] Specifically, in some embodiments, when the inverting circuit 106 includes a second resistor R2 and a first NMOS transistor M2, and the second switching transistor includes multiple diodes connected in series, the trigger circuit 103 operates as follows:

[0047] When the voltage of the ESD pulse signal does not meet the preset condition, the series diode is not turned on, generating a low-level detection signal, and the second terminal node of the series diode is at a low level. The gate of the first NMOS transistor M2 receives the low-level detection signal and is not turned on. The first switching circuit 104 is coupled between the first node A and the second node B and turns on in response to the power-on signal of the working power supply VDD. The gate of the bleeder NMOS transistor M1 is electrically connected to the second node B, causing the bleeder NMOS transistor M1 to turn off, thereby turning off the parasitic NPN BJT of the bleeder NMOS transistor M1, and thus reducing the latch-up risk of the semiconductor integrated circuit.

[0048] When the voltage of the ESD pulse signal meets the preset condition, the series diode conducts, generating a high-level detection signal, and the second terminal node of the series diode (refer to reference E in the figure) is at a high level. Furthermore, the first node A is pulled high, thereby pulling the second terminal node of the first capacitor C1 (the output of the first detection circuit) high. The gate of the first NMOS transistor M2 receives the high-level detection signal and conducts, forming a conductive channel between the drain and source of the first NMOS transistor M2. This causes the positive charge accumulated at the drain of the first NMOS transistor M2 to move to the source, resulting in the drain level of the first NMOS transistor M2 being pulled low, i.e., the first NMOS transistor M2 outputs a low-level trigger signal. The first switching circuit 104 responds to the low-level trigger signal and does not conduct, thereby coupling the gate of the discharge NMOS transistor M1 to the second terminal of the first capacitor C1, and conducting based on the high level at the second terminal of the first capacitor C1. This allows the electrostatic discharge circuit 11 to respond to the turn-on signal and provide a discharge channel between the first node A and the second node B, thereby improving the ESD protection capability.

[0049] Figure 3 A circuit diagram of another semiconductor integrated circuit provided in an embodiment of this disclosure.

[0050] refer to Figure 3 In other embodiments, the inverter circuit 106 (reference) Figure 2 The system may also include: a PMOS transistor M4, the first end of which is coupled to a first node A, and the gate of the PMOS transistor M4 receiving a detection signal; a first NMOS transistor M2, the first end of which is coupled to the second end of the PMOS transistor M4 and provides a trigger signal, the second end of which is coupled to a second node B, and the gate of the first NMOS transistor M2 receiving the detection signal. In some embodiments, the PMOS transistor M4 is turned on in response to a low-level detection signal, and the first end of the PMOS transistor M4 is the source, and the second end of the PMOS transistor M4 is the drain, so that when the PMOS transistor M4 is turned on, the second end of the PMOS transistor M4 outputs a high-level trigger signal; the first NMOS transistor M2 is turned on in response to a high-level detection signal, the first end of the first NMOS transistor M2 is the drain, and the second end of the first NMOS transistor M2 is the source, so that when the first NMOS transistor M2 is turned on, the first end of the first NMOS transistor M2 outputs a low-level trigger signal. In other words, when the detection signal is low, the PMOS transistor M4 is turned on and outputs a high-level trigger signal; when the detection signal is high, the first NMOS transistor M2 is turned on and outputs a low-level trigger signal, thus achieving an inverting effect.

[0051] In some embodiments, when the inverting circuit 106 includes a PMOS transistor M4 and a first NMOS transistor M2, and the second switching transistor includes a plurality of diodes connected in series, the trigger circuit 103 (reference) Figure 2 The working principle is as follows:

[0052] When the voltage of the ESD pulse signal does not meet the preset condition, the series diode is not turned on, generating a low-level detection signal, and the second terminal of the series diode is at a low level. The gate of the first NMOS transistor M2 receives the low-level detection signal and is not turned on, while the gate of the PMOS transistor M4 receives the low-level detection signal and is turned on. A conductive channel is formed between the source and drain of the PMOS transistor M4, causing the charge accumulated at the source to move to the drain, resulting in the drain level of the PMOS transistor M4 being pulled high, outputting a high-level trigger signal. The first switching circuit 104 (reference) Figure 2 In response to a high-level trigger signal, the gate of the bleeder NMOS transistor M1 is electrically connected to the second node B, causing the bleeder NMOS transistor M1 to turn off, thereby turning off the parasitic NPN BJT of the bleeder NMOS transistor M1 and reducing the latch-up risk of the semiconductor integrated circuit.

[0053] When the voltage of the ESD pulse signal meets the preset condition, the series diode conducts, generating a high-level detection signal, and the second terminal node of the series diode is at a high level. Furthermore, the first node A is pulled high, thereby pulling the second terminal of the first capacitor C1 high. The gate of the first NMOS transistor M2 receives the high-level detection signal and conducts, while the gate of the PMOS transistor M4 receives the high-level detection signal and does not conduct. A conductive channel is formed between the drain and source of the first NMOS transistor M2, causing the positive charge accumulated at the drain of the first NMOS transistor M2 to move to the source, resulting in the drain level of the first NMOS transistor M2 being pulled low, i.e., the first NMOS transistor M2 outputs a low-level trigger signal. (First switching circuit 104 - reference) Figure 2 In response to a low-level trigger signal, the circuit does not conduct, thereby coupling the gate of the discharge NMOS transistor M1 to the second terminal of the first capacitor C1, and conducting based on the high level of the second terminal node of the first capacitor C1. This allows the electrostatic discharge circuit 11 to provide a discharge channel between the first node A and the second node B in response to an enable signal, thereby improving the ESD protection capability.

[0054] refer to Figure 2 as well as Figure 3In some embodiments, the first switching circuit 104 may include a second NMOS transistor M3. The gate of the second NMOS transistor M3 receives a trigger signal. The first terminal of the second NMOS transistor M3 is coupled to the output terminal of the first detection circuit 101, and the second terminal of the second NMOS transistor M3 is coupled to the second node B. Specifically, when the voltage of the ESD pulse signal does not meet the preset condition, the second NMOS transistor M3 is coupled between the first node A and the second node B so that the gate of the second NMOS transistor M3 receives a power-on signal and is turned on, thereby improving the latch-up risk. When the voltage of the ESD pulse signal meets the preset condition, the first NMOS transistor M2 outputs a low-level trigger signal, and the gate of the second NMOS transistor M3 receives a low-level trigger signal and is not turned on, thereby improving the ESD protection capability.

[0055] Figure 4 A circuit diagram of another semiconductor integrated circuit provided in this disclosure embodiment.

[0056] refer to Figure 4 It is understood that in some other embodiments, the second switching circuit 107 (see reference 107) Figure 2 It may include at least one second capacitor C2. The first end of the second capacitor C2 is electrically connected to the first node A, and the second end of the second capacitor C2 provides a detection signal.

[0057] Specifically, the second switching circuit 107 (reference) Figure 2 When the second capacitor C2 is included, the trigger circuit 103 (reference) Figure 2 The working principle is as follows:

[0058] When the ESD pulse signal does not meet the preset conditions, the operating power supply VDD charges the second capacitor C2, causing the second capacitor C2 to act as a voltage divider. This results in the voltage at the second terminal of the second switching circuit 107 being the difference between the operating power supply VDD and the voltage across the second capacitor C2, meaning the second terminal of the second switching circuit 107 is at a low level. At this time, the detection signal is a low-level detection signal. The inverter circuit 106 responds to the low-level detection signal by outputting a high-level trigger signal, and the first switching circuit 104 turns on in response to the low-level trigger signal.

[0059] When the ESD pulse signal meets the preset conditions, the power line is subjected to an ESD impact, and the level of the first node A is rapidly pulled high. Since the voltage across the second capacitor C2 cannot change abruptly, the second capacitor C2 cannot be fully charged in time; that is, the second capacitor C2 does not function as a voltage divider. Therefore, the output voltage at the second terminal of the second switching circuit 107 rises with the operating power supply VDD, presenting a high level. At this time, the detection signal is a high-level detection signal. Inverting circuit 106 (reference) Figure 2In response to a high-level detection signal, a low-level trigger signal is output, and the first switching circuit 104 (reference) Figure 2 It does not conduct in response to a low-level trigger signal.

[0060] It is understood that in some other embodiments, the second switching circuit 107 (see reference 107) Figure 2 It can also be other logic gate circuits.

[0061] Figure 5 A circuit diagram of another semiconductor integrated circuit provided in an embodiment of this disclosure.

[0062] refer to Figure 5 In some embodiments, the electrostatic discharge circuit 11 (reference) Figure 2 This also includes a fourth resistor, R4, which is coupled between the first node A and the first terminal of the bleeder NMOS transistor M1. The fourth resistor R4 acts as a voltage divider. When the ESD pulse signal meets the preset conditions, the bleeder NMOS transistor M1 turns on, causing the operating power supply VDD to rise sharply, pulling the level of the first node A high. The fourth resistor R4, connected in series with the bleeder NMOS transistor M1, divides a portion of the operating power supply VDD, thus lowering the voltage input to the first terminal of the bleeder NMOS transistor M1 and reducing the transient current flowing through it. Furthermore, the fourth resistor R4 can also share some of the sharply increased operating power supply VDD caused by the ESD impact, thus mitigating the ESD impact.

[0063] In the semiconductor integrated circuit technical solution provided in the above-disclosed embodiments, a detection circuit 10 and an electrostatic discharge circuit 11 are provided. Both the detection circuit 10 and the electrostatic discharge circuit 11 are coupled between a first node A and a second node B. The electrostatic discharge circuit 11 includes a discharge NMOS transistor M1, the substrate and gate of which are coupled to the output terminal of the detection circuit 10. The first node A is coupled to the operating power supply VDD, and the second node B is grounded. The detection circuit 10 is configured to detect ESD pulse signals. When the ESD pulse signal meets a preset condition, the output terminal of the detection circuit 10 outputs an enable signal, allowing the electrostatic discharge circuit 11 to provide a discharge channel between the first node A and the second node B in response to the enable signal, thereby improving ESD protection capability. When the ESD pulse signal does not meet the preset condition, the output terminal of the detection circuit 10 is coupled to the second node B, thereby shutting down the parasitic NPN BJT in the discharge NMOS transistor and reducing latch-up risk.

[0064] Accordingly, this disclosure also provides a memory, including the semiconductor integrated circuit provided in any of the above embodiments. The memory can be a storage cell or device based on a semiconductor device or component. For example, the memory device can be a volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be a non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc. By incorporating detection circuits and electrostatic discharge circuits into the semiconductor integrated circuits located in the memory, a discharge channel is provided for the first and second nodes of the semiconductor integrated circuit when it is subjected to a certain degree of ESD impact, thereby improving ESD protection capability. When it is not subjected to ESD impact, the latch-up risk of the semiconductor integrated circuit can be reduced, thereby improving the reliability of the memory.

[0065] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor integrated circuit, characterized by comprising: include: First node and second node, the first node is coupled to the working power supply, and the second node is grounded; A detection circuit, coupled between the first node and the second node, is configured to detect ESD pulse signals. When the ESD pulse signal meets a preset condition, the output terminal of the detection circuit outputs an enable signal. When the ESD pulse signal does not meet the preset condition, the output terminal of the detection circuit is coupled to the second node. An electrostatic discharge circuit is coupled between a first node and a second node. The electrostatic discharge circuit includes a discharge NMOS transistor, the substrate and gate of which are coupled to the output of the detection circuit, and is configured to provide a discharge channel between the first node and the second node in response to the enable signal. The detection circuit includes: A first detection circuit, coupled between the first node and the second node, is configured to output the enable signal at its output terminal when the ESD pulse signal meets a preset condition. A second detection circuit is coupled between the first node and the second node and is configured such that when the ESD pulse signal does not meet a preset condition, the output of the first detection circuit is coupled to the second node. Wherein, the output terminal of the first detection circuit is used as the output terminal of the detection circuit; The second detection circuit includes: A trigger circuit, coupled between the first node and the second node, is configured to detect the ESD pulse signal and output a trigger signal based on the ESD pulse signal; A first switching circuit, coupled between the output of the first detection circuit and the second node, is configured to turn on the trigger signal corresponding to the ESD pulse signal not meeting the preset condition. The trigger circuit includes: A detection circuit, coupled between the first node and the second node, is configured to output a detection signal based on the ESD pulse signal, wherein the level of the detection signal corresponding to the ESD pulse signal satisfying a preset condition is different from the level of the detection signal corresponding to the ESD pulse signal not satisfying the preset condition. An inverting circuit is configured to output a trigger signal in response to the detection signal, wherein the trigger signal and the detection signal are signals with opposite phases. The inverting circuit includes: The second resistor has its first end coupled to the first node; A first NMOS transistor, wherein a first terminal of the first NMOS transistor is coupled to a second terminal of the second resistor and provides the trigger signal, a second terminal of the first NMOS transistor is coupled to the second node, and the gate of the first NMOS transistor receives the detection signal.

2. The semiconductor integrated circuit as described in claim 1, characterized in that, The first detection circuit includes: A first capacitor, wherein a first terminal of the first capacitor is coupled to the first node; The first resistor has a first end coupled to the second end of the first capacitor, and the first end of the first resistor serves as the output terminal of the first detection circuit. The second end of the first resistor is coupled to the second node.

3. The semiconductor integrated circuit as described in claim 1, characterized in that, The detection circuit includes: The second switching circuit, wherein the first terminal of the second switching circuit is coupled to the first node, is configured to be turned on when the ESD pulse signal meets a preset condition, and turned off when the ESD pulse signal does not meet the preset condition; A third resistor, the first end of which is coupled to the second end of the second switching circuit and provides the detection signal, and the second end of which is coupled to the second node.

4. The semiconductor integrated circuit as described in claim 3, characterized in that, The second switching circuit includes a plurality of diodes connected in series, and the positive terminal of one of the diodes is coupled to the first node.

5. The semiconductor integrated circuit as described in claim 3, characterized in that, The second switching circuit includes at least one second capacitor.

6. The semiconductor integrated circuit as described in claim 1, characterized in that, The first switching circuit includes a second NMOS transistor, the gate of which receives the trigger signal, a first terminal of which is coupled to the output terminal of the first detection circuit, and a second terminal of which is coupled to the second node.

7. The semiconductor integrated circuit as described in claim 1, characterized in that, The first end of the discharge NMOS transistor is coupled to the first node, and the second end of the discharge NMOS transistor is coupled to the second node.

8. The semiconductor integrated circuit as described in claim 1, characterized in that, The electrostatic discharge circuit further includes a fourth resistor, which is coupled between the first node and the first end of the discharge NMOS transistor.

9. A memory, characterized in that, Including the semiconductor integrated circuit as described in any one of claims 1-8.

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