A method of measuring a semiconductor structure, a semiconductor structure and a measuring apparatus

Abstract

The embodiment of the present disclosure provides a semiconductor structure measurement method, a semiconductor structure and a measurement device, wherein the method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a first region and a second region; a first test structure and a second test structure are arranged on the two sides of the first region respectively, and a second test structure and a third test structure are arranged on the two sides of the second region respectively; the first region has a first design width W1, and the second region has a second design width W2; wherein the first design width W1 is different from the second design width W2; a first electrical parameter R1 of the first region and a second electrical parameter R2 of the second region are measured and calculated; and a first deviation Δx between an actual width of the second region and the second design width W2 is determined based on the R1, the R2, the W1 and the W2.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for measuring semiconductor structures, a semiconductor structure, and a measuring device. Background Technology

[0002] With the miniaturization of dimensions and the increase in integration, dimensional fluctuations often occur during the fabrication of semiconductor structures. These fluctuations can easily have an adverse effect on the performance of the final semiconductor structure. Especially in some semiconductor structures with strict requirements on the shape and outline of the structure, dimensional fluctuations can lead to significant differences in electrical performance, making the semiconductor structure unable to meet normal application requirements.

[0003] Therefore, there is an urgent need to develop a structure that allows workers to obtain information about the dimensional changes of semiconductor structures during fabrication. Summary of the Invention

[0004] This disclosure provides a method for measuring semiconductor structures, including:

[0005] A semiconductor structure is provided, the semiconductor structure including a first region and a second region; a first test structure and a second test structure are respectively disposed on both sides of the first region, and a second test structure and a third test structure are respectively disposed on both sides of the second region; the first region has a first design width W1, and the second region has a second design width W2; wherein the first design width W1 and the second design width W2 are different;

[0006] Calculate the first electrical parameter R1 of the first region and the second electrical parameter R2 of the second region;

[0007] Based on R1, R2, W1, and W2, a first deviation Δx is determined between the actual width of the second region and the second design width W2.

[0008] In the above scheme, determining the first deviation Δx between the actual width of the second region and the second designed width W2 based on R1, R2, W1, and W2 includes:

[0009] Substituting the values ​​of R1, R2, W1, and W2 into the following relation (1), the first deviation Δx is calculated:

[0010]

[0011] In the above scheme, the calculation of the first electrical parameter R1 of the first region and the second electrical parameter R2 of the second region includes:

[0012] Measure the resistance r1 of the portion of the first region located between the first test structure and the second test structure, and the resistance r2 of the portion of the second region located between the second test structure and the third test structure;

[0013] According to the formula and The first electrical parameter R1 and the second electrical parameter R2 are calculated respectively; wherein, L1 is the distance between the first test structure and the second test structure, and L2 is the distance between the second test structure and the third test structure.

[0014] In the above scheme, the semiconductor structure further includes: a third region and a fourth test structure. The third region is located between the first region and the second region. The first region is provided with a first test structure and a second test structure on both sides. The third region is provided with a second test structure and a fourth test structure on both sides. The second region is provided with a fourth test structure and a third test structure on both sides. The third region has a third design width W3.

[0015] The method further includes:

[0016] Calculate the third electrical parameter R3 of the third region;

[0017] Based on R1, R3, W1, and W3, determine the second deviation Δx' between the actual width of the third region and the third design width W3.

[0018] The above scheme, the method further includes: according to the formula The first etch offset rate t1 of the second region is calculated;

[0019] According to the formula The second etch offset rate t2 of the third region is calculated;

[0020] Determine whether the first etching offset rate t1, the second etching offset rate t2, and the difference Δt between the first etching offset rate t1 and the second etching offset rate t2 meet the process requirements.

[0021] In the above scheme, determining the second deviation Δx' between the actual width of the third region and the third designed width W3 based on R1, R3, W1, and W3 includes:

[0022] Substituting the values ​​of R1, R3, W1, and W3 into the following equation (2), the second deviation Δx' is calculated:

[0023]

[0024] In the above scheme, the calculation of the third electrical parameter R3 of the third region includes:

[0025] Measure the resistance r3 of the portion of the third region located between the second test structure and the fourth test structure;

[0026] According to the formula The third electrical parameter R3 is calculated; where L3 is the distance between the second test structure and the fourth test structure.

[0027] In the above scheme, the semiconductor structure further includes a fifth test structure and a sixth test structure. The fifth test structure is located on the side of the first region away from the second region, and the sixth test structure is located on the side of the second region away from the first region.

[0028] In the above scheme, measuring the resistance r1 of the portion of the first region located between the first test structure and the second test structure, and the resistance r2 of the portion of the second region located between the second test structure and the third test structure, includes:

[0029] A current I is passed into the first region and the second region;

[0030] Measure the first voltage U1 between the first test structure and the second test structure, and the second voltage U2 between the second test structure and the third test structure.

[0031] According to the formula and formula The resistances r1 and r2 are calculated separately.

[0032] This disclosure also provides a semiconductor structure, including:

[0033] First and Second Zones;

[0034] A first test structure and a second test structure are respectively provided on both sides of the first region, and a second test structure and a third test structure are respectively provided on both sides of the second region; the first region has a first design width W1, and the second region has a second design width W2; wherein...

[0035] The first design width W1 is different from the second design width W2.

[0036] In the above scheme, the first region and the second region extend along a straight line.

[0037] In the above scheme, the semiconductor structure further includes: a third region and a fourth test structure. The third region is located between the first region and the second region. The first region is provided with a first test structure and a second test structure on both sides. The third region is provided with a second test structure and a fourth test structure on both sides. The second region is provided with a fourth test structure and a third test structure on both sides.

[0038] In the above scheme, the semiconductor structure further includes:

[0039] The fifth test structure and the sixth test structure are provided, wherein the fifth test structure is located on the side of the first region away from the second region, and the sixth test structure is located on the side of the second region away from the first region.

[0040] In the above scheme, in any of the above semiconductor structures, the semiconductor structure includes a core region and an edge region; the first region is located on the core region, and the second region is located on the edge region.

[0041] This disclosure also provides a measurement device for performing the measurement method in any of the above schemes.

[0042] In the above scheme, the measuring device includes:

[0043] The system includes a measurement unit, a data input unit, and a calculation unit. The measurement unit is used to measure the resistance in different regions of the semiconductor structure. The data input unit is used to input the design width of different regions in the semiconductor structure.

[0044] The calculation unit is used to calculate the deviation between the actual width and the design width of different regions based on the resistance value measured by the measurement unit and the design width of different regions input.

[0045] The semiconductor structure measurement method, semiconductor structure, and measurement equipment provided in this disclosure include the following measurement method: providing a semiconductor structure, the semiconductor structure including a first region and a second region; a first test structure and a second test structure are respectively disposed on both sides of the first region, and a second test structure and a third test structure are respectively disposed on both sides of the second region; the first region has a first design width W1, and the second region has a second design width W2; wherein the first design width W1 and the second design width W2 are different; calculating a first electrical parameter R1 of the first region and a second electrical parameter R2 of the second region; and determining a first deviation Δx between the actual width of the second region and the second design width W2 based on R1, R2, W1, and W2. Thus, based on the provided semiconductor structure, by first calculating the electrical parameter R1 of the first region and the electrical parameter R2 of the second region, and then combining the design width W1 of the first region and the design width W2 of the second region, the deviation value between the actual width of the second region and the design width of the second region can be obtained. This deviation value can reflect the change between the designed size of the semiconductor structure and the actual size after the process. The measurement method provided in this disclosure has the advantages of being simple to operate and easy to implement, and can help staff obtain the dimensional fluctuations of semiconductor structures during the fabrication process in a simple and effective manner.

[0046] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A flowchart illustrating a method for measuring semiconductor structures provided in an embodiment of this disclosure;

[0049] Figure 2 A schematic diagram of one embodiment of the semiconductor structure provided in this disclosure;

[0050] Figure 3 A schematic diagram of another embodiment of the semiconductor structure provided in this disclosure;

[0051] Figure 4 A schematic diagram of another embodiment of the semiconductor structure provided in this disclosure;

[0052] Figure 5 This is a schematic diagram of the composition of the measuring device provided in the embodiments of this disclosure. Detailed Implementation

[0053] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0054] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0055] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0056] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0057] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0059] After completing the product design phase, the production phase usually begins. To meet the electrical and other performance requirements of the final product, it is necessary to monitor the dimensional fluctuations during production and keep them within an acceptable range as much as possible.

[0060] Currently, the number of structures with measurement bias is relatively small, and the measurement methods used are quite complex, making it difficult to obtain measurement results with high accuracy in a convenient and effective manner.

[0061] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0062] This disclosure provides a method for measuring semiconductor structures, such as... Figure 1 The method includes the following steps:

[0063] Step S101: Provide a semiconductor structure, the semiconductor structure including a first region and a second region; a first test structure and a second test structure are respectively disposed on both sides of the first region, and a second test structure and a third test structure are respectively disposed on both sides of the second region; the first region has a first design width W1, and the second region has a second design width W2; wherein, the first design width W1 and the second design width W2 are different;

[0064] Step S102: Calculate the first electrical parameter R1 of the first region and the second electrical parameter R2 of the second region;

[0065] Step S103: Determine the first deviation Δx between the actual width of the second region and the second design width W2 based on R1, R2, W1 and W2.

[0066] In this embodiment, based on the provided semiconductor structure, the electrical parameters R1 of the first region and R2 of the second region are first calculated. Then, combined with the designed width W1 of the first region and the designed width W2 of the second region, the deviation between the actual width of the second region and the designed width of the second region can be obtained. This deviation reflects the change between the designed dimensions of the semiconductor structure and the actual dimensions after the manufacturing process. The measurement method provided in this embodiment has the advantages of being simple to operate and easy to implement, and can assist workers in easily and effectively obtaining the dimensional fluctuations of the semiconductor structure during the fabrication process.

[0067] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged off-scale for ease of explanation, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0068] Figure 1 A flowchart illustrating a method for measuring semiconductor structures provided in an embodiment of this disclosure; Figure 2 A schematic diagram of one embodiment of the semiconductor structure provided in this disclosure; Figure 3 A schematic diagram of another embodiment of the semiconductor structure provided in this disclosure; Figure 4 This is a schematic diagram of another embodiment of the semiconductor structure provided in this disclosure.

[0069] The following is combined with Figure 1 , Figure 2 , Figure 3 and Figure 4 The method for measuring semiconductor structures provided in the embodiments of this disclosure will be described in further detail.

[0070] First, execute step S101, as follows: Figure 2 As shown, a semiconductor structure is provided, the semiconductor structure including a first region 11 and a second region 12; a first test structure 21 and a second test structure 22 are respectively disposed on both sides of the first region 11, and a second test structure 22 and a third test structure 23 are respectively disposed on both sides of the second region 12; the first region 11 has a first design width W1, and the second region 12 has a second design width W2; wherein, the first design width W1 and the second design width W2 are different.

[0071] In this embodiment of the disclosure, the first region and the second region share the same second test structure near their boundary, which can effectively simplify the semiconductor structure used for measurement purposes and help staff obtain measurement results more conveniently and in a timely manner.

[0072] In some embodiments, the first region 11 and the second region 12 extend along a straight line. It is understood that when the resistor being measured contains a bent structure, the current tends to take the shortest path when flowing through the bent portion of the resistor structure, effectively reducing the cross-sectional area of ​​that portion of the resistor structure. This results in an overestimation of the measured resistance value and low accuracy of the measurement result. Furthermore, calculating the deviation value based on this partial result will further deviate from the final result, failing to objectively reflect the actual deviation between the design dimensions and the actual dimensions.

[0073] Therefore, compared with traditional structures, the linear design method of the semiconductor structure provided in this disclosure can help staff obtain more accurate measurement results.

[0074] Next, step S102 is executed to measure the first electrical parameter R1 of the first region 11 and the second electrical parameter R2 of the second region 12.

[0075] Continue to refer to Figure 2 In some embodiments, measuring the first electrical parameter R1 of the first region 11 and the second electrical parameter R2 of the second region 12 includes:

[0076] Measure the resistance r1 of the portion of the first region 11 located between the first test structure 21 and the second test structure 22, and the resistance r2 of the portion of the second region 12 located between the second test structure 22 and the third test structure 23;

[0077] According to the formula and The first electrical parameter R1 and the second electrical parameter R2 are calculated respectively; wherein, L1 is the distance between the first test structure 21 and the second test structure 22, and L2 is the distance between the second test structure 22 and the third test structure 23.

[0078] In this embodiment of the disclosure, the width direction of each region is perpendicular to the length direction of each region.

[0079] In actual operation, measuring the resistance r1 of the portion of the first region 11 located between the first test structure 21 and the second test structure 22, and the resistance r2 of the portion of the second region 12 located between the second test structure 22 and the third test structure 23, includes:

[0080] A current I is passed through the first region 11 and the second region 12;

[0081] Measure the first voltage U1 between the first test structure 21 and the second test structure 22, and the second voltage U2 between the second test structure 22 and the third test structure 23.

[0082] According to the formula and formula Resistances r1 and r2 are calculated respectively. In some embodiments, when current is passed into the first region 11 and the second region 12, the magnitude of the current I can be set to 200 μA. However, it is not limited to this; the magnitude of the current I can also be 50 μA, 80 μA, 100 μA, 120 μA, 150 μA, or 180 μA, etc. In actual operation, the current I can also be other values.

[0083] Thus, the first electrical parameter R1 of the first region 11 and the electrical parameter R2 of the second region 12 can be obtained by calculation through the above actual operation steps.

[0084] Finally, step S103 is executed to determine the first deviation Δx between the actual width of the second region and the second design width W2 based on R1, R2, W1, and W2.

[0085] First, within the theoretical framework, the relationship between Δx, R1, R2, W1, and W2 is derived:

[0086] The resistance formula Substitute them into the formula respectively and formula The following relationships were obtained:

[0087]

[0088]

[0089] Where ρ is the resistivity of the material in the first region and the second region, and t is the thickness of the material. Since the first region and the second region are formed through the same process steps, the resistivity and thickness of the material in the first region and the second region are the same.

[0090] Next, by combining relation (3) and relation (4) into a simultaneous equation, the following formula (1) can be obtained through calculation:

[0091]

[0092] In some embodiments, determining a first deviation Δx between the actual width of the second region 12 and the second designed width W2 based on R1, R2, W1, and W2 includes:

[0093] Substituting the values ​​of R1, R2, W1, and W2 into the following relation (1), the first deviation Δx is calculated:

[0094]

[0095] In other embodiments, such as Figure 3 As shown, the semiconductor structure further includes a third region 13 and a fourth test structure 24. The third region 13 is located between the first region 11 and the second region 12. The first region 11 has a first test structure 21 and a second test structure 22 on both sides. The third region 13 has a second test structure 22 and a fourth test structure 24 on both sides. The second region 12 has a fourth test structure 24 and a third test structure 23 on both sides. The third region 13 has a third design width W3.

[0096] The method further includes:

[0097] Calculate the third electrical parameter R3 of the third region 13;

[0098] Based on R1, R3, W1, and W3, determine the second deviation Δx' between the actual width of the third region 13 and the third design width W3.

[0099] In actual manufacturing processes, the third region may have a different width from the first and second regions. In some embodiments, the width of the first region is greater than the widths of the second and third regions, and the width of the third region is greater than the width of the second region.

[0100] In some embodiments, measuring the third electrical parameter R3 of the third region 13 includes:

[0101] Measure the resistance r3 of the portion of the third region 13 located between the second test structure 22 and the fourth test structure 24;

[0102] According to the formula The third electrical parameter R3 is calculated; where L3 is the distance between the second test structure 22 and the fourth test structure 24.

[0103] like Figure 4 As shown, in some other embodiments, the semiconductor structure further includes a fifth test structure 25 and a sixth test structure 26, wherein the fifth test structure 25 is located on the side of the first region 11 away from the second region 12, and the sixth test structure 26 is located on the side of the second region 12 away from the first region 11.

[0104] In actual operation, measuring the resistance r3 of the portion of the third region 13 located between the second test structure 22 and the fourth test structure 24 includes:

[0105] A current I is passed into the third region 13 through the fifth test structure 25 and the sixth test structure 26;

[0106] Measure the third voltage U3 between the second test structure 22 and the fourth test structure 24;

[0107] According to the formula The resistance r3 is calculated.

[0108] In this embodiment, by setting the fifth test structure on the side of the first region away from the second region and the sixth test structure on the side of the second region away from the first region, the semiconductor structure can be subjected to measurement operations using the four-probe method. Compared with the two-probe method used in traditional structures, the test results obtained by the four-probe method are more accurate, mainly because the influence of the resistance of the probe card on the test results can be ignored when using the four-probe method.

[0109] In some embodiments, when current is applied to the third region 13 through the fifth test structure 25 and the sixth test structure 26, the magnitude of the current I can be set to 200 μA. However, it is not limited to this; the magnitude of the current I can also be 50 μA, 80 μA, 100 μA, 120 μA, 150 μA, or 180 μA, etc. In actual operation, the current I can also be other values.

[0110] Understandably, in actual operation, the method for determining the second deviation △x' between the actual width of the third region and the designed width W3 of the third region is basically the same as the method for determining the first deviation △x of the second region, and will not be elaborated here.

[0111] The following formula (2) can be obtained through derivation:

[0112]

[0113] In some embodiments, determining a second deviation Δx' between the actual width of the third region and the third designed width W3 based on R1, R3, W1, and W3 includes:

[0114] Substituting the values ​​of R1, R3, W1, and W3 into the following equation (2), the second deviation Δx' is calculated:

[0115]

[0116] In practice, the first region can have a large design width, ensuring that it exhibits little or no dimensional fluctuation after the manufacturing process. To a certain extent, it can serve as a reference point to ultimately determine the deviation between the second and third regions.

[0117] It should be noted that the measurement method for deviation value or offset rate mentioned in the embodiments of this disclosure can be applied to the solution and calculation of the deviation value or dimensional offset rate between the design value and the actual value of the semiconductor structure after any possible changes in the process. For example, in some practical operations, the measurement method for deviation value or offset rate can be applied to the calculation of dimensional deviation and offset rate of the semiconductor structure after undergoing photolithography and etching processes.

[0118] Specifically, in some embodiments, the method further includes: according to the formula The first etch offset rate t1 of the second region 12 is calculated;

[0119] According to the formula The second etch offset rate t2 of the third region 13 is calculated;

[0120] Determine whether the first etching offset rate t1, the second etching offset rate t2, and the difference Δt between the first etching offset rate t1 and the second etching offset rate t2 meet the process requirements.

[0121] The measurement method provided in this disclosure has the advantages of being simple to operate and easy to implement, and can effectively assist staff in obtaining the dimensional fluctuations of semiconductor structures during the fabrication process.

[0122] It should be noted that although only three regions are provided as the structures to be measured in this embodiment, the number of regions can be four, five or other in actual operation. The specific situation can be flexibly adjusted and is not limited here.

[0123] This disclosure also provides a semiconductor structure, such as... Figure 2 As shown, it includes:

[0124] First area 11 and second area 12;

[0125] A first test structure 21 and a second test structure 22 are respectively provided on both sides of the first region 11, and a second test structure 22 and a third test structure 23 are respectively provided on both sides of the second region 12; the first region 11 has a first design width W1, and the second region 12 has a second design width W2;

[0126] in,

[0127] The first design width W1 is different from the second design width W2.

[0128] In this embodiment of the disclosure, the first region and the second region share the same second test structure near their boundary, which can effectively simplify the semiconductor structure used for measurement purposes and help staff obtain measurement results more conveniently and in a timely manner.

[0129] In some embodiments, the first region 11 and the second region 12 extend along a straight line. It is understood that when the resistor being measured contains a bent structure, the current tends to take the shortest path when flowing through the bent portion of the resistor structure, effectively reducing the cross-sectional area of ​​that portion of the resistor structure. This results in an overestimation of the measured resistance value and low accuracy of the measurement result. Furthermore, calculating the deviation value based on this partial result will further deviate from the final result, failing to objectively reflect the actual deviation between the design dimensions and the actual dimensions.

[0130] Therefore, compared with traditional structures, the linear design method of the semiconductor structure provided in this disclosure can help staff obtain more accurate measurement results.

[0131] In other embodiments, such as Figure 3As shown, the semiconductor structure further includes a third region 13 and a fourth test structure 24. The third region 13 is located between the first region 11 and the second region 12. A first test structure 21 and a second test structure 22 are respectively provided on both sides of the first region 11. A second test structure 22 and a fourth test structure 24 are respectively provided on both sides of the third region 13. A fourth test structure 24 and a third test structure 23 are respectively provided on both sides of the second region 12.

[0132] In actual manufacturing processes, the third region may have a different width from the first and second regions. In some embodiments, the width of the first region is greater than the widths of the second and third regions, and the width of the third region is greater than the width of the second region.

[0133] In practice, the first region can have a large design width, ensuring that it exhibits little or no dimensional fluctuation after the manufacturing process. To a certain extent, it can serve as a reference point to ultimately determine the deviation between the second and third regions.

[0134] It should be noted that although only three regions are provided as the structures to be measured in this embodiment, the number of regions can be four, five or other in actual operation. The specific situation can be flexibly adjusted and is not limited here.

[0135] like Figure 4 As shown, in some other embodiments, the semiconductor structure further includes:

[0136] The fifth test structure 25 and the sixth test structure 26 are located on the side of the first region 11 away from the second region 12, and the sixth test structure 26 is located on the side of the second region 12 away from the first region 11.

[0137] Here, the fifth test structure 25 and the sixth test structure 26 are configured to pass current into the first region 11, the second region 12 and the third region 13 in the semiconductor structure.

[0138] In this embodiment, by setting the fifth test structure on the side of the first region away from the second region and the sixth test structure on the side of the second region away from the first region, the semiconductor structure can be subjected to measurement operations using the four-probe method when measurement is required. Compared with the two-probe method used in traditional structures, the test results obtained by the four-probe method are more accurate, mainly because the influence of the resistance of the probe card on the test results can be ignored when using the four-probe method.

[0139] In some embodiments, in any of the above-described semiconductor structures, the semiconductor structure includes: a core region 31 and an edge region 32; the first region 11 is located on the core region 31, and the second region 12 is located on the edge region 32.

[0140] Figure 5 This is a schematic diagram illustrating the composition of the measuring device provided in an embodiment of this disclosure. Figure 5 As shown, this embodiment of the present disclosure also provides a measurement device 4, which is used to perform measurement operations on the semiconductor structure described in any of the above methods.

[0141] In some specific embodiments, the measuring device 4 includes:

[0142] The system includes a measurement unit, a data input unit, and a calculation unit. The measurement unit is used to measure the resistance in different regions of the semiconductor structure. The data input unit is used to input the design width of different regions in the semiconductor structure.

[0143] The calculation unit is used to calculate the deviation between the actual width and the design width of different regions based on the resistance value measured by the measurement unit and the design width of different regions input.

[0144] In summary, in this embodiment of the present disclosure, based on the provided semiconductor structure, after calculating the electrical parameters R1 of the first region and R2 of the second region, and combining the design width W1 of the first region and the design width W2 of the second region, the deviation value information between the actual width of the second region and the design width of the second region can be obtained. This deviation value can reflect the change between the design size of the semiconductor structure and the actual size after the process, specifically, the size deviation value generated after photolithography and etching processes.

[0145] Furthermore, the embodiments of this disclosure can also calculate the dimensional offset rate based on the deviation value, which can assist in determining whether process parameters need to be adjusted during the manufacturing process. If multiple areas need to be judged, adjustments can be made based on this disclosure to obtain the dimensional change information.

[0146] Furthermore, in this embodiment, the semiconductor structure adopts a linear design, which can help staff obtain more accurate measurement results.

[0147] The measurement method provided in this disclosure has the advantages of being simple to operate and easy to implement, and can help staff obtain the dimensional fluctuations of semiconductor structures during the fabrication process in a simple and effective manner.

[0148] It should be noted that the semiconductor structure measurement method provided in this disclosure can be applied to any semiconductor structure that requires measurement of dimensional deviations, and is not limited thereto. The embodiments of the semiconductor structure measurement method, the semiconductor structure, and the measurement equipment provided in this disclosure belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0149] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for measuring semiconductor structures, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a first region and a second region; a first test structure and a second test structure are respectively disposed on both sides of the first region, and a second test structure and a third test structure are respectively disposed on both sides of the second region; the first region has a first design width W1, and the second region has a second design width W2; wherein the first design width W1 and the second design width W2 are different; Calculate the first electrical parameter R1 of the first region and the second electrical parameter R2 of the second region; Based on R1, R2, W1, and W2, a first deviation Δx is determined between the actual width of the second region and the second design width W2.

2. The measurement method according to claim 1, characterized in that, Based on R1, R2, W1, and W2, the first deviation Δx between the actual width of the second region and the second designed width W2 is determined, including: Substituting the values ​​of R1, R2, W1, and W2 into the following relation (1), the first deviation Δx is calculated: （1）。 3. The measurement method according to claim 1, characterized in that, Calculating the first electrical parameter R1 of the first region and the second electrical parameter R2 of the second region includes: Measure the resistance r1 of the portion of the first region located between the first test structure and the second test structure, and the resistance r2 of the portion of the second region located between the second test structure and the third test structure; According to the formula and The first electrical parameter R1 and the second electrical parameter R2 are calculated respectively; wherein, L1 is the distance between the first test structure and the second test structure, and L2 is the distance between the second test structure and the third test structure.

4. The measurement method according to claim 1, characterized in that, The semiconductor structure further includes: a third region and a fourth test structure. The third region is located between the first region and the second region. The first region has a first test structure and a second test structure respectively on both sides. The third region has a second test structure and a fourth test structure respectively on both sides. The second region has a fourth test structure and a third test structure respectively on both sides. The third region has a third design width W3. The method further includes: Calculate the third electrical parameter R3 of the third region; Based on R1, R3, W1, and W3, determine the second deviation Δx' between the actual width of the third region and the third design width W3.

5. The measurement method according to claim 4, characterized in that, The method further includes: according to the formula The first etch offset rate t1 of the second region is calculated. According to the formula The second etch offset rate t2 of the third region is calculated. Determine whether the first etching offset rate t1, the second etching offset rate t2, and the difference Δt between the first etching offset rate t1 and the second etching offset rate t2 meet the process requirements.

6. The measurement method according to claim 4, characterized in that, Based on R1, R3, W1, and W3, the second deviation Δx' between the actual width of the third region and the third designed width W3 is determined, including: Substituting the values ​​of R1, R3, W1, and W3 into the following relation (2), the second deviation Δx' is calculated: （2）。 7. The measurement method according to claim 6, characterized in that, The calculation of the third electrical parameter R3 of the third region includes: Measure the resistance r3 of the portion of the third region located between the second test structure and the fourth test structure; According to the formula The third electrical parameter R3 is calculated; where L3 is the distance between the second test structure and the fourth test structure.

8. The measurement method according to claim 4, characterized in that, The semiconductor structure further includes a fifth test structure and a sixth test structure, wherein the fifth test structure is located on the side of the first region away from the second region, and the sixth test structure is located on the side of the second region away from the first region.

9. The measurement method according to claim 3, characterized in that, Measuring the resistance r1 of the portion of the first region located between the first test structure and the second test structure, and the resistance r2 of the portion of the second region located between the second test structure and the third test structure, includes: A current I is passed into the first region and the second region; Measure the first voltage U1 between the first test structure and the second test structure, and the second voltage U2 between the second test structure and the third test structure. According to the formula and formula The resistors r1 and r2 are calculated respectively.

10. A semiconductor structure, wherein the semiconductor structure performs the measurement method as described in any one of claims 1-9, characterized in that, include: First and Second Zones; A first test structure and a second test structure are respectively provided on both sides of the first region, and a second test structure and a third test structure are respectively provided on both sides of the second region; the first region has a first design width W1, and the second region has a second design width W2; wherein... The first design width W1 is different from the second design width W2.

11. The structure according to claim 10, characterized in that, The first region and the second region extend along a straight line.

12. The structure according to claim 11, characterized in that, The semiconductor structure further includes a third region and a fourth test structure. The third region is located between the first region and the second region. The first region has a first test structure and a second test structure on its two sides, the third region has a second test structure and a fourth test structure on its two sides, and the second region has a fourth test structure and a third test structure on its two sides.

13. The structure according to claim 12, characterized in that, The semiconductor structure also includes: The fifth test structure and the sixth test structure are provided, wherein the fifth test structure is located on the side of the first region away from the second region, and the sixth test structure is located on the side of the second region away from the first region.

14. The structure according to any one of claims 10-13, characterized in that, The semiconductor structure includes a core region and an edge region; the first region is located on the core region, and the second region is located on the edge region.

15. A measuring device, characterized in that, Used to perform the measurement method as described in any one of claims 1-9.

16. The measuring device according to claim 15, characterized in that, The measuring device includes: The system includes a measurement unit, a data input unit, and a calculation unit. The measurement unit is used to measure the resistance in different regions of the semiconductor structure. The data input unit is used to input the design width of different regions in the semiconductor structure. The calculation unit is used to calculate the deviation between the actual width and the design width of different regions based on the resistance value measured by the measurement unit and the design width of different regions input.

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