A multi-functional shielded gate trench power device and a manufacturing method thereof

Abstract

The application provides a multifunctional shield gate trench power device and a manufacturing method thereof. The device has an adjusting pad, a gate pad and a source pad, and has an adjusting gate polysilicon, a gate polysilicon and a shield gate polysilicon in the device trench. The adjusting gate polysilicon is above the shield gate polysilicon. The gate polysilicon includes a middle part and side wing parts. The middle part is above the adjusting gate polysilicon. The side wing parts are on both sides of the adjusting gate polysilicon and are connected with the middle part. The adjusting pad, the gate pad and the source pad are electrically connected with the adjusting gate polysilicon, the gate polysilicon and the shield gate polysilicon respectively. The application can realize devices with different performances through different wire bonding modes. When the potential of the adjusting pad is floating, the gate-source capacitance of the device is small, which is suitable for high frequency application. When the adjusting pad and the gate pad are shorted through wire bonding, the gate-source capacitance of the device is medium, and the performance of the device is balanced. When the adjusting pad and the source pad are shorted through wire bonding, the gate-source capacitance of the device is large.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a multifunctional shielded gate trench power device and its fabrication method. Background Technology

[0002] Power devices are a class of devices used in power management, power transmission, and high-speed switching control. Unlike ordinary low-frequency signal amplification devices, power devices are primarily used for operation at higher voltages and currents.

[0003] Based on their operating principles, power devices can be classified into several types, including junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), and thyristors (SCRs). According to their current and voltage handling capabilities, they can be divided into three categories: small-signal power devices, medium-power devices, and high-power devices.

[0004] Power devices can stably regulate the input and output of electrical energy, providing efficient power management for various electrical equipment. In electrical control systems, power devices can perform various operations such as switching on / off, regulating voltage, controlling transformer current, and driving electromechanical equipment. Furthermore, on solar panels, power devices can adjust the output power under different lighting conditions, improving the efficiency of solar energy utilization.

[0005] In MOSFET power devices, trench MOSFETs are mainly used in low-voltage (e.g., 100V) applications, shielded gate trench (SGT) MOSFETs are mainly used in medium-low voltage (e.g., 200V) applications, and superjunction MOSFETs (SJ-MOSFETs) are mainly used in high-voltage (e.g., 600V-800V) applications.

[0006] Among them, the shielded-gate trench MOSFET power device is an improved trench power MOSFET based on the traditional trench MOSFET. Based on charge balance technology, it adds an additional polysilicon field plate to the traditional trench MOSFET for electric field modulation, thereby improving voltage withstand and reducing on-resistance. It features low on-resistance, low switching loss, and good frequency characteristics. Its shielded gate acts as a body field plate in the drift region, giving the shielded-gate trench MOSFET significant advantages in specific on-resistance R_(ON(SP)) and quality factor (FOM = Ron * Qg), effectively improving the system's energy efficiency. Therefore, the shielded-gate trench MOSFET is used as a switching device in motor drive systems, inverter systems, and power management systems in fields such as new energy electric vehicles, new photovoltaic power generation, and energy-saving home appliances, and is a core power control component.

[0007] In shielded trench MOSFETs, the upper gate polysilicon layer is connected to the gate, and the lower shielded gate polysilicon layer is connected to the source. The gate-source capacitance is typically fixed, resulting in a relatively simple device function. How to provide a multifunctional shielded trench power device with adjustable gate-source capacitance and its fabrication method, enabling the device to possess different performance characteristics and achieve multifunctional applications, has become an important technical problem urgently needing to be solved by those skilled in the art.

[0008] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a multifunctional shielded trench power device and its manufacturing method, so as to solve the problem that the existing power devices have relatively limited functions.

[0010] To achieve the above and other related objectives, the present invention provides a multifunctional shielded trench power device, comprising:

[0011] Semiconductor layer;

[0012] Multiple trenches are located in the semiconductor layer and are spaced apart in the horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward;

[0013] A shielding gate polysilicon, a regulating gate polysilicon, and a gate polysilicon are located in the trench. The regulating gate polysilicon is located above the shielding gate polysilicon and is spaced apart from it. The gate polysilicon includes a middle portion and side wing portions. The middle portion is located above the regulating gate polysilicon and is spaced apart from it. The side wing portions are located on both sides of the regulating gate polysilicon and are connected to the middle portion.

[0014] The system comprises a first isolation layer, a second isolation layer, a third isolation layer, and a gate dielectric layer. The first isolation layer is located between the inner wall of the trench and the outer wall of the shielding gate polysilicon. The second isolation layer is located between the shielding gate polysilicon and the regulating gate polysilicon. The third isolation layer is located between the regulating gate polysilicon and the gate polysilicon. The gate dielectric layer is located between the inner wall of the trench and the outer wall of the gate polysilicon.

[0015] An adjustment metal line, a gate metal line, and a source metal line are located above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, and the source metal line is electrically connected to the shielding gate polysilicon.

[0016] An adjustment pad, a gate pad, and a source pad are located above the semiconductor layer. The adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

[0017] Optionally, the plurality of trenches are spaced apart in a first horizontal direction and all extend in a second horizontal direction perpendicular to the first horizontal direction. The shielded gate trench power device further includes a first polysilicon lead-out portion and a second polysilicon lead-out portion located in the trench. The first polysilicon lead-out portion is located at both ends of the shielded gate polysilicon in the second horizontal direction and is connected to the shielded gate polysilicon. The second polysilicon lead-out portion is located at both ends of the regulating gate polysilicon in the second horizontal direction and is connected to the regulating gate polysilicon. The top surface of the first polysilicon lead-out portion is higher than the top surface of the shielded gate polysilicon, and the top surface of the second polysilicon lead-out portion is higher than the top surface of the regulating gate polysilicon.

[0018] Optionally, the shielded gate trench power device further includes a first contact hole disposed on the first polysilicon lead-out portion, a second contact hole disposed on the second polysilicon lead-out portion, and a third contact hole disposed on the gate polysilicon. The source metal line is electrically connected to the shielded gate polysilicon through the first contact hole and the first polysilicon lead-out portion, the regulating metal line is electrically connected to the regulating gate polysilicon through the second contact hole and the second polysilicon lead-out portion, and the gate metal line is electrically connected to the gate polysilicon through the third contact hole.

[0019] Optionally, the shielded trench power device further includes a body region, a source region, and a fourth contact hole. The body region is located on the upper surface of the semiconductor layer on both sides of the trench, the source region is located on the upper surface of the body region, the fourth contact hole is located on the source region, and the source pad is electrically connected to the source region through the fourth contact hole.

[0020] Optionally, the potential of the adjustment pad is floating; or the adjustment pad is electrically connected to the gate pad; or the adjustment pad is electrically connected to the source pad.

[0021] This invention also provides a method for manufacturing a multifunctional shielded trench power device, comprising the following steps:

[0022] A semiconductor layer is provided, in which a plurality of trenches are formed at intervals in a horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward therefrom;

[0023] A first isolation layer and a shielding gate polysilicon are formed in the trench, and the inner wall of the trench and the shielding gate polysilicon are separated by the first isolation layer;

[0024] A second isolation layer is formed in the trench, the second isolation layer covering the upper surface of the shielding gate polysilicon;

[0025] A regulating gate polysilicon is formed in the trench, the regulating gate polysilicon being located above the shielding gate polysilicon and separated from the shielding gate polysilicon by the second isolation layer;

[0026] A third isolation layer, a gate dielectric layer, and a gate polysilicon are formed in the trench. The gate polysilicon includes a central portion and side portions. The central portion is located above the adjustment gate polysilicon, and the side portions are located on both sides of the adjustment gate polysilicon and connected to the central portion. The gate polysilicon and the adjustment gate polysilicon are separated by the third isolation layer, and the gate polysilicon and the inner wall of the trench are separated by the gate dielectric layer.

[0027] An adjustment metal line, a gate metal line, a source metal line, an adjustment pad, a gate pad, and a source pad are formed above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, the source metal line is electrically connected to the shield gate polysilicon, the adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

[0028] Optionally, the plurality of said trenches are spaced apart in a first horizontal direction and all extend in a second horizontal direction perpendicular to the first horizontal direction. The method for manufacturing the multifunctional shielded gate trench type power device further includes the following steps:

[0029] A first polysilicon lead-out portion is formed at both ends of the shielding gate polysilicon in a second horizontal direction. The first polysilicon lead-out portion is located in the trench and the top surface of the first polysilicon lead-out portion is higher than the top surface of the shielding gate polysilicon.

[0030] A second polysilicon lead-out portion is formed at both ends of the second horizontal direction of the regulating gate polysilicon. The second polysilicon lead-out portion is located in the trench and the top surface of the second polysilicon lead-out portion is higher than the top surface of the regulating gate polysilicon.

[0031] Optionally, the following steps are also included:

[0032] The solid regions are formed on the upper surface of the semiconductor layer on both sides of the trench;

[0033] The source region is formed on the upper surface layer of the body region;

[0034] An interlayer dielectric layer is formed above the semiconductor layer;

[0035] A first contact hole, a second contact hole, a third contact hole, and a fourth contact hole are formed in the interlayer dielectric layer. The first contact hole is located on the first polysilicon lead-out portion, the second contact hole is located on the second polysilicon lead-out portion, the third contact hole is located on the gate polysilicon, and the fourth contact hole is located on the source region.

[0036] Conductive plugs are formed in the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole;

[0037] The source metal line is electrically connected to the shielding gate polysilicon through the first contact hole and the first polysilicon lead-out portion; the adjustment metal line is electrically connected to the adjustment gate polysilicon through the second contact hole and the second polysilicon lead-out portion; the gate metal line is electrically connected to the gate polysilicon through the third contact hole; and the source pad is electrically connected to the source region through the fourth contact hole.

[0038] Optionally, the bottom surface of the side wing is lower than the top surface of the regulating gate polysilicon.

[0039] Optionally, the potential of the adjustable gate polysilicon is floating; or the method for fabricating the multifunctional shielded gate trench power device further includes the step of forming a bonding wire, one end of which is connected to the adjustable pad, and the other end of which is connected to the gate pad or the source pad.

[0040] As described above, the multifunctional shielded gate trench power device of the present invention has an adjustment pad, a gate pad, and a source pad. The device trench has an adjustment gate polysilicon, a gate polysilicon, and a shielded gate polysilicon. The adjustment gate polysilicon is located above the shielded gate polysilicon. The gate polysilicon includes a middle portion and side portions. The middle portion is located above the adjustment gate polysilicon. The side portions are located on both sides of the adjustment gate polysilicon and connected to the middle portion. The adjustment pad, the gate pad, and the source pad are electrically connected to the adjustment gate polysilicon, the gate polysilicon, and the shielded gate polysilicon, respectively. Different wire bonding methods can achieve devices with different performance characteristics. When the adjustment pad is floating, the device has a small gate-source capacitance Cgs, resulting in fast switching and making it suitable for high-frequency applications. When the adjustment pad and the gate pad are shorted together by a wire bonding, the device has a medium gate-source capacitance Cgs, resulting in balanced device performance. When the adjustment pad and the source pad are shorted together by a wire bonding, the device has a large gate-source capacitance Cgs, which can reduce switching oscillations, has strong shock resistance, and can reduce the ratio of reverse transfer capacitance to input capacitance Crss / Ciss, making it suitable for applications such as battery management systems (BMS) and motor control. Attached Figure Description

[0041] Figure 1The diagram shown is a cross-sectional view of an example of the multifunctional shielded grid trench power device of the present invention.

[0042] Figure 2 The diagram shown is a schematic planar layout of an example of the multifunctional shielded grid trench power device of the present invention.

[0043] Figure 3 The diagram shows another example planar layout structure of the multifunctional shielded gate trench power device of the present invention.

[0044] Figure 4 The diagram shown is a third example planar layout structure of the multifunctional shielded gate trench power device of the present invention.

[0045] Figure 5 The diagram shows a process flow chart of the fabrication method of the multifunctional shielded grid trench power device of the present invention.

[0046] Figure 6 The diagram shows a structural schematic after a mask layer is deposited on a semiconductor layer, which is a method for fabricating a multifunctional shielded gate trench power device according to the present invention.

[0047] Figure 7 The diagram shown is a structural schematic of the multifunctional shielded grid trench power device of the present invention after the trench is formed.

[0048] Figure 8 The diagram shows the structure after the first oxide layer and the first polysilicon layer are grown, according to the fabrication method of the multifunctional shielded gate trench power device of the present invention.

[0049] Figure 9 The diagram shows the structure of the multifunctional shielded gate trench power device of the present invention after the shielded gate polysilicon is formed.

[0050] Figure 10 The diagram shows the structure of the multifunctional shielded gate trench power device of the present invention after the second isolation layer and the regulating gate polysilicon are formed in the trench.

[0051] Figure 11 The diagram shows the structure after the third oxide layer is formed and planarized, according to the fabrication method of the multifunctional shielded gate trench power device of the present invention.

[0052] Figure 12 The diagram shows the structure after etching back the third oxide layer in the preset area and growing the fourth oxide layer, which is a fabrication method of the multifunctional shielded gate trench power device of the present invention.

[0053] Figure 13The diagram shows the structure of the multifunctional shielded gate trench power device of the present invention after the gate polysilicon is formed.

[0054] Component designation explanation

[0055] 1 Semiconductor layer

[0056] 2. Trench

[0057] 3. Shielded gate polycrystalline silicon

[0058] 4. Adjustable gate polysilicon

[0059] 5-Gate Polysilicon

[0060] 501 Middle Section

[0061] 502 Flanking Section

[0062] 6 First isolation layer

[0063] 7 Second isolation layer

[0064] 8 Third isolation layer

[0065] 9 Gate dielectric layer

[0066] 10. Adjust the metal wire

[0067] 11 Gate metal line

[0068] 12 source metal wires

[0069] 13 Adjust the pads

[0070] 14 Gate pads

[0071] 15 Source pads

[0072] 16 First Polysilicon Lead-Out Section

[0073] 17 Second polysilicon lead-out section

[0074] 18 First contact hole

[0075] 19 Second contact hole

[0076] 20 Third contact hole

[0077] 21 Fourth contact hole

[0078] Wires 22 and 23

[0079] 24 Mask layers

[0080] 25 First Oxide Layer

[0081] 26 First polycrystalline silicon layer

[0082] 27 Third Oxide Layer

[0083] 28. Fourth oxide layer

[0084] Steps S1 to S6 Detailed Implementation

[0085] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0086] Please see Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0087] Example 1

[0088] This embodiment provides a multifunctional shielded gate trench type power device. Please refer to [link / reference]. Figure 1 The diagram shows an example cross-sectional structure of this multifunctional shielded gate trench power device, including a semiconductor layer 1, trenches 2, shielded gate polysilicon 3, regulating gate polysilicon 4, and gate polysilicon 5, wherein the number of trenches 2 is multiple. Figure 1 (Only one is shown in the image). A plurality of trenches 2 are located in the semiconductor layer 1 and are spaced apart in the horizontal direction. The trenches 2 open from the top surface of the semiconductor layer 1 and extend downward. The shielding gate polysilicon 3, the regulating gate polysilicon 4 and the gate polysilicon 5 are all located in the trenches 2. The regulating gate polysilicon 4 is located above the shielding gate polysilicon 3 and is spaced apart from the shielding gate polysilicon 3. The gate polysilicon 5 includes a middle portion 501 and a side portion 502. The middle portion 501 is located above the regulating gate polysilicon 4 and is spaced apart from the regulating gate polysilicon 4. The side portions 502 are located on both sides of the regulating gate polysilicon 4 and are connected to the middle portion 501.

[0089] Specifically, the semiconductor layer 1 can be a single-layer or multi-layer structure. For example, it can be a single substrate or a stacked structure consisting of a single substrate and an epitaxial layer thereon. The material, doping type, and doping concentration of the substrate and / or epitaxial layer can be selected as needed and are not excessively limited here. For example, the substrate material can be selected from silicon, germanium silicon, III-V compound, silicon carbide, or other suitable semiconductor materials, and its doping type can be N-type or P-type. In this embodiment, the semiconductor layer 1 is an example of N-type doped silicon.

[0090] Specifically, the depth of the trench 2 can be set according to the specific device performance requirements.

[0091] Specifically, the shielded gate trench power device further includes a first isolation layer 6, a second isolation layer 7, a third isolation layer 8, and a gate dielectric layer 9 located in the trench 2. The first isolation layer 6 is located between the inner wall of the trench 2 and the outer wall of the shielded gate polysilicon 3. The second isolation layer 7 is located between the shielded gate polysilicon 3 and the regulating gate polysilicon 4. The third isolation layer 8 is located between the regulating gate polysilicon 4 and the gate polysilicon 5. The gate dielectric layer 9 is located between the inner wall of the trench 2 and the outer wall of the gate polysilicon 5.

[0092] As an example, the first isolation layer 6, the second isolation layer 7, and the third isolation layer 8 can be selected from silicon oxide or other suitable insulating materials. The first isolation layer 6 acts as a field oxide layer for electrically isolating the semiconductor layer 1 from the shielding gate polysilicon 3, the second isolation layer 7 is used to electrically isolate the shielding gate polysilicon 3 from the regulating gate polysilicon 4, and the third isolation layer 8 is used to electrically isolate the regulating gate polysilicon 4 from the gate polysilicon 5.

[0093] As an example, the gate dielectric layer 9 can be made of silicon oxide or other suitable materials, and its thickness can be set according to the specific device performance requirements.

[0094] Please see Figure 2 The diagram shows an example planar layout structure of a multifunctional shielded gate trench power device according to this embodiment, wherein a plurality of the trenches 2 are arranged in a first horizontal direction ( Figure 2 Arranged at intervals along the X-direction and all pointing towards the second horizontal direction perpendicular to the first horizontal direction. Figure 2 Extending in the Y direction.

[0095] Specifically, the multifunctional shielded gate trench power device further includes an adjustment metal line 10, a gate metal line 11, a source metal line 12 located above the semiconductor layer 1, and a drain metal layer (not shown) located on the lower surface of the semiconductor layer 1. The adjustment metal line 10 is electrically connected to the adjustment gate polysilicon 4, the gate metal line 11 is electrically connected to the gate polysilicon 5, and the source metal line 12 is electrically connected to the shielded gate polysilicon 3.

[0096] Specifically, the multifunctional shielded gate trench power device also includes an adjustment pad 13, a gate pad 14 and a source pad 15 located above the semiconductor layer 1. The adjustment pad 13 is connected to the adjustment metal line 10, the gate pad 14 is connected to the gate metal line 11, and the source pad 14 is connected to the source metal line 12.

[0097] As an example, the adjustment metal line 10, the gate metal line 11, the source metal line 12, the adjustment pad 13, the gate pad 14, and the source pad 15 can be located in the same metal layer or in different metal layers as needed. The materials of the adjustment metal line 10, the gate metal line 11, the source metal line 12, the adjustment pad 13, the gate pad 14, and the source pad 15 can be aluminum or other suitable conductive metal materials.

[0098] As an example, the multifunctional shielded gate trench power device further includes a first polysilicon lead-out portion 16 and a second polysilicon lead-out portion 17 located in the trench 2, wherein the first polysilicon lead-out portion 16 is located in the second horizontal direction of the shielded gate polysilicon 3. Figure 2 The second polysilicon lead-out portion 17 is located at both ends of the second horizontal direction of the regulating gate polysilicon 4 and is connected to the shielding gate polysilicon 3. Figure 2 (in the Y direction) and connected to the regulating gate polysilicon 4, the top surface of the first polysilicon lead-out portion 16 is higher than the top surface of the shielding gate polysilicon 3, and the top surface of the second polysilicon lead-out portion 17 is higher than the top surface of the regulating gate polysilicon 4.

[0099] As an example, the multifunctional shielded gate trench power device further includes a first contact hole 18 disposed on the first polysilicon lead-out portion 16, a second contact hole 19 disposed on the second polysilicon lead-out portion 17, and a third contact hole 20 disposed on the gate polysilicon 5. The source metal line 12 is electrically connected to the shielded gate polysilicon 3 through the first contact hole 18 and the first polysilicon lead-out portion 16. The regulating metal line 10 is electrically connected to the regulating gate polysilicon 4 through the second contact hole 19 and the second polysilicon lead-out portion 17. The gate metal line 11 is electrically connected to the gate polysilicon 5 through the third contact hole 20.

[0100] As an example, the multifunctional shielded gate trench power device further includes a body region (not shown), a source region (not shown), and a fourth contact hole 21. The body region is located on the upper surface of the semiconductor layer 1 on both sides of the trench 2, the source region is located on the upper surface of the body region, the fourth contact hole 21 is located on the source region, and the source pad 15 is electrically connected to the source region through the fourth contact hole 21.

[0101] like Figure 2 As shown, in some embodiments, the potential of the adjustment pad 13 is floating, thereby the potential of the adjustment gate polysilicon 4 connected thereto is floating. In this case, the adjustment gate polysilicon 4 acts as part of the dielectric layer between the gate polysilicon 5 and the source polysilicon (the shielding gate polysilicon 3), which is equivalent to thickening the dielectric between the gate polysilicon and the source polysilicon, resulting in a smaller device gate-source capacitance Cgs, enabling fast switching and making it suitable for high-frequency applications.

[0102] Please see Figure 3 The diagram shows another example planar layout structure of the multifunctional shielded gate trench power device of this embodiment. In this case, the regulating pad 13 and the gate pad 14 are electrically connected by bonding wire 22, which is equivalent to the regulating gate polysilicon 4 and the gate polysilicon 5 being short-circuited. In this case, the regulating gate polysilicon 4 constitutes part of the gate polysilicon. The device is similar to a device using a planar gate polysilicon, with a medium gate-source capacitance Cgs and relatively balanced device performance.

[0103] Please see Figure 4 The diagram shows a third example planar layout structure of the multifunctional shielded gate trench power device of this embodiment, wherein the adjustment pad 13 and the source pad 15 are electrically connected by a bonding wire 23 (e.g., Figure 4 As shown in the diagram, this is equivalent to the regulating gate polysilicon 4 being short-circuited with the shielding gate polysilicon 3. In this case, the regulating gate polysilicon 4 constitutes part of the source polysilicon, increasing the relative area between the source polysilicon and the gate polysilicon. This results in a larger gate-source capacitance Cgs, which can reduce switching oscillations, enhance shock resistance, and lower the ratio of reverse transfer capacitance to input capacitance Crss / Ciss. This makes it suitable for applications such as battery management systems (BMS) and motor control.

[0104] In other words, this invention can achieve devices with different performance characteristics by using different wire bonding methods.

[0105] Specifically, in the multifunctional shielded gate trench power device of this embodiment, since the gate polysilicon 5 includes a middle portion 501 located above the regulating gate polysilicon 4 and side wing portions 502 located on both sides of the regulating gate polysilicon 4 and connected to the middle portion 501, the cross-section of the gate polysilicon 5 is shaped like an inverted U, forming a wrap around the regulating gate polysilicon 4. When the regulating gate polysilicon 4 is short-circuited with the shielded gate polysilicon 3, the wrapped gate polysilicon 5 has a larger relative area with the source polysilicon (at this time, the regulating gate polysilicon 4 is part of the source polysilicon) compared to the planar gate polysilicon structure, thereby increasing the gate-source parasitic capacitance of the device.

[0106] It should be noted that the bottom surface of the side wing portion 502 of the gate polysilicon 5 is lower than the top surface of the regulating gate polysilicon 4 so that the gate polysilicon 5 forms a wrapping around the regulating gate polysilicon 4. The degree of wrapping of the regulating gate polysilicon 4 by the gate polysilicon 5 varies depending on the depth of the bottom surface of the side wing portion 502. The deeper the bottom surface of the side wing portion 502 is, the larger the gate-source parasitic capacitance of the device. In this invention, the bottom depth of the side wing portion 502 of the gate polysilicon 5 can be adjusted according to the actual situation. For example, the bottom surface of the side wing portion 502 can be flush with the bottom surface of the regulating gate polysilicon 4, higher than the bottom surface of the regulating gate polysilicon 4, or lower than the bottom surface of the regulating gate polysilicon 4. In the case where the bottom surface of the side wing portion 502 is lower than the regulating gate polysilicon 4, the gate-source parasitic capacitance of the device is larger when the regulating gate polysilicon 4 is short-circuited with the shielding gate polysilicon 3.

[0107] It should be noted that when the bottom surface of the side wing portion 502 is higher than the bottom surface of the regulating gate polysilicon 4, a portion of the first isolation layer 6 is located between the inner wall of the trench 2 and the outer wall of the regulating gate polysilicon 4.

[0108] Specifically, the thickness of the shielding gate polysilicon 3 in the vertical direction and the thickness of the regulating gate polysilicon 4 in the vertical direction can be adjusted according to application requirements. For example, the thickness of the shielding gate polysilicon 3 in the vertical direction is greater than the thickness of the regulating gate polysilicon 4 in the vertical direction.

[0109] Specifically, the thicknesses of the second isolation layer 7 and the third isolation layer 8 in the vertical direction can be adjusted according to application requirements. For example, the thickness of the second isolation layer 7 in the vertical direction can be greater than that of the third isolation layer 8. Short-circuiting the regulating gate polysilicon 4 and the gate polysilicon 5 is to obtain a device with more balanced performance, where a large gate-source capacitance is not required. Therefore, the thickness of the second isolation layer 7 does not need to be too thin (the thinner the dielectric thickness between the gate polysilicon and the source polysilicon, the larger the gate-source capacitance). Short-circuiting the regulating gate polysilicon 4 and the shielding gate polysilicon 3 is for slow-switching applications to reduce switching oscillations. Therefore, a larger gate-source capacitance is required, thus requiring a thinner third isolation layer 8. The specific thicknesses of the second isolation layer 7 and the third isolation layer 8 can be designed according to specific performance parameter requirements and are not specifically limited here.

[0110] As described above, the multifunctional shielded gate trench power device of this embodiment not only has gate pads and source pads, but also adjustment pads. The device trench not only has gate polysilicon and shielded gate polysilicon, but also adjustment gate polysilicon. By flexibly using the bonding method of the adjustment pads, devices with different performance can be realized.

[0111] Example 2

[0112] This embodiment provides a method for fabricating a multifunctional shielded trench power device. Please refer to [link / reference]. Figure 5 The diagram shows the process flow of this method, which includes the following steps:

[0113] S1: A semiconductor layer is provided, in which a plurality of trenches are formed at intervals in a horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward therefrom;

[0114] S2: A first isolation layer and a shielding gate polysilicon are formed in the trench, and the inner wall of the trench and the shielding gate polysilicon are separated by the first isolation layer;

[0115] S3: A second isolation layer is formed in the trench, the second isolation layer covering the upper surface of the shielding gate polysilicon;

[0116] S4: Forming a regulating gate polysilicon in the trench, the regulating gate polysilicon being located above the shielding gate polysilicon and separated from the shielding gate polysilicon by the second isolation layer;

[0117] S5: A third isolation layer, a gate dielectric layer, and a gate polysilicon are formed in the trench. The gate polysilicon includes a middle portion and side portions. The middle portion is located above the adjustment gate polysilicon. The side portions are located on both sides of the adjustment gate polysilicon and connected to the middle portion. The gate polysilicon and the adjustment gate polysilicon are separated by the third isolation layer. The gate polysilicon and the inner wall of the trench are separated by the gate dielectric layer.

[0118] S6: Form an adjustment metal line, a gate metal line, a source metal line, an adjustment pad, a gate pad, and a source pad above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, the source metal line is electrically connected to the shield gate polysilicon, the adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

[0119] Please refer to the following first. Figures 6-7 Perform step S1: Provide a semiconductor layer 1, and form a plurality of trenches 2 arranged at intervals in the horizontal direction in the semiconductor layer 1. The trenches 2 open from the top surface of the semiconductor layer 1 and extend downward.

[0120] As an example, the semiconductor layer 1 can be a single-layer structure or a multi-layer structure. For example, it can be a single substrate or a stacked structure consisting of a single substrate and an epitaxial layer thereon. The material, doping type, and doping concentration of the substrate and / or epitaxial layer can be selected as needed, without excessive limitations. For example, the substrate material can be selected from silicon, germanium-silicon, III-V compound semiconductors, silicon carbide, or other suitable semiconductor materials, and its doping type can be N-type or P-type. In this embodiment, the semiconductor layer 1 is exemplified by N-type doped silicon.

[0121] As an example, the plurality of said trenches 2 in the first horizontal direction (see Figure 2 Arranged at intervals along the X-direction and all pointing towards the second horizontal direction perpendicular to the first horizontal direction (see... Figure 2 Extending in the Y direction.

[0122] As an example, such as Figure 6 As shown, a mask layer 24 is first deposited on the semiconductor layer 1. The mask layer 24 can be selected from silicon oxide, silicon nitride or other suitable material layers.

[0123] like Figure 7 As shown, openings are formed in the mask layer 24 using semiconductor patterning processes such as photolithography and etching, and the semiconductor layer 1 is etched based on the mask layer 24 with openings to obtain the trench 2. The depth of the trench 2 can be set according to specific device performance requirements.

[0124] Please see again Figures 8-9 S2 is performed: a first isolation layer 6 and a shielding gate polysilicon 3 are formed in the trench 2, and the inner wall of the trench 2 and the shielding gate polysilicon 3 are separated by the first isolation layer 6.

[0125] As an example, the first isolation layer 6 can be made of silicon oxide or other suitable insulating material, wherein the first isolation layer 6 acts as a field oxide layer for electrically isolating the semiconductor layer 1 from the shielding gate polysilicon 3.

[0126] As an example, such as Figure 8 As shown, the mask layer 24 is first removed (see...) Figure 7 Then, a first oxide layer 25 is grown and a first polysilicon layer 26 is deposited. The first oxide layer 25 covers the sidewalls and bottom surface of the trench 2 and the upper surface of the semiconductor layer 1. The first polysilicon layer 26 fills the remaining space in the trench 2 and covers the upper surface of the portion of the first oxide layer 25 located outside the trench 2.

[0127] like Figure 9 As shown, the first polysilicon layer 26 is planarized until the upper surface of the first polysilicon layer 26 is flush with or approximately flush with the upper surface of the semiconductor layer 1. The first polysilicon layer 26 in the preset area is etched back using semiconductor patterning processes such as photolithography and etching to obtain the shielding gate polysilicon 3 located in the trench 2. The top surface of the shielding gate polysilicon 3 is lower than the top surface of the semiconductor layer 1.

[0128] As an example, when the first polysilicon layer 26 in the preset area is etched back using semiconductor patterning processes such as photolithography and etching, a portion of the first polysilicon layer 26 in the trench 2 is still shielded by photoresist or other mask layers and is not etched. The top surface of this un-etched portion of the first polysilicon layer 26 is still flush or approximately flush with the upper surface of the semiconductor layer 1, serving as the lead-out portion of the shielding gate polysilicon 3. Subsequently, the shielding gate polysilicon 3 is electrically connected to the source metal line through this lead-out portion and the contact hole located on the lead-out portion. In this embodiment, the first polysilicon lead-out portion 16 is formed on the shielding gate polysilicon 3 (see...). Figure 2 At both ends of the second horizontal direction (Y direction), the first polysilicon lead-out portion 16 is located in the trench 2 and the top surface of the first polysilicon lead-out portion 16 is higher than the top surface of the shielding gate polysilicon 3.

[0129] Specifically, the portion of the first oxide layer 25 located between the inner wall of the trench 2 and the shielding gate polysilicon 3 serves as at least part of the first isolation layer 6.

[0130] Please see again Figure 10Perform steps S3 and S4: form a second isolation layer 7 and an adjustment gate polysilicon 4 in the trench 2. The second isolation layer 7 covers the upper surface of the shielding gate polysilicon 3. The adjustment gate polysilicon 4 is located above the shielding gate polysilicon 3 and is separated from the shielding gate polysilicon 3 by the second isolation layer 7.

[0131] As an example, the second isolation layer 7 may be selected from silicon oxide or other suitable insulating materials, wherein the second isolation layer 7 is used to electrically isolate the shielding gate polysilicon 3 from the regulating gate polysilicon 4.

[0132] As an example, a second oxide layer is first grown on the upper surface of the shielding gate polysilicon 3 as the second isolation layer 7, then a second polysilicon layer is deposited in the trench 2 and on the upper surface of the first oxide layer 25 outside the trench 2, and then the second polysilicon layer is etched back to a preset depth to obtain the adjustment gate polysilicon 4, the adjustment gate polysilicon 4 being lower than the top surface of the semiconductor layer 1.

[0133] As an example, the thickness of the shielding gate polysilicon 3 in the vertical direction is greater than the thickness of the regulating gate polysilicon 4 in the vertical direction.

[0134] As an example, during the etching of the second polysilicon layer, photoresist or other mask layers are used to shield a portion of the second polysilicon layer in the trench 2 so that the second polysilicon layer in that region is not etched. The top surface of this unetched portion of the second polysilicon layer remains flush or substantially flush with the upper surface of the semiconductor layer 1, serving as the lead-out portion of the regulating gate polysilicon 4. Subsequently, the regulating gate polysilicon 4 is electrically connected to the required components through this lead-out portion and the contact hole located on the lead-out portion. In this embodiment, a second polysilicon lead-out portion 17 is formed (see...). Figure 2 At both ends of the second horizontal direction (Y direction) of the regulating gate polysilicon 4, the second polysilicon lead-out portion 17 is located in the trench 2 and the top surface of the second polysilicon lead-out portion 17 is higher than the top surface of the regulating gate polysilicon 4.

[0135] Please see again Figures 11-13 Step S5 is performed: a third isolation layer 8, a gate dielectric layer 9, and a gate polysilicon 5 are formed in the trench 2. The gate polysilicon 5 includes a middle portion 501 and side portions 502. The middle portion 501 is located above the regulating gate polysilicon 4 and is spaced apart from the regulating gate polysilicon 4. The side portions 502 are located on both sides of the regulating gate polysilicon 4 and are connected to the middle portion 501. The gate polysilicon 5 and the regulating gate polysilicon 4 are separated by the third isolation layer 8. The gate polysilicon 5 and the inner wall of the trench 2 are separated by the gate dielectric layer 9.

[0136] As an example, the third isolation layer 8 can be made of silicon oxide or other suitable insulating material, wherein the third isolation layer 8 is used to electrically isolate the regulating gate polysilicon 4 and the gate polysilicon 5. The gate dielectric layer 9 can be made of silicon oxide or other suitable material, and its thickness can be set according to the specific device performance requirements.

[0137] As an example, such as Figure 11 As shown, a third oxide layer 27 is first formed in the trench 2 and on the upper surface of the first oxide layer 25 outside the trench 2 using high-density plasma chemical vapor deposition (HDP CVD). Then, the third oxide layer 27 is planarized by chemical mechanical polishing (CMP) until the upper surface of the third oxide layer 27 is flush or approximately flush with the upper surface of the semiconductor layer 1. At this time, the portion of the first oxide layer 25 located outside the trench 2 is also removed.

[0138] like Figure 12 As shown, semiconductor processes such as photoresist coating, exposure, development, and wet etching are used to remove the third oxide layer 27. During this process, a portion of the first oxide layer 25 is also etched back. The remaining top surface of the first oxide layer 25 is lower than the top surface of the regulating gate polysilicon 4, serving as the first isolation layer 6. Simultaneously, the sidewalls of the portion of the trench 2 above the first isolation layer 6 are exposed, as are the top surface and sidewalls of the portion of the regulating gate polysilicon 4 above the first isolation layer 6. Then, the photoresist is removed, and a fourth oxide layer 28 is grown using thermal oxidation or other suitable methods. The fourth oxide layer 28 covers the exposed sidewalls of the trench 2 and the exposed sidewalls of the regulating gate polysilicon 4.

[0139] Specifically, the portion of the fourth oxide layer 28 located on the sidewall of the trench 2 serves as the gate dielectric layer 9, and the portion of the fourth oxide layer 28 located on the top surface and sidewall of the regulating gate polysilicon 4 serves as the third isolation layer 8.

[0140] As an example, in this embodiment, the thickness of the third isolation layer 8 and the gate dielectric layer 9 is controlled by the thermal oxidation time. It should be noted that since the gate dielectric layer 9 is formed by oxidizing the semiconductor layers 1 on both sides of the trench 2, and the third isolation layer 8 is formed by oxidizing the regulating gate polysilicon 4, the semiconductor layers 1 and the regulating gate polysilicon 4 are made of different materials. Therefore, even with the same thermal oxidation time, the thickness of the third isolation layer 8 and the gate dielectric layer 9 may differ. Furthermore, in different applications, the doping type (e.g., P-type or N-type) and doping concentration of the regulating gate polysilicon 4 may differ. Even under the same oxidation conditions, the thickness of the resulting third isolation layer 8 may differ. Therefore, the oxidation process parameters need to be set according to the required thickness of the third isolation layer 8 and the specific oxidation target.

[0141] It should be noted that the portion of the fourth oxide layer 28 located on the upper surface of the semiconductor layer 1 can be retained or removed as needed. In this embodiment, the portion of the fourth oxide layer 28 located on the upper surface of the semiconductor layer 1 is retained to serve as a protective layer for the semiconductor layer 1 during subsequent ion implantation.

[0142] like Figure 13 As shown, a third polysilicon layer is deposited in the trench 2 and above the semiconductor layer 1, and the third polysilicon layer is etched back until the upper surface of the third polysilicon layer is flush or approximately flush with the upper surface of the semiconductor layer 1, thereby obtaining a gate polysilicon 5 located in the trench 2. The gate polysilicon 5 is composed of a middle portion 501 located above the adjustment gate polysilicon 4 and side wing portions 502 located on both sides of the adjustment gate polysilicon 4 and connected to the middle portion 501, and its cross-section is shaped like an inverted U.

[0143] As an example, the bottom surface of the side wing portion 502 of the gate polysilicon 5 is lower than the top surface of the regulating gate polysilicon 4.

[0144] Please see Figure 2 Next, step S6 is executed: forming an adjustment metal line 10, a gate metal line 11, a source metal line 12, an adjustment pad 13, a gate pad 14, and a source pad 15 above the semiconductor layer 1. The adjustment metal line 10 is electrically connected to the adjustment gate polysilicon 4, the gate metal line 11 is electrically connected to the gate polysilicon 5, the source metal line 12 is electrically connected to the shielding gate polysilicon 3, the adjustment pad 13 is connected to the adjustment metal line 10, the gate pad 14 is connected to the gate metal line 11, and the source pad 14 is connected to the source metal line 12.

[0145] As an example, firstly, a body region (e.g., a P-type doped region) is formed on the upper surface of the semiconductor layer 1 on both sides of the trench 2 using ion implantation. Then, a source region (e.g., a higher concentration N-type doped region) is formed on the upper surface of the body region using ion implantation. Next, an interlayer dielectric layer is deposited above the semiconductor layer 1, and first contact holes 18, 19, 20, and 21 are formed in the interlayer dielectric layer using semiconductor patterning processes such as photolithography and etching. The first contact hole 18 is located on the first polysilicon lead-out portion 16, and the second contact hole 19 is located on the second polysilicon lead-out portion 16. On the polysilicon lead-out portion 17, the third contact hole 20 is located on the gate polysilicon 5, and the fourth contact hole 21 is located on the source region. Then, conductive plugs (e.g., W plugs) are formed in the first contact hole 18, the second contact hole 19, the third contact hole 20, and the fourth contact hole 21. Finally, a metal layer is formed on the interlayer dielectric layer and patterned to obtain the adjustment metal line 10, the gate metal line 11, the source metal line 12, the adjustment pad 13, the gate pad 14, and the source pad 15. In this embodiment, a drain metal layer (not shown) is also formed on the lower surface of the semiconductor layer 1.

[0146] Specifically, the source metal line 12 is electrically connected to the shielding gate polysilicon 3 through the first contact hole 18 and the first polysilicon lead-out portion 16, the regulating metal line 10 is electrically connected to the regulating gate polysilicon 4 through the second contact hole 19 and the second polysilicon lead-out portion 17, the gate metal line 11 is electrically connected to the gate polysilicon 5 through the third contact hole 20, and the source pad 15 is electrically connected to the source region through the fourth contact hole 21.

[0147] As an example, the adjustment metal line 10, the gate metal line 11, the source metal line 12, the adjustment pad 13, the gate pad 14, and the source pad 15 can be located in the same metal layer or in different metal layers as needed. The materials of the adjustment metal line 10, the gate metal line 11, the source metal line 12, the adjustment pad 13, the gate pad 14, and the source pad 15 can be aluminum or other suitable conductive metal materials.

[0148] like Figure 2 As shown, in some embodiments, the potential of the regulating gate polysilicon 4 is floated. In this case, in the shielded gate trench power device, the regulating gate polysilicon 4 acts as part of the dielectric layer between the gate polysilicon 5 and the source polysilicon (the shielded gate polysilicon 3), which is equivalent to thickening the dielectric between the gate polysilicon and the source polysilicon, resulting in a smaller gate-source capacitance Cgs, fast switching, and suitability for high-frequency applications.

[0149] Please see Figure 3 In other embodiments, the regulating pad 13 and the gate pad 14 are electrically connected by a bonding wire 22, so that the regulating gate polysilicon 4 is shorted to the gate pad 14 in sequence through the second polysilicon lead-out portion 17, the second contact hole 19, the regulating metal line 10, the regulating pad 13, and the bonding wire 22. In this case, in the multifunctional shielded gate trench power device, the regulating gate polysilicon 4 constitutes part of the gate polysilicon. The device is similar to a device using a planar gate polysilicon, with a moderate gate-source capacitance Cgs and relatively balanced device performance.

[0150] Please see Figure 4 In other embodiments, the regulating pad 13 and the source pad 15 are electrically connected by a bonding wire 23, thereby the regulating gate polysilicon 4 is shorted to the source pad 15 in sequence through the second polysilicon lead-out portion 17, the second contact hole 19, the regulating metal line 10, the regulating pad 13, and the bonding wire 23. In this case, in the fabricated multifunctional shielded gate trench power device, the regulating gate polysilicon 4 constitutes part of the source polysilicon, increasing the relative area of ​​the source polysilicon and the gate polysilicon, resulting in a larger gate-source capacitance Cgs, which can reduce switching oscillation, strengthen shock resistance, and reduce the ratio of reverse transfer capacitance to input capacitance Crss / Ciss. This makes it suitable for applications such as battery management systems (BMS) and motor control.

[0151] As described above, the fabrication method of the multifunctional shielded gate trench power device in this embodiment is simple. The fabricated multifunctional shielded gate trench power device not only has gate pads and source pads, but also adjustment pads. The device trench not only has gate polysilicon and shielded gate polysilicon, but also adjustment gate polysilicon. By flexibly using the bonding method of the adjustment pads, devices with different performance can be realized.

[0152] In summary, the multifunctional shielded gate trench power device of the present invention has an adjustment pad, a gate pad, and a source pad. The device trench has an adjustment gate polysilicon, a gate polysilicon, and a shielded gate polysilicon. The adjustment gate polysilicon is located above the shielded gate polysilicon. The gate polysilicon includes a middle portion and side portions. The middle portion is located above the adjustment gate polysilicon, and the side portions are located on both sides of the adjustment gate polysilicon and connected to the middle portion. The adjustment pad, the gate pad, and the source pad are electrically connected to the adjustment gate polysilicon, the gate polysilicon, and the shielded gate polysilicon, respectively. Different wire bonding methods can achieve devices with different performance characteristics. When the adjustment pad is floating, the device has a small gate-source capacitance (Cgs), resulting in fast switching and suitability for high-frequency applications. When the adjustment pad and gate pad are shorted together via wire bonding, the device has a medium gate-source capacitance (Cgs), resulting in balanced device performance. When the adjustment pad and source pad are shorted together via wire bonding, the device has a large gate-source capacitance (Cgs), which reduces switching oscillations, enhances shock resistance, and lowers the ratio of reverse transfer capacitance to input capacitance (Crss / Ciss), making it suitable for applications such as Battery Management Systems (BMS) and motor control. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0153] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A multifunctional shielded grid trench type power device, characterized in that, include: Semiconductor layer; Multiple trenches are located in the semiconductor layer and are spaced apart in the horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward; A shielding gate polysilicon, a regulating gate polysilicon, and a gate polysilicon are located in the trench. The regulating gate polysilicon is located above the shielding gate polysilicon and is spaced apart from it. The gate polysilicon includes a middle portion and side wing portions. The middle portion is located above the regulating gate polysilicon and is spaced apart from it. The side wing portions are located on both sides of the regulating gate polysilicon and are connected to the middle portion. The system comprises a first isolation layer, a second isolation layer, a third isolation layer, and a gate dielectric layer. The first isolation layer is located between the inner wall of the trench and the outer wall of the shielding gate polysilicon. The second isolation layer is located between the shielding gate polysilicon and the regulating gate polysilicon. The third isolation layer is located between the regulating gate polysilicon and the gate polysilicon. The gate dielectric layer is located between the inner wall of the trench and the outer wall of the gate polysilicon. An adjustment metal line, a gate metal line, and a source metal line are located above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, and the source metal line is electrically connected to the shielding gate polysilicon. An adjustment pad, a gate pad, and a source pad are located above the semiconductor layer. The adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

2. The multifunctional shielded grid trench power device according to claim 1, characterized in that: The plurality of trenches are spaced apart in a first horizontal direction and extend in a second horizontal direction perpendicular to the first horizontal direction. The shielded gate trench power device further includes a first polysilicon lead-out portion and a second polysilicon lead-out portion located in the trench. The first polysilicon lead-out portion is located at both ends of the shielded gate polysilicon in the second horizontal direction and is connected to the shielded gate polysilicon. The second polysilicon lead-out portion is located at both ends of the regulating gate polysilicon in the second horizontal direction and is connected to the regulating gate polysilicon. The top surface of the first polysilicon lead-out portion is higher than the top surface of the shielded gate polysilicon, and the top surface of the second polysilicon lead-out portion is higher than the top surface of the regulating gate polysilicon.

3. The multifunctional shielded grid trench power device according to claim 2, characterized in that: The shielded gate trench power device further includes a first contact hole disposed on the first polysilicon lead-out portion, a second contact hole disposed on the second polysilicon lead-out portion, and a third contact hole disposed on the gate polysilicon. The source metal line is electrically connected to the shielded gate polysilicon through the first contact hole and the first polysilicon lead-out portion, the regulating metal line is electrically connected to the regulating gate polysilicon through the second contact hole and the second polysilicon lead-out portion, and the gate metal line is electrically connected to the gate polysilicon through the third contact hole.

4. The multifunctional shielded grid trench power device according to claim 1, characterized in that: The shielded trench power device further includes a body region, a source region, and a fourth contact hole. The body region is located on the upper surface of the semiconductor layer on both sides of the trench. The source region is located on the upper surface of the body region. The fourth contact hole is located on the source region. The source pad is electrically connected to the source region through the fourth contact hole.

5. The multifunctional shielded grid trench power device according to claim 1, characterized in that: The adjustment pad is floating at a potential; or the adjustment pad is electrically connected to the gate pad; or the adjustment pad is electrically connected to the source pad.

6. A method for fabricating a multifunctional shielded trench power device, characterized in that, Includes the following steps: A semiconductor layer is provided, in which a plurality of trenches are formed at intervals in a horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward therefrom; A first isolation layer and a shielding gate polysilicon are formed in the trench, and the inner wall of the trench and the shielding gate polysilicon are separated by the first isolation layer; A second isolation layer is formed in the trench, the second isolation layer covering the upper surface of the shielding gate polysilicon; A regulating gate polysilicon is formed in the trench, the regulating gate polysilicon being located above the shielding gate polysilicon and separated from the shielding gate polysilicon by the second isolation layer; A third isolation layer, a gate dielectric layer, and a gate polysilicon are formed in the trench. The gate polysilicon includes a central portion and side portions. The central portion is located above the adjustment gate polysilicon, and the side portions are located on both sides of the adjustment gate polysilicon and connected to the central portion. The gate polysilicon and the adjustment gate polysilicon are separated by the third isolation layer, and the gate polysilicon and the inner wall of the trench are separated by the gate dielectric layer. An adjustment metal line, a gate metal line, a source metal line, an adjustment pad, a gate pad, and a source pad are formed above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, the source metal line is electrically connected to the shield gate polysilicon, the adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

7. The method for manufacturing a multifunctional shielded grid trench power device according to claim 6, characterized in that, The plurality of said trenches are arranged at intervals in a first horizontal direction and all extend in a second horizontal direction perpendicular to the first horizontal direction. The method for manufacturing the multifunctional shielded gate trench type power device further includes the following steps: A first polysilicon lead-out portion is formed at both ends of the shielding gate polysilicon in a second horizontal direction. The first polysilicon lead-out portion is located in the trench and the top surface of the first polysilicon lead-out portion is higher than the top surface of the shielding gate polysilicon. A second polysilicon lead-out portion is formed at both ends of the second horizontal direction of the regulating gate polysilicon. The second polysilicon lead-out portion is located in the trench and the top surface of the second polysilicon lead-out portion is higher than the top surface of the regulating gate polysilicon.

8. The method for manufacturing a multifunctional shielded grid trench power device according to claim 7, characterized in that, It also includes the following steps: The solid regions are formed on the upper surface of the semiconductor layer on both sides of the trench; The source region is formed on the upper surface layer of the body region; An interlayer dielectric layer is formed above the semiconductor layer; A first contact hole, a second contact hole, a third contact hole, and a fourth contact hole are formed in the interlayer dielectric layer. The first contact hole is located on the first polysilicon lead-out portion, the second contact hole is located on the second polysilicon lead-out portion, the third contact hole is located on the gate polysilicon, and the fourth contact hole is located on the source region. Conductive plugs are formed in the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole; The source metal line is electrically connected to the shielding gate polysilicon through the first contact hole and the first polysilicon lead-out portion; the adjustment metal line is electrically connected to the adjustment gate polysilicon through the second contact hole and the second polysilicon lead-out portion; the gate metal line is electrically connected to the gate polysilicon through the third contact hole; and the source pad is electrically connected to the source region through the fourth contact hole.

9. The method for manufacturing a multifunctional shielded grid trench power device according to claim 6, characterized in that: The bottom surface of the side wing is lower than the top surface of the regulating gate polysilicon.

10. The method for manufacturing a multifunctional shielded trench power device according to claim 6, characterized in that: The potential of the adjustable gate polysilicon is floating; or the method for fabricating the multifunctional shielded gate trench power device further includes the step of forming a bonding wire, one end of which is connected to the adjustable pad, and the other end of which is connected to the gate pad or the source pad.

Images