A distributed equivalent circuit of a GaN HEMT device

Abstract

The present invention discloses a distributed equivalent circuit for a GaN HEMT device. The circuit comprises a gate terminal, a drain terminal, and a source terminal. A distributed gate-source capacitor and a distributed first intrinsic resistor are provided between the gate terminal and the source terminal. A distributed gate-drain capacitor and a distributed second intrinsic resistor are provided between the gate terminal and the drain terminal. A current source, a first capacitor, and a first resistor are provided between the drain terminal and the source terminal. A distributed gate inductor and a distributed gate resistor are provided at the gate terminal. A second resistor and a first inductor are provided at the drain terminal. A third resistor and a second inductor are provided at the source terminal. Embodiments of the present invention can characterize the distributed effects within a GaN HEMT device under high-frequency operating conditions, thereby making the model parameters more accurate. As a distributed equivalent circuit for a GaN HEMT device, the present invention can be widely applied in the field of semiconductor device modeling technology.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device modeling, and in particular to a distributed equivalent circuit of a GaN HEMT device. Background Art

[0002] Microwave transistors play an important role in both military and communications fields. High electron mobility transistors (HEMTs) fabricated from GaN materials, with their high frequency, high power, and high efficiency, have been widely used in microwave circuits. To improve circuit design efficiency and shorten design cycles, establishing accurate models for GaN HEMTs is crucial. With the continuous advancement and development of semiconductor materials, devices, and their fabrication processes, traditional semiconductor device modeling methods are no longer able to accurately describe complex device characteristics. Furthermore, the continued development of GaN HEMT devices has placed higher demands on model accuracy, wide bandwidth, and multi-bias applicability. Numerous empirical models of GaN HEMTs have been developed, and empirical modeling technology has matured. However, most empirical models use lumped equivalent circuit models. When devices operate in high-frequency environments, distributed effects within components must be considered. Therefore, lumped model parameters lose their physical meaning, resulting in limited model accuracy. Furthermore, lumped empirical model parameters often lack physical meaning, making it difficult to establish an intuitive connection with the device, thus failing to provide guidance for device processing and fabrication. Summary of the Invention

[0003] In order to solve the above technical problems, the purpose of the present invention is to provide a distributed equivalent circuit of a GaN HEMT device, which can characterize the distributed effects inside the GaN HEMT device under high-frequency operating conditions, making the model parameters more accurate.

[0004] The first technical solution adopted by the present invention is: a distributed equivalent circuit of a GaN HEMT device, the circuit having a gate terminal, a drain terminal, and a source terminal, a distributed gate-source capacitor and a distributed first intrinsic resistor are provided between the gate terminal and the source terminal, a distributed gate-drain capacitor and a distributed second intrinsic resistor are provided between the gate terminal and the drain terminal, a current source, a first capacitor, and a first resistor are provided at the drain terminal and the source terminal, a distributed gate inductor and a distributed gate resistor are provided at the gate terminal, a second resistor and a first inductor are provided at the drain terminal, and a third resistor and a second inductor are provided at the source terminal, wherein:

[0005] The distributed gate-source capacitor includes a plurality of gate-source capacitors, and the plurality of gate-source capacitors are connected in parallel;

[0006] The distributed first intrinsic resistor includes a plurality of first intrinsic resistors, and the plurality of first intrinsic resistors are connected in parallel;

[0007] The distributed gate-drain capacitor includes a plurality of gate-drain capacitors, and the plurality of gate-drain capacitors are connected in parallel;

[0008] The distributed second intrinsic resistor includes a plurality of second intrinsic resistors, and the plurality of second intrinsic resistors are connected in parallel;

[0009] The distributed gate inductor includes a plurality of gate inductors, and the distributed gate resistor includes a plurality of gate resistors, wherein the plurality of gate resistors and the plurality of gate inductors are connected in series.

[0010] Furthermore, a gate terminal of the circuit is connected to a first end of the distributed gate inductor, a second end of the distributed gate inductor is connected to a first end of the distributed gate resistor, a second end of the distributed gate resistor and a first end of the distributed gate-drain capacitor are connected to a first end of the distributed gate-source capacitor, a second end of the distributed gate-source capacitor is connected to a first end of the distributed first intrinsic resistor, a second end of the distributed gate-drain capacitor is connected to a first end of the distributed second intrinsic resistor, a second end of the distributed first intrinsic resistor, a second end of the current source, a second end of the first capacitor, a second end of the first resistor are connected to a first end of the third resistor, a second end of the distributed second intrinsic resistor, a first end of the current source, a first end of the first capacitor, a first end of the first resistor are connected to a first end of the second resistor, a second end of the second resistor is connected to a first end of the first inductor, a second end of the first inductor is connected to a drain terminal of the circuit, a second end of the third resistor is connected to a first end of the second inductor, and a second end of the second inductor is connected to a source terminal of the circuit.

[0011] Furthermore, the circuit further includes a gate pad parasitic capacitor, a drain pad parasitic capacitor and a gate-drain pad coupling capacitor, wherein:

[0012] The first end of the gate pad parasitic capacitor is respectively connected to the gate terminal of the circuit, the first end of the distributed gate inductor and the first end of the gate-drain pad coupling capacitor;

[0013] The second end of the gate pad parasitic capacitor is connected to the source end of the circuit, the second end of the second inductor is connected to the second end of the drain pad parasitic capacitor respectively.

[0014] The second end of the gate-drain pad coupling capacitor is respectively connected to the drain end of the circuit, the second end of the first inductor is connected to the first end of the drain pad parasitic capacitor.

[0015] Furthermore, the circuit further includes a distributed gate-drain metal coupling capacitor, a distributed gate-source metal coupling capacitor and a second capacitor, wherein:

[0016] The distributed gate-drain metal coupling capacitor includes a plurality of gate-drain metal coupling capacitors, and the plurality of gate-drain metal coupling capacitors are connected in parallel;

[0017] The distributed gate-source metal coupling capacitor includes a plurality of gate-source metal coupling capacitors, and the plurality of gate-source metal coupling capacitors are connected in parallel.

[0018] Furthermore, the first end of the distributed gate-drain metal coupling capacitor is respectively connected to the second end of the distributed gate inductor, the first end of the distributed gate resistor is respectively connected to the first end of the distributed gate-source metal coupling capacitor, the second end of the distributed gate-drain metal coupling capacitor is respectively connected to the second end of the second resistor, the first end of the first inductor and the first end of the second capacitor, and the second end of the distributed gate-source metal coupling capacitor is respectively connected to the second end of the third resistor, the first end of the second inductor and the second end of the second capacitor.

[0019] The beneficial effect of the circuit of the present invention is: by replacing the traditional gate-source capacitance, gate-drain capacitance and intrinsic resistance with corresponding distributed structures, the distributed equivalent circuit model can characterize the distributed effects inside the device under high-frequency working conditions. The parameters of the model are more accurate and have certain physical meanings, which can better guide device process design and circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic structural diagram of a distributed equivalent circuit of a GaN HEMT device according to the present invention;

[0021] Figure 2 is a structural schematic diagram of a distributed equivalent circuit of a second GaN HEMT device provided by a specific embodiment of the present invention;

[0022] Figure 3 It is a structural schematic diagram of a distributed equivalent circuit of a third GaN HEMT device provided in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are provided for ease of description only and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted based on the understanding of those skilled in the art.

[0024] Reference Figure 1The present invention provides a distributed equivalent circuit of a GaN HEMT device, wherein the circuit has a gate terminal G, a drain terminal D and a source terminal S, and a distributed gate-source capacitor C is provided between the gate terminal and the source terminal. gs With the distributed first intrinsic resistance R gs A distributed gate-drain capacitor C is provided between the gate terminal and the drain terminal. gd With the distributed second intrinsic resistance R gd The drain terminal and the source terminal are provided with a current source I ds , the first capacitor C ds With the first resistor R ds , the gate end is provided with a distributed gate inductor L g With the distributed gate resistance R g The drain terminal is provided with a second resistor R d With the first inductor L d The source terminal is provided with a third resistor R s With the second inductor L s ,in:

[0025] The distributed gate-source capacitance includes several gate-source capacitances C gs1 ,C gs2 ,…C gsn , a plurality of gate-source capacitors are connected in parallel;

[0026] The distributed first intrinsic resistor includes a plurality of first intrinsic resistors R gs1 ,R gs2 ,…R gsn , a plurality of said first intrinsic resistors are connected in parallel;

[0027] The distributed gate-drain capacitors include several gate-drain capacitors C gd1 ,C gd2 ,…C gdn , a plurality of the gate-drain capacitors are connected in parallel;

[0028] The distributed second intrinsic resistor includes a plurality of second intrinsic resistors R gd1 ,R gd2 ,…R gdn , a plurality of said second intrinsic resistors are connected in parallel;

[0029] The distributed gate inductance includes several gate inductors L g1 ,L g2 ,…L gn , the distributed gate resistors include several gate resistors R g1 ,R g2 ,…R gn , several of the gate resistors and several of the gate inductors are connected in series.

[0030] It should be further explained that the gate terminal G of the circuit and the distributed gate inductance L g The first end of the distributed gate inductor L g The second end of the distributed gate resistor R g The first end of the distributed gate resistor R g The second end of the distributed gate-drain capacitor C gd The first end and the distributed gate-source capacitance C gs The first end of the distributed gate-source capacitor C gs The second end and the distributed first intrinsic resistance R gs The first end of the distributed gate-drain capacitor C gd The second end of the distributed second intrinsic resistance R gd The first end of the distributed first intrinsic resistance R gs The second end of the current source I ds The second end of the first capacitor C ds The second end of the first resistor R ds The second end of the third resistor R s The first end of the distributed second intrinsic resistor R gd The second end of the current source I ds The first end of the first capacitor C ds The first end of the first resistor R ds The first end and the second resistor R d The first end of the second resistor R d The second end of the first inductor L d The first end of the first inductor L is connected d The second end of the third resistor R is connected to the drain D end of the circuit. s The second end of the second inductor L s The first end of the second inductor L is connected s The second end is connected to the source terminal S of the circuit.

[0031] In this embodiment, the equivalent circuit topology of the GaN HEMT has three electrodes: gate G, drain D, and source S. The gate-source capacitance C between the gate G and the source S is gs , the gate-drain capacitance C between the gate G and the drain D gd , the intrinsic resistance R between the gate G and the source S gs , the intrinsic resistance R between the gate G and the drain D gd , gate inductance L g , gate resistance R gIn signal transmission, it is no longer simply abstracted into a single component, but is replaced by distributed capacitors, resistors, and inductors;

[0032] The gate-source capacitance C between the gate G and the source S gs , replaced by C gs1 ,C gs2 ,…C gsn ;

[0033] The gate-drain capacitance C between the gate G and the drain D gd , replaced by C gd1 ,C gd2 ,…C gdn ;

[0034] The intrinsic resistance R between the gate G and the source S gs , replaced by R gs1 ,R gs2 ,…R gsn ;

[0035] The intrinsic resistance R between the gate G and the drain D gd , replaced by R gd1 ,R gd2 ,…R gdn ;

[0036] Gate inductance L g , replaced by L g1 ,L g2 ,…L gn ;

[0037] Gate resistance R g , replaced by R g1 ,R g2 ,…R gn ;

[0038] Gate G connected to inductor L g1 One end of the source S is connected to the inductor L s One end of the drain D is connected to the inductor L d one end;

[0039] Inductor L g1 The other end of the resistor R g1 One end of the resistor R g1 The other end of the inductor L g2 , capacitor C gd1 and capacitor C gs1 One end of each; capacitor C gd1 The other end of the resistor R gd1 One end of the capacitor C gs1 The other end of the resistor R gs1 One end of the resistor R gs1 The other end of the resistor Rs ;Resistor R gd1 The other end is connected to the current source I ds , capacitor C ds , resistor R ds and resistor R d One end of each; inductor L g2 The other end of the resistor R g2 One end of the resistor R g2 The other end of the inductor L g3 , capacitor C gd2 and capacitor C gs2 One end of each; capacitor C gd2 The other end of the resistor R gd2 One end of the capacitor C gs2 The other end of the resistor R gs2 One end of the resistor R gs2 The other end of the resistor R s One end of the resistor R gd2 The other end is connected to the current source I ds , capacitor C ds , resistor R ds and resistor R d Each end.

[0040] Similar description to L gn Inductance L gn The other end of the resistor R gn One end of the resistor R gn The other end of the inductor L gn , capacitor C gdn and capacitor C gsn One end of each; capacitor C gdn The other end of the resistor R gdn One end of the capacitor C gsn The other end of the resistor R gsn One end of the resistor R gs The other end of the resistor R s One end of the resistor R gdn The other end is connected to the current source I ds , capacitor C ds , resistor R ds and resistor R d One end of each; resistor R d The other end of the inductor L d The other end of the resistor R s The other end of the inductor L s the other end.

[0041] Wherein n≥2, and n selects different values ​​according to the gate electrode structure and operating frequency of the GaN HEMT device.

[0042] Further, refer to Figure 2 , the circuit also includes a gate pad parasitic capacitance C pgo , Drain pad parasitic capacitance C pdo Coupling capacitance C between gate and drain pad pgdo ,in:

[0043] The gate pad parasitic capacitance C pgo The first end is respectively connected to the gate terminal G of the circuit, the distributed gate inductor L g The first end of the gate drain pad is coupled with the capacitor C pgdo The first end of the connection;

[0044] The gate pad parasitic capacitance C pgo The second end of the circuit is connected to the source terminal S and the second inductor L s The parasitic capacitance C between the second end and the drain pad pdo The second end of the connection:

[0045] The gate-drain pad coupling capacitor P pgdo The second end of the circuit is connected to the drain terminal D of the circuit and the first inductor L d The parasitic capacitance C between the second end and the drain pad pdo The first end of the connection.

[0046] In this embodiment, the parasitic capacitance C pgo , Drain pad parasitic capacitance C pdo , gate pad and drain pad coupling capacitance C pgdo ; Gate G is connected to capacitor C pgo and capacitor C pgdo One end of each; source S is connected to capacitor C pgo and capacitor C pdo One end of each; drain D is connected to capacitor C pgdo and capacitor C pdo Each end.

[0047] Further, refer to Figure 3 The circuit also includes a distributed gate-drain metal coupling capacitor C pgdi , distributed gate-source metal coupling capacitance C pgi With the second capacitor C pdi ,in:

[0048] The distributed gate-drain metal coupling capacitor includes a plurality of gate-drain metal coupling capacitors C pgdi1 ,C pgdi2 ,…,C pgdin , a plurality of the gate-drain metal coupling capacitors are connected in parallel;

[0049] The distributed gate-source metal coupling capacitor includes a plurality of gate-source metal coupling capacitors C pgi1 ,C pgi2 ,…,C pgin , several of the gate-source metal coupling capacitors are connected in parallel.

[0050] It should be further explained that the distributed gate-drain metal coupling capacitance C pgdi The first end of each of the distributed gate inductors L g The second end of the distributed gate resistor R g The first end of the distributed gate-source metal coupling capacitor C pgi The first end is connected to the distributed gate-drain metal coupling capacitor C pgdi The second end of the second resistor R d The second end of the first inductor L d The first terminal and the second capacitor C pdi The first end of the distributed gate-source metal coupling capacitor C pgi The second end of each resistor R s The second end of the second inductor L s The first terminal and the second capacitor C pdi The second end of the

[0051] In this embodiment, the gate-drain metal coupling capacitance C is added to reflect the coupling capacitance between the gate and drain metal and the coupling capacitance between the gate and source metal. pgdi and gate-source metal coupling capacitance C pgi In signal transmission, it is no longer simply abstracted as a single component, but is replaced by distributed capacitance;

[0052] Gate-drain metal coupling capacitance C pgdi , replaced by C pgdi1 ,C pgdi2 ,…,C pgdin ;

[0053] Gate-source metal coupling capacitance C pgi , replaced by C pgi1 ,C pgi2 ,…,C pgin .

[0054] Inductor L g1 One end of the capacitor C pgi and capacitor C pgdi1 One end of each; inductor L g2 One end of the capacitor C pgi2 and capacitor C pgdi2 Each end.

[0055] Similar description to Lgn Inductance L gn One end of the capacitor C pgin and capacitor C pgdin One end of each; capacitor C pgin One end is connected to the inductor L s The other end of the capacitor C pgdin One end of the inductor L is connected d The other end of the resistor R d One end of the capacitor C pdi and capacitor C pgdi1 ,C pgdi2 ,…,C pgdin The other end of each; resistor R s One end of the capacitor C pdi and capacitor C pgi1 ,C pgi2 ,…,C pgin The other end of each.

[0056] Finally, it should be noted that the circuit topology of the embodiment of the present invention can be applied to GaN HMET device construction models and process development kits (PDKs) to further assist in RF circuit design.

[0057] In summary, at high frequencies, the distributed effects within the device are significant, making traditional lumped parameter circuit models inapplicable. Distributed models, however, offer more precise characterization, thus providing better guidance for device process and circuit design. Accurate distributed models enable rapid verification and improvement of design solutions using simulation and optimization tools, reducing data optimization iterations and the number of data tests, thereby improving design efficiency.

[0058] Finally, it should be noted that the drawings of the present invention are schematic diagrams of various structures drawn according to the embodiments of the present invention, and are not made according to the actual scale. Some details are enlarged for clearer expression, and some details may be omitted to simplify the display. gs , the gate capacitance C between the gate G and the drain D gd , the intrinsic resistance R between the gate G and the source S gs , the intrinsic resistance R between the gate G and the drain D gd , gate inductance L g , gate resistance R g , gate-drain metal coupling capacitance C pgdi and gate-source metal coupling capacitance C pgi In signal transmission, they can no longer be simply abstracted as single components, but should be replaced by distributed capacitors, resistors, and inductors.

[0059] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A distributed equivalent circuit of a GaN HEMT device, characterized in that: The circuit has a gate terminal, a drain terminal, and a source terminal; a distributed gate-source capacitor and a distributed first intrinsic resistor are provided between the gate terminal and the source terminal; a distributed gate-drain capacitor and a distributed second intrinsic resistor are provided between the gate terminal and the drain terminal; a current source, a first capacitor, and a first resistor are provided between the drain terminal and the source terminal; a distributed gate inductor and a distributed gate resistor are provided at the gate terminal; a second resistor and a first inductor are provided at the drain terminal; and a third resistor and a second inductor are provided at the source terminal, wherein: The distributed gate-source capacitor includes a plurality of gate-source capacitors, and the plurality of gate-source capacitors are connected in parallel; The distributed first intrinsic resistor includes a plurality of first intrinsic resistors, and the plurality of first intrinsic resistors are connected in parallel; The distributed gate-drain capacitor includes a plurality of gate-drain capacitors, and the plurality of gate-drain capacitors are connected in parallel; The distributed second intrinsic resistor includes a plurality of second intrinsic resistors, and the plurality of second intrinsic resistors are connected in parallel; The distributed gate inductor includes a plurality of gate inductors, the distributed gate resistor includes a plurality of gate resistors, and the plurality of gate resistors and the plurality of gate inductors are connected in series; The gate terminal of the circuit is connected to the first end of the distributed gate inductor, the second end of the distributed gate inductor is connected to the first end of the distributed gate resistor, the second end of the distributed gate resistor and the first end of the distributed gate-drain capacitor are connected to the first end of the distributed gate-source capacitor, the second end of the distributed gate-source capacitor is connected to the first end of the distributed first intrinsic resistor, the second end of the distributed gate-drain capacitor is connected to the first end of the distributed second intrinsic resistor, the second end of the distributed first intrinsic resistor, the second end of the current source, the second end of the first capacitor, the second end of the first resistor are connected to the first end of the third resistor, the second end of the distributed second intrinsic resistor, the first end of the current source, the first end of the first capacitor, the first end of the first resistor are connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the first inductor, the second end of the first inductor is connected to the drain terminal of the circuit, the second end of the third resistor is connected to the first end of the second inductor, and the second end of the second inductor is connected to the source terminal of the circuit.

2. The distributed equivalent circuit of a GaN HEMT device according to claim 1, characterized in that: The circuit further includes a gate pad parasitic capacitor, a drain pad parasitic capacitor, and a gate-drain pad coupling capacitor, wherein: The first end of the gate pad parasitic capacitor is respectively connected to the gate terminal of the circuit, the first end of the distributed gate inductor and the first end of the gate-drain pad coupling capacitor; The second end of the gate pad parasitic capacitor is connected to the source end of the circuit, the second end of the second inductor is connected to the second end of the drain pad parasitic capacitor respectively. The second end of the gate-drain pad coupling capacitor is respectively connected to the drain end of the circuit, the second end of the first inductor is connected to the first end of the drain pad parasitic capacitor.

3. The distributed equivalent circuit of a GaN HEMT device according to claim 2, characterized in that: The circuit further includes a distributed gate-drain metal coupling capacitor, a distributed gate-source metal coupling capacitor and a second capacitor, wherein: The distributed gate-drain metal coupling capacitor includes a plurality of gate-drain metal coupling capacitors, and the plurality of gate-drain metal coupling capacitors are connected in parallel; The distributed gate-source metal coupling capacitor includes a plurality of gate-source metal coupling capacitors, and the plurality of gate-source metal coupling capacitors are connected in parallel.

4. The distributed equivalent circuit of a GaN HEMT device according to claim 3, characterized in that: The first end of the distributed gate-drain metal coupling capacitor is respectively connected to the second end of the distributed gate inductor, and the first end of the distributed gate resistor is respectively connected to the first end of the distributed gate-source metal coupling capacitor; the second end of the distributed gate-drain metal coupling capacitor is respectively connected to the second end of the second resistor, the first end of the first inductor and the first end of the second capacitor; and the second end of the distributed gate-source metal coupling capacitor is respectively connected to the second end of the third resistor, the first end of the second inductor and the second end of the second capacitor.

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