Offset driving scheme for digital displays

Abstract

A novel method for driving a digital display with multiple pixel rows includes receiving a data frame to be written to the display within a predetermined frame time, dividing the frame time into multiple time intervals, defining multiple row groups, and defining a unique sequence for each row group to display a corresponding multi-bit data word and multiple off states on the pixels of the rows in the row group. The driving sequence for each row has a predetermined number of off states that are uniquely offset relative to the initial row. The predetermined number of off states ensures that pixel updates for these groups do not overlap.

Description

Technical Field

[0001] This invention relates generally to digital displays, and more specifically to pixel driving systems and methods for digital displays. Background Technology

[0002] As digital displays (e.g., liquid crystal displays on silicon, micro-LED displays, etc.) are increasingly adopted in devices, there is a growing need to improve their performance. A typical digital display includes a driving circuit electrically connected to an m×n pixel array arranged in m columns and n rows. Each row of pixels is electrically connected to a corresponding row select line, and each column of pixels is electrically connected to a corresponding group of data lines. When an assert signal is given on a particular row select line, each pixel in that row will lock the asserted data on one or more corresponding data lines it is connected to. For a single frame, data is provided on the data lines, and the row select lines are actuated in a predetermined order such that each bit of data is displayed by its intended pixel for an amount of time corresponding to its bit weight. As a result, each pixel will display the intensity of the intensity value of the corresponding multi-bit data word.

[0003] The least significant bit (LSB) time is the amount of time required for each LSB of data displayed per pixel. Shorter LSB times can increase frame rate (reducing visible artifacts), increase bit depth (higher intensity precision), and increase display resolution (e.g., more display lines). However, loading a single bit into a row of pixels requires a finite amount of time, depending on the speed of the circuitry. Therefore, the length of the LSB time can be limited. Summary of the Invention

[0004] This invention overcomes the problems associated with the prior art by providing a display, and the display driving scheme relaxes the time constraint imposed by the duration of the least significant bit (LSB) of asserted data on the display. This invention helps improve the accuracy of intensity values ​​(e.g., by using a shorter LSB time). This invention also facilitates the use of slower and therefore cheaper circuitry for displaying data.

[0005] An example method for driving a digital display comprising multiple pixels arranged in multiple rows is disclosed. One example method includes receiving a data frame. The data frame is intended to be written to the digital display during a predefined frame time. The data frame may include a multi-bit data word corresponding to each pixel of the display, and each multi-bit data word may include multiple individual bits. Each bit may have a weight corresponding to the amount of time that bit should be displayed by the corresponding pixel, and each multi-bit data word can define a maximum number of different intensity values. Additionally, the example method includes dividing the frame time into a total number of time intervals, and the total number of time intervals may be greater than the maximum number of different intensity values. Additionally, the example method includes defining a first set of rows of the display and defining a second set of rows of the display. The example method also includes defining a first sequence for displaying corresponding multi-bit data words and one or more off states across rows of the first set of rows, and defining a second sequence for displaying corresponding multi-bit data words and one or more off states across rows of the second set of rows. The first sequence may begin with the bits displaying the multi-bit data words, and the second sequence may begin with the display of an initial off state. The first sequence and the second sequence may begin during the same time interval across multiple time intervals. Additionally, the example method includes displaying data frames and a closed state on a display based on the first sequence and the second sequence.

[0006] In one particular example method, the multi-bit data word is a binary weighted data word, and the duration of the initial off state of the second sequence can be equal to 5, 10, 23, 43, 52, 77, or 88 time intervals. In a particularly effective example method, the duration of the initial off state of the second sequence is equal to 5 time intervals.

[0007] In one example method, the first sequence may include loading data into pixels of a first set of rows during a first set of time intervals. The second sequence may include loading data into pixels of a second set of rows during a second set of time intervals. The first and second set of time intervals may be mutually exclusive.

[0008] In one example method, the first sequence may include loading data bits of a multi-bit data word into a pixel in descending order of bit importance, loading a closed state into the pixel, and then reloading the bits of the multi-bit data word into the pixel in ascending order of bit importance. The second sequence may include loading a first closed state into the pixel sequentially, loading data bits of a multi-bit data word into the pixel in descending order of bit importance, reloading the bits of a multi-bit data word into the pixel in ascending order of bit importance, and then loading a second closed state into the pixel. The duration of the closed state in the first sequence may be equal to the sum of the durations of the first and second closed states in the second sequence.

[0009] In one example method, the first sequence includes displaying a first digit lasting a first time period. The second sequence may include a second digit displayed during at least a portion of the first time period, and the second sequence may also include a third digit displayed during at least a portion of the first time period. The second sequence may also include a fourth digit displayed during at least a portion of the first time period. The third digit may indicate a second time period lasting a second time period. The second time period may begin after the start of the first time period and end before the end of the first time period.

[0010] In the example method, the number of time intervals during the first sequence that assert the off state on the pixels of the first row set is the same as the number of time intervals during the second sequence that assert the off state on the pixels of the second row set.

[0011] Additionally, these example methods may include defining one or more additional row sets for the display, and asserting that the off state persists for the same number of time intervals on the pixels of each row in each row set. The number of time intervals can be determined based on the total number of row sets defined. For example, when exactly 3 row sets are defined, the time interval for asserting the off state for the same number of time intervals is 10. When exactly 4 row sets are defined, the time interval for asserting the off state for the same number of time intervals is 23. When exactly 5 row sets are defined, the time interval for asserting the off state for the same number of time intervals is 43. When exactly 6 row sets are defined, the time interval for asserting the off state for the same number of time intervals is 52. When exactly 7 row sets are defined, the time interval for asserting the off state for the same number of time intervals is 77. When exactly 8 row sets are defined, the time interval for asserting the off state for the same number of time intervals is 88. In any of these or other example methods, data is written to no more than one row set during each time interval.

[0012] Another example method for displaying data on a display comprising multiple pixels arranged in multiple rows. The example method includes receiving a data frame to be written to the display during a predefined frame time. The data frame may include a multi-bit data word corresponding to each pixel of the display. Each multi-bit data word may include multiple individual bits, each bit having a weight corresponding to the amount of time that bit should be displayed by the corresponding pixel. Each multi-bit data word can define a maximum number of different intensity values. Additionally, the example method includes dividing the frame time into a total number of time intervals. This total number of time intervals may be greater than the maximum number of intensity values. Additionally, the example method includes defining multiple groups of rows, and defining a different update sequence for each group of rows. Each update sequence defines a specific time interval within a time interval and other time intervals within the time intervals, during which the pixels of the row in the associated group are updated by the bits of the multi-bit data word, and during the other time intervals, the pixels of the row in the associated group are updated with a closed state. Additionally, the example method includes displaying the data frame and the closed state on the display according to the different update sequences. During each specific time interval, the update of the pixel may be restricted to a single row in the group of rows.

[0013] In the example method, a first update sequence associated with the first group of rows may begin by sequentially asserting bits of a multi-bit data word. The number of time intervals for which each bit can be asserted corresponds to the importance of the asserted bit. This first update sequence may end by asserting a closed state for a predetermined number of time intervals. This predetermined number of time intervals may depend on the number of groups in the multiple groups. A second update sequence associated with the rows of the second group may begin by asserting a closed state for a predetermined number of time intervals and may end by sequentially asserting bits of a multi-bit data word. The number of time intervals for which each bit can be asserted corresponds to the importance of the asserted bit. A third update sequence associated with the rows of the third group may begin by asserting a closed state for an initial number of time intervals and proceed to sequentially asserting bits of a multi-bit data word. The number of time intervals for which each bit can be asserted corresponds to the importance of the asserted bit. This third update sequence may end by asserting a closed state for a number of time intervals. The sum of the initial number of closed states and the number of closed states can be equal to the predetermined number of closed states.

[0014] In the example method, multiple additional update sequences, each associated with multiple sets of additional rows, can each begin with a time interval asserting a unique initial number of times the off state persists, and proceed to asserting bits of multiple data words sequentially. The number of time intervals for which each bit can be asserted corresponds to the importance of the asserted bit. Each additional update sequence can end with a time interval asserting a unique tail number of times the off state persists. For each of the multiple additional update sequences, the sum of the unique initial number of time intervals and the unique tail number of time intervals equals the predetermined number of off states.

[0015] The example display system includes a display, a frame buffer, configuration data, and a controller. The display has multiple pixels arranged in multiple rows. The frame buffer can be used to receive data frames and provide data to the pixels of the display in response to control signals received from the controller. The data frame can include a multi-bit data word corresponding to each pixel of the display. Each multi-bit data word can include multiple individual bits, and each bit can have a weight corresponding to the amount of time that bit should be displayed by the corresponding pixel. Therefore, each multi-bit data word can define a maximum number of different intensity values. The configuration data can define frame time as a total number of time intervals. The total number of time intervals can be greater than the maximum number of different intensity values. The configuration data can also define a first set of rows and a second set of rows for the display. The configuration data can also define a first sequence for displaying corresponding multi-bit data words and one or more off states through rows of the first set. The first sequence can begin with the bit displaying the multi-bit data word. The configuration data can also define a second sequence for displaying corresponding multi-bit data words and one or more off states on rows of the second set. The second sequence can begin with the display of an initial off state. The first sequence and the second sequence can begin during the same time interval of multiple time intervals. The controller can be configured to generate control signals and can be coupled to provide the control signals to the frame buffer and the display. These control signals can cause data frames and off states to be transmitted to the pixels of the display according to a first sequence and a second sequence.

[0016] In these example systems, the multi-bit data word is a binary weighted data word. The duration of the initial off state of the second sequence can be equal to 5, 10, 23, 43, 52, 77, or 88 time intervals. In an example system that defines only two row sets, the duration of the initial off state of the second sequence is equal to 5 time intervals.

[0017] In the example display system, this configuration data can define one or more additional row sets for the display (i.e., in addition to the first two sets). This configuration data can define the total number of time intervals to assert the duration of the off state in each sequence. The total number of time intervals can depend on the total number of row sets defined. This configuration data can also define additional unique sequences for asserting the data and off state on each additional row set. Each additional unique sequence can begin with a unique initial number of time intervals asserting the duration of the off state and can proceed to asserting bits of multiple data words sequentially. The number of time intervals for which each bit can be asserted corresponds to the importance of the asserted bit. Each additional unique sequence can end with a time interval asserting the unique tail number of the off state. For each additional unique sequence, the sum of the unique initial number of time intervals and the unique tail number of time intervals equals the total number of time intervals to assert the duration of the off state in each sequence. Attached Figure Description

[0018] The invention is described with reference to the following figures, wherein similar reference numerals denote substantially similar elements:

[0019] Figure 1 A perspective view of a pair of glasses with an integrated digital display system is shown;

[0020] Figure 2 yes Figure 1 A block diagram of a digital display system;

[0021] Figure 3 Showing Figure 2 The pixel array of a digital display system;

[0022] Figure 4 yes Figure 3 The circuit diagram of the pixels in the pixel array;

[0023] Figure 5 yes Figure 3 Timing diagrams of the first and second row groups of the pixel array;

[0024] Figure 6 This is a table showing the pulse width modulation (PWM) write times corresponding to different row groups of a single display;

[0025] Figure 7 It is used for driving Figure 3 Timing diagram of the pixel array;

[0026] Figure 8 It is used for driving Figure 3 A timing diagram of a pixel array with four different predefined row groups;

[0027] Figure 9It is a table that correlates various offset values, the number of row groups, bit depth, and optical efficiency values; and

[0028] Figure 10 This is a flowchart summarizing example methods for driving pixel arrays. Detailed Implementation

[0029] This invention overcomes the problems associated with the prior art by providing a display having a pixel array logically separated into at least two groups of pixels and a pixel driver that drives a first group of pixels according to a driving sequence that is time-shifted by a driving sequence of the second group. In the following description, numerous specific details (e.g., the number of pixels in the pixel array, specific display host devices, specific display circuitry, specific pixel weighting schemes, etc.) are set forth to provide a full understanding of the invention. However, those skilled in the art will recognize that the invention may be practiced in addition to these specific details. In other instances, details of well-known display manufacturing practices and components have been omitted to avoid unnecessarily obscuring the invention.

[0030] Figure 1 A digital display system 100 integrated into a host device is shown, depicted as a pair of glasses 102. More specifically, the display system 100 is integrated into a projector system fixed inside the arm 104 of the glasses 102 to project images directly onto the lenses 106 of the glasses 102. In this example, the display system 100 is a micro light-emitting diode (μLED) display. Although the display system 100 is described as a μLED display, the invention can also be used in conjunction with other digital display types, such as liquid crystal displays (LCDs). Furthermore, the glasses 102 are intended to illustrate an example environment. However, the displays and display driving methods disclosed herein can be used in any display environment.

[0031] Figure 2 This is a block diagram showing example components of a digital display system 100 in more detail. The display system 100 includes a timing generator 200, a controller 202, an input buffer 204, a line decoder 206, and a pixel array 208. The timing generator 200 is coupled to the controller 202 and configured to provide timing signals 210 thereto. The controller 202 is coupled to receive timing signals from the timing generator 200 and to provide control signals to the input buffer 204 and the line decoder 206 to coordinate and control the transfer of multi-bit image data via the input buffer 204 to the pixel array 208. The input buffer 204 is configured to receive 24-bit RGB (red-green-blue) data 212, reformat the data into bit-planarized data 214, and provide planarized data to the pixel array 208.

[0032] In this double-buffered example embodiment, the input buffer 204 has the ability to hold two frames of input data. One frame of input data is the data required to represent a complete image on the screen. That is, a data frame includes: (number of display rows) × (number of display columns) × (number of colors) × (number of bits per color). For example, for a 1920×1080 display using 24-bit RGB data (8 bits per color), a data frame would be 49,766,400 bits (approximately 50 Mb). Because system 100 is a double-buffered system, the input buffer 204 will have a capacity of two frames, or 99,532,800 bits (approximately 100 Mb). In a double-buffered system, a data frame can be written to one half of the input buffer 204, while the previous data frame is read from the second half of the input buffer 204.

[0033] Each 24-bit data entry includes an 8-bit data word indicating a specific red intensity, an 8-bit data word indicating a specific green intensity, and an 8-bit data word indicating a specific blue intensity. In this example, each 8-bit data word is a binary weighted data word. That is, the weights (or importance) of each bit are as follows: 2 7 2 6 2 5 2 4 2 3 2 2 2 1 and 2 0 Therefore, each 8-bit data word can define 256 different intensity values, ranging from 0 to 255 (128+64+32+16+8+4+2+1). For example, an 8-bit data word (10101001) represents an intensity value of 169 (i.e., 128+0+32+0+8+0+0+1). A value of 255 represents the maximum intensity / brightness, and a value of 0 represents the minimum intensity / brightness. A value of 0 represents the possibly darkest pixel and can also be used to put a pixel in an "off" state. Asserting three different intensity values ​​on three different colored LEDs of a pixel results in the appearance of a single pixel with intermediate colors and intensities.

[0034] A line decoder 206 is coupled between the controller and the pixel array 208 and is configured to selectively assert a enable signal 216 onto individual pixel rows of the pixel array 208, causing the pixels in the enabled row to load a row of data 214 from the input buffer 204 into the pixel array 208. More specifically, the line decoder 206 receives line address data 218 that identifies the row to which the enable signal 216 will be asserted. The pixel array 208 is an m×n pixel array, where m is the number of columns and n is the number of rows. The pixel array 208 displays video (e.g., a series of fast images) by asserting the bit-planarized data 214 received and locked from the input buffer 204. (See reference...) Figure 3-4 A more detailed description of the pixel array 208.

[0035] Figure 3 This diagram illustrates additional details of a pixel array 208 comprising a plurality of pixels 300 arranged in an array of m columns and n rows. Each column of pixels 300 is electrically connected to three data lines 302 of a corresponding group. Each group of data lines 302 includes a line for transmitting data bits of a data word indicating an intensity value of a specific color from an input buffer 204. More specifically, one line of the group is coupled to transmit one bit of an 8-bit data word corresponding to red light intensity, a second line of the group is coupled to transmit one bit of an 8-bit data word corresponding to green light intensity, and a third line of the group is coupled to transmit one bit of an 8-bit data word corresponding to blue light intensity.

[0036] Ultimately, all 24 bits of the RGB data will be passed to the corresponding pixels and displayed by those pixels. However, as mentioned above, this is done bit by bit. For example, during a line loading, B7 R B7 G and B7 B Bits can be transmitted to the red, green, and blue LEDs of the pixel via the three data lines 302 of this group. Then, during subsequent line loading, B6 R B6 G and B6 B Bits can be passed to the red, green, and blue LEDs of the same pixel via the three data lines 302 of this group. This process is repeated until all 24 bits of the RGB data are displayed at least once within a frame.

[0037] Each row of pixels 300 is electrically coupled to a corresponding enable signal line 304. In response to the row decoder 206 asserting an enable signal on the enable signal line 304, each pixel 300 in that particular row latches data from the corresponding group of data lines 302 (e.g., red, green, and blue bits). To load a single data frame from the input buffer 204 into the pixels 300, enable signals are asserted on the signal lines 304 in a predetermined order. For example, it could start from line 3041 and extend to line 304. m End, but the controller can be configured to transmit data to pixel rows in any useful order. Each time the controller 202 transitions a row enable signal from one row to another, the controller 202 also provides a control signal to the input buffer 204 to coordinate the input buffer 204's response to data lines 3021-302. n Assertions on different sets of data bits.

[0038] The following example summarizes the loading of a single pixel data frame. Initially, the line decoder 206 does not assert an enable signal on any line enable line 304. Then, in response to the line address from the controller 202, the input buffer asserts the corresponding data lines 3021-302. n The bit values ​​of a specific pixel row on the line. Then, in response to the row address and load signals from the controller 202, the row decoder asserts the exercise power signal on the corresponding line in the exercise power signal line (e.g., signal line 3041), thereby transmitting the bit values ​​from lines 3021-302. n The data is latched into the corresponding enable pixel 300. The enable signal is asserted by the line decoder 206 for a predetermined time and then removed. Next, in response to the next line address from the controller 202, the input buffer 204 asserts for data lines 3021-302. n The second row bit value of pixel 300. Then, in response to the corresponding row address and load signal from controller 202, row decoder 206 asserts the enable signal on the next enable signal line (e.g., signal line 3042), thereby enabling lines 3021-302. n The newly asserted data is locked into the corresponding enable pixel 300 in the second row. Data bits are transferred to the display line by line, repeating this process until the entire data frame (e.g., all bits of each multi-bit data word) and any off states have been transferred to the display one or more times. Subsequent data frames can then be transferred to the display using the same procedure. The relative timing of data bit transfers, enable signals, etc., will be discussed in more detail below with reference to several additional diagrams.

[0039] Figure 4 This is a block diagram showing additional details of a set of data lines 302, one of the enable signal lines 304, and an example pixel in the multicolor pixel 300. As shown, each set of data lines 302 includes a red bit data line. R (Bit R ), green data line Bit G and blue bit data line Bit B Each pixel 300 includes a red light circuit 400, a green light circuit 402, and a blue light circuit 404.

[0040] The red light circuit 400 includes a switch 406, a latch 408, a first red μLED 410, and a second red μLED 412. The switch 406 has a control input coupled to the power signal line 304 at node 414 and a red light intensity data line coupled to the red light intensity data line at node 416. rThe data input and the data output coupled to the input of latch 408 at node 418. Latch 408 has an output coupled to the input of both the first μLED 410 and the second μLED 412 at node 420.

[0041] The green light circuit 402 includes a switch 422, a latch 424, and a green μLED 426. The switch 422 has a control input coupled to the power signal line 304 at node 414 and a green light intensity data line bit coupled to node 428. g The data input is coupled to the output of latch 424 at node 430. Latch 424 has an output coupled to the input of μLED 426 at node 432.

[0042] The blue light circuit 404 includes a switch 434, a latch 436, and a green μLED 438. The switch 434 has a control input coupled to the power signal line 304 at node 414 and a blue light intensity data line Bit at node 440. B The data input is a latch 436 at node 442. The latch 436 has an output that is coupled to the input of μLED438 at node 444.

[0043] The operation of pixel 300 is summarized as follows. First, the three data bits of a multi-bit RGB data word are asserted simultaneously on the corresponding data line 302. Specifically, at the data line bit... r The first red position is asserted above, at the data line position. g The second green bit is asserted above, and on the data line Bit b The third blue bit is asserted. Then, on the power signal line 304, and via node 414, the power signal (e.g., digital high bit signal) is asserted on the control inputs of switches 406, 422, and 434. In response to the power signal being asserted on its control input, each of switches 406, 422, and 434 asserts a bit on its data input to its output. Thus, actuating switch 406 causes the bit... r The bit value is stored in latch 408. Similarly, actuation switch 422 causes the bit... g The bit value is stored in latch 424, and actuation switch 434 causes the bit to... b The bit value is stored in latch 436. When the enable signal on enable line 3041 terminates (e.g., goes low), the data bits latched in latches 408, 424 and 436 remain stored until a subsequent enable signal is asserted on enable signal line 304 to load the next bit.

[0044] The bit value stored in latch 408 is output to node 420, so that when the bit value is a high-power bit signal, both red μLEDs 410 and 412 are lit. On the other hand, when the bit value stored in latch 408 and output to μLEDs 410 and 412 is a low-power bit signal, both red μLEDs 410 and 412 will be off (e.g., dark). Similarly, the bit value stored in latch 424 is output to node 432, so that when the bit value stored in latch 424 is a high-power bit signal, green μLED 426 will be lit. However, if the bit value stored in latch 424 is a low-power bit signal, green μLED 426 will be off. The bit value stored in latch 436 is output to node 444, so that if the bit value stored in latch 436 is a high-power bit signal, blue μLED 438 will be lit. However, if the bit value stored in latch 436 is a low-power bit signal, the blue μLED 438 will be turned off.

[0045] Figure 5 This is a timing diagram 500 for driving the pixel array 208 according to an example offset driving scheme. It shows the relative time amounts of brightness and color displayed by each of the μLEDs 410, 426, and 438 in a given pixel 300. Compared to conventional driving schemes, this offset driving scheme allows for significantly higher accuracy in terms of the displayable pixel light intensity and / or color. The offset driving scheme also relaxes the speed requirements on the driving circuitry.

[0046] Example driving involves grouping the pixels of pixel array 208 into two or more groups and driving different groups at different times, even if different groups share the same data lines. Time offsets allow pixel data to be loaded into one group while the other group is in between data update times. The invention is not limited to any number of groups or how these groups are defined. For example, one group may include the upper half of a pixel row, while another group includes the remaining lower half of the pixel row. As another example, the first group may include an odd number of pixel rows, while the second group includes an even number of pixel rows.

[0047] In this example, 24-bit RGB video data is loaded into pixel array 208. Each 24-bit segment includes an 8-bit data word defining the red intensity level, an 8-bit data word defining the green intensity level, and an 8-bit data word defining the blue intensity level. The three 8-bit data words are combined to determine the color and brightness displayed by the pixel.

[0048] The example method uses a binary weighted bit scheme. More specifically, each 8-bit data word (b7, b6, b5, b4, b3, b2, b1, b0) is a binary number specifying an intensity value. The time during which all the data corresponding to a displayed image is asserted (once or multiple times) on the pixels of the display is called the frame time. The frame time can be divided into multiple equal time periods, and the importance of each bit of the binary number corresponds to multiple equal time periods in which a specific position will be displayed. In a particular binary weighting scheme, for example: bit b0 has 2... 0 The importance of bit b1 is displayed for a duration of 1 time period; bit b1 has 2 1 The importance of the position is shown for two consecutive time periods; b2 has 2 2 The importance of the bit is shown for four consecutive time periods; bit b3 has 2 3 The importance of the bit is displayed for a duration of 8 time periods; bit b4 has 2 4 The importance of the bit is displayed for a duration of 16 time periods; bit b5 has 2 5 The importance of the bit is displayed for a duration of 32 time periods; bit b6 has 2 6 The importance of the bit is shown, and it is displayed for a duration of 64 time periods; and bit b7 has 2 7 The importance of the bit is displayed for a duration of 128 time periods. Therefore, b0 is the least significant bit (LSB) with 1 / 256th of the intensity precision of the full intensity. In this particular driving scheme, each frame consists of 72 time periods.

[0049] In some cases, it is desirable to write the same data frame to the display multiple times within a single frame time. For example, in Figure 5 In the sequence shown, each bit is written to the display twice within a single frame time. Furthermore, as... Figure 5 As shown, the bit assertions are arranged to be temporally symmetrical about the center of the time frame. This "center-driven" scheme effectively reduces visual artifacts such as flicker and ghosting, but requires faster circuitry because at least twice the pixel load must occur within the frame time. Problems arise when the time period during which the least significant bit (LSB) must be displayed is too short to allow for pixel updates / data loading across all lines of the display. This problem is overcome by dividing the lines of the display into logical segments and loading data into the lines of those segments according to a sequence where the data loading in the lines of one segment (specifically the LSB) is inconsistent with the data loading in the lines of another segment.

[0050] The following example summarizes a process for loading a single video data frame into pixel array 208. As previously mentioned, pixel array 208 can be driven by 24-bit video data, which includes 8-bit data words for red intensity, 8-bit data words for green intensity, and 8-bit data words for blue intensity. However, the invention is not limited to displays driven by 8-bit data words. Instead, this driving scheme is applicable to other display systems using data words with more or fewer bits. To simplify the drawing and explanation of the example process, timing diagram 500 will depict the loading of a frame of 5-bit grayscale data.

[0051] like Figure 5 As shown, the rows of the display are logically grouped into row group (1) and row group (2). At time t0, bit b4 begins to be loaded row by row into row group (1) 502 in the order from pixel row 1 to pixel row 540 (1080 / 2 = 540). 4 The loading of the bits into row group (1) is completed before time t1. These b4 bits are latched for 16 time periods. At the same time t0, the low-power bit signal corresponding to the off state of the μLED has been loaded into row group 2 504 (at time t1 of the previous frame). 67 (Loading during the period). Then, at time t5, bit b4 is loaded row by row into row group 2 504 in the order from pixel row 541 to pixel row 1080. (The b4 bits are then loaded...) 4 The bits are loaded into the row of group (2) before time t6. These b4 bits are latched in row group 2 504 for 16 time periods.

[0052] The time difference between loading bit b4 into rows 502 of group (1) and 504 of group (2) can be considered a time "offset". In this case, the "offset" is 5 time intervals. It is worth noting that for a binary weighted data scheme, this offset of five time intervals ensures that the data load of subsequent bits in the row of group (1) 502 will not overlap with the data load of subsequent bits in the row of group (2) 504.

[0053] Next, at time t 16 Bit b3 is loaded sequentially into line (1)502 and displayed for 8 consecutive time intervals. At time t 21 Bit b3 begins loading into line (2)504 and is displayed for a duration of 8 time intervals. Then, at time t... 24 Bit b2 is loaded into line (1)502 and is displayed for four consecutive time periods. At time t 28 Bit b1 begins loading into line (1)502 and is displayed for two consecutive time periods. Next, at time t... 29Bit b2 is loaded into line (2)504 and is displayed for four consecutive time intervals. At time t 30 The b0 bit (LSB) begins loading into line (1)502 and is displayed for a duration of one LSB. Then, at time t... 31 The low voltage signal value corresponding to the off state begins to be loaded into the row of group (2) 502 and is displayed for 10 time periods. At time t 33 Bit b1 begins loading into line (2)504 and is displayed for two consecutive time periods. Next, at time t... 35 The b0 bit starts loading into the line of group (2)504 and is displayed for a period of 1 time.

[0054] Time t 36 The time center of the frame time is marked. At this point, bits b0-b4 (the complete data frame) have been displayed in descending order of importance in both group (1) 502 and group (2) 504. In the latter half of the frame time, all bits b0-b4 will be loaded and displayed again, but this time in ascending order of importance. As a result, the data will be displayed symmetrically in time about the center point of the frame time.

[0055] At time t 36 Bits b0 do not need to be reloaded into the row of group (2) 504 because they have already been loaded, and are only displayed for an additional time period of 1. Then, at time t 37 Bit b1 begins loading into line (2)504 and is displayed for two consecutive time periods. At time t 39 Bit b2 begins loading into line (2)504 and is displayed for four consecutive time periods. Next, at time t... 41 The b0 bit is loaded into line (1)502 and displayed for a duration of 1 time period. Then, at time t... 42 Bit b1 is loaded into line (1)502 and displayed for two time periods. Then, at time t 43 Bit b3 begins loading into line (2)504 and is displayed for a duration of 8 time intervals. At time t 44 Bit b2 is loaded into line (1)502 and displayed for four consecutive time periods. Next, at time t... 48 Bit b3 begins loading into line (1)502 and is displayed for a duration of 8 time intervals. At time t 51 Bit b4 is loaded into line (2)504 and is retained for 16 time intervals. Then, at time t 56The b4 bit is loaded into line (1)502 and is displayed for a duration of 16 time intervals. At time t 67 The low-power bit signal value (off state) begins to be loaded into the row of group 504 and is displayed for 10 time periods. When the b4 bit of the next frame is loaded into the row of group (2) 504, the 10 time periods continue and end at time t5 of the next frame. As described above, and Figure 5 As can be seen, there is no time overlap between the data loading of row group (1) 502 and row group (2) 504.

[0056] In this example, the off state (e.g., a dark pixel) is achieved by loading a low-power bit signal into the pixel. However, other types of displays may have different ways of "turning off" pixels. The processes and driving methods disclosed herein are compatible with any such different displays and can be used with any such different displays.

[0057] exist Figure 5 In the view, the leading edge of each bit duration slopes downwards to represent the finite loading time T that takes to sequentially load new data into all pixel rows of the corresponding row group. L As shown in the figure, the loading time T L Slightly less than the duration of a time interval, or in other words, slightly less than the LSB time T. LSB If the timing sequence of line group (2) 504 is not delayed / offset from the timing sequence of line group 504, then the LSB duration T LSB It will have to be significantly longer because the rows of group (1) 502 and group (2) 504 cannot be loaded during a single LSB time interval.

[0058] For example, consider time t30, where the LSB is loaded into the row of group (1) 502. If the row of group (2) 504 is also loaded during t30 (immediately after the loading of group (1) 502), then by time t31, the loading of group (2) 504 will not be complete. When the loading of the row of group (2) 504 is complete, the LSB will have been displayed for too long by the row of group (1) 502.

[0059] Figure 5Also shown are a first digital signal 506 and a second digital signal 508, which represent the same example data word (same intensity value) displayed by a row of pixels in group (1) 502 and a row of pixels in group (2) 504, respectively, but at an offset time. In this example, the data word is 01110, where b4 is the digit 0, b3 is 1, b2 is 1, b1 is 1, and b0 is 0. The intensity value of the example data word is 14. The 5-bit data word corresponds to 32 time intervals, and the offset is 5 time intervals. Therefore, because the 5-bit data word and the off state are displayed twice within the frame time, the frame time is divided into 72 equal time intervals.

[0060] Although signals 506 and 508 may look different, the resulting strengths are the same. Because the data word and the off state are displayed twice within the frame time, the voltage is high (V) for a total of 28 time periods (2 × 14) out of 72 time periods. H (Pixels open), while the voltage is low (V) in the other 44 time periods. L (Pixel off), with 10 time periods in the off state. The human eye will integrate the on state, so the intensity (01110) will show the same value no matter which group of rows displays this value.

[0061] The same number of off states should be introduced into the driving sequence of each row group. If additional logical groups of these rows are defined, more off states will be used to offset the driving sequences of those additional groups. However, each row group will use the same number of off states as the row group requiring the maximum offset. As described below, the distribution of those off states within the driving sequence of the respective rows will differ.

[0062] Introducing off states to accommodate the offset between line groups results in a loss of optical efficiency. For example, because the off states corresponding to the offset occupy a total of 10 time slots (5 in the first half of the frame time and 5 in the second half), the maximum possible intensity represented by data word 11111 will result in 62 (2×31) of the 72 time slots being on. To accommodate this loss of optical efficiency... The current supplied to the μLED can be increased. The optical efficiency of data words of different lengths will be referenced in the upcoming... Figure 7 Further detailed discussion.

[0063] When selecting the number of time intervals to offset the loading of row group (2) 504 from the loading of row group (1) 502, certain unique offset amounts will prevent the time intervals in which bits are loaded into row group (1) 502 from being the same as the time intervals in which bits are loaded into row group (2) 504. For example, by offsetting row group 504 from row group 502 by 5 time intervals, the times when new data is loaded into rows of group (1) 502 (i.e., t0, t16, t24, t28, t30, t31, t41, t42, t44, t48, and t56) do not overlap or coincide with the times when new data is loaded into rows of group (2) 504 (i.e., t5, t21, t29, t33, t35, t36, t37, t39, t43, t51, and t67). On the other hand, if row group 504 is offset from row group 502 by multiple time intervals other than these unique numbers, then the time interval in which new data is loaded into rows of group (1) 502 will overlap at least once with the time interval in which new data is loaded into rows of group (2) 504. As mentioned earlier, due to the LSB time constraint, it is expected that these times should not overlap.

[0064] It should also be noted that data bits can be loaded into each segment in the same order (e.g., b4, b3, b2, b1, b0, b0, b1, b2, b3, b4). In existing systems, more complex bit ordering is used in an attempt to accommodate shorter LSB times.

[0065] Figure 6 Table 600 compares the time it takes to load the binary pulse width modulation (PWM) sequence of these bits without offset with the time it takes to load the binary PWM sequence of these bits with various offset values. As shown, no overlap occurs when the offset values ​​are 0, 5, 10, 23, 43, 52, 77, and 88. Table 600 also shows the offset values ​​for different numbers of pixel groups. For example, to define four logical pixel row groups for a display, the first pixel row group will have no offset, the second pixel row group can be offset by 5 time intervals, the third pixel row group can be offset by 10 time intervals, and the fourth pixel row group can be offset by 23 time intervals.

[0066] The row group # identifies a logical group of rows, but does not necessarily specify the sequence or number of defined row groups. For example, the rows of a display could be divided into three groups, where group 1 has no offset, group 2 is offset by 10, and group 3 is offset by 52. ​​In this case, there would be no overlap when updating rows in the group. However, as will be explained below, there would be an unnecessarily large loss in optical efficiency. For efficiency, once the number of row groups is determined, it is preferable to use row groups with the smallest offset.

[0067] Figure 7This is an example timing diagram 700 summarizing the use of multiple logically defined pixel row groups to write data frames to the display. Initially, at time t0, data from row group 1 begins to be displayed. Once the data from pixel row group 1 is complete, the pixels in row group 1 display the off states for a total of (x) off states. As used herein, the number of off states refers to the number of time intervals during which pixels are off.

[0068] The total number of closed states (for each half of the frame time) is determined based on the number of defined logical line groups. Specifically, the total number of closed states is chosen to be equal to the offset of the line with the largest offset. Therefore, according to... Figure 6 In Table 600, if two row groups are defined, the total number of closed states will be 5. If four row groups are defined, the total number of closed states will be 23. If seven row groups are defined, the total number of closed states will be 77, and so on.

[0069] After the midpoint of frame time 702, the same number of pixels in row group 1 are displayed in the off state, and then the data in row group 1 is displayed again. During the second display of the data in row group 1, the data is rearranged to maintain temporal symmetry about the midpoint 702. For example, in the first half of the frame time, the data bits can be displayed in descending order of importance. Then, in the second half of the frame time, the data bits can be displayed in ascending order of importance.

[0070] The sequence of row group 2 consists of multiple boot off states (L) corresponding to the required offset of row group 2. 关闭 Begin with ) Since row group 2 is the second defined group of these rows, therefore according to Figure 6 In Table 600, the number of guided off states in row group 2 is 5. After displaying the data in row group 2, the pixels in row group 2 display multiple after-off states T. 关闭 (that is, T) 关闭 (Closed state of the time period). For row group 2, T 关闭 =x–L 关闭 = x - 5. As mentioned above, m depends on the total number of pixel row groups for a given display. For example, if there are 4 pixel row groups, then x = 23, which will also be the number of off states for each pixel row group. If x = 23, then T for pixel row group 2 关闭 Will be T 关闭 =x–L 关闭 =23-5=18. Therefore, T of pixel row group 3 关闭 Will be T 关闭 =xP 关闭 =23-10=13.

[0071] The sequence for row group 3 begins by displaying multiple guided off states, proceeds to displaying pixel data, and then displays multiple subsequent off states. For row group 3, according to Table 600, the number of guided off states is 10. Therefore, if the total number of off states x = 23, the number of subsequent off states will be 13 (23-10).

[0072] The sequence of line group (y) begins by displaying the maximum number of boot shutdown states (x). x boot shutdown states are displayed, followed by pixel data, ending at the midpoint of frame time 702. The sequence of line group (y) does not include any subsequent shutdown states.

[0073] For each line group 1-y, the display sequence in the latter half of the frame time is the reverse of the display sequence in the first half of the frame time. As described above, the reverse sequence is used in the latter half of the frame time to maintain temporal symmetry about the midpoint 702. Furthermore, the sequence for each line group includes the same number of off states.

[0074] Figure 8 Timing diagram 800 shows a specific example drive sequence for an 8-bit system. In this particular example, four logical row groups are defined. According to... Figure 6 In Table 600, the offset of group 1 is 0, the offset of group 2 is 5, the offset of group 3 is 10, and the offset of group 4 is 23. Because group 4 has the largest offset, the total number of closed states in each row will be 23.

[0075] The sequence for line group 1 begins at time t0, displaying pixel data for 255 time intervals, followed by 23 off states until the midpoint of the frame time. Then, in the latter half of the frame time, the same sequence for line group 1 is displayed in reverse order. The sequence for line group 2 begins at time t0, displaying off states for 5 time intervals, then proceeding to display the pixel data for line group 2 for 255 time intervals, followed by another 18 (23-5) time intervals of off states until the midpoint of the frame time. Then, in the latter half of the frame time, the same sequence for line group 2 is displayed in reverse order. The sequence for line group 3 begins at time t0, displaying off states for 10 time intervals. Then, the pixel data for line group 3 is displayed for the next 255 time intervals. After displaying the pixel data, the off states are displayed again for 13 (23-10) time intervals until the midpoint of the frame time. Then, in the latter half of the frame time, the same sequence for line group 3 is displayed in reverse order. Finally, for line group 4, the off state begins at time t0 and lasts for 23 time intervals. Then, the pixel data for line group 4 is displayed over the next 255 time intervals until the midpoint of the frame time. Then, in the latter half of the frame time, the same sequence of line group 4 is displayed in reverse order.

[0076] Figure 9 Table 900 combines offset values, group numbers, and optical efficiency for both 8-bit and 10-bit display systems. When using offset or "off" values ​​in a driving scheme, efficiency loss is unavoidable. For example, if a single display has only one pixel group, no offset is used, and therefore no efficiency is lost. On the other hand, if the display has multiple pixel rows with offsets, the off state causes a slight decrease in optical efficiency because some time periods are always off. Efficiency is calculated as the maximum number of time periods that can be "on" divided by the total number of time periods. For example, in an 8-bit system with three pixel rows, there are a total of 255 time periods and 10 time periods that are always off. Of the total 265 (255+10) time periods, only 255 can be lit. Therefore, the efficiency is 255 / 265 = 96.23%. To accommodate this efficiency decrease, the inventors have discovered that increasing the current in the diodes can achieve an acceptable gain in illumination intensity.

[0077] Table 900 is useful in determining a good trade-off between the number of row groups to use and efficiency. The more row groups, the higher the bit depth, color precision, and intensity precision. However, increasing the number of row groups comes at the cost of efficiency. The inventors found that approximately 95% efficiency is acceptable, at least in part because the output of the μLED can be slightly increased by increasing the current through it. Therefore, for a 10-bit system, 5 or 6 logic row groups are a good trade-off. On the other hand, for an 8-bit system, 3 logic row groups are a good trade-off.

[0078] Figure 10This is a flowchart 1000 summarizing a method for driving a digital display. In the first step 1002, a frame time is defined. In the second step 1004, a multi-bit data frame to be written to the display during the frame time is received. Then, in the third step 1006, the frame time is divided into multiple equal intervals, the number of equal intervals being greater than the number of different intensity values ​​that can be defined for the multi-bit data. Next, in the fourth step 1008, the rows of the display are arranged / organized into multiple groups. Then, in the fifth step 1010, multiple off states (time intervals of pixel darkness) to be displayed along with the multi-bit data during the frame time are determined. The number of off states is determined based on the number of groups into which the rows are arranged. Next, in the sixth step 1012, a first sequence is defined for displaying the multi-bit data and the determined number of off states on the first row group. This first sequence begins with the assertion of the bits of the multi-bit data word. Then, in the seventh step 1014, a second sequence is defined for displaying the multi-bit data and the determined number of off states on the second row group. The second sequence begins by asserting a first non-zero number of off states (i.e., asserting the off state for the time interval of the first non-zero value) and ends with a second non-zero value of off states. Next, in step 1016 of the eighth step, a third sequence is defined for displaying multiple bits of data and the determined number of off states on the third row group. The third sequence begins with the number of off states determined in step 1010 of the fifth step. In step 1018 of the ninth step, multiple bits of data and off states are asserted on the pixels of the display according to the first, second, and third sequences. These sequences are defined such that during each time interval of the frame time, data is written to a row that does not exceed a single row in the row group.

[0079] The description of specific embodiments of the invention is now complete. Many of the described features may be substituted, changed, or omitted without departing from the scope of the invention. For example, other types of digital displays (e.g., liquid crystal displays, monochrome displays, etc.) may replace the μLED display. As another example, the pixel array may include different circuitry for loading data bits and / or turning off states. As yet another example, although the example embodiments include multi-color pixels, the methods described herein are also advantageous in grayscale displays. As yet another example, in the illustrated driving scheme, each multi-bit data word is written twice during the frame time (symmetric about the time center of the frame time). However, a data word can only be written once during each frame time, provided that the loading of each segment is not consistent with the loading of another segment. These and other modifications to the specific embodiments shown will be readily apparent to those skilled in the art, especially in light of the prior disclosure.

Claims

1. A method for driving a digital display comprising a plurality of pixels arranged in multiple rows, the method comprising: Receive a data frame that will be written to the digital display during a predefined frame time. The data frame includes a multi-bit data word corresponding to each pixel of the display. Each multi-bit data word includes multiple individual bits. Each bit has a weight corresponding to the amount of time that bit should be displayed by the corresponding pixel. Each multi-bit data word can define a maximum number of different intensity values. The frame time is divided into a total number of time intervals, the total number of time intervals being greater than the maximum number of different intensity values; Define the first row set of the display; Define the second row set of the display; Define a first sequence for displaying a corresponding multi-bit data word and one or more off states through the rows in the first set of rows, the first sequence starting with the bit that displays the multi-bit data word; A second sequence is defined for displaying corresponding multi-bit data words and one or more off states on the rows in the second set of rows, the second sequence starting with the display of an initial off state, and the first sequence and the second sequence starting during the same time interval of the plurality of time intervals; as well as The data frame and the off state are displayed on the display according to the first sequence and the second sequence; as well as in The number of time intervals during which the off state is asserted on pixels of the first row set during the first sequence is the same as the number of time intervals during which the off state is asserted on pixels of the second row set during the second sequence.

2. The method according to claim 1, wherein: The multi-bit data word is a binary weighted data word; and The duration of the initial off state of the second sequence is equal to 5, 10, 23, 43, 52, 77 or 88 of the time intervals.

3. The method according to claim 2, wherein, The duration of the initial off state of the second sequence is equal to 5 of the time intervals.

4. The method according to claim 1, wherein: The first sequence includes loading data into the pixels of the first row set during the first set of time intervals; The second sequence includes loading data into the pixels of the second row set during the second set of time intervals; as well as The time intervals in the first group and the time intervals in the second group are mutually exclusive.

5. The method according to claim 1, wherein: The first sequence includes loading the data bits of the multi-bit data word into the pixel in descending order of bit importance, loading the off state into the pixel, and then reloading the bits of the multi-bit data word into the pixel in ascending order of bit importance; as well as The second sequence includes sequentially loading a first off state into the pixel, loading the data bits of the multi-bit data word into the pixel in descending order of bit importance, reloading the bits of the multi-bit data word into the pixel in ascending order of bit importance, and then loading a second off state into the pixel.

6. The method according to claim 5, wherein, The duration of the off state in the first sequence is equal to the sum of the durations of the first off state and the second off state in the second sequence.

7. The method according to claim 1, wherein: The first sequence includes the first element that is displayed for a first time period; The second sequence includes a second position displayed during at least a portion of the first time period; and The second sequence includes a third position displayed during at least a portion of the first time period.

8. The method according to claim 7, wherein, The second sequence includes a fourth position displayed during at least a portion of the first time period.

9. The method according to claim 8, wherein: The third position is displayed for a continuous second time period; The second time period begins after the first time period begins; and The second time period ends before the first time period ends.

10. The method according to claim 1, further comprising: Define one or more additional row sets for the display; Assert that the off state persists for the same number of time intervals on the pixels of each row in each row set; as well as The same number of time intervals are determined based on the total number of rows in the defined set.

11. The method of claim 10, wherein: Define exactly 3 sets of rows, and assert that the time interval for the closed state to last for the same number of times is 10; We define exactly 4 sets of rows and assert that the time interval for the closed state to last for the same number of times is 23; Define exactly 5 row sets, and assert that the closed state persists for the same number of time intervals, which is 43. We define exactly 6 sets of rows and assert that the same number of time intervals during which the closed state persists are 52. Define exactly 7 rows and assert that the off state persists for the same number of time intervals, which is 77; or We define exactly 8 row sets and assert that the closed state persists for the same number of time intervals, which is 88.

12. The method according to claim 1, further comprising: Define multiple additional row sets; and among them During each of the aforementioned time intervals, data is written to no more than one set of rows.

13. A method for displaying data on a display comprising a plurality of pixels arranged in multiple rows, the method comprising: Receive a data frame that will be written to the display during a predefined frame time. The data frame includes a multi-bit data word corresponding to each pixel of the display. Each multi-bit data word includes multiple individual bits. Each bit has a weight corresponding to the amount of time that bit should be displayed by the corresponding pixel. Each multi-bit data word can define a maximum number of different intensity values. The frame time is divided into a total number of time intervals, the total number of time intervals being greater than the maximum number of intensity values; Define multiple sets of the rows; and A different update sequence is defined for each of the rows in the plurality of groups, each of the update sequences defining a specific time interval and other time intervals in the time interval, during which the pixel of the row in the associated group will be updated bit by bit of the plurality of data words, and during the other time intervals, the pixel of the row in the associated group will be updated in a closed state; as well as According to the different update sequences, the data frame and the off state are displayed on the display; and wherein... During each specific time interval of the time interval, pixels in no more than one set of rows will be updated, where: The first update sequence associated with the first group of the row begins by sequentially asserting the bits of the multi-bit data word and ends by asserting the off state for a predetermined number of time intervals, the number of time intervals for which each bit is asserted corresponding to the importance of the asserted bit; The second update sequence associated with the second group of the rows begins with an assertion-off state lasting the predetermined number of time intervals and ends with sequential assertions of the bits of the multi-bit data word, the number of time intervals for which each bit is asserted corresponding to the importance of the asserted bit; and The third update sequence associated with the third group of the row begins with the assertion off state lasting for an initial number of time intervals, proceeds to sequentially asserting the bits of the multi-bit data word, and ends with the assertion off state lasting for a tail number of time intervals, the number of time intervals for which each bit is asserted corresponding to the importance of the asserted bit.

14. The method of claim 13, wherein: The predetermined number of time intervals depends on the number of groups in the plurality of groups; as well as The sum of the initial number of the closed states and the last digit of the closed states is equal to the predetermined number of the closed states.

15. The method of claim 14, wherein: The additional multiple update sequences are associated with additional multiple sets of rows, each update sequence starting with the time interval for a unique initial number of assertion-off states, proceeding to the sequential assertion of the bits of the multiple data words, and ending with the time interval for a unique last number of assertion-off states, the number of time intervals for which each bit is asserted corresponds to the importance of the asserted bit. as well as For each of the additional plurality of update sequences, the sum of the unique initial number of the time interval and the unique tail number of the time interval is equal to the predetermined number of the off states.

16. A display system, comprising: A display comprising a plurality of pixels arranged in multiple rows; A frame buffer is used to receive data frames and provide the data to the pixels of the display in response to a control signal. The data frame includes a multi-bit data word corresponding to each pixel of the display. Each multi-bit data word includes multiple individual bits, each bit having a weight corresponding to the amount of time the bit should be displayed by the corresponding pixel. Each multi-bit data word can define a maximum number of different intensity values. Configuration data, which defines frame time as a total number of time intervals, the total number of time intervals being greater than the maximum number of different intensity values; defines a first row set for the display; defines a second row set for the display; A first sequence is defined for displaying a corresponding multi-bit data word and one or more off states through the rows of the first set of rows, the first sequence starting with the bit that displays the multi-bit data word; And define a second sequence for displaying corresponding multi-bit data words and one or more off states on the rows of the second row set, the second sequence starting with displaying an initial off state, the first sequence and the second sequence starting during the same time interval of the plurality of time intervals; as well as A controller configured to generate control signals and coupled to provide the control signals to the frame buffer and the display, the control signals causing the data frame and a shutdown state to be transmitted to the pixels of the display according to the first sequence and the second sequence; and in The configuration data defines one or more additional row sets for the display; The configuration data defines the total number of time intervals in each sequence for which the off state is to be asserted to persist, the total number of time intervals depending on the total number of rows in the set; The configuration data defines an additional unique sequence for asserting the data and closed state on each additional row set. Each additional unique sequence begins with the time interval for asserting the closed state to remain unique for an initial number of times, proceeds to asserting the bits of the multiple data words sequentially, and ends with the time interval for asserting the closed state to remain unique for a last number of times. The number of time intervals for which each bit is asserted corresponds to the importance of the bit being asserted. as well as For each additional unique sequence, the sum of the unique initial number of the time intervals and the unique tail number of the time intervals is equal to the total number of time intervals for which the off state is to be asserted in each sequence.

17. The display system according to claim 16, wherein: The multi-bit data word is a binary weighted data word; and The duration of the initial off state of the second sequence is equal to 5, 10, 23, 43, 52, 77 or 88 of the time intervals.

18. The display system according to claim 17, wherein, The duration of the initial off state of the second sequence is equal to 5 of the time intervals.

19. A method for driving a digital display comprising a plurality of pixels arranged in multiple rows, the method comprising: Receive a data frame that will be written to the digital display during a predefined frame time. The data frame includes a multi-bit data word corresponding to each pixel of the display. Each multi-bit data word includes multiple individual bits. Each bit has a weight corresponding to the amount of time that bit should be displayed by the corresponding pixel. Each multi-bit data word can define a maximum number of different intensity values. The frame time is divided into a total number of time intervals, the total number of time intervals being greater than the maximum number of different intensity values; Define the first row set of the display; Define the second row set of the display; Define a first sequence for displaying a corresponding multi-bit data word and one or more off states through the rows in the first set of rows, the first sequence starting with the bit that displays the multi-bit data word; A second sequence is defined for displaying corresponding multi-bit data words and one or more off states on the rows in the second set of rows, the second sequence starting with the display of an initial off state, and the first sequence and the second sequence starting during the same time interval of the plurality of time intervals; as well as The data frame and the off state are displayed on the display according to the first sequence and the second sequence; and wherein... The first sequence includes the first element that displays a duration of a first time period; The second sequence includes a second position displayed during at least a portion of the first time period; and The second sequence includes a third position displayed during at least a portion of the first time period, wherein The number of time intervals during which the off state is asserted on pixels of the first row set during the first sequence is the same as the number of time intervals during which the off state is asserted on pixels of the second row set during the second sequence.

20. A method for driving a digital display comprising a plurality of pixels arranged in multiple rows, the method comprising: Receive a data frame that will be written to the digital display during a predefined frame time. The data frame includes a multi-bit data word corresponding to each pixel of the display. Each multi-bit data word includes multiple individual bits. Each bit has a weight corresponding to the amount of time that bit should be displayed by the corresponding pixel. Each multi-bit data word can define a maximum number of different intensity values. The frame time is divided into a total number of time intervals, the total number of time intervals being greater than the maximum number of different intensity values; Define the first row set of the display; Define the second row set of the display; Define one or more additional row sets for the display; Define a first sequence for displaying a corresponding multi-bit data word and one or more off states through the rows in the first set of rows, the first sequence starting with the bit that displays the multi-bit data word; A second sequence is defined for displaying corresponding multi-bit data words and one or more off states on the rows in the second set of rows, the second sequence starting with the display of an initial off state, and the first sequence and the second sequence starting during the same time interval of the plurality of time intervals; Define one or more additional sequences for displaying corresponding multi-digit data words and one or more off states on the rows of the one or more additional row sets; The time interval of the same number is determined based on the total number of rows in the defined row set; as well as By asserting that the off state persists for the same number of time intervals on the pixels of each row in the row set, the data frame and the off state are displayed on the display according to the first sequence, the second sequence, and the one or more additional sequences.

Images