A red light mini LED epitaxial structure, chip and manufacturing method thereof

Abstract

The application provides a red light Mini LED epitaxial structure, a chip and a manufacturing method thereof. The Mini LED epitaxial structure comprises a stacked structure, and the stacked structure comprises a first type semiconductor layer, a first interface layer, a first waveguide layer, an active region, a second waveguide layer, a second interface layer and a second type semiconductor layer which are sequentially stacked. The first interface layer can avoid the roughening of the interface between the first type confinement layer and the first waveguide layer caused by the diffusion of the dopant of the first type semiconductor layer. The second interface layer can avoid the roughening of the interface between the second type confinement layer and the second waveguide layer caused by the diffusion of the dopant of the second type semiconductor layer. Meanwhile, the diffusion of the dopant of the first type semiconductor layer and the second type semiconductor layer to the active region to form non-radiative recombination centers and cause the problem of reduced reliability can be avoided. In addition, the first interface, the first waveguide layer, the second waveguide layer and the second interface layer all comprise a semiconductor material layer without doping, so that the crystal quality of the active region can be effectively improved, and the internal quantum efficiency and the light output power are improved.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and more specifically, to a red Mini LED epitaxial structure, chip, and fabrication method thereof. Background Technology

[0002] With the rapid development of light-emitting diodes (LEDs), their applications are changing rapidly, especially in display technology. As the resolution of LED displays increases, the size and spacing of LED chips are becoming smaller and smaller.

[0003] Compared to current LCD and OLED displays, Mini-LED devices offer advantages such as faster response, wider color gamut, higher PPI, and lower power consumption. Currently, Mini-LED devices are used as backlights in displays, with the optimal effect achieved through the mixing of RGB Mini-LED chips in their three primary colors. Conventional designs typically use encapsulation at the packaging end. However, with prolonged use, the color mixing effect of existing RGB Mini-LED chips deteriorates, primarily due to the brightness decay of the red Mini-LED chip, leading to a decline in display quality. High doping of the P-type confinement layer in red Mini-LED chips can raise the quasi-Fermi level position of the P-type confinement layer, increasing the effective barrier against leakage electrons and helping to reduce the threshold current. However, high doping concentrations in the P-confinement layer can cause dopant diffusion, leading to coarsening of the interface between the confinement layer and the waveguide layer, and the formation of non-radiative recombination centers in the active region, resulting in reduced reliability. Furthermore, the metal materials of the electrodes and mirrors in red Mini-LED chips are prone to migration to the active region, causing aging and severe brightness decay. Summary of the Invention

[0004] In view of this, the present invention provides a red Mini LED epitaxial structure, chip and its fabrication method to solve the problems in the prior art, such as the coarsening of the interface between the confinement layer and the waveguide layer caused by dopant diffusion, the formation of non-radiative recombination centers in the active region, resulting in reduced reliability; and the easy migration of metal materials such as electrodes and mirrors of the chip to the active region, leading to chip aging and severe brightness decay.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A red-light Mini LED epitaxial structure includes:

[0007] Growth substrate;

[0008] A buffer layer, an etching stop layer, and a stacked structure are sequentially stacked on the growth substrate. The stacked structure includes a first type semiconductor layer, a first interface layer, a first waveguide layer, an active region, a second waveguide layer, a second interface layer, and a second type semiconductor layer, sequentially stacked along a first direction. The first interface layer and the second interface layer are used to block dopant diffusion and metal migration. The first direction is perpendicular to the growth substrate and extends from the growth substrate to the stacked structure.

[0009] Wherein, the first type of semiconductor layer includes a first type of ohmic contact layer, a first type of current spreading layer and a first type of confinement layer stacked sequentially along the first direction; the second type of semiconductor layer includes a second type of confinement layer, a second type of current spreading layer and a second type of ohmic contact layer stacked sequentially along the first direction;

[0010] The first interface layer, the first waveguide layer, the second waveguide layer, and the second interface layer all include undoped semiconductor material layers.

[0011] Preferably, the thickness of the first interface layer increases with the doping concentration of the first type of confinement layer; the thickness of the second interface layer increases with the doping concentration of the second type of confinement layer.

[0012] Preferably, the thickness of the first interface layer is H1, then 1nm < H1 < 50nm; the thickness of the second interface layer is H2, then 1nm < H2 < 50nm.

[0013] Preferably, the first type semiconductor layer is an N-type semiconductor layer, the second type semiconductor layer is a P-type semiconductor layer, the first type confinement layer is an N-type confinement layer, the second confinement layer is a highly doped P-type confinement layer, the doping concentration of the P-type confinement layer is higher than the doping concentration of the N-type confinement layer, and the thickness of the second interface layer is greater than the thickness of the first interface layer.

[0014] Alternatively, the first type semiconductor layer is a P-type semiconductor layer, the second type semiconductor layer is an N-type semiconductor layer, the first type confinement layer is a highly doped P-type confinement layer, the second type confinement layer is an N-type confinement layer, the doping concentration of the P-type confinement layer is higher than the doping concentration of the N-type confinement layer, and the thickness of the first interface layer is greater than the thickness of the second interface layer.

[0015] Preferably, the first interface layer comprises undoped Al x1 Ga y1 In z1 A P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, 0 < z1 ≤ 1; the first waveguide layer comprises undoped Al. x2 Ga y2 In z2P material layer, wherein 0 < x2 ≤ 1, 0 < y2 ≤ 1, 0 < z2 ≤ 1; the first type of confinement layer includes Al x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

[0016] Preferably, the second interface layer comprises undoped Al x1 Ga y1 In z1 The first waveguide layer comprises a P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, and 0 < z1 ≤ 1; the second waveguide layer comprises undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x² ≤ 1, 0 < y² ≤ 1, 0 < z² ≤ 1; the second type confinement layer includes Al. x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

[0017] A red Mini LED chip, comprising:

[0018] The stacking structure described in any of the above items;

[0019] A transparent conductive layer, a transparent adhesive layer, and a transparent substrate are sequentially stacked on the side surface of the first type semiconductor layer that is away from the first interface layer.

[0020] A reflector is disposed on the side surface of the second type semiconductor layer opposite to the second interface layer;

[0021] The upper surface of the reflector is provided with a groove extending toward the first type of current spreading layer, and a portion of the first type of current spreading layer is exposed.

[0022] The upper surface edge of the reflector has a groove extending toward the transparent substrate and exposing the transparent substrate, the groove surrounding the stacked structure;

[0023] An insulating layer covers the exposed surfaces of the reflector, the stacked structure, the transparent conductive layer, and the transparent adhesive layer, and exposes the bottom of the groove. The insulating layer has a second electrode conductive via that exposes a portion of the reflector.

[0024] The first electrode is disposed on the side surface of the insulating layer opposite to the reflector and extends to the exposed portion of the groove, forming an electrical connection with the first type of current spreading layer.

[0025] The second electrode is disposed on the side surface of the insulating layer opposite to the reflector and extends to the conductive via of the second electrode, forming an electrical connection with the reflector, and the first electrode and the second electrode are disposed at intervals.

[0026] This invention also provides a method for manufacturing a red Mini LED chip, the method comprising the following steps:

[0027] Step 01: Provide a growth substrate;

[0028] Step 02: A buffer layer, an etch stop layer, and a stacked structure are sequentially grown on the surface of the growth substrate;

[0029] The stacked structure includes a first type semiconductor layer, a first interface layer, a first waveguide layer, an active region, a second waveguide layer, a second interface layer, and a second type semiconductor layer stacked sequentially along the growth direction; the first interface layer and the second interface layer are used to block dopant diffusion and metal material migration.

[0030] The first type semiconductor layer includes a first type ohmic contact layer, a first type current spreading layer, and a first type confinement layer stacked sequentially along the growth direction; the second type semiconductor layer includes a second type confinement layer, a second type current spreading layer, and a second type ohmic contact layer stacked sequentially along the growth direction.

[0031] The first interface layer, the first waveguide layer, the second waveguide layer, and the second interface layer all include undoped semiconductor material layers;

[0032] Step 03: Peel off the growth substrate, the buffer layer, and the etching stop layer to expose the first type of semiconductor layer;

[0033] Step 04: Grow a transparent conductive layer on the side of the first type of semiconductor layer that is away from the first interface layer;

[0034] Step 05: Fix the chip structure formed in step 04 to the transparent substrate using a transparent adhesive layer, wherein the transparent adhesive layer is formed on the side surface of the transparent conductive layer that is away from the first type of semiconductor layer.

[0035] Step 06: Grow a reflective mirror on the surface of the second type semiconductor layer that is opposite to the second interface layer;

[0036] Step 07: Using an etching process, etch along the upper surface of the reflector to expose part of the first type of current spreading layer, forming a groove;

[0037] Simultaneously, the transparent substrate is exposed by etching along the edge of the upper surface of the mirror, forming a trench that surrounds the stacked structure;

[0038] Step 08: Deposit an insulating layer, which covers the exposed surfaces of the reflector, stacked structure, transparent conductive layer and transparent adhesive layer, and pattern the insulating layer to form a second electrode conductive via on the exposed portion of the reflector surface, and expose the bottom of the groove;

[0039] Step 09: Fabricate the first and second electrodes;

[0040] The first electrode is disposed on the side surface of the insulating layer opposite to the reflector and extends to the exposed portion of the groove, forming an electrical connection with the first type of current spreading layer;

[0041] The second electrode is disposed on the side surface of the insulating layer opposite to the reflector and extends to the conductive via of the second electrode, forming an electrical connection with the reflector, and the first electrode and the second electrode are disposed at intervals.

[0042] Preferably, the thickness of the first interface layer increases with the doping concentration of the first type of confinement layer; the thickness of the second interface layer increases with the doping concentration of the second type of confinement layer.

[0043] Preferably, the thickness of the first interface layer is H1, then 1nm < H1 < 50nm; the thickness of the second interface layer is H2, then 1nm < H2 < 50nm.

[0044] Preferably, the first type semiconductor layer is an N-type semiconductor layer, the second type semiconductor layer is a P-type semiconductor layer, the first type confinement layer is an N-type confinement layer, the second confinement layer is a highly doped P-type confinement layer, the doping concentration of the P-type confinement layer is higher than the doping concentration of the N-type confinement layer, and the thickness of the second interface layer is greater than the thickness of the first interface layer.

[0045] Alternatively, the first type semiconductor layer is a P-type semiconductor layer, the second type semiconductor layer is an N-type semiconductor layer, the first type confinement layer is a highly doped P-type confinement layer, the second type confinement layer is an N-type confinement layer, the doping concentration of the P-type confinement layer is higher than the doping concentration of the N-type confinement layer, and the thickness of the first interface layer is greater than the thickness of the second interface layer.

[0046] Preferably, the first interface layer comprises undoped Al x1 Ga y1 In z1A P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, 0 < z1 ≤ 1; the first waveguide layer comprises undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x2 ≤ 1, 0 < y2 ≤ 1, 0 < z2 ≤ 1; the first type of confinement layer includes Al x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

[0047] Preferably, the second interface layer comprises undoped Al x1 Ga y1 In z1 The first waveguide layer comprises a P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, and 0 < z1 ≤ 1; the second waveguide layer comprises undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x² ≤ 1, 0 < y² ≤ 1, 0 < z² ≤ 1; the second type confinement layer includes Al. x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

[0048] An RGB Mini LED chip, comprising:

[0049] The red Mini LED chip described in any of the above items.

[0050] The above technical solution achieves the following results:

[0051] 1. The present invention provides a red Mini LED epitaxial structure, which, through a stacked structure, includes a first type semiconductor layer, a first interface layer, a first waveguide layer, an active region, a second waveguide layer, a second interface layer, and a second type semiconductor layer stacked sequentially along a first direction; the first interface layer and the second interface layer are used to block dopant diffusion and metal material migration; the first interface layer can prevent dopant diffusion in the first type semiconductor layer from causing roughening of the interface between the first type confinement layer and the first waveguide layer; the second interface layer can prevent dopant diffusion in the second type semiconductor layer from causing roughening of the interface between the second confinement layer and the second waveguide layer; at the same time, it can also prevent dopant diffusion in the first type semiconductor layer and the second type semiconductor layer to the active region to form non-radiative recombination centers, which would lead to a decrease in reliability; and the first interface, the first waveguide layer, the second waveguide layer, and the second interface layer all include undoped semiconductor material layers, which can form different material interfaces, further blocking dopant diffusion to the active region, reducing the influence of dopant on the growth interface of the active region, effectively improving the crystal quality of the active region, and thus improving the internal quantum efficiency and light output power.

[0052] 2. Furthermore, the thickness of the first interface layer is set to increase with the doping concentration of the first type confinement layer; the thickness of the second interface layer is set to increase with the doping concentration of the second type confinement layer, so that the first interface layer and the second interface layer can play a better blocking effect.

[0053] 3. Furthermore, the thickness of the first interface layer is set to H1, then 1nm < H1 < 50nm; the thickness of the second interface layer is set to H2, then 1nm < H2 < 50nm. This avoids the problem that the recombination efficiency of holes and electrons in the active region will decrease if the thickness of the first and second interface layers is too thick, while the thickness will not play a blocking effect if the thickness is too thin, thereby further improving the internal quantum efficiency and optical output power.

[0054] 4. The red Mini LED chip provided by this invention, by using the aforementioned red Mini LED epitaxial structure in conjunction with a transparent conductive layer, a transparent adhesive layer, a transparent substrate, a reflector, an insulating layer, and electrodes, can effectively solve the problem of reduced reliability caused by dopant diffusion leading to roughening of the interface between the confinement layer and the waveguide layer, and the formation of non-radiative recombination centers in the active region. Furthermore, the first and second interface layers can also prevent the metal materials of the chip's electrodes and reflectors from migrating to the active region, avoiding chip aging and severe brightness decay, thereby improving the luminous efficiency and reliability of the red Mini LED chip.

[0055] 5. The method for fabricating a red Mini LED chip provided by this invention can effectively solve the problems of reduced reliability caused by the diffusion of dopants in the red Mini LED chip leading to roughening of the interface between the confinement layer and the waveguide layer, and the formation of non-radiative recombination centers in the active region; and the easy migration of metal materials such as electrodes and mirrors of the chip to the active region, leading to chip aging and severe brightness decay. This method improves the luminous efficiency and reliability of the red Mini LED chip.

[0056] 6. The RGB Mini LED chip provided by this invention, by using the aforementioned red Mini LED chip, can effectively solve the problem of deteriorating display effect due to the brightness decay of the red Mini LED chip, resulting in poor color mixing effect after long use of the RGB Mini LED chip, thereby improving the brightness uniformity of the three primary colors of the RGB Mini LED chip. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0058] Figure 1 This is a schematic diagram of a red Mini LED epitaxial structure provided in an embodiment of the present invention;

[0059] Figures 2.1 to 2.2 This is a schematic diagram of a red Mini-LED chip structure provided in an embodiment of the present invention;

[0060] Figures 3.1 to 3.9 This is a schematic diagram of the structure corresponding to each step of the method for manufacturing a red Mini LED chip provided in an embodiment of the present invention;

[0061] Explanation of symbols in the diagram:

[0062] 01. Growth substrate; 02. Buffer layer; 03. Etching stop layer;

[0063] 1. Transparent substrate; 2. Transparent adhesion layer; 3. Transparent conductive layer; 4. Type I semiconductor layer; 41. Type I ohmic contact layer; 42. Type I current spreading layer; 43. Type I confinement layer; 5. First interface layer; 6. First waveguide layer; 7. Active region; 8. Second waveguide layer; 9. Second interface layer; 10. Type II semiconductor layer; 101. Type II confinement layer; 102. Type II current spreading layer; 103. Type II ohmic contact layer; 11. Mirror; 12. Insulating layer; 13. First electrode; 14. Second electrode; A. Groove; B. Trench; C. Conductive via of the second electrode. Detailed Implementation

[0064] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0065] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0066] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0067] This invention provides a red Mini LED epitaxial structure, such as... Figure 1 As shown, it includes:

[0068] Growth substrate 01;

[0069] A buffer layer 02, an etching stop layer 03, and a stacked structure are sequentially stacked on a growth substrate 01. The stacked structure includes a first type semiconductor layer 4, a first interface layer 5, a first waveguide layer 6, an active region 7, a second waveguide layer 8, a second interface layer 9, and a second type semiconductor layer 10, which are sequentially stacked along a first direction. The first interface layer 5 and the second interface layer 9 are used to block dopant diffusion and metal migration. The first direction is perpendicular to the growth substrate 01 and points from the growth substrate 01 to the stacked structure.

[0070] The first type semiconductor layer 4 includes a first type ohmic contact layer 41, a first type current spreading layer 42 and a first type confinement layer 43 stacked sequentially along a first direction; the second type semiconductor layer 10 includes a second type confinement layer 101, a second type current spreading layer 102 and a second type ohmic contact layer 103 stacked sequentially along a first direction.

[0071] The first interface layer 5, the first waveguide layer 6, the second waveguide layer 8, and the second interface layer 9 all include undoped semiconductor material layers.

[0072] Optionally, in this embodiment, the first interface layer 5, the first waveguide layer 6, the second waveguide layer 8, and the second interface layer 9 all include undoped phosphides.

[0073] Optionally, in this embodiment, the growth substrate 01 can be a GaAs substrate. This application does not limit the material of the growth substrate 01, but it depends on the specific circumstances.

[0074] Optionally, in this embodiment, the buffer layer 02 includes a GaAs material layer.

[0075] Optionally, in this embodiment, the corrosion stop layer 03 includes a GaInP material layer.

[0076] Optionally, in this embodiment, the active region 7 includes an AlGaInP / AlGaInP multi-quantum-well structure.

[0077] Optionally, in this embodiment, both the first type ohmic contact layer 41 and the second type ohmic contact layer 103 include a GaAs material layer.

[0078] Optionally, in this embodiment, both the first type current spreading layer 42 and the second type current spreading layer 102 include an AlGaInP material layer.

[0079] Optionally, in this embodiment, the reflector 11 includes a metal reflector.

[0080] Optionally, in this embodiment, the reflector 11 includes any one or more of Ag, Al, and Au in a stacked structure.

[0081] Optionally, in this embodiment, the thickness of the first interface layer 5 increases with the increase of the doping concentration of the first type confinement layer 43; the thickness of the second interface layer 9 increases with the increase of the doping concentration of the second type confinement layer 101.

[0082] Optionally, in this embodiment, the thickness of the first interface layer is H1, then 1nm < H1 < 50nm; the thickness of the second interface layer is H2, then 1nm < H2 < 50nm.

[0083] It should be noted that this embodiment does not limit the specific doping type of the first type semiconductor layer 4 and the second type semiconductor layer 10. The doping type of the first type semiconductor layer 4 is opposite to that of the second type semiconductor layer 10. The first type semiconductor layer 4 can be a P-type semiconductor layer or an N-type semiconductor layer. The specific materials of the N-type semiconductor layer and the P-type semiconductor layer can be selected according to the actual situation.

[0084] Optionally, in another embodiment of this application, the first type semiconductor layer 4 is an N-type semiconductor layer, and the second type semiconductor layer 10 is a P-type semiconductor layer; the first type confinement layer 43 is an N-type confinement layer, and the second type confinement layer 101 is a highly doped P-type confinement layer, wherein the doping concentration of the P-type confinement layer is higher than that of the N-type confinement layer, and the thickness of the second interface layer 9 is greater than that of the first interface layer 5.

[0085] Alternatively, the first type semiconductor layer 4 is a P-type semiconductor layer, and the second type semiconductor layer 10 is an N-type semiconductor layer; the first type confinement layer 43 is a highly doped P-type confinement layer, and the second type confinement layer 101 is an N-type confinement layer, with the doping concentration of the P-type confinement layer being higher than that of the N-type confinement layer, and the thickness of the first interface layer 5 being greater than that of the second interface layer 9.

[0086] Optionally, in this embodiment, the dopant of the N-type semiconductor layer is one or more of Te, Se, and Si; and the dopant of the P-type semiconductor layer is one or more of Zn, C, Mg, and Be.

[0087] It should be noted that in this embodiment, a highly doped P-type confinement layer is provided. High doping can increase the quasi-Fermi level position of the P-type confinement layer, improve the effective barrier to block leakage electrons, and help reduce the threshold current. Correspondingly, the thickness of the interface layer adjacent to the highly doped P-type confinement layer is greater than the thickness of the interface layer adjacent to the N-type confinement layer, which can better achieve the blocking effect.

[0088] Optionally, in another embodiment of this application, the first interface layer 5 comprises undoped Al. x1 Ga y1 In z1 The P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, 0 < z1 ≤ 1; the first waveguide layer 6 includes undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x2 ≤ 1, 0 < y2 ≤ 1, 0 < z2 ≤ 1; Type I confinement layer 43 includes Al x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

[0089] It should be noted that in this embodiment, the Al composition of the first interface layer is greater than that of the first waveguide layer, and the Al composition of the first interface layer is less than or equal to that of the first type confinement layer. This can increase the barrier effect of the interface on electrons and holes, and can also improve the crystal quality of the material growth in the active region through the interface, thereby ultimately improving the light extraction efficiency.

[0090] Optionally, in another embodiment of this application, the second interface layer 9 comprises undoped Al. x1 Ga y1 In z1 The P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, 0 < z1 ≤ 1; the second waveguide layer 8 includes undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x2 ≤ 1, 0 < y2 ≤ 1, 0 < z2 ≤ 1; the second type confinement layer 101 includes Al x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

[0091] It should be noted that in this embodiment, the Al composition of the second interface layer is greater than that of the second waveguide layer, and the Al composition of the second interface layer is less than or equal to that of the second type confinement layer. This can increase the barrier effect of the interface on electrons and holes, and can also improve the crystal quality of the material growth in the active region through the interface, thereby ultimately improving the light extraction efficiency.

[0092] Optionally, in another embodiment of this application, both the first interface layer 5 and the second interface layer 9 comprise undoped AlGaInP material layers.

[0093] Optionally, in another embodiment of this application, both the first waveguide layer 6 and the second waveguide layer 8 comprise undoped AlGaInP material layers.

[0094] Optionally, in another embodiment of this application, the first type of confinement layer 43 includes one or more stacks of AlGaInP material layers, AlInP material layers, and AlGaP material layers; the second type of confinement layer 101 includes one or more stacks of AlGaInP material layers, AlInP material layers, and AlGaP material layers.

[0095] This invention provides a red Mini LED chip, such as... Figures 2.1 to 2.2 As shown, it includes:

[0096] Stacking structure of any of the above;

[0097] A transparent conductive layer 3, a transparent adhesive layer 2, and a transparent substrate 1 are sequentially stacked on the side of the first semiconductor layer 4 facing away from the first interface layer 5.

[0098] A reflector 11 is disposed on the surface of the second type semiconductor layer 10 facing away from the second interface layer 9;

[0099] The upper surface of the reflector 11 is provided with a groove A extending toward the first type current spreading layer 42, and a portion of the first type current spreading layer 42 is exposed.

[0100] The upper surface edge of the reflector 11 is provided with a trench B extending toward the transparent substrate 1 and exposing the transparent substrate 1. The trench B surrounds the stacked structure.

[0101] The insulating layer 12 covers the exposed surfaces of the reflector 11, the stacked structure, the transparent conductive layer 3 and the transparent adhesive layer 2, and exposes the bottom of the groove A. The insulating layer 12 has a second electrode conductive through hole C (not shown in the figure) that exposes a portion of the reflector 11.

[0102] The first electrode 13 is disposed on the side surface of the insulating layer 12 away from the reflector 11 and extends to the exposed portion of the groove A, forming an electrical connection with the first type current spreading layer 42.

[0103] The second electrode 14 is disposed on the side surface of the insulating layer 12 away from the reflector 11 and extends to the second electrode conductive through hole C, forming an electrical connection with the reflector 11, and the first electrode 13 and the second electrode 14 are disposed at intervals.

[0104] Optionally, in this embodiment, the insulating layer 12 includes a DBR reflective structure layer.

[0105] Optionally, in this embodiment, the side surface of the first electrode 13 facing away from the insulating layer 12 and the side surface of the second electrode 14 facing away from the insulating layer 12 are on the same horizontal plane.

[0106] It should be noted that in this embodiment, the surface of the first electrode 13 facing away from the insulating layer 12 and the surface of the second electrode 14 facing away from the insulating layer 12 are on the same horizontal plane, which can improve the electrode wire bonding yield and prevent defects such as tilting and short circuits.

[0107] This invention also provides a method for manufacturing a red Mini LED chip, the method comprising the following steps:

[0108] Step 01, as follows Figure 3.1 As shown, a growth substrate 01 is provided;

[0109] Step 02, as follows Figure 3.2As shown, a buffer layer 02, an etching stop layer 03, and a stacked structure are sequentially grown on the surface of the growth substrate 01.

[0110] The stacked structure includes a first type semiconductor layer 4, a first interface layer 5, a first waveguide layer 6, an active region 7, a second waveguide layer 8, a second interface layer 9, and a second type semiconductor layer 10, which are stacked sequentially along the growth direction; the first interface layer 5 and the second interface layer 9 are used to block the diffusion of dopants and the migration of metal materials.

[0111] The first type semiconductor layer 4 includes a first type ohmic contact layer 41, a first type current spreading layer 42 and a first type confinement layer 43 stacked sequentially along the growth direction; the second type semiconductor layer 10 includes a second type confinement layer 101, a second type current spreading layer 102 and a second type ohmic contact layer 103 stacked sequentially along the growth direction.

[0112] The first interface layer 5, the first waveguide layer 6, the second waveguide layer 8 and the second interface layer 9 all include undoped semiconductor material layers.

[0113] Step 03, as follows Figure 3.3 As shown, the growth substrate 01, buffer layer 02 and etching stop layer 03 are peeled off to expose the first type semiconductor layer 4;

[0114] Step 04, as follows Figure 3.4 As shown, a transparent conductive layer 3 is grown on the surface of the first semiconductor layer 4 on the side opposite to the first interface layer 5.

[0115] Step 05, as follows Figure 3.5 As shown, the chip structure formed in step 04 is fixed to the transparent substrate 1 by the transparent adhesive layer 2, and the transparent adhesive layer 2 is formed on the side surface of the transparent conductive layer 3 facing away from the first type semiconductor layer 4.

[0116] Step 06, as follows Figure 3.6 As shown, a reflector 11 is grown on the surface of the second type semiconductor layer 10 on the side opposite to the second interface layer 9;

[0117] Step 07, as follows Figure 3.7 As shown, through an etching process, a portion of the first type current extension layer 42 is exposed by etching along the upper surface of the reflector 11, forming a groove A;

[0118] Simultaneously, the upper surface edge of the mirror 11 is etched to expose the transparent substrate 1, forming a trench B, which surrounds the stacked structure.

[0119] Step 08, as follows Figure 3.8As shown, an insulating layer 12 is deposited, which covers the exposed surfaces of the reflector 11, the stacked structure, the transparent conductive layer 3, and the transparent adhesive layer 2. The insulating layer 12 is patterned so that a second electrode conductive via C is formed on a portion of the exposed surface of the reflector 11, and the bottom of the groove A is exposed.

[0120] Step 09, as follows Figure 3.9 As shown, the first electrode 13 and the second electrode 14 are fabricated.

[0121] The first electrode 13 is disposed on the side surface of the insulating layer 12 away from the reflector 11 and extends to the exposed portion of the groove A, forming an electrical connection with the first type current spreading layer 42.

[0122] The second electrode 14 is disposed on the side surface of the insulating layer 12 away from the reflector 11 and extends to the second electrode conductive through hole C, forming an electrical connection with the reflector 11, and the first electrode 13 and the second electrode 14 are disposed at intervals.

[0123] Optionally, in this embodiment, the first interface layer 5, the first waveguide layer 6, the second waveguide layer 8, and the second interface layer 9 all include undoped phosphides.

[0124] Optionally, in this embodiment, the growth substrate 01 can be a GaAs substrate. This application does not limit the material of the growth substrate 01, but it depends on the specific circumstances.

[0125] Optionally, in this embodiment, the buffer layer 02 includes a GaAs material layer.

[0126] Optionally, in this embodiment, the corrosion stop layer 03 includes a GaInP material layer.

[0127] Optionally, in this embodiment, the active region 7 includes an AlGaInP / AlGaInP multi-quantum-well structure.

[0128] Optionally, in this embodiment, both the first type ohmic contact layer 41 and the second type ohmic contact layer 103 include a GaAs material layer.

[0129] Optionally, in this embodiment, both the first type current spreading layer 42 and the second type current spreading layer 102 include an AlGaInP material layer.

[0130] Optionally, in this embodiment, the reflector 11 includes a metal reflector.

[0131] Optionally, in this embodiment, the reflector 11 includes any one or more of Ag, Al, and Au in a stacked structure.

[0132] Optionally, in this embodiment, the thickness of the first interface layer 5 increases with the increase of the doping concentration of the first type confinement layer 43; the thickness of the second interface layer 9 increases with the increase of the doping concentration of the second type confinement layer 101.

[0133] Optionally, in this embodiment, the thickness of the first interface layer is H1, then 1nm < H1 < 50nm; the thickness of the second interface layer is H2, then 1nm < H2 < 50nm.

[0134] Optionally, in this embodiment, the insulating layer 12 includes a DBR reflective structure layer.

[0135] Optionally, in this embodiment, the side surface of the first electrode 13 facing away from the insulating layer 12 and the side surface of the second electrode 14 facing away from the insulating layer 12 are on the same horizontal plane.

[0136] It should be noted that in this embodiment, the surface of the first electrode 13 facing away from the insulating layer 12 and the surface of the second electrode 14 facing away from the insulating layer 12 are on the same horizontal plane, which can improve the electrode wire bonding yield and prevent defects such as tilting and short circuits.

[0137] It should also be noted that the specific doping type of the first type semiconductor layer 4 and the second type semiconductor layer 10 is not limited in this embodiment. The doping type of the first type semiconductor layer 4 is opposite to that of the second type semiconductor layer 10. The first type semiconductor layer 4 can be a P-type semiconductor layer or an N-type semiconductor layer. The specific materials of the N-type semiconductor layer and the P-type semiconductor layer can be selected according to the actual situation.

[0138] Optionally, in another embodiment of this application, the first type semiconductor layer 4 is an N-type semiconductor layer, and the second type semiconductor layer 10 is a P-type semiconductor layer; the first type confinement layer 43 is an N-type confinement layer, and the second type confinement layer 101 is a highly doped P-type confinement layer, wherein the doping concentration of the P-type confinement layer is higher than that of the N-type confinement layer, and the thickness of the second interface layer 9 is greater than that of the first interface layer 5.

[0139] Alternatively, the first type semiconductor layer 4 is a P-type semiconductor layer, and the second type semiconductor layer 10 is an N-type semiconductor layer; the first type confinement layer 43 is a highly doped P-type confinement layer, and the second type confinement layer 101 is an N-type confinement layer, with the doping concentration of the P-type confinement layer being higher than that of the N-type confinement layer, and the thickness of the first interface layer 5 being greater than that of the second interface layer 9.

[0140] Optionally, in this embodiment, the dopant of the N-type semiconductor layer is one or more of Te, Se, and Si; and the dopant of the P-type semiconductor layer is one or more of Zn, C, Mg, and Be.

[0141] It should be noted that in this embodiment, a highly doped P-type confinement layer is provided. High doping can increase the quasi-Fermi level position of the P-type confinement layer, improve the effective barrier to block leakage electrons, and help reduce the threshold current. Correspondingly, the thickness of the interface layer adjacent to the highly doped P-type confinement layer is greater than the thickness of the interface layer adjacent to the N-type confinement layer, which can better achieve the blocking effect.

[0142] Optionally, in another embodiment of this application, the first interface layer 5 comprises undoped Al. x1 Ga y1 In z1 The P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, 0 < z1 ≤ 1; the first waveguide layer 6 includes undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x2 ≤ 1, 0 < y2 ≤ 1, 0 < z2 ≤ 1; Type I confinement layer 43 includes Al x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

[0143] It should be noted that in this embodiment, the Al composition of the first interface layer is greater than that of the first waveguide layer, and the Al composition of the first interface layer is less than or equal to that of the first type confinement layer. This can increase the barrier effect of the interface on electrons and holes, and can also improve the crystal quality of the material growth in the active region through the interface, thereby ultimately improving the light extraction efficiency.

[0144] Optionally, in another embodiment of this application, the second interface layer 9 comprises undoped Al. x1 Ga y1 In z1 The P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, 0 < z1 ≤ 1; the second waveguide layer 8 includes undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x2 ≤ 1, 0 < y2 ≤ 1, 0 < z2 ≤ 1; the second type confinement layer 101 includes Al x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

[0145] It should be noted that in this embodiment, the Al composition of the second interface layer is greater than that of the second waveguide layer, and the Al composition of the second interface layer is less than or equal to that of the second type confinement layer. This can increase the barrier effect of the interface on electrons and holes, and can also improve the crystal quality of the material growth in the active region through the interface, thereby ultimately improving the light extraction efficiency.

[0146] Optionally, in another embodiment of this application, both the first interface layer 5 and the second interface layer 9 comprise undoped AlGaInP material layers.

[0147] Optionally, in another embodiment of this application, both the first waveguide layer 6 and the second waveguide layer 8 comprise undoped AlGaInP material layers.

[0148] Optionally, in another embodiment of this application, the first type of confinement layer 43 includes one or more stacks of AlGaInP material layers, AlInP material layers, and AlGaP material layers; the second type of confinement layer 101 includes one or more stacks of AlGaInP material layers, AlInP material layers, and AlGaP material layers.

[0149] The present invention provides an RGB Mini LED chip, which includes any of the above-mentioned red Mini LED chips.

[0150] In summary, the above technical solution achieves the following results:

[0151] 1. The red Mini LED epitaxial structure provided in this embodiment, by setting a stacked structure, includes a first type semiconductor layer, a first interface layer, a first waveguide layer, an active region, a second waveguide layer, a second interface layer, and a second type semiconductor layer stacked sequentially along a first direction; the first interface layer and the second interface layer are used to block dopant diffusion and metal material migration; the first interface layer can prevent dopant diffusion in the first type semiconductor layer from causing roughening of the interface between the first type confinement layer and the first waveguide layer; the second interface layer can prevent dopant diffusion in the second type semiconductor layer from causing roughening of the interface between the second confinement layer and the second waveguide layer; at the same time, it can also prevent dopant diffusion in the first type semiconductor layer and the second type semiconductor layer to the active region to form non-radiative recombination centers, which would lead to a decrease in reliability; and the first interface, the first waveguide layer, the second waveguide layer, and the second interface layer all include undoped semiconductor material layers, which can form different material interfaces, further blocking dopant diffusion to the active region, reducing the influence of dopant on the growth interface of the active region, effectively improving the crystal quality of the active region, and thus improving the internal quantum efficiency and light output power.

[0152] 2. Furthermore, the thickness of the first interface layer is set to increase with the doping concentration of the first type confinement layer; the thickness of the second interface layer is set to increase with the doping concentration of the second type confinement layer, so that the first interface layer and the second interface layer can play a better blocking effect.

[0153] 3. Furthermore, the thickness of the first interface layer is set to H1, then 1nm < H1 < 50nm; the thickness of the second interface layer is set to H2, then 1nm < H2 < 50nm. This avoids the problem that the recombination efficiency of holes and electrons in the active region will decrease if the thickness of the first and second interface layers is too thick, while the thickness will not play a blocking effect if the thickness is too thin, thereby further improving the internal quantum efficiency and optical output power.

[0154] 4. The red Mini LED chip provided in this embodiment, by using the aforementioned red Mini LED epitaxial structure in conjunction with a transparent conductive layer, a transparent adhesive layer, a transparent substrate, a reflector, an insulating layer, and electrodes, can effectively solve the problem of reduced reliability caused by dopant diffusion leading to roughening of the interface between the confinement layer and the waveguide layer, and the formation of non-radiative recombination centers in the active region. Furthermore, the first and second interface layers can also prevent the metal materials of the chip's electrodes and reflectors from migrating to the active region, avoiding chip aging and severe brightness decay, thereby improving the luminous efficiency and reliability of the red Mini LED chip.

[0155] 5. The method for fabricating a red Mini LED chip provided in this embodiment can effectively solve the problems of reduced reliability caused by the diffusion of dopants in the red Mini LED chip leading to roughening of the interface between the confinement layer and the waveguide layer, and the formation of non-radiative recombination centers in the active region; and the easy migration of metal materials such as electrodes and mirrors of the chip to the active region, leading to chip aging and severe brightness decay. This method improves the luminous efficiency and reliability of the red Mini LED chip.

[0156] 6. The RGB Mini LED chip provided in this embodiment, by using the aforementioned red Mini LED chip, can effectively solve the problem of deteriorating display effect due to the brightness decay of the red Mini-LED chip, resulting in poor color mixing effect after long use of the RGB Mini-LED chip, thereby improving the brightness uniformity of the three primary colors of the RGB Mini LED chip.

[0157] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0158] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0159] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A red-light Mini LED epitaxial structure, characterized in that, include: Growth substrate; A buffer layer, an etching stop layer, and a stacked structure are sequentially stacked on the growth substrate. The stacked structure includes a first type semiconductor layer, a first interface layer, a first waveguide layer, an active region, a second waveguide layer, a second interface layer, and a second type semiconductor layer, sequentially stacked along a first direction. The first interface layer and the second interface layer are used to block dopant diffusion and metal migration. The first direction is perpendicular to the growth substrate and extends from the growth substrate to the stacked structure. Wherein, the first type of semiconductor layer includes a first type of ohmic contact layer, a first type of current spreading layer and a first type of confinement layer stacked sequentially along the first direction; the second type of semiconductor layer includes a second type of confinement layer, a second type of current spreading layer and a second type of ohmic contact layer stacked sequentially along the first direction; The first interface layer, the first waveguide layer, the second waveguide layer, and the second interface layer all include undoped semiconductor material layers.

2. The red Mini LED epitaxial structure according to claim 1, characterized in that: The thickness of the first interface layer increases with the doping concentration of the first type confinement layer; the thickness of the second interface layer increases with the doping concentration of the second type confinement layer.

3. The red Mini LED epitaxial structure according to claim 1, characterized in that: If the thickness of the first interface layer is H1, then 1nm < H1 < 50nm; if the thickness of the second interface layer is H2, then 1nm < H2 < 50nm.

4. The red Mini LED epitaxial structure according to claim 1, characterized in that: The first type semiconductor layer is an N-type semiconductor layer, the second type semiconductor layer is a P-type semiconductor layer, the first type confinement layer is an N-type confinement layer, the second type confinement layer is a highly doped P-type confinement layer, the doping concentration of the P-type confinement layer is higher than the doping concentration of the N-type confinement layer, and the thickness of the second interface layer is greater than the thickness of the first interface layer. Alternatively, the first type semiconductor layer is a P-type semiconductor layer, the second type semiconductor layer is an N-type semiconductor layer, the first type confinement layer is a highly doped P-type confinement layer, the second type confinement layer is an N-type confinement layer, the doping concentration of the P-type confinement layer is higher than the doping concentration of the N-type confinement layer, and the thickness of the first interface layer is greater than the thickness of the second interface layer.

5. The red Mini LED epitaxial structure according to claim 1, characterized in that: The first interface layer comprises undoped Al x1 Ga y1 In z1 A P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, 0 < z1 ≤ 1; the first waveguide layer comprises undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x2 ≤ 1, 0 < y2 ≤ 1, 0 < z2 ≤ 1; the first type of confinement layer includes Al x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

6. The red Mini LED epitaxial structure according to claim 1, characterized in that: The second interface layer comprises undoped Al x1 Ga y1 In z1 The first waveguide layer comprises a P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, and 0 < z1 ≤ 1; the second waveguide layer comprises undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x² ≤ 1, 0 < y² ≤ 1, 0 < z² ≤ 1; the second type confinement layer includes Al. x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

7. A red Mini LED chip, characterized in that, include: A stacked structure employing the red Mini LED epitaxial structure as described in any one of claims 1-6; A transparent conductive layer, a transparent adhesive layer, and a transparent substrate are sequentially stacked on the side surface of the first type semiconductor layer that is away from the first interface layer. A reflector is disposed on the side surface of the second type semiconductor layer opposite to the second interface layer; The upper surface of the reflector is provided with a groove extending toward the first type of current spreading layer, and a portion of the first type of current spreading layer is exposed. The upper surface edge of the reflector has a groove extending toward the transparent substrate and exposing the transparent substrate, the groove surrounding the stacked structure; An insulating layer covers the exposed surfaces of the reflector, the stacked structure, the transparent conductive layer, and the transparent adhesive layer, and exposes the bottom of the groove. The insulating layer has a second electrode conductive via that exposes a portion of the reflector. The first electrode is disposed on the side surface of the insulating layer opposite to the reflector and extends to the exposed portion of the groove, forming an electrical connection with the first type of current spreading layer. The second electrode is disposed on the side surface of the insulating layer opposite to the reflector and extends to the conductive via of the second electrode, forming an electrical connection with the reflector, and the first electrode and the second electrode are disposed at intervals.

8. A method for manufacturing a red Mini LED chip, characterized in that, The manufacturing method includes the following steps: Step 01: Provide a growth substrate; Step 02: A buffer layer, an etch stop layer, and a stacked structure are sequentially grown on the surface of the growth substrate; The stacked structure includes a first type semiconductor layer, a first interface layer, a first waveguide layer, an active region, a second waveguide layer, a second interface layer, and a second type semiconductor layer stacked sequentially along the growth direction; the first interface layer and the second interface layer are used to block dopant diffusion and metal material migration; The first type of semiconductor layer includes a first type of ohmic contact layer, a first type of current spreading layer, and a first type of confinement layer stacked sequentially along the growth direction; the second type of semiconductor layer includes a second type of confinement layer, a second type of current spreading layer, and a second type of ohmic contact layer stacked sequentially along the growth direction. The first interface layer, the first waveguide layer, the second waveguide layer, and the second interface layer all include undoped semiconductor material layers; Step 03: Peel off the growth substrate, the buffer layer, and the etching stop layer to expose the first type of semiconductor layer; Step 04: Grow a transparent conductive layer on the side of the first type of semiconductor layer that is away from the first interface layer; Step 05: Fix the chip structure formed in step 04 to the transparent substrate using a transparent adhesive layer, wherein the transparent adhesive layer is formed on the side surface of the transparent conductive layer that is away from the first type of semiconductor layer. Step 06: Grow a reflective mirror on the surface of the second type semiconductor layer that is opposite to the second interface layer; Step 07: Using an etching process, etch along the upper surface of the reflector to expose part of the first type of current spreading layer, forming a groove; Simultaneously, the transparent substrate is exposed by etching along the edge of the upper surface of the mirror, forming a trench that surrounds the stacked structure; Step 08: Deposit an insulating layer, which covers the exposed surfaces of the reflector, stacked structure, transparent conductive layer and transparent adhesive layer, and pattern the insulating layer to form a second electrode conductive via on the exposed portion of the reflector surface, and expose the bottom of the groove; Step 09: Fabricate the first and second electrodes; The first electrode is disposed on the side surface of the insulating layer opposite to the reflector and extends to the exposed portion of the groove, forming an electrical connection with the first type of current spreading layer; The second electrode is disposed on the side surface of the insulating layer opposite to the reflector and extends to the conductive via of the second electrode, forming an electrical connection with the reflector, and the first electrode and the second electrode are disposed at intervals.

9. The method for manufacturing a red Mini LED chip according to claim 8, characterized in that: The thickness of the first interface layer increases with the doping concentration of the first type confinement layer; the thickness of the second interface layer increases with the doping concentration of the second type confinement layer.

10. The method for manufacturing a red Mini LED chip according to claim 8, characterized in that: If the thickness of the first interface layer is H1, then 1nm < H1 < 50nm; if the thickness of the second interface layer is H2, then 1nm < H2 < 50nm.

11. The method for manufacturing a red Mini LED chip according to claim 8, characterized in that: The first type semiconductor layer is an N-type semiconductor layer, the second type semiconductor layer is a P-type semiconductor layer, the first type confinement layer is an N-type confinement layer, the second type confinement layer is a highly doped P-type confinement layer, the doping concentration of the P-type confinement layer is higher than the doping concentration of the N-type confinement layer, and the thickness of the second interface layer is greater than the thickness of the first interface layer. Alternatively, the first type semiconductor layer is a P-type semiconductor layer, the second type semiconductor layer is an N-type semiconductor layer, the first type confinement layer is a highly doped P-type confinement layer, the second type confinement layer is an N-type confinement layer, the doping concentration of the P-type confinement layer is higher than the doping concentration of the N-type confinement layer, and the thickness of the first interface layer is greater than the thickness of the second interface layer.

12. The method for manufacturing a red Mini LED chip according to claim 8, characterized in that: The first interface layer comprises undoped Al x1 Ga y1 In z1 A P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, 0 < z1 ≤ 1; the first waveguide layer comprises undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x2 ≤ 1, 0 < y2 ≤ 1, 0 < z2 ≤ 1; the first type of confinement layer includes Al x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

13. The method for manufacturing a red Mini LED chip according to claim 8, characterized in that: The second interface layer comprises undoped Al x1 Ga y1 In z1 The first waveguide layer comprises a P-material layer, wherein 0 < x1 ≤ 1, 0 < y1 ≤ 1, and 0 < z1 ≤ 1; the second waveguide layer comprises undoped Al. x2 Ga y2 In z2 P material layer, wherein 0 < x² ≤ 1, 0 < y² ≤ 1, 0 < z² ≤ 1; the second type confinement layer includes Al. x3 Ga y3 In z3 Material layer P, wherein 0 < x3 ≤ 1, 0 < y3 ≤ 1, 0 ≤ z3 ≤ 1, or 0 < x3 ≤ 1, 0 ≤ y3 ≤ 1, 0 < z3 ≤ 1; and x2 < x1 ≤ x3.

14. An RGB Mini LED chip, characterized in that, include: The red Mini LED chip described in claim 7 is used.

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