3D transparent optical sensor package structure

Abstract

The application discloses a 3D transparent optical sensor packaging structure, which comprises a substrate, an ASIC chip, a Vcsel chip, a first packaging glue layer, a second packaging glue layer, a 3D transparent glue layer and a conductive pad layer; the ASIC chip is attached to the top surface of the substrate and is packaged through the first packaging glue layer; the Vcsel chip is packaged on the top of the ASIC chip through the 3D transparent glue layer, forming a stacked chip structure, the Vcsel chip is packaged through the second packaging glue layer, and the top surface of the 3D transparent glue layer extends above the top surface of the second packaging glue layer; the conductive pad layer is arranged between the first packaging glue layer and the second packaging glue layer, and the conductive pad layer is electrically connected with the Vcsel chip and the substrate, and the Vcsel chip is electrically connected with the substrate. The application relates to the technical field of optical sensors and can solve the problems of large volume and poor heat dissipation performance of optical sensors in the prior art.

Description

Technical Field

[0001] The present invention relates to the technical field of optical sensors, and in particular to a 3D transparent optical sensor packaging structure. Background Art

[0002] Please see the attached Figure 1 The optical sensor of the prior art includes a substrate 1, a cover 2, a first chip 3 and a second chip 4; the cover 2 is arranged on the substrate 1 to form two cavities, and the first chip 3 and the second chip 4 are respectively encapsulated in the two cavities and electrically connected to the substrate 1 through wire bonding.

[0003] Existing optical sensors require two cavities, occupying a large amount of space horizontally. Furthermore, the gold wires require a certain height for bonding, which requires a certain amount of vertical space. This results in a large overall optical sensor size and poor heat dissipation. Therefore, a 3D transparent optical sensor packaging structure is needed to address the issues of bulky optical sensors and poor heat dissipation in existing technologies. Summary of the Invention

[0004] The purpose of the present invention is to provide a 3D transparent optical sensor packaging structure that can solve the problems of large size and poor heat dissipation performance of optical sensors in the prior art.

[0005] The present invention is achieved in that:

[0006] A 3D transparent optical sensor packaging structure includes a substrate, an ASIC chip, a Vcsel chip, a first encapsulation adhesive layer, a second encapsulation adhesive layer, a 3D transparent adhesive layer, and a conductive pad layer; the ASIC chip is mounted on the top surface of the substrate and encapsulated by the first encapsulation adhesive layer; the Vcsel chip is encapsulated on top of the ASIC chip by the 3D transparent adhesive layer to form a stacked chip structure, the Vcsel chip is encapsulated by the second encapsulation adhesive layer, and the top surface of the 3D transparent adhesive layer extends above the top surface of the second encapsulation adhesive layer; the conductive pad layer is arranged between the first encapsulation adhesive layer and the second encapsulation adhesive layer, the conductive pad layer is electrically connected to the Vcsel chip and the substrate, and the Vcsel chip is electrically connected to the substrate.

[0007] The Vcsel chip and the photosensitive area on the ASIC chip are staggered, the 3D transparent adhesive layer covers the top of the Vcsel chip and the photosensitive area, and the gap between the top of the Vcsel chip and the photosensitive area is filled by the second packaging adhesive layer.

[0008] The top surface of the 3D transparent adhesive layer is a curved surface structure.

[0009] A first conductive through hole is formed in the first packaging adhesive layer along the thickness direction. A first gold wire is arranged in the first conductive through hole. The upper end of the first gold wire is electrically connected to the conductive pad layer, and the lower end of the first gold wire is electrically connected to the substrate.

[0010] The internal bonding of the Vcsel chip forms a second gold wire and a third gold wire. The second gold wire is located in the second packaging glue layer and is electrically connected to the conductive pad layer. The third gold wire is located in the first packaging glue layer and is electrically connected to the substrate.

[0011] The diameters of the second gold wire and the third gold wire are smaller than the diameter of the first gold wire.

[0012] Several second conductive through holes are formed in the substrate along the thickness direction, and the fourth gold wire and the fifth gold wire are respectively arranged in the several second conductive through holes. The upper end of the fourth gold wire is electrically connected to the first gold wire, the upper end of the fifth gold wire is electrically connected to the third gold wire, and the lower ends of the fourth gold wire and the fifth gold wire are respectively led out to the bottom surface of the substrate.

[0013] The diameters of the fourth gold wire and the fifth gold wire are greater than the diameter of the third gold wire.

[0014] The conductive pad layer is located at the interface between the first packaging adhesive layer and the second packaging adhesive layer, and the conductive pad layer is higher than the bottom surface of the 3D transparent adhesive layer.

[0015] The substrate is a laminated substrate.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. The present invention adopts a stacking method to arrange the ASIC chip and the Vcsel chip, and at the same time, by providing a conductive pad layer between two layers of packaging adhesive layers, it can meet the electrical connection between the stacked ASIC chip and the Vcsel chip and the substrate. There is no need to set up two cavities to encapsulate the ASIC chip and the Vcsel chip respectively, thereby effectively reducing the lateral occupied space of the packaging structure and further reducing the volume of the packaging structure.

[0018] 2. In the present invention, since the first gold wire is arranged through the first conductive through-hole in the first packaging adhesive layer, and the fourth gold wire and the fifth gold wire are arranged through the second conductive through-hole in the substrate, electrical connection with the Vcsel chip can be achieved through the gold wire via the conductive pad layer, and the diameter of the gold wire in the conductive through-hole is large, which can meet the functional requirements of high current and high heat dissipation. The conductive through-hole arranged along the thickness direction enables the gold wire to have good stress bonding while making the routing of the gold wire as short as possible, thereby reducing costs.

[0019] 3. Since the present invention performs wire bonding inside the Vcsel chip, the bonding positions of the second and third gold wires are moved inside the chip, which can effectively reduce the vertical space required for wire bonding, thereby reducing the thickness of the packaging structure and further reducing the volume of the packaging structure.

[0020] 4. The present invention uses 3D transparent adhesive to cover the ASIC chip and the Vcsel chip, and the photosensitive areas of the Vcsel chip and the ASIC chip are staggered, which can ensure that the photosensitive area of ​​the ASIC chip receives light and the Vcsel chip emits light, thereby ensuring the optical performance of the light sensor; at the same time, the second packaging adhesive layer is used to fill the gap between the top of the Vcsel chip and the photosensitive area to form a partition, ensuring that the Vcsel chip and the ASIC chip do not crosstalk with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural diagram of the prior art optical sensor packaging structure;

[0022] Figure 2 It is a structural schematic diagram of the 3D transparent optical sensor packaging structure of the present invention;

[0023] Figure 3 This is a top view of the stacking of the ASIC chip and the Vcsel chip in the 3D transparent optical sensor packaging structure of the present invention;

[0024] Figure 4 This is a front view of the stacking of the ASIC chip and the Vcsel chip in the 3D transparent optical sensor packaging structure of the present invention.

[0025] In the figure, 1 is the substrate, 101 is the fourth gold wire, 102 is the fifth gold wire, 2 is the cover, 3 is the first chip, 4 is the second chip, 5 is the ASIC chip, 6 is the Vcsel chip, 601 is the second gold wire, 602 is the third gold wire, 7 is the first packaging glue layer, 701 is the first gold wire, 8 is the second packaging glue layer, 9 is the 3D transparent glue layer, 10 is the photosensitive area, and 11 is the conductive pad layer. DETAILED DESCRIPTION

[0026] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0027] Please see the attached Figure 2A 3D transparent optical sensor packaging structure includes a substrate 1, an ASIC (Application Specific Integrated Circuit) chip 5, a VCSEL (Vertical-Cavity Surface-Emitting Laser) chip 6, a first encapsulation layer 7, a second encapsulation layer 8, a 3D transparent adhesive layer 9, and a conductive pad layer 11; the ASIC chip 5 is mounted on the top surface of the substrate 1 and encapsulated by the first encapsulation layer 7; the VCSEL chip 6 is encapsulated on top of the ASIC chip 5 through the 3D transparent adhesive layer 9 to form a stacked chip structure, the VCSEL chip 6 is encapsulated by the second encapsulation layer 8, and the top surface of the 3D transparent adhesive layer 9 extends above the top surface of the second encapsulation layer 8; the conductive pad layer 11 is arranged between the first encapsulation layer 7 and the second encapsulation layer 8, the conductive pad layer 11 is electrically connected to the VCSEL chip 6 and the substrate 1, and the VCSEL chip 6 is electrically connected to the substrate 1.

[0028] The ASIC chip 5 and the VCSEL chip 6 are stacked, eliminating the need for two separate cavities to house the ASIC chip 5 and VCSEL chip 6, effectively reducing lateral space usage. The ASIC chip 5 is mounted on the substrate 1 using conductive silver adhesive or other methods, while the VCSEL chip 6 is connected to the substrate 1 via wire bonding, meeting electrical connection requirements.

[0029] The encapsulation layer can be a two-layer black encapsulation layer structure, namely a first encapsulation layer 7 and a second encapsulation layer 8. The first encapsulation layer 7 and the second encapsulation layer 8 are electrically connected through a conductive pad layer 11, which satisfies the electrical connection between the ASIC chip 5 and the Vcsel chip 6 and the substrate 1. The conductive pad layer 11 can preferably be a metal pad layer.

[0030] 3D transparent glue is directly applied on the ASIC chip 5 and the Vcsel chip 6 to form a 3D transparent glue layer 9. The 3D transparent glue has a light-transmitting function and can meet the light receiving and light transmission requirements of the ASIC chip 5 and the Vcsel chip 6. The rest of the packaging is filled with black packaging glue, and the 3D transparent glue layer 9 extends to the top surface of the second packaging glue layer 8 to ensure that the second packaging glue layer 8 does not block the light receiving and light transmission of the ASIC chip 5 and the Vcsel chip 6.

[0031] Please see the attached Figure 3 and attached Figure 4 The Vcsel chip 6 and the photosensitive area 10 on the ASIC chip 5 are staggered, the 3D transparent adhesive layer 9 covers the top of the Vcsel chip 6 and the photosensitive area 10, and the gap between the top of the Vcsel chip 6 and the photosensitive area 10 is filled by the second encapsulation adhesive layer 8.

[0032] The stacked VCSEL chips 6 do not block the light-receiving area 10 on the ASIC chip 5. The 3D transparent adhesive layer 9 covers the VCSEL chips 6 and the ASIC chip 5, ensuring that the photosensitive area 10 receives light and the VCSEL chip 6 emits light while maintaining the packaging effect. A second encapsulation adhesive layer 8 fills the gap between the top of the VCSEL chip 6 and the photosensitive area 10 to form a partition, ensuring that the VCSEL chip 6 and the ASIC chip 5 do not interfere with each other.

[0033] Please see the attached Figure 4 The top surface of the 3D transparent adhesive layer 9 is a curved surface structure, which can refract and transmit light through curved surface structures of different sizes, thereby meeting the light transmission and reception requirements of the Vcsel chip 6 and the ASIC chip 5, reducing stray light interference, and ensuring the optical performance of the packaging structure.

[0034] Please see the attached Figure 2 A first conductive through hole (not shown in the figure) is formed in the first packaging glue layer 7 along the thickness direction, and a first gold wire 701 is arranged in the first conductive through hole. The upper end of the first gold wire 701 is electrically connected to the conductive pad layer 11, and the lower end of the first gold wire 701 is electrically connected to the substrate 1.

[0035] The first conductive vias and the first gold wires 701 ensure electrical connection between the substrate 1 and the conductive pad layer 11. The vertical arrangement of the first conductive vias and the first gold wires 701 can minimize the length of the first gold wires 701 and ensure stress bonding.

[0036] Please see the attached Figure 2 The internal bonding of the Vcsel chip 6 forms a second gold wire 601 and a third gold wire 602. The second gold wire 601 is located in the second packaging glue layer 8 and is electrically connected to the conductive pad layer 11. The third gold wire 602 is located in the first packaging glue layer 7 and is electrically connected to the substrate 1.

[0037] The second gold wire 601 and the third gold wire 602 of the Vcsel chip 6 are set by internal bonding. The bonding positions of the second gold wire 601 and the third gold wire 602 are moved to the inside of the chip, which can effectively reduce the vertical height required for bonding, thereby saving vertical space and reducing the volume of the packaging structure.

[0038] Please see the attached Figure 2 , the diameters of the second gold wire 601 and the third gold wire 602 are smaller than the diameter of the first gold wire 701 .

[0039] Preferably, the diameter of the first gold wire 701 may be twice or more than twice the diameter of the second gold wire 601 and the third gold wire 602 , meeting functional requirements of high current and high heat dissipation.

[0040] Please see the attached Figure 2 A plurality of second conductive through holes (not shown in the figure) are formed in the substrate 1 along the thickness direction. The fourth gold wire 101 and the fifth gold wire 102 are respectively arranged in the plurality of second conductive through holes. The upper end of the fourth gold wire 101 is electrically connected to the first gold wire 701, and the upper end of the fifth gold wire 102 is electrically connected to the third gold wire 602. The lower ends of the fourth gold wire 101 and the fifth gold wire 102 are respectively led out to the bottom surface of the substrate 1.

[0041] Through the arrangement of the second conductive vias and the fourth and fifth gold wires 101 and 102, the electrical connection between the ASIC chip 5 and the Vcsel chip 6 and the external components of the package structure can be met. At the same time, the internal heat of the package structure can be dissipated outward through the fourth and fifth gold wires 101 and 102, meeting the functional requirements of high current and high heat dissipation.

[0042] Please see the attached Figure 2 The diameters of the fourth gold wire 101 and the fifth gold wire 102 are greater than the diameter of the third gold wire 602 .

[0043] Preferably, the diameters of the fourth gold wire 101 and the fifth gold wire 102 may be twice or more than twice the diameter of the third gold wire 602 , meeting functional requirements of high current and high heat dissipation.

[0044] Please see the attached Figure 2 The conductive pad layer 11 is located at the interface between the first encapsulation adhesive layer 7 and the second encapsulation adhesive layer 8 , and the conductive pad layer 11 is slightly higher than the bottom surface of the 3D transparent adhesive layer 9 .

[0045] The height of the conductive pad layer 11 can be adaptively adjusted according to the bonding position of the Vcsel chip 6 to facilitate electrical connection between the second gold wire 601 and the conductive pad layer 11 , and the setting of the conductive pad layer 11 will not interfere with the bonding of the third gold wire 602 .

[0046] The substrate 1 is a laminated substrate, which is composed of a base material, a laminate, a solder mask and a silk screen, and is produced using a circuit board manufacturing PCB lamination process.

[0047] Please see the attached Figure 2 To the attached Figure 4 , the production process of the present invention is:

[0048] The fourth and fifth gold wires 101 and 102 can be laid out on the substrate 1 at the factory according to circuit design requirements. The ASIC chip 5 is mounted on the substrate 1 using conductive silver adhesive. The VCSEL chip 6 is encapsulated on the non-photosensitive area of ​​the ASIC chip 5 using a 3D transparent adhesive layer 9, staggered with the photosensitive area 10.

[0049] A first encapsulating layer 7 is encapsulated on the substrate 1 to encapsulate the bottom of the ASIC chip 5 and the VCSEL chip 6. A conductive pad layer 11 is attached to the top surface of the first encapsulating layer 7. When encapsulating the first encapsulating layer 7, a first conductive via is reserved for routing a first gold wire 701, which forms an electrical connection between the fourth gold wire 101 on the substrate 1 and the conductive pad layer 11. A wire is bonded internally at the bottom of the VCSEL chip 6 to form a third gold wire 602, which is electrically connected to the fifth gold wire 102 on the substrate 1.

[0050] Wire bonding is performed on the upper portion of the VCSEL chip 6 to form a second gold wire 601, which is electrically connected to the conductive pad layer 11. A second encapsulation layer 8 is encapsulated on the first encapsulation layer 7 to encapsulate the VCSEL chip 6 and fill the gap between the VCSEL chip 6 and the photosensitive area 10 to isolate interference from light transmission. The top surface of the second encapsulation layer 8 is slightly lower than the top surface of the 3D transparent adhesive layer 9.

[0051] The above are only preferred embodiments of the present invention and are not intended to limit the scope of protection of the invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A 3D transparent optical sensor packaging structure, characterized by: It comprises a substrate (1), an ASIC chip (5), a Vcsel chip (6), a first encapsulation adhesive layer (7), a second encapsulation adhesive layer (8), a 3D transparent adhesive layer (9) and a conductive pad layer (11); the ASIC chip (5) is mounted on the top surface of the substrate (1) and encapsulated by the first encapsulation adhesive layer (7); The Vcsel chip (6) is encapsulated on top of the ASIC chip (5) through a 3D transparent adhesive layer (9) to form a stacked chip structure. The Vcsel chip (6) is encapsulated through a second encapsulation adhesive layer (8), and the top surface of the 3D transparent adhesive layer (9) extends above the top surface of the second encapsulation adhesive layer (8). The conductive pad layer (11) is arranged between the first encapsulation adhesive layer (7) and the second encapsulation adhesive layer (8). The conductive pad layer (11) is electrically connected to the Vcsel chip (6) and the substrate (1), and the Vcsel chip (6) is electrically connected to the substrate (1). The Vcsel chip (6) and the photosensitive area (10) on the ASIC chip (5) are staggered, the 3D transparent adhesive layer (9) covers the top of the Vcsel chip (6) and the photosensitive area (10), and the gap between the top of the Vcsel chip (6) and the photosensitive area (10) is filled by the second packaging adhesive layer (8); A first conductive through hole is formed in the first packaging adhesive layer (7) along the thickness direction, and a first gold wire (701) is arranged in the first conductive through hole. The upper end of the first gold wire (701) is electrically connected to the conductive pad layer (11), and the lower end of the first gold wire (701) is electrically connected to the substrate (1).

2. The 3D transparent optical sensor package structure according to claim 1, wherein: The top surface of the 3D transparent adhesive layer (9) is a curved surface structure.

3. The 3D transparent optical sensor package structure according to claim 1, wherein: The internal bonding of the Vcsel chip (6) forms a second gold wire (601) and a third gold wire (602), wherein the second gold wire (601) is located in the second packaging glue layer (8) and is electrically connected to the conductive pad layer (11), and the third gold wire (602) is located in the first packaging glue layer (7) and is electrically connected to the substrate (1).

4. The 3D transparent optical sensor package structure according to claim 3, wherein: The diameters of the second gold wire (601) and the third gold wire (602) are smaller than the diameter of the first gold wire (701).

5. The 3D transparent optical sensor package structure according to claim 3, wherein: A plurality of second conductive through holes are formed in the substrate (1) along the thickness direction. The fourth gold wire (101) and the fifth gold wire (102) are respectively arranged in the plurality of second conductive through holes. The upper end of the fourth gold wire (101) is electrically connected to the first gold wire (701), the upper end of the fifth gold wire (102) is electrically connected to the third gold wire (602), and the lower ends of the fourth gold wire (101) and the fifth gold wire (102) are respectively led out to the bottom surface of the substrate (1).

6. The 3D transparent optical sensor package structure according to claim 5, wherein: The diameters of the fourth gold wire (101) and the fifth gold wire (102) are greater than the diameter of the third gold wire (602).

7. The 3D transparent optical sensor package structure according to claim 1, wherein: The conductive pad layer (11) is located at the interface between the first encapsulation adhesive layer (7) and the second encapsulation adhesive layer (8), and the conductive pad layer (11) is higher than the bottom surface of the 3D transparent adhesive layer (9).

8. The 3D transparent optical sensor package structure according to any one of claims 1, 3, and 5, wherein: The substrate (1) is a laminated substrate.

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