Power synchronization control method and apparatus, storage medium, and device

Abstract

The application discloses a power synchronization control method and device, a storage medium and equipment. The method comprises the following steps: an initial power synchronization control model is established; an active power control loop and a DC link control loop in the initial power synchronization control model are analyzed and processed to obtain an analysis result; a target power synchronization control model is determined based on the analysis result; and the target power synchronization control model is used for power synchronization control. The application solves the technical problem that the power synchronization control method in the prior art is limited by a short-circuit ratio and operation conditions of a power grid and has poor stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to a power synchronization control method and device, a storage medium and equipment. BACKGROUND

[0002] The power synchronization control (PSC) of grid-connected voltage source converter is a common control scheme at present, which can participate in the dynamic characteristic simulation of synchronous motor, referred to as virtual synchronous machine (VSM). The simulation of synchronous motor mainly controls the active power by adjusting the voltage angle of the converter, and does not need to use phase-locked loop (PLL) during normal operation. The design of VSM and synchronous converter is mainly to form a power grid, including providing virtual inertia PSC to realize stable interconnection with weak grid converter, but when the power grid is very weak and the PCC voltage changes greatly with the injected current, the control of the current vector outer loop is invalid, and the closed-loop system cannot guarantee good robustness.

[0003] At present, no effective solution has been proposed for the above problems. SUMMARY

[0004] The embodiments of the present application provide a power synchronization control method, device, storage medium and equipment to at least solve the technical problem that the power synchronization control method in the prior art is limited by the short-circuit ratio and operating conditions of the power grid, and has poor stability.

[0005] According to an aspect of an embodiment of the present application, a power synchronization control method is provided, including: establishing an initial power synchronization control model; analyzing and processing the active power control loop and the DC link control loop in the initial power synchronization control model to obtain an analysis result; determining a target power synchronization control model based on the analysis result; and performing power synchronization control using the target power synchronization control model.

[0006] Optionally, the establishment of the initial power synchronization control model includes: determining a first space vector of converter voltage, a second space vector of grid voltage and a third space vector of converter output current; determining a model relationship based on the first space vector, the second space vector and the third space vector; and establishing the initial power synchronization control model based on the model relationship.

[0007] Optionally, the analysis and processing of the active power control loop and the DC link control loop in the initial power synchronization control model to obtain an analysis result includes: determining an open-loop transfer function and a closed-loop transfer function of the initial power synchronization control model; determining the dynamic performance of the active power control loop and the DC link control loop based on the open-loop transfer function and the closed-loop transfer function; and determining the dynamic performance as the analysis result.

[0008] Optionally, the determining the target power synchronization control model based on the analysis result comprises: performing robust design of a direct current link control gain based on the analysis result to obtain the target power synchronization control model.

[0009] According to another aspect of the embodiments of the present application, a power synchronization control device is further provided, comprising: an establishing module configured to establish an initial power synchronization control model; an analyzing module configured to analyze and process an active power control loop and a direct current link control loop in the initial power synchronization control model to obtain an analysis result; a determining module configured to determine a target power synchronization control model based on the analysis result; and a control module configured to perform power synchronization control by using the target power synchronization control model.

[0010] According to another aspect of the embodiments of the present application, a nonvolatile storage medium is further provided, which stores a plurality of instructions, and the instructions are adapted to be loaded and executed by a processor to perform any of the power synchronization control methods.

[0011] According to another aspect of the embodiments of the present application, a processor is further provided, which is used to run a program, wherein the program is configured to perform any of the power synchronization control methods when running.

[0012] According to another aspect of the embodiments of the present application, an electronic device is further provided, which comprises a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to perform any of the power synchronization control methods.

[0013] In the embodiments of the present application, by establishing an initial power synchronization control model, analyzing and processing an active power control loop and a direct current link control loop in the initial power synchronization control model to obtain an analysis result, determining a target power synchronization control model based on the analysis result, and performing power synchronization control by using the target power synchronization control model, the robust design of the active power control loop and the direct current link control loop is achieved, thereby realizing the technical effect of good robustness under different short-circuit ratios and different control modes, and further solving the technical problem of poor stability of the power synchronization control method in the prior art which is limited by the short-circuit ratio and the operating condition of the power grid. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application. In the drawings:

[0015] Figure 1is a power synchronization control method flow chart according to an embodiment of the present application;

[0016] Figure 2 is an optional circuit model schematic diagram of a grid-connected voltage source converter according to an embodiment of the present application;

[0017] Figure 3 is an optional control block diagram schematic diagram based on PSC according to an embodiment of the present application;

[0018] Figure 4 is an optional closed-loop system block diagram according to an embodiment of the present application;

[0019] Figure 5 is an optional DC link control loop schematic diagram according to an embodiment of the present application;

[0020] Figure 6 is a structure schematic diagram of a power synchronization control device according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the personnel in the art better understand the present application scheme, the technical scheme in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0023] Embodiment 1

[0024] According to the power synchronization control method provided by the embodiment of the present application, it should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0025] Figure 1 is a flowchart of the power synchronization control method according to the embodiment of the present application, as shown in the method comprising the following steps: Figure 1

[0026] Step S102, establishing an initial power synchronization control model;

[0027] Step S104, analyzing and processing the active power control loop and the DC link control loop in the initial power synchronization control model to obtain an analysis result;

[0028] Step S106, determining a target power synchronization control model based on the analysis result;

[0029] Step S108, using the target power synchronization control model for power synchronization control.

[0030] In the embodiment of the present application, the execution subject of the power synchronization control method provided in the above steps S102 to S108 is a power synchronization control system, and the above system is used to establish an initial power synchronization control model; the active power control loop and the DC link control loop in the initial power synchronization control model are analyzed and processed to obtain an analysis result; a target power synchronization control model is determined based on the analysis result; and the target power synchronization control model is used for power synchronization control.

[0031] Through the embodiment of the present application, it is not limited by the short circuit ratio (SCR) and the operating condition of the power grid, has a large enough stability margin and good robustness. First, the system model is established based on certain basic assumptions and the principle of PSC is simply introduced; then based on the dynamic performance analysis of PSC, the active power and DC link control loop are robustly designed; finally, the proposed robust design is compared with the typical VSM design under different intensity of the power grid (i.e. different short circuit ratios), the stability margin is larger, through analysis and verification, it can be concluded that it has good robustness, even if the control system is disturbed by certain parameters, the stability of the system can still be guaranteed.

[0032] ​In an alternative embodiment, the establishing the initial power synchronization control model comprises: determining a first space vector of the converter voltage, a second space vector of the grid voltage and a third space vector of the converter output current; determining a model relationship based on the first space vector, the second space vector and the third space vector; and establishing the initial power synchronization control model based on the model relationship.

[0033] As an alternative embodiment, a conventional grid model consisting of an infinite bus and line inductance L is adopted, as shown in Figure 2 The circuit model of the grid-connected voltage source converter, where the series line resistance R is neglected. L is the sum of the filter inductance of the converter, the transformer inductance connecting the converter to the grid and the grid inductance, v s and v sg are the space vectors of the converter voltage and the grid voltage, respectively, while i s is the space vector of the converter output current. The superscript s indicates the space vector in the αβ frame, i.e. rotating at the synchronous angular frequency ω1, while the corresponding space vector in the dq frame is denoted without superscript, e.g. i. Here we assume that the grid voltage magnitude V g is constant and the space vector rotates at the synchronous frequency, which gives

[0034] where s = d / dt. To avoid having to split L into grid and converter inductance, the SCR can be defined as the voltage at the converter terminals; it is smaller than the SCR value derived from the PCC point, but does not affect the result. According to this definition, the SCR is the inverse of the value of L per unit (p.u.);

[0035]

[0036] Alternatively, the basic principle of the PSC is to select the converter voltage as

[0037] v s = Ve jθ (3)

[0038] where V is the converter voltage magnitude. Assuming that the control loop response is slow enough, V is treated as a constant. The angle θ is controlled as follows:

[0039]

[0040] where Kp is the active power control gain and P is the active power output of the converter.

[0041]

[0042] Alternatively, P refThis is the baseline value for active power. In equation (5), K is the spatial vector scaling constant. For the per-unit scaling of variables or vectors with constant power... κ = 1. From equation (4), we can obtain:

[0043]

[0044] Optionally, during grid disturbances, the grid angular frequency ω g =dθ / dt may differ from ω1, meaning that PSC inherently adds a frequency drop to the active power reference, with a drop gain of 1 / K. p If the PSC principle shown in equation (3) is followed, the damping of the closed-loop system will deteriorate. To address this problem, the remedy is to subtract the gain R from the converter voltage. a The term, also known as the active resistance, includes the high-pass filtered component i = e of the synchronous dq-axis current vector. -jθ i s :

[0045]

[0046] Wherein, the filter bandwidth ω b It should be less than ω1, typically within the range of 0.1ω1 to 0.2ω1, i.e., 0.1 to 0.2pu. Then, the vector V is transformed into v in the αβ coordinate system. s =e jθ v and θ are still given by equation (4). Figure 3 The diagram shown is a control block diagram based on PSC, with vector v s This serves as a reference value for the pulse width modulator. It also includes an embedded current controller (CC), but this current controller does not function during normal operation; it is only used to limit current during transients, which is particularly important for fault ride-through.

[0047] In one optional embodiment, the analysis and processing of the active power control loop and the DC link control loop in the initial power synchronization control model to obtain the analysis result includes: determining the open-loop transfer function and the closed-loop transfer function of the initial power synchronization control model; determining the dynamic performance of the active power control loop and the DC link control loop based on the open-loop transfer function and the closed-loop transfer function; and determining the dynamic performance as the analysis result.

[0048] As an alternative embodiment, the open-loop transfer function G from Δθ to ΔP is given, taking into account the active resistance, i.e., neglecting R. θP (s), the numerator coefficient of the transfer function—the current at the operating point—is represented by the steady-state dq-axis converter current i0 = i d0 +ji q0 The components are represented.

[0049] κv0i0 * = κv(i d0 - j q0 ) (8)

[0050] Optionally, i d0 and -i q0 are proportional to the active and reactive output power, respectively. Thus, i q0 < 0 and i q0 > 0 correspond to injection and absorption of reactive current, respectively. The open-loop transfer function G θP (s) is expressed as:

[0051]

[0052] where,

[0053] Optionally, from equation (9) the following conclusions about the open-loop system dynamic performance can be drawn: when R a = 0, the system is at the critical stability condition ( in practice, R is much smaller than R a , still asymptotic stability is obtained, but the damping is very poor; when ω b → 0, the high-pass filter becomes a pure active resistance, i.e., H a (s) → R a . Thus, equation (9) simplifies to a second order system with poles at s = -R a / L ± jω1, i.e., the damping increases with the increase of SCR; the static gain G θP (0) is proportional to 1 + a + b(0), thus it is related to the operating point. High injection of reactive current (a < 0) reduces the gain. This in turn reduces the bandwidth of the closed-loop system; equation (10) shows that the static gain is also affected by the active resistance through b(s).

[0054] As an optional embodiment, the active power control mode of the closed-loop system dynamic performance can be expressed in terms of the disturbance variable as:

[0055]

[0056] Optionally, the closed-loop system block diagram as shown in Fig. 2, and the open-loop and closed-loop transfer functions are given as: Figure 4

[0057]

[0058] where, the gain selection for robust stability: G p (s) can be analyzed by applying the Nyquist criterion to G c ​stability of (s). In one aspect, based on robustness, phase and gain margins Φ m and g m need to be large enough, i.e. Φ m ≥ 45° and g m ≥ 2. On the other hand, too large stability margins can affect the bandwidth of the closed loop system. Therefore, a design approach targeting at minimum gain margin is sought, which can be formulated as:

[0059]

[0060] For the gain selection, it is noted that: in order to achieve the desired gain margin, equation (13) does not contain inductance L, therefore is independent of SCR, as long as the phase margin is sufficient, this design provides robust stability; K p is inversely proportional to V 2 , and needs to be adjusted in case of any change in V. It has marginal effect under normal operating conditions, as V is maintained at or close to the reference voltage (1.0 p.u.). However, in case of fault ride-through, V can need to be temporarily reduced to a value much lower than the reference value, in order to avoid overcurrent. In this case, keeping K p at its reference value can result in insufficient gain.

[0061] As an alternative embodiment, the closed loop transfer function: G

[0062]

[0063] Alternatively, the denominator can be approximated as a product of two factors:

[0064]

[0065] Alternatively, from equation (14), the following conclusions can be drawn about the dynamic performance of the closed loop system: there is a pair of poles whose relative damping increases with SCR, as follows:

[0066]

[0067] Alternatively, there is a real pole at s = -(1 + a + b)R a / L, which dominates for weak grids with R a / L < ω1. Therefore, for low converter current (a and b are small), the minimum bandwidth of G c (s) is:

[0068]

[0069] where L max is the maximum expected grid inductance (Lmax = 1.0 p.u. if SCR > 1).

[0070] Optionally, for R a For a strong grid with ω1> ωL, the pole pair dominates. If ζ < 1, the pole pair is complex and each pole is at a distance ω1from the origin, thus, G c The maximum bandwidth of G

[0071] ω c,max ≈ ω1(18)

[0072] Optionally, for weak and strong grids, excessive R a may significantly reduce the bandwidth. For example, assume R a = 1.0 p.u., i q0 = 0, and V = 1.0 p.u. Then, from equation (10), it can be shown that as |i d0 |→ 1.0 p.u., b→ -1, i.e., the real pole approaches the origin and the bandwidth approaches zero. To reduce the impact on the bandwidth and achieve better damping, select:

[0073] R a = 0.2 p.u. (19)

[0074] Optionally, b can be ignored and the relative damping given by equation (16) can be expressed as:

[0075] ζ = 0.1 SCR (20)

[0076] Optionally, high reactive current injection (i q0 < 0) can significantly limit the bandwidth:

[0077]

[0078] Optionally, if the PSC is cascaded with the DC link controller, the bandwidth reduction of G c (s) due to high reactive current injection needs to be considered.

[0079] As an optional embodiment, the DC link control can be added as an outer loop cascaded with the active power control loop. If the converter losses are ignored, the DC link dynamic behavior can be represented by the energy W d stored in the DC link as:

[0080]

[0081] where P d is the DC source power. The DC link energy is related to the DC link voltage v d and the DC link capacitance C d as Wd =(C d / 2)v d 2 Typically, Pd is known and used as a feedforward, or it may be a low-pass filter (P... d f ):

[0082] P ref =F d (s)(W d -W d ref )+P d f (twenty three)

[0083] Among them, W d ref It is the reference energy, F d (s) is the transfer function of the DC-link controller. Through feedforward, the DC-link controller can be given weak integral action, allowing F... d (s) is approximately a proportional controller F d (s)=K d Gain K d It can be considered as the bandwidth of an ideal DC link control loop.

[0084] Optionally, equations (22) and (23) are formed together with the active power control loop. Figure 5 The schematic diagram of the DC link control loop shown has an open-loop transfer function G. d (s)=K d *G c (s) / s. Robust design of DC link control gain can be achieved using a method similar to that used for active power control gain. To obtain a sufficiently large phase margin, the minimum gain margin is 4.

[0085] In one optional embodiment, determining the target power synchronization control model based on the analysis results includes: performing robust design of the DC link control gain based on the analysis results to obtain the target power synchronization control model.

[0086] As an optional implementation, P is manually set. ref The DC link voltage is controlled by a DC power converter. Simulations were performed under different short-circuit ratio settings, i.e., applied in very weak, weak, and strong networks.

[0087] In existing technologies, the typical goal of a VSM is to form a network by utilizing frequency droop and virtual inertia, the latter of which is introduced by adding a low-pass filter through PSC control. For a VSM, the DC power supply P... dmust be controllable so that the active power output P responds to changes in the grid frequency. Therefore, for VSM design, it is preferable to implement DC link control through P d instead of cascading with the active power control loop.

[0088] In the embodiment of the present application, a robust design scheme of PSC active power and DC link control gain is provided, which is not limited by grid short circuit ratio (SCR) and operating conditions, has a large enough stability margin and good robustness. First, a system model is established based on certain basic assumptions and the principle of PSC is briefly introduced; then, based on dynamic performance analysis of PSC, the active power and DC link control loop are robustly designed.

[0089] Through the embodiment of the present application, under different intensity of the grid (i.e. different short circuit ratios), the stability margin is large, and through analysis and verification, it can be concluded that it has good robustness, that is, even if the control system is disturbed by certain parameters, the stability of the system can still be guaranteed.

[0090] Through the above steps, the system model is established based on certain basic assumptions and the principle of PSC is briefly introduced; then, based on dynamic performance analysis of PSC, the active power and DC link control loop are robustly designed, which is not limited by grid short circuit ratio (SCR) and operating conditions, has a large enough stability margin and good robustness.

[0091] Embodiment 2

[0092] According to the embodiment of the present application, a device embodiment for implementing the above power synchronization control method is also provided, Figure 6 is a structural schematic diagram of a power synchronization control device according to the embodiment of the present application, as Figure 6 shown, the device comprises: an establishing module 60, an analysis module 62, a determining module 64 and a control module 66, wherein:

[0093] The establishing module 60 is configured to establish an initial power synchronization control model;

[0094] The analysis module 62 is configured to analyze and process the active power control loop and the DC link control loop in the initial power synchronization control model to obtain an analysis result;

[0095] The determining module 64 is configured to determine a target power synchronization control model based on the analysis result;

[0096] The control module 66 is configured to perform power synchronization control by using the target power synchronization control model.

[0097] It should be noted that the above-mentioned establishing module 60, analyzing module 62, determining module 64 and controlling module 66 correspond to steps S102 to S108 in Embodiment 1, and the four modules have the same instances and application scenarios as the corresponding steps, but are not limited to the above-mentioned disclosure in Embodiment 1.

[0098] It should be noted that the preferred embodiments of the present embodiment can refer to the related description in Embodiment 1, which will not be repeated here.

[0099] According to the embodiments of the present application, an embodiment of a computer readable storage medium is also provided. Optionally, in the present embodiment, the above-mentioned computer readable storage medium can be used to save the program code executed by the power synchronization control method provided in Embodiment 1.

[0100] Optionally, in the present embodiment, the above-mentioned computer readable storage medium can be located in any one of the computer terminals in the computer terminal group in the computer network, or in any one of the mobile terminals in the mobile terminal group.

[0101] Optionally, in the present embodiment, the computer readable storage medium is configured to store program code for performing the following steps: establishing an initial power synchronization control model; analyzing and processing the active power control loop and the DC link control loop in the initial power synchronization control model to obtain an analysis result; determining a target power synchronization control model based on the analysis result; and performing power synchronization control using the target power synchronization control model.

[0102] Optionally, the above-mentioned computer readable storage medium is configured to store program code for performing the following steps: determining a first space vector of the converter voltage, a second space vector of the grid voltage and a third space vector of the converter output current; determining a model relationship based on the first space vector, the second space vector and the third space vector; and establishing the initial power synchronization control model based on the model relationship.

[0103] Optionally, the above-mentioned computer readable storage medium is configured to store program code for performing the following steps: determining an open-loop transfer function and a closed-loop transfer function of the initial power synchronization control model; determining the dynamic performance of the active power control loop and the DC link control loop based on the open-loop transfer function and the closed-loop transfer function; and determining the dynamic performance as the analysis result.

[0104] Optionally, the above-mentioned computer readable storage medium is configured to store program code for performing the following steps: performing robust design of the DC link control gain based on the analysis result to obtain the target power synchronization control model.

[0105] According to an embodiment of the present application, a processor is also provided. Optionally, in this embodiment, the computer readable storage medium described above can be used to save the program code executed by the power synchronization control method provided in embodiment 1.

[0106] An electronic device is provided in an embodiment of the present application. The device includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the following steps are implemented: an initial power synchronization control model is established; the active power control loop and the DC link control loop in the initial power synchronization control model are analyzed and processed to obtain an analysis result; a target power synchronization control model is determined based on the analysis result; and the target power synchronization control model is used for power synchronization control.

[0107] The present application also provides a computer program product adapted to execute the following steps when executed on a data processing device: an initial power synchronization control model is established; the active power control loop and the DC link control loop in the initial power synchronization control model are analyzed and processed to obtain an analysis result; a target power synchronization control model is determined based on the analysis result; and the target power synchronization control model is used for power synchronization control.

[0108] The above-mentioned embodiment numbers of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0109] In the above-mentioned embodiments of the present application, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0110] In several embodiments provided in the present application, it should be understood that the disclosed technical contents can be implemented by other ways. Among them, the above-mentioned device embodiments are only schematic, for example, the division of the units can be a logical function division, and actual implementation can have another division way, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or modules shown or discussed can be indirect coupling or communication connection through some interfaces, units or modules, which can be electrical or other forms.

[0111] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple units. Part or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0112] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function unit.

[0113] When the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application, essentially or the part that contributes to the prior art, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various program code storage media.

[0114] The above is only the preferred embodiment of the present application, and it should be pointed out that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A power synchronization control method, characterized in that, include: Establish an initial power synchronization control model; The active power control loop and DC link control loop in the initial power synchronization control model are analyzed and processed to obtain the analysis results. Based on the analysis results, a target power synchronization control model is determined; Power synchronization control is performed using the target power synchronization control model. The establishment of the initial power synchronization control model includes: determining a first space vector of the converter voltage, a second space vector of the grid voltage, and a third space vector of the converter output current; determining model relationships based on the first space vector, the second space vector, and the third space vector; and establishing the initial power synchronization control model based on the model relationships. The process of analyzing and processing the active power control loop and the DC link control loop in the initial power synchronization control model to obtain analysis results includes: determining the open-loop transfer function and the closed-loop transfer function of the initial power synchronization control model; determining the dynamic performance of the active power control loop and the DC link control loop based on the open-loop transfer function and the closed-loop transfer function; and determining the dynamic performance as the analysis result. Wherein, the open-loop transfer function G θP (s) and the closed-loop transfer function G c The expression for (s) is: ， ， ， in, K is the space vector scaling constant, V is the converter voltage amplitude, ω1 is the synchronization angular frequency, L is the line inductance, and the current at the operating point i0 = i d0 +ji q0 i q0 i represents the current of the q-axis converter. d0 R is the current of the d-axis converter. a For active resistance, ω b This represents the filter bandwidth.

2. The method according to claim 1, characterized in that, The determination of the target power synchronization control model based on the analysis results includes: Based on the analysis results, a robust design of the DC link control gain is performed to obtain the target power synchronization control model.

3. A power synchronization control device, characterized in that, include: Establish a module to build the initial power synchronization control model; The analysis module is used to analyze and process the active power control loop and DC link control loop in the initial power synchronization control model to obtain analysis results; The determination module is used to determine the target power synchronization control model based on the analysis results; The control module is used to perform power synchronization control using the target power synchronization control model; The analysis module is further configured to determine the open-loop transfer function and closed-loop transfer function of the initial power synchronization control model; based on the open-loop transfer function and the closed-loop transfer function, determine the dynamic performance of the active power control loop and the DC link control loop; and determine the dynamic performance as the analysis result. The process of analyzing and processing the active power control loop and the DC link control loop in the initial power synchronization control model to obtain analysis results includes: determining the open-loop transfer function and the closed-loop transfer function of the initial power synchronization control model; determining the dynamic performance of the active power control loop and the DC link control loop based on the open-loop transfer function and the closed-loop transfer function; and determining the dynamic performance as the analysis result. Wherein, the open-loop transfer function G θP (s) and the closed-loop transfer function G c The expression for (s) is: ， ， ， in, K is the space vector scaling constant, V is the converter voltage amplitude, ω1 is the synchronization angular frequency, L is the line inductance, and the current at the operating point i0 = i d0 +ji q0 i q0 i represents the current of the q-axis converter. d0 R is the current of the d-axis converter. a For active resistance, ω b This represents the filter bandwidth.

4. A non-volatile storage medium, characterized in that, The non-volatile storage medium stores multiple instructions, which are adapted to be loaded by a processor and executed by the power synchronization control method according to any one of claims 1 to 2.

5. A processor, characterized in that, The processor is used to run a program, wherein the program is configured to execute the power synchronization control method according to any one of claims 1 to 2 when running.

6. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the power synchronization control method according to any one of claims 1 to 2.

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