A MIPI radio frequency switch

Abstract

The application discloses a MIPI radio frequency switch, which can meet the control requirements of the radio frequency switch, and can avoid mutual interference and signal overlap in switching moment of the switch, and comprises a radio frequency switch unit and a driving circuit module; the driving circuit module comprises a charge pump unit and a level conversion unit; the charge pump unit comprises a positive voltage charge pump and a negative voltage charge pump; the positive voltage charge pump is used for generating a positive voltage Vpose; the negative voltage charge pump is used for generating a negative voltage Vneg; the radio frequency switch unit comprises at least two switches, i.e., a first switch and a second switch; the level conversion unit comprises a first-level conversion unit and a second-level conversion unit; first driving voltage and second driving voltage generated by the first-level conversion unit are sent to the first switch and the second switch; and third driving voltage and fourth driving voltage generated by the second-level conversion unit are sent to the first switch and the second switch in the radio frequency switch unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency switch, in particular to a MIPI radio frequency switch. BACKGROUND

[0002] With the rapid development of mobile communication technology, radio frequency transceiver, power amplifier, low noise amplifier, filter, switch, power management module and antenna tuner and other radio frequency front-end devices are widely used in mobile phones, notebook computers and other communication equipment. The configuration of control and working mode in these radio frequency front-end devices is mainly carried out by the host through the digital bus.

[0003] Among them, the opening and closing operation of the MIPI radio frequency switch (MIPI PFFE interface) and other small size radio frequency front-end devices such as antenna tuner is controlled by positive voltage and negative voltage. The MIPI radio frequency switch complies with the MIPI protocol, and the radio frequency switch is turned on by positive voltage and turned off by negative voltage, so as to realize the transmission and reception switching of mobile communication equipment. The control signal of positive voltage and negative voltage is a square wave clock signal, which is generated by a clock circuit. In the existing radio frequency switch, the control of positive voltage and negative voltage is generated by the same clock circuit. When the radio frequency device transmits a signal, the clock circuit sends the generated complementary clock signal CLK to the positive voltage charge pump for generating positive voltage and the negative voltage charge pump for generating negative voltage. The positive voltage and the negative voltage are the driving voltage of the radio frequency switch. When it is necessary to switch the radio frequency switch for generating a radio frequency signal, the complementary clock signals CLK+ and CLK- are switched. However, at the switching moment, the switching tubes in the circuit are prone to mutual interference and signal overlap, resulting in unstable voltage. Unstable external driving voltage can easily cause the internal performance of the radio frequency switch device to deteriorate. Therefore, it is urgent for those skilled in the art to provide a radio frequency switch driving circuit device that can provide stable driving voltage for the radio frequency switch. SUMMARY

[0004] In view of the above problems in the prior art, the present application provides a MIPI radio frequency switch which can meet the control requirements of the radio frequency switch, avoid mutual interference and signal overlap at the switching moment of the switch, and ensure the stability of the voltage at the switching moment of the switch.

[0005] To achieve the above-mentioned purposes, the present application adopts the following technical solutions:

[0006] A MIPI radio frequency switch includes a radio frequency switch unit and a driving circuit module. The driving circuit module includes a charge pump unit and a level conversion unit. The charge pump unit includes a positive voltage charge pump and a negative voltage charge pump. The positive voltage charge pump is used to generate a positive voltage Vpose, and the negative voltage charge pump is used to generate a negative voltage Vneg. The radio frequency switch unit includes at least two switches: a first switch and a second switch. The input of the radio frequency switch unit is connected to an antenna. The level conversion unit includes a first-level level conversion unit and a second-level level conversion unit. The second-level level conversion unit includes a second-level level conversion circuit. The input terminals of the positive voltage charge pump and the negative voltage charge pump are both connected to a voltage source VIO and a complementary non-overlapping clock signal.

[0007] The input terminal of the first-level level conversion unit is connected to the negative voltage Vneg and the voltage source VIO. The output terminal of the first-level level conversion unit includes output terminals sw_in, Vb1-1, and Vb1-2. The output terminal sw_in is connected to the input terminal of the second-level level conversion unit.

[0008] The input terminal of the two-level level conversion unit is connected to the positive voltage Vpose, the voltage source VIO, and the output terminal sw_in. The output terminal of the two-level level conversion unit includes output terminals Vg1-1 and Vg1-2.

[0009] The output terminals Vb1-1 and Vg1-2 are connected to the first switch in the radio frequency switch unit, and the output terminals Vg1-1 and Vg1-2 are connected to the second switch in the radio frequency switch unit.

[0010] The input terminal of the first-level level conversion unit is also connected to the control signal terminal BS. The control signal terminal BS transmits logic control signals. The first-level level conversion unit is used to generate a first driving voltage and a second driving voltage. The first driving voltage and the second driving voltage are sent to the first switch and the second switch in the radio frequency switch unit through the output terminals Vb1-1 and Vb1-2, respectively.

[0011] The secondary level conversion unit is used to generate a third driving voltage and a fourth driving voltage. The third driving voltage and the fourth driving voltage are sent to the first switch and the second switch in the radio frequency switch unit through the output terminals Vg1-1 and Vg1-2, respectively. The first switch and the second switch are turned on or off by the first driving voltage, the second driving voltage, the third driving voltage and the fourth driving voltage.

[0012] Its further feature is that,

[0013] The first-level level conversion unit includes a first-level level conversion circuit and a second-level level conversion circuit. The second-level level conversion circuit includes a first-second-level level conversion circuit and a second-second-level level conversion circuit. The input terminals of the first-level level conversion circuit and the second-level level conversion circuit are both connected to a negative voltage Vneg and a voltage source VIO, and their output terminals are Vb1-1 and Vb1-2, respectively. The input terminals of the first-second-level level conversion circuit and the second-second-level level conversion circuit are both connected to a voltage source VIO and a positive voltage Vpose, and their output terminals are Vg1-1 and Vg1-2, respectively. The first-second-level level conversion circuit and the second-second-level level conversion circuit have the same structure.

[0014] Both the first switch and the second switch are MOSFETs. The gate of the first switch is connected to the output terminals Vg1-1 and Vb1-1, respectively. The gate of the second switch is connected to the output terminals Vb1-2 and Vg1-2, respectively. The source of the first switch is connected to the antenna. The drain of the first switch is connected to the source of the second switch and the RF output terminal T1, respectively. The drain of the second switch is grounded.

[0015] Both the first-level and second-level level conversion circuits employ a two-level level conversion circuit. The two-level level conversion circuit includes an initial level conversion unit, a first control switch, and a second control switch. The inputs of the initial level conversion unit are respectively connected to the logic control signal BS, the voltage source VIO, and the positive voltage Vpose. The initial level conversion unit includes several MOS transistors. The output of the initial level conversion unit is connected to the input of a first inverter. The output of the first inverter is connected to the input of the first control switch. The output of the first control switch is connected to the output of the second control switch and its output terminal sw-out. The input of the second control switch is connected to the output terminal sw_in of the first-level level conversion circuit, the voltage source VIO, and the negative voltage Vneg.

[0016] The initial level conversion unit includes a second inverter and a third inverter connected in series. The input terminal of the second inverter is connected to the control signal terminal BS and the voltage source VIO. The output terminal of the third inverter is connected to the gate of MOSFET M1. The source of MOSFET M1 is connected to the output terminal OUTB, the drain of MOSFET M2, and the gate of MOSFET M3. The gate of MOSFET M2 is connected to the source of MOSFET M3 and the source of MOSFET M4. The drains of MOSFET M2 and MOSFET M3 are both connected to the voltage source Vdd. The drains of MOSFETs M1 and M2 are both grounded.

[0017] The first control switch includes MOSFETs M5 and M6, and the second control switch includes MOSFETs M7 and M8. The source of MOSFET M5 is connected to the output of the first inverter, the drain of MOSFET M5 is connected to the drain of MOSFET M6, the source of MOSFET M6 is connected to the drain of MOSFET M8 and the output terminal sw-out, the source of MOSFET M8 is connected to the drain of MOSFET M7, and the drain of MOSFET M7 is connected to the output terminal sw_in.

[0018] The MOS transistors M1, M3, M5, and M6 are all PMOS transistors, and the MOS transistors M2, M4, M7, and M8 are all NMOS transistors.

[0019] The above-described structure of this invention achieves the following beneficial effects: The charge pump unit in this MIPI RF switch includes a positive charge pump and a negative charge pump, and the level conversion unit includes a first-level level conversion unit and a second-level level conversion unit. Since the control signals of the positive and negative charge pumps are complementary and non-overlapping clock signals, under the control of the complementary and non-overlapping clock signals, the positive voltage Vpose and negative voltage Vneg output by the positive and negative charge pumps are complementary and non-overlapping voltage signals. The drive voltage signals output by the first-level and second-level level conversion units are also complementary and non-overlapping signals. This avoids the simultaneous weak conduction of the switching transistors in the first-level and second-level level conversion units at the instant of clock signal CLK+ and CLK- conversion, i.e., when switching control is performed on the first and second switches in the RF switch. This avoids mutual interference and signal overlap, and ensures the stability of the drive voltage. Attached Figure Description

[0020] Figure 1 This is a structural block diagram of the present invention;

[0021] Figure 2 This is a circuit diagram of the two-level level conversion circuit of the present invention;

[0022] Figure 3 This is a circuit diagram of the initial level conversion unit in the two-level level conversion circuit of the present invention;

[0023] Figure 4 This is a circuit schematic diagram of the clock circuit of the present invention;

[0024] Figure 5 This is a circuit diagram of the complementary clock signal generation circuit of the present invention;

[0025] Figure 6 This is a circuit schematic diagram of the non-overlapping clock signal generation circuit of the present invention;

[0026] Figure 7This is a simulation diagram showing the logic control signal BS, the voltage signal output from the output terminal sw_in, the voltage of the voltage source VIO, the positive voltage Vpose, and the voltage signal output from the output terminal sw_out in the MIPI RF switch of this invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and the above-mentioned drawings of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products or devices.

[0028] See Figure 1 The following provides a specific embodiment of a MIPI radio frequency switch, which includes a radio frequency switch unit 1 and a driving circuit module. The driving circuit module includes a charge pump unit 2 and a level conversion unit 3. The charge pump unit 2 includes a positive charge pump and a negative charge pump. The positive charge pump is used to generate a positive voltage Vpose, and the negative charge pump is used to generate a negative voltage Vneg. The inputs of the positive charge pump and the negative charge pump each include a first input terminal, a second input terminal, and a third input terminal. The first input terminal is connected to a voltage source VIO, and the second and third input terminals are connected to complementary non-overlapping clock signals CLK+ and CLK-. The complementary non-overlapping clock signals CLK+ and CLK- are generated by a clock circuit.

[0029] Level conversion unit 3 includes a first-level level conversion unit and a second-level level conversion unit. The input terminals of the first-level level conversion unit are connected to a voltage source VIO, a control signal terminal BS, and a negative voltage Vneg output from a negative charge pump, respectively. The input terminals of the level conversion unit are connected to a logic decoder, which is a MIPI decoder conforming to the MIPI interface protocol. External signals sclk and sdata are decoded by the logic decoder to generate a set of logic control signal arrays. This logic signal array is transmitted to the first and second level conversion units in the first-level level conversion unit via the control signal terminal BS for logic control of the first-level and second-level level conversion units. The input terminals of the first-level level conversion unit are also connected to the negative voltage Vneg output from the negative charge pump and the voltage source VIO. The output terminals of the first-level level conversion unit include an output terminal sw_in, an output terminal Vb1-1, and a Vb1-2. The output terminal sw_in is connected to the input of the second-level level conversion unit. The input terminals of each level conversion unit are connected to the positive voltage Vpose output by the positive charge pump, the voltage source VIO, and the output terminal sw_in of the first-level level conversion circuit. The output terminals of the second-level level conversion unit include output terminals Vg1-1 and Vg1-2; output terminals Vb1-1 and Vg1-2 are connected to the first switch in the RF switch unit, and output terminals Vg1-1 and Vg1-2 are connected to the second switch in the RF switch unit. The first-level level conversion unit is used to generate a first driving voltage and a second driving voltage, which are sent to the first and second switches in the RF switch unit via output terminals Vb1-1 and Vb1-2, respectively. The second-level level conversion unit is used to generate a third driving voltage and a fourth driving voltage, which are sent to the second switch in the RF switch unit via output terminals Vg1-1 and Vg1-2, respectively, to drive the first and second switches to open or close.

[0030] In this embodiment, the first-level level conversion unit includes a first-level level conversion circuit and a second-level level conversion circuit, and the second-level level conversion unit includes a first-second-level level conversion circuit and a second-second-level level conversion circuit. The input terminals of the first-level level conversion circuit and the second-level level conversion circuit are both connected to a voltage source VIO, and the output terminals are Vb1-1 and Vb1-2, respectively. The input terminals of the first-second-level level conversion circuit and the second-second-level level conversion circuit are both connected to a voltage source VIO and a positive voltage Vpose, and the output terminals of the first-second-level level conversion circuit and the second-second-level level conversion circuit are Vg1-1 and Vg1-2, respectively. The value of the voltage source VIO is equal to the value of the voltage source Vdd.

[0031] The first switch and the second switch in the RF switch unit are both MOS transistors. The gate of the first switch is connected to the output terminals Vg1-1 and Vb1-1, respectively. The gate of the second switch is connected to the control signal terminals Vb1-2 and Vg1-2, respectively. The source of the first switch is connected to the antenna. The drain of the first switch is connected to the source of the second switch and the RF output terminal T1, respectively. The drain of the second switch is grounded.

[0032] See Figure 2 Both the first-level and second-level level conversion circuits employ a two-level level conversion circuit. The two-level level conversion circuit includes an initial level conversion unit 31, a first control switch 32, and a second control switch 33. The inputs of the initial level conversion unit 31 are connected to the logic control signal BS, the voltage source VIO, and the positive voltage Vpose, respectively. The initial level conversion unit includes several MOS transistors. The output of the initial level conversion unit is connected to the input of the first inverter Q1. The output of the first inverter is connected to the input of the first control switch. The output of the first control switch is connected to the output of the second control switch and the output sw-out, respectively. The input of the second control switch is connected to the output sw_in of the first-level level conversion circuit, the voltage source VIO, and the negative voltage Vneg.

[0033] See Figure 3The initial level conversion unit 31 includes a second inverter Q2 and a third inverter Q3 connected in series. The input terminal of the second inverter Q2 is connected to the control signal terminal BS and the voltage source VIO. The output terminal of the third inverter Q3 is connected to the gate of MOSFET M1. The source of MOSFET M1 is connected to the output terminal OUTB, the drain of MOSFET M2, and the gate of MOSFET M3. The gate of MOSFET M2 is connected to the source of MOSFET M3 and the source of MOSFET M4. The drains of MOSFET M2 and MOSFET M3 are both connected to the voltage source Vdd. The drains of MOSFETs M1 and M2 are both grounded (Vss). In this initial level conversion unit, the voltage source VIO is inverted once by the second inverter to obtain the inverted voltage inb, and then inverted twice by the third inverter to obtain the inverted voltage inbb. The inverted voltage inb is the driving voltage of MOSFET M4, and the inverted voltage inbb is the driving voltage of MOSFET M2. MOSFETs M1~M2 are turned on or off under the combined action of the voltage source VIO and the inverted voltage inb or inbb. For example, when the voltage source VIO is 1.8V / 0V, that is, when the voltage source VIO is 1.8V / 0V, the voltage source VIO is turned on or off. When VIO is high (1.8V) and low (0V), MOSFETs M2 and M3 are turned on, while MOSFETs M1 and M4 are turned off, and the output voltage OUTB is 1.8V. When the control signal changes and the voltage source VIO is 0V / 1.8V, MOSFETs M2 and M3 are turned off, while MOSFETs M1 and M4 are turned on, and the output voltage OUTB is 0. The output voltage OUTB is connected to the input of the first inverter in the two-stage level conversion circuit, thus providing a power signal to one input of the two-stage level conversion circuit.

[0034] The first control switch includes MOSFETs M5 and M6, and the second control switch includes MOSFETs M7 and M8. The source of MOSFET M5 is connected to the output of the first inverter, and the drain of MOSFET M5 is connected to the drain of MOSFET M6. The source of MOSFET M6 is connected to the drain of MOSFET M8 and the output terminal sw-out. The source of MOSFET M8 is connected to the drain of MOSFET M7, and the drain of MOSFET M7 is connected to the output terminal sw_in. The voltage output at output terminal OUTB is applied to one end of the first control switch via the first inverter, and under the action of the inverted voltage inbb, MOSFETs M5 and M6 are turned on or off. The control signal sw_in output from the first-level level conversion unit is applied to one end of the second control switch, and under the action of the inverted voltage inb and the voltage source VIO / Vneg, MOSFETs M7 and M8 are turned off or on. For example, when the voltage source VIO is high (1.8V), the negative voltage charge pump outputs a negative voltage Vneg of -2.8V, and the positive voltage... When the positive voltage Vpose of the load pump is 2.8V, MOSFETs M5 and M6 are turned on, while MOSFETs M7 and M8 are turned off. The voltage output at the output terminal SW_OUT is 2.8V. Conversely, under the action of the control signal sw_in and the negative voltage Vneg, the second control switch turns off MOSFETs M5 and M6 and turns on MOSFETs M7 and M8. At this time, the voltage output at the output terminal SW_OUT is -2.8V. That is, the output terminals Vg1-1 and Vg1-2 output voltages of 2.8V and -2.8V, respectively.

[0035] The complementary, non-overlapping clock signals CLK+ and CLK- are generated by the clock circuit, the complementary clock signal generation circuit, and the non-overlapping clock signal generation circuit. The clock circuit includes an inverter composed of MOSFETs and resistors R1 to R3. For details on the electronic components included in the clock circuit and their interconnections, please refer to [link to relevant documentation]. Figure 4 The clock circuit input is connected to a voltage source Vdd, and the output is a clock signal CLK. The clock signal CLK is then processed by a complementary clock signal generation circuit (see...). Figure 5 The complementary clock signals CLKa and CLKb are generated. The complementary clock signal generation circuit includes PMOS transistors M26~M28 and NMOS transistors M29~M31. PMOS transistors M26 and M29, M27 and M30, and M28 and M31 are respectively configured as inverters. These inverters invert the complementary clock signals CLKa and CLKb, which are then passed through a non-overlapping clock signal generation circuit to generate non-overlapping clock signals CLK+ and CLK-. The non-overlapping clock signal generation circuit is described in [link to circuit description]. Figure 6 The circuit includes PMOS transistors M51 and M53, NMOS transistors M52 and M54, NOR gates F11 and F21, and NOT gates F12, F22, F13, F23, F14, and F24. See details... Figure 6By using inverters composed of PMOS and NMOS transistors, logic NOR gates, logic NOT gates, and crossover structures, complementary clock signals are not output at the same time, thus generating complementary non-overlapping clock signals CLK+ and CLK-.

[0036] In this application, an initial level conversion unit is provided at one input terminal of the secondary level conversion circuit. The initial level conversion unit includes several MOSFETs. The other input terminal of the secondary level conversion circuit is connected to a primary level conversion circuit. Through the combined action of the conduction control of the MOSFETs in the initial level conversion unit and the primary level conversion circuit, the first control switch and the second control switch in the secondary level conversion circuit are turned on at different times. The setting of the primary level conversion unit facilitates the rapid turn-on or turn-off of the second control switch on the other side of the secondary level conversion circuit. The setting of the initial level conversion unit causes the first control switch on one side of the secondary level conversion circuit to be delayed in turning off or on after the second control switch, thereby preventing the problem of the first control switch and the second control switch being weakly turned on at the same time in the secondary level conversion circuit, avoiding mutual interference and signal overlap, and ensuring the stability of the output voltage.

[0037] When switching control of the first and second switches in the RF switch unit is required, the positive and negative charge pumps are controlled by complementary non-overlapping clock signals CLK+ and CLK- generated by the clock circuit. The first-level level conversion unit and the second-level level conversion unit are controlled sequentially by logic control signals to obtain the switch drive voltages of the RF switch unit: the first drive voltage, the second drive voltage, the third drive voltage, and the fourth drive voltage. The first switch in the RF switch unit is turned on or off under the action of the first and third drive voltages, and the second switch is turned off or on under the action of the second and fourth drive voltages, thereby realizing the switching drive control of the switches in the RF switch unit. Since the signals used to control the positive and negative charge pumps are complementary and non-overlapping clock signals, the positive voltage Vpose and negative voltage Vneg output by the positive and negative charge pumps are complementary and non-overlapping voltage signals under the control of the complementary and non-overlapping clock signals. The drive voltage signals output by the first-level and second-level level conversion units are also complementary and non-overlapping signals. This avoids the simultaneous weak conduction of the switching transistors in the first-level and second-level level conversion units at the moment of clock signal CLK+ and CLK- conversion, i.e. when the first and second switches in the RF switch are switched, thus improving the isolation effect and avoiding mutual interference and signal overlap, ensuring the stability of the drive voltage.

[0038] Figure 7Simulation results are presented for the logic control signal BS, the voltage signal output from the output terminal sw_in, the voltage of the voltage source VIO, the positive voltage Vpose, and the voltage signal output from the output terminal sw_out in the MIPI RF switch of this invention. Figure 7 The horizontal axis represents time dx, and the vertical axes A, B, C, D, E, and F represent the logic control signal BS, the voltage signal output from the output terminal sw_in, the voltage of the voltage source VIO, the positive voltage Vpose, and the voltage signal output from the output terminal sw_out, respectively. Figure 7 As can be seen, when the voltage of the voltage source VIO is 1.8V, the voltage of the logic control signal BS is 1.8V, the voltage output of the first-stage charge pump output terminal sw_in is 1.8V, and the positive voltage Vpose output of the positive charge pump is 2.8V, using the MIPI RF switch structure of this application, the voltage output of the output terminal sw_out reaches approximately 2.8V, that is, the output terminals Vg1-1 and Vg1-2 output voltages of 2.8V and -2.8V respectively, thereby meeting the control requirements of the RF switch.

[0039] The above are merely preferred embodiments of this application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that are directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A MIPI radio frequency switch, comprising a radio frequency switch unit and a driving circuit module, the driving circuit module comprising a charge pump unit and a level conversion unit, the charge pump unit comprising a positive voltage charge pump and a negative voltage charge pump, the positive voltage charge pump being used to generate a positive voltage Vpose, and the negative voltage charge pump being used to generate a negative voltage Vneg, the radio frequency switch unit comprising at least two switches: a first switch and a second switch, the input of the radio frequency switch unit being connected to an antenna, characterized in that, The level conversion unit includes a first-level level conversion unit and a second-level level conversion unit. The second-level level conversion unit includes a second-level level conversion circuit. The input terminals of the positive and negative charge pumps are both connected to a voltage source VIO and a complementary non-overlapping clock signal. The complementary non-overlapping clock signal includes complementary non-overlapping clock signals CLK+ and CLK-. The complementary non-overlapping clock signals CLK+ and CLK- are generated by a clock circuit, a complementary clock signal generation circuit, and a non-overlapping clock signal generation circuit. The input terminal of the first-level level conversion unit is connected to the negative voltage Vneg and the voltage source VIO. The output terminal of the first-level level conversion unit includes output terminals sw_in, Vb1-1, and Vb1-2. The output terminal sw_in is connected to the input terminal of the second-level level conversion unit. The input terminal of the two-level level conversion unit is connected to the positive voltage Vpose, the voltage source VIO, and the output terminal sw_in. The output terminal of the two-level level conversion unit includes output terminals Vg1-1 and Vg1-2. The output terminals Vb1-1 and Vg1-2 are connected to the first switch in the radio frequency switch unit, and the output terminals Vg1-1 and Vg1-2 are connected to the second switch in the radio frequency switch unit. The input terminal of the first-level level conversion unit is also connected to the control signal terminal BS. The control signal terminal BS transmits logic control signals. The first-level level conversion unit is used to generate a first driving voltage and a second driving voltage. The first driving voltage and the second driving voltage are sent to the first switch and the second switch in the radio frequency switch unit through the output terminals Vb1-1 and Vb1-2, respectively. The secondary level conversion unit is used to generate a third driving voltage and a fourth driving voltage. The third driving voltage and the fourth driving voltage are sent to the first switch and the second switch in the radio frequency switch unit through the output terminals Vg1-1 and Vg1-2, respectively. The first switch and the second switch are turned on or off by the first driving voltage, the second driving voltage, the third driving voltage and the fourth driving voltage.

2. The MIPI radio frequency switch according to claim 1, characterized in that, The first-level level conversion unit includes a first-level level conversion circuit and a second-level level conversion circuit. The second-level level conversion circuit includes a first-second-level level conversion circuit and a second-second-level level conversion circuit. The input terminals of the first-level level conversion circuit and the second-level level conversion circuit are both connected to the negative voltage Vneg and the voltage source VIO, and the output terminals are Vb1-1 and Vb1-2, respectively. The input terminals of the first-second-level level conversion circuit and the second-second-level level conversion circuit are both connected to the voltage source VIO and the positive voltage Vpose, and the output terminals of the first-second-level level conversion circuit and the second-second-level level conversion circuit are Vg1-1 and Vg1-2, respectively. The structures of the first-second-level level conversion circuit and the second-second-level level conversion circuit are identical.

3. The MIPI radio frequency switch according to claim 2, characterized in that, Both the first switch and the second switch are MOSFETs. The gate of the first switch is connected to the output terminals Vg1-1 and Vb1-1, respectively. The gate of the second switch is connected to the output terminals Vb1-2 and Vg1-2, respectively. The source of the first switch is connected to the antenna. The drain of the first switch is connected to the source of the second switch and the RF output terminal T1, respectively. The drain of the second switch is grounded.

4. The MIPI radio frequency switch according to claim 2 or 3, characterized in that, Both the first-level and second-level level conversion circuits employ a two-level level conversion circuit. The two-level level conversion circuit includes an initial level conversion unit, a first control switch, and a second control switch. The inputs of the initial level conversion unit are connected to the logic control signal BS, the voltage source VIO, and the positive voltage Vpose, respectively. The initial level conversion unit includes several MOS transistors. The output of the initial level conversion unit is connected to the input of a first inverter. The output of the first inverter is connected to the input of the first control switch. The output of the first control switch is connected to the output of the second control switch and its output terminal sw-out, respectively. The input of the second control switch is connected to the output terminal sw_in of the first-level level conversion circuit, the voltage source VIO, and the negative voltage Vneg.

5. The MIPI radio frequency switch according to claim 4, characterized in that, The initial level conversion unit includes a second inverter and a third inverter connected in series. The input terminal of the second inverter is connected to the control signal terminal BS and the voltage source VIO. The output terminal of the third inverter is connected to the gate of MOSFET M1. The source of MOSFET M1 is connected to the output terminal OUTB, the drain of MOSFET M2, and the gate of MOSFET M3. The gate of MOSFET M2 is connected to the source of MOSFET M3 and the source of MOSFET M4. The drains of MOSFET M2 and MOSFET M3 are both connected to the voltage source Vdd. The drains of MOSFETs M1 and M2 are both grounded.

6. The MIPI radio frequency switch according to claim 5, characterized in that, The first control switch includes MOSFETs M5 and M6, and the second control switch includes MOSFETs M7 and M8. The source of MOSFET M5 is connected to the output of the first inverter, the drain of MOSFET M5 is connected to the drain of MOSFET M6, the source of MOSFET M6 is connected to the drain of MOSFET M8 and the output terminal sw-out, the source of MOSFET M8 is connected to the drain of MOSFET M7, and the drain of MOSFET M7 is connected to the output terminal sw_in.

7. The MIPI radio frequency switch according to claim 6, characterized in that, The MOS transistors M1, M3, M5, and M6 are all PMOS transistors, and the MOS transistors M2, M4, M7, and M8 are all NMOS transistors.

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