A zero-crossing detection circuit for improving the light-load efficiency of a switching power supply

Abstract

The present invention provides a zero-crossing detection circuit for improving the light-load efficiency of a switching power supply. The zero-crossing detection circuit includes a current sampling circuit, whose input terminals are respectively connected to a switching voltage node and an output terminal of the switching power supply, and whose output terminal is connected to an input terminal of an offset processing circuit. The current sampling circuit outputs a sampling current proportional to the current flowing through a rectifier tube during the inductor current decreasing stage; and an offset processing circuit, whose input terminal is connected to the output terminal of the current sampling circuit, and whose output terminal is connected to an input terminal of a logic control unit. The offset processing circuit compares the sampling current during the inductor current increasing stage with the sampling current during the inductor current decreasing stage during the inductor current decreasing stage, and generates a corresponding logic unit jump signal when the comparison result is equal. The logic unit jump signal causes the logic control unit to generate a second clock signal for controlling the rectifier tube to turn off. The zero-crossing detection circuit of the present invention improves the accuracy and timeliness of the zero-crossing detection function, thereby improving the conversion efficiency of the switching power supply under light load.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a zero-crossing detection circuit for improving the light-load efficiency of a switching power supply. Background Art

[0002] Due to its advantages such as high power density and high conversion efficiency, switching power supplies are widely used in portable and handheld electronic devices. In wearable devices, it is often required that the switching power supply has a high conversion efficiency under light-load conditions. Since the switching power supply adopts the synchronous rectification technology, the energy loss problem caused by the reverse injection of the inductor current challenges the conversion efficiency under light-load conditions.

[0003] To improve the light-load efficiency, it is often necessary to adopt the DCM operating mode, that is, when the inductor current drops to 0A, the power tube and the rectifier tube are turned off to maintain the zero-current state until the next operating cycle. The operating state of the output inductor current in one operating cycle can be divided into an ascending stage, in which the power tube is turned on and the rectifier tube is turned off, and the inductor current rises; a descending stage, in which the power tube is turned off and the rectifier tube is turned on, and the inductor current drops; and a zero-current stage, in which both the power tube and the rectifier tube are turned off, and the inductor maintains the zero-current state.

[0004] Compared with asynchronous rectification, the special structure of the synchronous rectification circuit determines that a zero-crossing detection circuit is required to provide an accurate zero-crossing detection signal to turn off the rectifier tube when the inductor current drops to 0A. Affected by factors such as process errors and temperature deviations in the semiconductor manufacturing process, the zero-crossing detection circuit has a random input offset, so that the generation time of the zero-crossing detection signal cannot be accurately synchronized with the inductor zero-current point. The two abnormal phenomena caused thereby are called the zero-crossing trigger lead phenomenon and the zero-crossing trigger lag phenomenon. As Figure 1 shown, when the zero-crossing detection signal is ahead of the inductor zero-current point, it is called the zero-crossing trigger lead phenomenon. At this time, both the power tube and the rectifier tube are turned off, and the positive current on the inductor will flow through the body diode of the rectifier tube, causing additional losses; when the zero-crossing detection signal lags behind the inductor zero-current point, it is called the zero-crossing trigger lag phenomenon. At this time, a negative current is generated on the inductor, resulting in an increase in losses. At the same time, a large voltage overshoot will occur at the switching nodes of the power tube and the rectifier tube, further increasing the switching losses and introducing EMI problems.

[0005] The existing zero-crossing detection methods can generally be divided into two types. One is the indirect sampling method, which compares the voltage of the switching node of the sampling power tube and the rectifier tube with a fixed voltage. For example, in a BUCK-BOOST switching power supply, the node voltage is compared with the output voltage. When the current in the inductor is positive, the output voltage is greater than the node voltage. When the inductor current crosses zero and generates a negative current, the node voltage is greater than the output voltage, thereby generating a zero-crossing detection signal. The other is the direct sampling method, which samples the inductor current, that is, the switching current, and compares it with 0 A to generate a zero-crossing detection signal.

[0006] Since these two detection methods compare the sampling signal with a fixed voltage or current, the random input offset of the sampling circuit cannot be corrected in time, resulting in zero-crossing detection deviation and the phenomenon of zero-crossing triggering being advanced or delayed, thereby reducing the conversion efficiency under light load. Even though there is a method that uses a counter to implement the offset cancellation function by gradually approaching, it takes several cycles to complete the calibration and cannot achieve real-time correction. At the same time, the complex circuit structure adds additional pressure to the system design. Summary of the Invention

[0007] The purpose of the present invention is to provide a design concept of a zero-crossing detection circuit applied to a switching power supply to improve the conversion efficiency of the switching power supply under light load.

[0008] To solve the above problems, the present invention provides a zero-crossing detection circuit for improving the light-load efficiency of a switching power supply. The switching power supply includes a power tube, a rectifier tube, and a storage inductor, one end of which is connected to the switching voltage node. The other end of the power tube is connected to the positive pole of the power supply voltage. The other end of the rectifier tube is the output end of the switching power supply. The gate terminals of the power tube and the rectifier tube are both connected to a logic control unit, and the logic control unit is configured to provide a first clock signal to the gate terminal of the power tube and a second clock signal to the gate terminal of the rectifier tube. The zero-crossing detection circuit includes a current sampling circuit and an offset processing circuit. The first input terminal of the current sampling circuit is connected to the switching voltage node, its second input terminal is connected to the output end of the switching power supply, and its output end is connected to the first input terminal of the offset processing circuit. It is configured to output a sampling current proportional to the current flowing through the rectifier tube during the inductor current drop phase. The first input terminal of the offset processing circuit is connected to the output end of the current sampling circuit, and its output end is connected to the input terminal of the logic control unit. It is configured to compare the sampling current during the inductor current rise phase and the sampling current during the inductor current drop phase during the inductor current drop phase, and generate a corresponding logic unit jump signal when the comparison result is equal. This logic unit jump signal causes the logic control unit to generate a second clock signal for controlling the rectifier tube to turn off.

[0009] The current sampling circuit includes:

[0010] A multiplexer, the first input terminal of the multiplexer is connected to the second input terminal of the current sampling circuit, the second input terminal of the multiplexer is connected to the first input terminal of the current sampling circuit, and the selection control terminal is connected to the first clock signal and the second clock signal;

[0011] A first NMOS transistor, whose source terminal is connected to the output terminal of the multiplexer;

[0012] A second NMOS transistor, whose source terminal is connected to the second input terminal of the current sampling circuit, and the gate terminal of the second NMOS transistor is connected to the gate terminal of the first NMOS transistor and is connected to the drain terminal of the second NMOS transistor;

[0013] A first resistor, which is connected between the source terminal of the first NMOS transistor and the output terminal of the multiplexer;

[0014] A second resistor, which is connected between the source terminal of the second NMOS transistor and the second input terminal of the zero-crossing detection circuit;

[0015] A first current source, the positive pole of the first current source is connected to the power supply voltage, and the negative pole is connected to the drain terminal of the first NMOS transistor;

[0016] A second current source, the positive pole of the second current source is connected to the power supply voltage, and the negative pole is connected to the drain terminal of the second NMOS transistor; and

[0017] A third NMOS transistor, the source terminal of the third NMOS transistor is connected to the source terminal of the second NMOS transistor, the gate terminal of the third NMOS transistor is connected to the drain terminal of the first NMOS transistor, and the drain terminal of the third NMOS transistor is the output terminal of the current sampling circuit.

[0018] The currents of both the first current source and the second current source are equal, and the resistance value of the first resistor is equal to 2 times the resistance value of the second resistor.

[0019] The selection control ports of the multiplexer are respectively connected to the first clock signal and the second clock signal. The selection of the first input terminal and the second input terminal of the multiplexer is controlled by the first clock signal and the second clock signal. During the inductor current drop phase, the second clock signal is high and the first clock signal is low, and the multiplexer selects the second input terminal to be electrically connected to its output terminal; otherwise, the multiplexer selects the first input terminal to be electrically connected to its output terminal.

[0020] The second input terminal of the offset processing circuit is connected to the second clock signal through an inverter, and the offset processing circuit is set to terminate the logic unit jump signal when the comparison results are not equal through the inverted signal of the second clock signal.

[0021] The offset processing circuit includes:

[0022] The first PMOS transistor, the drain terminal of the first PMOS transistor is connected to the gate terminal and is connected to the output terminal of the current sampling circuit, and the source terminal of the first PMOS transistor is connected to the power supply voltage;

[0023] The second PMOS transistor, the source terminal of the second PMOS transistor is connected to the power supply voltage, and the gate terminal of the second PMOS transistor is connected to the gate terminal of the first PMOS transistor;

[0024] The third PMOS transistor, the source terminal of the third PMOS transistor is connected to the power supply voltage, and the gate terminal of the third PMOS transistor is connected to the gate terminal of the second PMOS transistor;

[0025] The fourth NMOS transistor, the source terminal of the fourth NMOS transistor is grounded, and the drain terminal of the fourth NMOS transistor is connected to the gate terminal and is connected to the drain terminal of the second PMOS transistor;

[0026] The fifth NMOS transistor, the source terminal of the fifth NMOS transistor is grounded, and the drain terminal of the fifth NMOS transistor is connected to the drain terminal of the third PMOS transistor;

[0027] The sixth NMOS transistor, the source terminal of the sixth NMOS transistor is grounded, the drain terminal of the sixth NMOS transistor is connected to the drain terminal of MP3, and the gate terminal of the sixth NMOS transistor is connected to the inverted signal of the second clock signal;

[0028] The first controlled switch, the first controlled switch is connected between the source terminal of the third PMOS transistor and the power supply voltage;

[0029] The first holding capacitor, the negative electrode of the first holding capacitor is grounded, and the positive electrode is connected to the gate terminal of the fourth NMOS transistor;

[0030] The second holding capacitor, the negative electrode of the second holding capacitor is grounded, and the positive electrode of the second holding capacitor is connected to the gate terminal of the fifth NMOS transistor;

[0031] The second controlled switch, the second controlled switch is connected between the gate terminal of the fourth NMOS transistor and the positive electrode of the first holding capacitor;

[0032] The third controlled switch, the third controlled switch is connected between the positive electrode of the first holding capacitor and the positive electrode of the second holding capacitor; and

[0033] The buffer, the input terminal of the buffer is connected to the connection point of the drain terminal of the third PMOS transistor and the drain terminal of the fifth NMOS transistor, and the output terminal of the buffer is the output terminal of the offset processing circuit.

[0034] The switching states of the first, second, and third controlled switches are determined by the output signal of one selected by the multiplexer from the first input terminal and the second input terminal. During the inductor current drop phase, the multiplexer selects the second input terminal to connect to its output terminal and drives the first, second, and third controlled switches, such that the first controlled switch and the third controlled switch are turned on and the second controlled switch is turned off; otherwise, the multiplexer selects the first input terminal to connect to its output terminal and drives the first, second, and third controlled switches, such that the first controlled switch and the third controlled switch are turned off and the second controlled switch is turned on.

[0035] The fourth NMOS transistor and the fifth NMOS transistor have proportional sizes, and the second PMOS transistor and the third PMOS transistor have sizes in the same proportion as the size ratio of the fourth NMOS transistor and the fifth NMOS transistor.

[0036] The other end of the energy storage inductor is grounded, and the output terminal of the switching power supply is connected to both the output capacitor and the load resistor, and both the output capacitor and the load resistor are grounded.

[0037] The zero-crossing detection circuit provided by the present invention can overcome the influence of temperature and semiconductor manufacturing process errors on the detection accuracy by outputting a sampling current proportional to the current flowing through the rectifier diode and comparing the sampling currents in the rising and falling phases, improving the accuracy and timeliness of the zero-crossing detection function, thereby improving the conversion efficiency of the switching power supply under light load. Description of the Drawings

[0038] Figure 1 are schematic diagrams of two abnormal phenomena in a typical zero-crossing detection process;

[0039] Figure 2 is a zero-crossing detection circuit diagram provided by the present invention for improving the light load efficiency of a switching power supply;

[0040] Figure 3 is a partial circuit diagram of the zero-crossing detection circuit provided by the present invention;

[0041] Figure 4 is a partial circuit diagram of the zero-crossing detection circuit provided by the present invention;

[0042] Figure 5 is a signal timing diagram of the first clock signal, the second clock signal, the OZ signal, and the current of the energy storage inductor. Detailed Embodiment

[0043] In the process of optimizing the zero-crossing detection circuit, it is found that the existing zero-crossing detection methods can be roughly divided into two types. One is to compare the sampled voltage of the switching node of the power tube and the rectifier tube with a fixed voltage. For example, in a BUCK-BOOST switching power supply, the node voltage is compared with the output voltage. When the current in the inductor is positive, the output voltage is greater than the node voltage. When the inductor current crosses zero and generates a negative current, the node voltage is greater than the output voltage, thereby generating a zero-crossing detection signal. The other is to compare the sampled inductor current with 0A to generate a zero-crossing detection signal. However, the accuracy of zero-crossing detection is greatly affected by random input offset caused by process errors and temperature deviations, which directly affects the conversion efficiency of the switching power supply in the light load state.

[0044] The offsets of different chips are often different, resulting in different zero-current points for each chip. Especially in the existing switching power supply solutions, in order to improve the heavy load efficiency, the on-resistance is getting smaller and smaller, and a small detection error will cause a large inductor current error, which will weaken the advantages of synchronous rectification and even cause the opposite effect.

[0045] To solve the above problems, the present invention provides a zero-crossing detection circuit for improving the light load efficiency of a switching power supply.

[0046] For a clearer description, the present invention will be described in detail below with reference to the accompanying drawings.

[0047] As Figure 2 shown is a zero-crossing detection circuit for improving the light load efficiency of a switching power supply according to an embodiment of the present invention. The switching power supply includes a power tube MH, a rectifier tube ML, and a storage inductor Lsw, one end of which is connected to the switching voltage node SW. The other end of the storage inductor Lsw is grounded, and the other end of the power tube MH is connected to the positive pole of the power supply voltage V in The other end of the rectifier tube ML is the output terminal V out of the switching power supply, which is connected to both an output capacitor Co and a load resistor RL, and both the output capacitor Co and the load resistor RL are grounded. The load resistor RL represents the load of the switching power supply during use.

[0048] The gate terminals of the power transistor MH and the rectifier transistor ML are both connected to a logic control unit 200. The logic control unit 200 is configured to provide a first clock signal HDRV to the gate terminal of the power transistor MH and a second clock signal LDRV to the gate terminal of the rectifier transistor ML. In this embodiment, both the first clock signal HDRV and the second clock signal LDRV are PWM signals. The source terminal of the power transistor MH and the drain terminal of the rectifier transistor ML are connected to the switching voltage node SW. Both the power transistor MH and the rectifier transistor ML are NMOS power transistors. The power transistor MH conducts when the first clock signal HDRV is high and turns off when the first clock signal HDRV is low; the rectifier transistor ML conducts when the second clock signal LDRV is high and turns off when the LDRV is low. The signal timing diagrams of the first clock signal HDRV and the second clock signal LDRV are as Figure 5 shown.

[0049] The zero-crossing detection circuit 100 for improving the light-load efficiency of the switching power supply according to the present invention has a first input terminal, a second input terminal, and a third input terminal; the first input terminal of the zero-crossing detection circuit 100 is connected to the switching voltage node SW, its second input terminal is connected to the output terminal V of the switching power supply out , and its third input terminal is connected to the inverted signal of the second clock signal LDRV , that is, connected to the second clock signal LDRV through an inverter; the output terminal of the zero-crossing detection circuit 100 is connected to the input terminal of the logic control unit 200.

[0050] As Figure 2 shown, the zero-crossing detection circuit 100 includes a current sampling circuit 110 and an offset processing circuit 120 connected to the output terminal of the current sampling circuit 110. The current sampling circuit 110 has a first input terminal and a second input terminal. The first input terminal of the current sampling circuit 110 serves as the first input terminal of the zero-crossing detection circuit 100, and the second input terminal of the current sampling circuit 110 serves as the second input terminal of the zero-crossing detection circuit 100; the offset processing circuit 120 has a first input terminal and a second input terminal. The first input terminal of the offset processing circuit 120 is connected to the output terminal of the current sampling circuit 110, and the second input terminal of the offset processing circuit 120 is connected to the inverted signal of the second clock signal LDRV connected, and the output terminal of the offset processing circuit 120 serves as the output terminal of the zero-crossing detection circuit 100.

[0051] As Figure 3 shown is the specific circuit structure diagram of the current sampling circuit 110. The current sampling circuit 110 is configured to output a sampling current I proportional to the current flowing through the rectifier transistor ML during the inductor current falling stage S. Because the inductor current zero-crossing event always occurs when the rectifier diode ML is conducting and the power transistor MH is turned off, the current sampling circuit 110 only needs to sample the current flowing through the rectifier diode ML when the rectifier diode ML is conducting and the power transistor MH is turned off. As Figure 3 shown, the current sampling circuit 110 includes: a multiplexer SL, a first input terminal Φ of the multiplexer SL is connected to a second input terminal of the current sampling circuit 110 (thus connected to the output terminal V of the switching power supply out ), a second input terminal of the multiplexer SL is connected to a first input terminal of the current sampling circuit 110 (thus connected to the switching voltage node SW), a selection control signal of the multiplexer SL is connected to the first clock signal HDRV and the second clock signal LDRV, so that the multiplexer SL selects the first input terminal Φ and the second input terminal is controlled by the first clock signal HDRV and the second clock signal LDRV; a first NMOS transistor MN1, whose source terminal is connected to the output terminal of the multiplexer SL; a second NMOS transistor MN2, whose source terminal is connected to the second input terminal of the current sampling circuit 110, and the gate terminal of the second NMOS transistor MN2 is connected to the gate terminal of the first NMOS transistor MN1 and is connected to the drain terminal of the second NMOS transistor MN2; a first resistor R1, which is connected between the source terminal of the first NMOS transistor MN1 and the output terminal of the multiplexer SL; a second resistor Rs, which is connected between the source terminal of the second NMOS transistor and the second input terminal of the zero-crossing detection circuit; a first current source IX1, the positive pole of the first current source IX1 is connected to the power supply voltage V in , the negative pole is connected to the drain terminal of the first NMOS transistor MN1; a second current source IX2, the positive pole of the second current source IX2 is connected to the power supply voltage V in , the negative pole is connected to the drain terminal of the second NMOS transistor MN2; a third NMOS transistor MN3, the source terminal of the third NMOS transistor MN3 is connected to the source terminal of the second NMOS transistor MN2, the gate terminal of the third NMOS transistor MN3 is connected to the drain terminal of the first NMOS transistor MN1, and the drain terminal of the third NMOS transistor MN3 is the output terminal ISENSE of the current sampling circuit 110.

[0052] The first current source IX1 and the second current source IX2 are bias currents to ensure the normal operation of the circuit. In this embodiment, the currents of the first current source IX1 and the second current source IX2 are equal. The resistance value of the first resistor R1 is twice the resistance value of the second resistor Rs.

[0053] Therefore, the multiplexer SL selects the first input terminal Φ and the second input terminal The selection is controlled by the first clock signal HDRV and the second clock signal LDRV. Thus, the working process of the multiplexer SL is as follows: During the inductor current falling phase, corresponding to the second clock signal LDRV being high and the first clock signal HDRV being low, and accordingly the rectifier diode ML being turned on and the power transistor MH being turned off, the multiplexer SL selects the second input terminal and connects it to its output terminal. At this time, the rectifier diode ML is connected to the current sampling circuit 110, and the output terminal ISENSE of the current sampling circuit 110 outputs a current proportional to the current flowing through the rectifier diode ML to complete the sampling; while during the inductor current rising phase, corresponding to the first clock signal HDRV being high and the second clock signal LDRV being low, and during the phase when the power transistor MH is turned on and the rectifier diode ML is turned off, the multiplexer SL selects the first input terminal Φ and connects it to its output terminal. At this time, the output terminal ISENSE of the current sampling circuit 110 outputs a constant value independent of the current flowing through the rectifier diode ML.

[0054] As Figure 4 shown is the specific circuit structure diagram of the offset processing circuit 120. The offset processing circuit 120 is configured to compare the sampling current in the inductor current rising phase with the sampling current in the inductor current falling phase during the inductor current falling phase, and generate a corresponding logic unit jump signal when the comparison result is equal. This logic unit jump signal causes the logic control unit 200 to generate the second clock signal LDRV that controls the rectifier diode ML to turn off. The offset processing circuit 120 includes: a first PMOS transistor MP1, the drain terminal of the first PMOS transistor MP1 is connected to its gate terminal and is connected to the output terminal ISENSE of the current sampling circuit 110, and the source terminal of the first PMOS transistor MP1 is connected to the power supply voltage V in ; a second PMOS transistor MP2, the source terminal of the second PMOS transistor MP2 is connected to the power supply voltage V in , the gate terminal of the second PMOS transistor MP2 is connected to the gate terminal of the first PMOS transistor MP1; a third PMOS transistor MP3, the source terminal of the third PMOS transistor MP3 is connected to the power supply voltage V in , the gate terminal of the third PMOS transistor MP3 is connected to the gate terminal of the second PMOS transistor MP2; a fourth NMOS transistor MN4, the source terminal of the fourth NMOS transistor MN4 is grounded, the drain terminal of the fourth NMOS transistor MN4 is connected to its gate terminal and is connected to the drain terminal of the second PMOS transistor PM2; a fifth NMOS transistor MN5, the source terminal of this fifth NMOS transistor MN5 is grounded, the drain terminal of the fifth NMOS transistor MN5 is connected to the drain terminal of the third PMOS transistor MP3; a sixth NMOS transistor MN6, the source terminal of the sixth NMOS transistor MN6 is grounded, the drain terminal of the sixth NMOS transistor MN6 is connected to the drain terminal of MP3, and the gate terminal of the sixth NMOS transistor MN6 is connected to the inverted signal of the second clock signal LDRV The first controlled switch sd1 is connected between the source terminal of the third PMOS transistor MP3 and the power supply voltage V in ; the first holding capacitor C1, the negative electrode of the first holding capacitor C1 is grounded, and the positive electrode is connected to the gate terminal of the fourth NMOS transistor MN4; the second holding capacitor C2, the negative electrode of the second holding capacitor C2 is grounded, and the positive electrode of the second holding capacitor C2 is connected to the gate terminal of the fifth NMOS transistor MN5; the second controlled switch sd2, the second controlled switch sd2 is connected between the gate terminal of the fourth NMOS transistor MN4 and the positive electrode of the first holding capacitor C1; the third controlled switch sd3, the third controlled switch sd3 is connected between the positive electrode of the first holding capacitor C1 and the positive electrode of the second holding capacitor C2; the buffer BUFF, the input terminal of the buffer BUFF is connected to the connection point IZCMP of the drain terminal of the third PMOS transistor MP3 and the drain terminal of the fifth NMOS transistor MN5, and the output terminal of the buffer BUFF is the output terminal of the offset processing circuit 120 and also the output terminal of the zero-crossing detection circuit 100.

[0055] As Figure 4 shown, the switching states of the controlled switches sd1, sd2, and sd3 are determined by the output signal of one selected by the multiplexer SL from the first input terminal Φ and the second input terminal . The selection of the multiplexer SL for the first input terminal Φ and the second input terminal is controlled by the first clock signal HDRV and the second clock signal LDRV. When the inductor current is in the falling stage, that is, the stage when the second clock signal LDRV is high and the first clock signal HDRV is low, the multiplexer SL selects the second input terminal and electrically connects it to its output terminal to drive the controlled switches sd1, sd2, and sd3, so that the first controlled switch sd1 and the third controlled switch sd3 are turned on, and the second controlled switch sd2 is turned off; otherwise, when the inductor current is in the rising stage, that is, the stage when the first clock signal HDRV is high and the second clock signal LDRV is low, the multiplexer SL selects the first input terminal Φ and electrically connects it to its output terminal to drive the controlled switches sd1, sd2, and sd3, so that the first controlled switch sd1 and the third controlled switch sd3 are turned off, and the second controlled switch sd2 is turned on.

[0056] In this embodiment, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 have the same size. Of course, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 can also be designed to have proportional sizes, but at the same time, the second PMOS transistor MP2 and the third PMOS transistor MP3 also need to adopt the same proportional size as the size ratio of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5.

[0057] According to an embodiment of the present invention, the implementation process of the function of the zero-crossing detection circuit for improving the light-load efficiency of a switching power supply includes:

[0058] When the inductor current is in the rising stage, that is, when the power transistor MH is turned on and the rectifier diode ML is turned off, the multiplexer in the current sampling circuit 110 selects the first input terminal Φ, and one ends of the first resistor R1 and the second resistor RS are connected to the same voltage (i.e., the output terminal V of the fixed switching power supply out 's voltage). The first current source IX1 and the second current source IX2 are two currents of the same magnitude that flow through the NMOS transistors MN1 and MN2 and the resistors R1 and RS connected thereto respectively. The first NMOS transistor MN1 and the second NMOS transistor MN2 form a current mirror structure, which can ensure that the other ends (i.e., the same end) of the first resistor R1 and the second resistor RS are at the same voltage. As can be seen above, the voltages across the first resistor R1 and the second resistor RS are equal. Since R1 = 2RS, in order to maintain the equal voltage across the resistors, the current flowing through the second resistor RS is equal to twice the current I flowing through the first resistor R1 RS That is, the current source current I B , I RS = 2I B . There are two branches for the current flowing through the second resistor RS. One is the current source current I generated by the second current source IX2 B , and the other is the current I flowing through the third NMOS transistor MN3 S . It can be obtained that I S = I B . The function of the third NMOS transistor MN3 is an adjustment transistor, which will adjust the current I flowing through the third NMOS transistor MN3 according to the current demand of the second resistor RS S . Therefore, when the inductor current is in the rising stage, there are three current branches in the current sampling circuit 110, and the currents are all the current source current I B , and the magnitude of the current at the output terminal ISENSE is equal to the current source current I B . That is to say, at this time, the current at the output terminal ISENSE of the current sampling circuit 110 (i.e., the sampling current I S ) is a fixed value.

[0059] When the inductor current is in the falling stage, that is, when the power transistor is turned off and the rectifier diode is turned on, at this time, the rectifier diode ML is connected to the circuit. The multiplexer in the current sampling circuit 110 selects the second input terminal At this time, the rectifier diode ML is connected to the circuit. Since the rectifier diode ML is in the on state at this time, there is a conduction resistance R of the rectifier diode between the output terminal V of the switching power supply out and the switching voltage node SW on , and the current flowing through the rectifier diode ML is the inductor current Ilsw , in the direction from right to left. As the inductor current decreases, the sampling current I S and the inductor current I lsw have the following voltage relationship formula: I B ·R1 = (I B +I S )·RS + I lsw ·R on . After simplification, the sampling current I S = I B - I lsw ·R on / RS, where R on is the on-resistance of the rectifier diode ML. It should be noted that the current I B +I S flowing through RS will also flow into the rectifier diode ML, but I B +I S is of a much larger magnitude difference from the inductor current I lsw and can be ignored, so it is not reflected in the formula.

[0060] In the offset processing circuit 120, the sampling current I S generates an induced voltage VDS at the gate terminal of the fourth NMOS transistor MN4 through the first PMOS transistor MP1 and the second PMOS transistor MP2. The induced voltage VDS is used to act on the gate terminal of the fifth NMOS transistor MN5 later to generate a current proportional to the sampling current I S . Since the sampling current I S flows into the drain terminal of the fourth NMOS transistor MN4 through the current mirror structure of the first PMOS transistor MP1 and the second PMOS transistor MP2, the current inflow causes the fourth NMOS transistor MN4 to turn on. When the inductor current is in the rising stage, the control signals of all controlled switches are the signals of the first input terminal Φ of the current sampling circuit 110. The first controlled switch sd1 and the third controlled switch sd3 are turned off, and the second controlled switch sd2 is turned on to store the induced charge on the first holding capacitor C1. When the inductor current is in the falling stage, the control signals of all controlled switches are the output signals of the second input terminal . The second controlled switch sd2 is turned off, the first controlled switch sd1 and the third controlled switch sd3 are turned on, and the conduction of the third controlled switch sd3 transfers the charge on the first holding capacitor C1 to the second holding capacitor C2 to generate the same induced voltage as that on the gate of the fourth NMOS transistor MN4. At the same time, a sampling current I S in the rising stage of the inductor current is generated at the drain terminal of MN5. According to the basic principle of the current mirror, the conduction of sd1 will generate a sampling current I S in the falling stage of the inductor current at the drain terminal of MP3., a current flows through the third PMOS transistor MP3, which can be considered to be turned on. The sampling current I during the inductor current rising stage S and the sampling current I during the inductor current falling stage S These two currents are compared at the connection point IZCMP, and when the comparison result of the buffer BUFF is , a corresponding logic unit jump signal (i.e., the signal OZ jumps up) is generated and the logic unit jump signal is output to the logic control unit 200 to generate a second clock signal LDRV for controlling the turn-off of the rectifier diode ML. Among them, the second clock signal LDRV corresponding to the rising OZ signal is at a low level, and the rectifier diode ML is turned off when it receives that LDRV is at a low level; at the same time, the inverted signal of the second clock signal LDRV terminates the logic unit jump signal (i.e., the signal OZ jumps down) to turn on the sixth NMOS transistor MN6, and the input signal of the buffer BUFF is pulled down to prepare for the next detection cycle. That is to say, the offset processing circuit 120 is set to terminate the logic unit jump signal when the comparison results are not equal through the inverted signal of the second clock signal LDRV. Among them, the width-to-length ratio of the sixth NMOS transistor MN6 is slightly larger than that of the fifth NMOS transistor MN5. The implementation principle of the offset cancellation process lies in that when the inductor current is in the rising stage, the sampling current I S contains the input offset information of the chip. When the inductor current is in the falling stage and a comparison is made at the IZCMP point, the input offset information will be cancelled out. Thus, within one working cycle, the influence of the input offset on the zero-crossing detection accuracy can be eliminated, thereby improving the conversion efficiency of the switching power supply under light load.

[0061] The relationship of the above calibration process can also be expressed by a formula, and specifically, there can be the following relational expressions.

[0062] As Figure 3 shown, in the current sampling circuit 110, the first current source IX1 and the second current source IX2 generate equal currents IB, and the resistor R1 = 2Rs. When the inductor current I lsw is in the rising stage, the following formula can be obtained:

[0063] I SΦ = I B ;

[0064] Among them, I SΦ is the sampling current during the inductor current rising stage, is the sampling current during the inductor current falling stage.

[0065] When the inductor current I lsw is in the falling stage, the following formula can be obtained:

[0066]

[0067] wherein, R on is the on-resistance of the rectifier diode, and I SΦ is the sampled current during the inductor current falling stage.

[0068] In the offset processing circuit 120, when the inductor current I lsw is in the falling stage, I SΦ and are compared in magnitude at IZCMP. The following comparison results can be obtained from the above formula:

[0069] When the inductor current is positive,

[0070] When the inductor current is zero,

[0071] When the inductor current is negative,

[0072] When the inductor current is zero, the buffer BUFF generates an OZ signal, which, through the logic control unit, controls the rectifier diode to turn off.

[0073] Compared with the existing two methods of comparing the SW voltage with the output terminal V out of the switching power supply or comparing the sampled current with 0A, the zero-crossing detection circuit provided by the present invention is characterized in that the object of the sampled current comparison is a fixed current IB containing random input offset information. During the comparison process, the random input offset information will be cancelled, thereby eliminating the influence of the input offset on the zero-crossing detection accuracy, and further improving the conversion efficiency of the switching power supply in the light load mode.

[0074] The content of the present invention is disclosed as above, which is only used to illustrate the technical solution of the present invention and is not limited thereto. Those of ordinary skill in the art should understand that the technical solution of the present invention can be changed or equivalently replaced. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A zero-crossing detection circuit for improving the light-load efficiency of a switching power supply, the switching power supply comprising a power transistor, a rectifier diode and a storage inductor, one end of which is connected to a switching voltage node, the other end of the power transistor being connected to the positive pole of the power supply voltage, the other end of the rectifier diode being the output end of the switching power supply, the gate terminals of the power transistor and the rectifier diode being both connected to a logic control unit, the logic control unit being configured to provide a first clock signal to the gate terminal of the power transistor and a second clock signal to the gate terminal of the rectifier diode, characterized in that, The zero-crossing detection circuit includes a current sampling circuit and an offset processing circuit; a first input end of the current sampling circuit is connected to a switching voltage node, a second input end of the current sampling circuit is connected to an output end of a switching power supply, and an output end of the current sampling circuit is connected to a first input end of the offset processing circuit. The current sampling circuit is configured to output a sampling current proportional to the current flowing through a rectifying diode during a falling stage of an inductor current; a first input end of the offset processing circuit is connected to an output end of the current sampling circuit, and an output end of the offset processing circuit is connected to an input end of a logic control unit. The offset processing circuit is configured to compare the sampling current during a rising stage of the inductor current and the sampling current during a falling stage of the inductor current during the falling stage of the inductor current, and generate a corresponding logic unit jump signal when the comparison result is equal. The logic unit jump signal enables the logic control unit to generate a second clock signal for controlling the rectifying diode to turn off. The current sampling circuit includes: A multiplexer, a first input end of the multiplexer is connected to a second input end of the current sampling circuit, and a second input end of the multiplexer is connected to a first input end of the current sampling circuit; A first NMOS transistor, a source end of the first NMOS transistor is connected to an output end of the multiplexer; A second NMOS transistor, a source end of the second NMOS transistor is connected to the second input end of the current sampling circuit, and a gate end of the second NMOS transistor is connected to a gate end of the first NMOS transistor and is connected to a drain end of the second NMOS transistor; A first resistor, which is connected between a source end of the first NMOS transistor and an output end of the multiplexer; A second resistor, which is connected between a source end of the second NMOS transistor and a second input end of the zero-crossing detection circuit; A first current source, a positive pole of the first current source is connected to a power supply voltage, and a negative pole of the first current source is connected to a drain end of the first NMOS transistor; A second current source, a positive pole of the second current source is connected to a power supply voltage, and a negative pole of the second current source is connected to a drain end of the second NMOS transistor; and A third NMOS transistor, a source end of the third NMOS transistor is connected to a source end of the second NMOS transistor, a gate end of the third NMOS transistor is connected to a drain end of the first NMOS transistor, and a drain end of the third NMOS transistor is an output end of the current sampling circuit; A second input end of the offset processing circuit is connected to a second clock signal through an inverter, and the offset processing circuit is configured to terminate the logic unit jump signal when the comparison result is not equal through an inverted signal of the second clock signal.

2. The zero-crossing detection circuit for improving the light-load efficiency of a switching power supply according to claim 1, characterized in that, The currents of the first current source and the second current source are equal, and the resistance value of the first resistor is equal to twice the resistance value of the second resistor.

3. The zero-crossing detection circuit for improving the light-load efficiency of a switching power supply according to claim 1, characterized in that, Selection control ports of the multiplexer are respectively connected to a first clock signal and a second clock signal. The selection of the first input end and the second input end is controlled by the first clock signal and the second clock signal. During a falling stage of an inductor current, the second clock signal is high and the first clock signal is low, and the multiplexer selects the second input end to be connected to its output end; Otherwise, the multiplexer selects the first input end to be connected to its output end.

4. The zero-crossing detection circuit for improving the light-load efficiency of a switching power supply according to claim 1, characterized in that, The offset processing circuit includes: A first PMOS transistor, a drain end of the first PMOS transistor is connected to a gate end of the first PMOS transistor and is connected to an output end of the current sampling circuit, and a source end of the first PMOS transistor is connected to a power supply voltage; The second PMOS transistor, the source terminal of the second PMOS transistor is connected to the power supply voltage, and the gate terminal of the second PMOS transistor is connected to the gate terminal of the first PMOS transistor; The third PMOS transistor, the source terminal of the third PMOS transistor is connected to the power supply voltage, and the gate terminal of the third PMOS transistor is connected to the gate terminal of the second PMOS transistor; The fourth NMOS transistor, the source terminal of the fourth NMOS transistor is grounded, and the drain terminal of the fourth NMOS transistor is connected to its gate terminal and is also connected to the drain terminal of the second PMOS transistor; The fifth NMOS transistor, the source terminal of the fifth NMOS transistor is grounded, and the drain terminal of the fifth NMOS transistor is connected to the drain terminal of the third PMOS transistor; The sixth NMOS transistor, the source terminal of the sixth NMOS transistor is grounded, the drain terminal of the sixth NMOS transistor is connected to the drain terminal of MP3, and the gate terminal of the sixth NMOS transistor is connected to the inverted signal of the second clock signal; The first controlled switch, the first controlled switch is connected between the source terminal of the third PMOS transistor and the power supply voltage; The first holding capacitor, the negative electrode of the first holding capacitor is grounded, and the positive electrode is connected to the gate terminal of the fourth NMOS transistor; The second holding capacitor, the negative electrode of the second holding capacitor is grounded, and the positive electrode of the second holding capacitor is connected to the gate terminal of the fifth NMOS transistor; The second controlled switch, the second controlled switch is connected between the gate terminal of the fourth NMOS transistor and the positive electrode of the first holding capacitor; The third controlled switch, the third controlled switch is connected between the positive electrode of the first holding capacitor and the positive electrode of the second holding capacitor; and The buffer, the input terminal of the buffer is connected to the connection point of the drain terminals of the third PMOS transistor and the fifth NMOS transistor, and the output terminal of the buffer is the output terminal of the offset processing circuit.

5. The zero-crossing detection circuit for improving the light-load efficiency of a switching power supply according to claim 4, wherein, The switching states of the first, second, and third controlled switches are determined by the output signal of one selected by the multiplexer from the first input terminal and the second input terminal. When the inductor current is in the falling stage, the multiplexer selects the second input terminal to be connected to its output terminal and drives the first, second, and third controlled switches, so that the first controlled switch and the third controlled switch are turned on, and the second controlled switch is turned off; Otherwise, the multiplexer selects the first input terminal to be connected to its output terminal and drives the first, second, and third controlled switches, so that the first controlled switch and the third controlled switch are turned off, and the second controlled switch is turned on.

6. The zero-crossing detection circuit for improving the light-load efficiency of a switching power supply according to claim 4, characterized in that, The fourth NMOS transistor and the fifth NMOS transistor have proportional sizes, and the second PMOS transistor and the third PMOS transistor have the same proportional size as the size ratio of the fourth NMOS transistor and the fifth NMOS transistor.

7. The zero-crossing detection circuit for improving the light-load efficiency of a switching power supply according to claim 1, wherein The other end of the energy storage inductor is grounded, the output terminal of the switching power supply is connected to both the output capacitor and the load resistor, and both the output capacitor and the load resistor are grounded.

Images