Method of manufacturing an ldmos device structure

Abstract

The application provides a manufacturing method of an LDMOS device structure. A substrate of a first conductive type is provided, a local field oxide layer is formed on the substrate to define an active region, a drift region of a second conductive type is formed in the active region by ion implantation, the active region between the drift regions of the second conductive type is a channel region, the channel region is a region where a source region is formed, and an end of the drift region away from the channel region is a region where a drain region is formed; a first photoresist layer is formed on the substrate, a photoetching is performed to open the first photoresist layer above the drift region to form a comb structure, so that the opening area from the channel region to the drain region gradually decreases; a resurf layer of the first conductive type is formed below the drift region by ion implantation, the ion implantation concentration of the resurf layer gradually decreases from the channel region to the drain region, and then the first photoresist layer is removed; a gate dielectric layer and a gate polysilicon layer located on the gate dielectric layer are formed on the substrate; and a second photoresist layer is formed on the gate polysilicon layer. The device of the application can improve the overall performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing an LDMOS device structure. Background Technology

[0002] Due to its high voltage tolerance, high current drive capability, and extremely low power consumption, DMOS (Double-diffused MOS) is widely used in power management circuits. In LDMOS (Lateral DMOS) devices, the breakdown voltage and on-resistance are optimized by introducing laterally uniformly distributed drift regions (I-106) and resurf regions (I-105), but this design has not yet achieved optimal device characteristics.

[0003] Existing LDMOS structures (such as Figure 1 Taking N-LDMOS as an example, Figure 1 The structures indicated by the numbers are as follows: 101—P-type substrate / P-type epitaxial layer, 102—Field plate dielectric layer / Shallow Trench Isolation (STI), 103—Gate insulating dielectric layer, 104—Gate polysilicon layer, 105—Laterally uniformly distributed P-type resurf (Reduced Surface E-Field) layer implantation, 106—N-type drift region implantation that gradually becomes denser from the channel end to the drain end, 107—P-type body region implantation, 108—Sidewall dielectric layer, 109—Heavy N-type doped implantation, 110—Heavy P-type doped implantation, 111—Metal silicide, 112—ILD etch stop layer (bottom silicon oxide layer, top silicon nitride layer), 113—Interlayer Dielectric (ILD), 114—Contact via.

[0004] For device reliability (especially HCI reliability, hot carrier injection), hot carrier injection mainly depends on the performance of the P-type body-N-type drift junction (107-106 junction). Therefore, hot carrier injection optimization often involves the optimization of the 107-106 junction of the device.

[0005] To solve the above problems, a novel method for manufacturing LDMOS device structures needs to be proposed. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for manufacturing an LDMOS device structure, which solves the problem that in the prior art, the breakdown voltage and on-resistance of LDMOS (Lateral DMOS) devices are optimized by introducing laterally uniformly distributed drift region injection and resurf injection, but this design has not yet achieved the optimal device characteristics.

[0007] To achieve the above and other related objectives, the present invention provides a method for manufacturing an LDMOS device structure, comprising: Step 1: Provide a substrate of a first conductivity type, form a local field oxide layer on the substrate to define an active region, and form a drift region of a second conductivity type in the active region by ion implantation. The active region between the drift regions of the second conductivity type is a channel region, the channel region is the region that forms the source region, and the end of the drift region away from the channel region is the region that forms the drain region. Step 2: A first photoresist layer is formed on the substrate. The first photoresist layer above the drift region is opened by photolithography to form a comb-like structure, so that the open area from the channel region to the drain region gradually decreases. Step 3: Form a resurf layer of the first conductivity type under the drift region by ion implantation. The ion implantation concentration of the resurf layer gradually decreases from the channel region to the drain region. Then, remove the first photoresist layer. Step 4: Form a gate dielectric layer and a gate polysilicon layer on the substrate; Step 5: Form a second photoresist layer on the gate polysilicon layer, and use photolithography to open the second photoresist layer to define the boundary of the gate polysilicon layer in the channel region. Then, etch away part of the gate polysilicon layer and the gate dielectric layer in the channel region, so that one end of the gate dielectric layer extends into the channel region, and the rest of the channel region is exposed. Step 6: Form a first conductivity type body region on the exposed channel region using ion implantation, and then remove the second photoresist layer; Step 7: Form a third photoresist layer on the substrate covering the gate polysilicon layer; use photolithography to open the third photoresist layer to define the boundary of the gate polysilicon layer in the drift region; etch away a portion of the gate polysilicon layer and the gate dielectric layer in the drift region; and then remove the third photoresist layer. Step 8: Form a sidewall on the sidewall of the gate polysilicon layer; Step 9: Form the first and second doped regions in the source and drain regions, respectively; Step 10: Form metal silicides on the source, drain, and gate polysilicon layers; Step 11: Form an etch barrier layer on the substrate, then form an interlayer dielectric layer on the etch barrier layer, and then form a contact hole structure on the interlayer dielectric layer for leading out the source, drain and gate polysilicon layers.

[0008] Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.

[0009] Preferably, an NLDMOS is formed on the substrate in step one, wherein the first conductivity type is P-type and the second conductivity type is N-type.

[0010] Preferably, a PLDMOS is formed on the substrate in step one, wherein the first conductivity type is N-type and the second conductivity type is P-type.

[0011] Preferably, in step three, the ion implantation concentration of the resurf layer gradually decreases from 1e17 to 1e18 cm⁻³ to 5e16 to 5e17 cm⁻³ from the channel region to the drain region.

[0012] Preferably, the etching method described in step five is dry etching.

[0013] Preferably, the photolithography in step five also includes defining the gate structure of other devices.

[0014] Preferably, the etching method described in step seven is dry etching.

[0015] Preferably, the material of the sidewall in step eight is silicon nitride.

[0016] Preferably, the method for forming the sidewall in step eight includes: forming a sidewall material layer covering the gate polysilicon layer on the substrate; and etching back the sidewall material layer to form the sidewall.

[0017] Preferably, the etching method described in step eight is dry etching.

[0018] Preferably, the method for forming the metal silicide in step ten includes: forming a metal silicide barrier layer on the substrate, and then patterning the metal silicide barrier layer to define the location of the metal silicide; forming a metal layer covering the gate polysilicon layer on the substrate; forming a protective layer on the metal layer; forming the metal silicide on the source region, drain region and gate polysilicon layer by annealing; and removing the remaining protective layer, the metal layer and the metal silicide barrier layer.

[0019] Preferably, the material of the metal layer in step ten is cobalt, titanium, nickel, or a nickel-platinum alloy.

[0020] Preferably, the material of the metal silicide barrier layer in step ten includes at least one of silicon-rich oxide, SiO2, SiON, and Si3N4.

[0021] Preferably, the method for forming a contact hole structure for leading out the source, drain, and gate polysilicon layers on the interlayer dielectric layer in step eleven includes: forming a photoresist layer on the interlayer dielectric layer; photolithographically opening the photoresist layer to define the formation location of the contact hole; etching the interlayer dielectric layer to form a contact hole whose bottom end communicates with the source, drain, and gate polysilicon layers; and depositing and polishing conductive metal in the contact hole.

[0022] Preferably, the etching method in step eleven is dry etching.

[0023] Preferably, the conductive metal in step eleven is tungsten.

[0024] As described above, the method for manufacturing the LDMOS device structure of the present invention has the following beneficial effects: The device of this invention, taking N-LDMOS as an example, incorporates a laterally uniformly distributed N-type drift region and a P-type reducer layer implanted (Reduced Surface E-Field) that gradually fades from the channel end to the drain end. By forming a denser (1e17~1e18cm-3) P-type region below the N-type drift region near the channel end, a junction that is more easily depleted by the reducer layer is achieved, improving junction performance; while by forming a fainter (5e16~5e17cm-3) P-type region below the N-type drift region near the drain end, a higher device breakdown voltage is achieved, improving the overall device performance. Attached Figure Description

[0025] Figure 1 The diagram shown is a schematic representation of an existing LDMOS device structure. Figure 2 The diagram shown is a schematic representation of the process flow of the present invention. Figure 3 The diagram shown illustrates the formation of the drift region according to the present invention. Figure 4 The diagram shown is a schematic diagram of the photolithography opening of the first photoresist layer according to the present invention. Figure 5 The diagram shows the first patterned gate dielectric layer and gate polysilicon layer of the present invention. Figure 6 The diagram shows the second patterned gate dielectric layer and gate polysilicon layer of the present invention. Figure 7 The diagram shown is a schematic of the LDMOS device structure of the present invention. Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] Please see Figure 2 This invention provides a method for manufacturing an LDMOS device structure, comprising: Step 1: Provide a substrate 101 of a first conductivity type, form a local field oxide layer 102 on the substrate 101 to define an active region, and form a drift region 106 of a second conductivity type in the active region by ion implantation. The active region between the drift regions 106 of the second conductivity type is a channel region 107, the channel region 107 is the region where the source region is formed, and the end of the drift region 106 away from the channel region 107 is the region where the drain region is formed. For example, please see Figure 3 The method for forming the drift region 106 includes: forming a local field oxide layer 102 on the substrate 101, forming a fourth photoresist layer 501 on the substrate 101, photolithographically opening the fourth photoresist layer 501 to define the formation location of the drift region 106, forming the drift region 106 by ion implantation, and then removing the fourth photoresist layer 501 by ashing and wet cleaning.

[0028] In an optional embodiment, the substrate 101 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The semiconductor of the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0029] In one alternative embodiment, an NLDMOS is formed on the substrate 101 in step one, with the first conductivity type being P-type and the second conductivity type being N-type.

[0030] In one optional implementation, a PLDMOS is formed on the substrate 101 in step one, with the first conductivity type being N-type and the second conductivity type being P-type.

[0031] Step Two, please refer to Figure 4 A first photoresist layer 502 is formed on the substrate 101. The first photoresist layer 502 above the photolithographically opened drift region 106 forms a comb-like structure, so that the open area from the channel region 107 to the drain region gradually decreases. Step 3: A first conductivity type resurf layer 105 is formed below the drift region 106 by ion implantation. The ion implantation concentration of the resurf layer 105 gradually decreases from the channel region 107 to the drain region. Then the first photoresist layer 502 is removed. In one alternative implementation, the ion implantation concentration of the resurf layer 105 in step three gradually decreases from 1e17 to 1e18 cm⁻³ to 5e16 to 5e17 cm⁻³ from the channel region 107 to the drain region.

[0032] Step 4: Form a gate dielectric layer 103 and a gate polysilicon layer 104 on the gate dielectric layer 103 on the substrate 101; Step 5: Form a second photoresist layer 503 on the gate polysilicon layer 104. Photolithography is used to open the second photoresist layer 503, defining the boundary of the gate polysilicon layer 104 in the channel region 107. Then, etching is used to remove a portion of the gate polysilicon layer 104 and the gate dielectric layer 103 on the channel region 107, so that one end of the gate dielectric layer 103 extends into the channel region 107, exposing the remaining portion of the channel region 107, forming a structure as shown in the image. Figure 5 The structure shown; In one alternative implementation, the etching method in step five is dry etching.

[0033] In an alternative implementation, the photolithography in step five also includes defining the gate structure of other devices.

[0034] Step 6: Form a first conductivity type body region on the exposed channel region 107 by ion implantation, and then remove the second photoresist layer 503; Step 7: Form a third photoresist layer 504 covering the gate polysilicon layer 104 on the substrate 101. Photolithography is used to open the third photoresist layer 504 to define the boundary of the gate polysilicon layer 104 in the drift region 106. Etching is used to remove a portion of the gate polysilicon layer 104 and the gate dielectric layer 103 on the drift region 106, forming a layer as shown in the image. Figure 6 The structure shown is then removed after the third photoresist layer 504 is removed. In one alternative implementation, the etching method in step seven is dry etching.

[0035] Step 8: Form sidewalls 108 on the sidewalls of the gate polysilicon layer 104; In one alternative implementation, the sidewall 108 in step eight is made of silicon nitride.

[0036] In an alternative embodiment, the method of forming the sidewall 108 in step eight includes: forming a sidewall 108 material layer covering the gate polysilicon layer 104 on the substrate 101; and etching back the sidewall 108 material layer to form the sidewall 108.

[0037] In one alternative implementation, the etching method in step eight is dry etching.

[0038] Step 9: Form the first and second doped regions (110, 109) in the source and drain regions respectively; for example, when forming an NLDMOS, the first doped region 110 in the source region is a P-type heavy doped region implanted, and the second doped region 109 in the drain region is an N-type heavy doped region implanted.

[0039] Step 10: Form metal silicide 111 on the source, drain, and gate polysilicon layers 104; In one alternative embodiment, the method for forming the metal silicide 111 in step ten includes: forming a metal silicide 111 barrier layer on a substrate 101, and then patterning the metal silicide 111 barrier layer to define the location of the metal silicide 111; forming a metal layer covering the gate polysilicon layer 104 on the substrate 101; forming a protective layer on the metal layer; forming the metal silicide 111 on the source region, drain region and gate polysilicon layer 104 by annealing; and removing the remaining protective layer, metal layer and metal silicide 111 barrier layer.

[0040] In one alternative implementation, the material of the metal layer in step ten is cobalt, titanium, nickel, or a nickel-platinum alloy.

[0041] In an optional embodiment, the material of the metal silicide 111 barrier layer in step ten includes at least one of silicon-rich oxide, SiO2, SiON, and Si3N4.

[0042] Step 11: An etch stop layer 112 is formed on the substrate 101, followed by the formation of an interlayer dielectric layer 113 on the etch stop layer 112, and then the formation of contact hole structures 114 for leading out the source, drain, and gate polysilicon layers 104 on the interlayer dielectric layer 113, forming as shown in the figure. Figure 7 The structure shown.

[0043] In an optional embodiment, the method of forming a contact hole structure 114 for leading out the source, drain and gate polysilicon layers 104 on the interlayer dielectric layer 113 in step eleven includes: forming a photoresist layer on the interlayer dielectric layer 113; photolithographically opening the photoresist layer to define the formation location of the contact hole; etching the interlayer dielectric layer 113 to form a contact hole whose bottom end is connected to the source, drain and gate polysilicon layers 104; and forming conductive metal in the contact hole by deposition and polishing.

[0044] In one alternative implementation, the etching method in step eleven is dry etching.

[0045] In one alternative implementation, the conductive metal in step eleven is tungsten.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] In summary, the device of this invention, taking N-LDMOS as an example, incorporates a laterally uniformly distributed N-type drift region and a P-type restorer layer (Reduced Surface E-Field) that gradually fades from the channel end to the drain end. By forming a denser (1e17~1e18cm⁻³) P-type region below the N-type drift region near the channel end, a junction that is more easily depleted by the restorer layer is achieved, improving junction performance. Conversely, by forming a fainter (5e16~5e17cm⁻³) P-type region below the N-type drift region near the drain end, a higher device breakdown voltage is achieved, improving the overall device performance. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing an LDMOS device structure, characterized in that, At least including: Step 1: Provide a substrate of a first conductivity type, form a local field oxide layer on the substrate to define an active region, and form a drift region of a second conductivity type in the active region by ion implantation. The active region between the drift regions of the second conductivity type is a channel region, the channel region is the region that forms the source region, and the end of the drift region away from the channel region is the region that forms the drain region. Step 2: A first photoresist layer is formed on the substrate. The first photoresist layer above the drift region is opened by photolithography to form a comb-like structure, so that the open area from the channel region to the drain region gradually decreases. Step 3: Form a resurf layer of the first conductivity type under the drift region by ion implantation. The ion implantation concentration of the resurf layer gradually decreases from the channel region to the drain region. Then, remove the first photoresist layer. Step 4: Form a gate dielectric layer and a gate polysilicon layer on the substrate; Step 5: Form a second photoresist layer on the gate polysilicon layer, and use photolithography to open the second photoresist layer to define the boundary of the gate polysilicon layer in the channel region. Then, etch away part of the gate polysilicon layer and the gate dielectric layer in the channel region, so that one end of the gate dielectric layer extends into the channel region, and the rest of the channel region is exposed. Step 6: Form a first conductivity type body region on the exposed channel region using ion implantation, and then remove the second photoresist layer; Step 7: Form a third photoresist layer on the substrate covering the gate polysilicon layer; use photolithography to open the third photoresist layer to define the boundary of the gate polysilicon layer in the drift region; etch away a portion of the gate polysilicon layer and the gate dielectric layer in the drift region; and then remove the third photoresist layer. Step 8: Form a sidewall on the sidewall of the gate polysilicon layer; Step 9: Form the first and second doped regions in the source and drain regions, respectively; Step 10: Form metal silicides on the source, drain, and gate polysilicon layers; Step 11: Form an etch barrier layer on the substrate, then form an interlayer dielectric layer on the etch barrier layer, and then form a contact hole structure on the interlayer dielectric layer for leading out the source, drain and gate polysilicon layers.

2. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: The substrate in step one includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.

3. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: An NLDMOS is formed on the substrate in step one, wherein the first conductivity type is P-type and the second conductivity type is N-type.

4. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: In step one, a PLDMOS is formed on the substrate, wherein the first conductivity type is N-type and the second conductivity type is P-type.

5. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: In step three, the ion implantation concentration of the resurf layer gradually decreases from 1e17 to 1e18 cm⁻³ to 5e16 to 5e17 cm⁻³ from the channel region to the drain region.

6. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: The etching method described in step five is dry etching.

7. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: The photolithography in step five also includes defining the gate structure of other devices.

8. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: The etching method described in step seven is dry etching.

9. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: The sidewall material mentioned in step eight is silicon nitride.

10. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: The method for forming the sidewall in step eight includes: forming a sidewall material layer covering the gate polysilicon layer on the substrate; and etching back the sidewall material layer to form the sidewall.

11. The method for manufacturing an LDMOS device structure according to claim 10, characterized in that: The etching method described in step eight is dry etching.

12. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: The method for forming the metal silicide in step ten includes: forming a metal silicide barrier layer on the substrate, and then patterning the metal silicide barrier layer to define the location of the metal silicide; forming a metal layer covering the gate polysilicon layer on the substrate; forming a protective layer on the metal layer; forming the metal silicide on the source region, drain region and gate polysilicon layer by annealing; and removing the remaining protective layer, the metal layer and the metal silicide barrier layer.

13. The method for manufacturing the LDMOS device structure according to claim 12, characterized in that: The material of the metal layer in step ten is cobalt, titanium, nickel, or a nickel-platinum alloy.

14. The method for manufacturing an LDMOS device structure according to claim 12, characterized in that: The material of the metal silicide barrier layer in step ten includes at least one of silicon-rich oxide, SiO2, SiON, and Si3N4.

15. The method for manufacturing the LDMOS device structure according to claim 1, characterized in that: The method for forming a contact hole structure for leading out the source, drain and gate polysilicon layers on the interlayer dielectric layer in step eleven includes: forming a photoresist layer on the interlayer dielectric layer; photolithographically opening the photoresist layer to define the formation location of the contact hole; etching the interlayer dielectric layer to form a contact hole whose bottom end is connected to the source, drain and gate polysilicon layers; and depositing and polishing conductive metal in the contact hole.

16. The method for manufacturing an LDMOS device structure according to claim 15, characterized in that: The etching method described in step eleven is dry etching.

17. The method for manufacturing an LDMOS device structure according to claim 15, characterized in that: The conductive metal mentioned in step eleven is tungsten.

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