Laterally diffused metal oxide semiconductor device and preparation method thereof

Abstract

The invention relates to a laterally diffused metal oxide semiconductor device and a preparation method thereof. The laterally diffused metal oxide semiconductor device includes: a substrate; the first doped region is arranged in the substrate; the second doped region is arranged in the substrate and is positioned on one side, close to the surface of the substrate, of the first doped region; the first groove is formed in the substrate, is opened from the surface of the substrate and extends to the first doped region so as to expose part of the first doped region; the drain region is arranged in the exposed part of the first doped region; the source region is arranged in the substrate; the grid electrode is arranged on one side, away from the drain region, of the source region; the well region is arranged in the substrate; the well region extends from the surface of the substrate to the first doped region and is adjacent to the second doped region; the well region is located between the gate and the drain region. According to the embodiment of the invention, the Cgd capacitance can be reduced while the withstand voltage of the device is improved, so that the adverse effect on the FOM value is reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a laterally diffused metal oxide semiconductor device and a method for preparing the same. Background Art

[0002] With the continuous development of semiconductor technology, the application of lateral double-diffuse MOS (LDMOS) devices has become increasingly widespread, and at the same time, higher requirements have been placed on the performance of lateral diffused metal oxide semiconductor devices. The FOM value is a key indicator for measuring device performance. The smaller the FOM value, the better the device performance. Among them, FOM = Cgd*Rsp, which is determined by the Cgd capacitance and Rsp on-resistance of LDMOS. In related LDMOS technology, while improving the withstand voltage of the device, the Rsp on-resistance and Cgd capacitance are usually increased, causing the FOM value of the device to deteriorate as the withstand voltage increases. How to reduce the adverse effects on the FOM value while improving the withstand voltage of the device has become the direction of designers' efforts. Summary of the invention

[0003] Based on this, it is necessary to provide a laterally diffused metal oxide semiconductor device and a method for preparing the same in order to address the above problems.

[0004] In order to achieve the above objectives, in a first aspect, the present application provides a laterally diffused metal oxide semiconductor device, comprising:

[0005] substrate;

[0006] A first doped region, disposed in the substrate;

[0007] A second doping region is disposed in the substrate and is located on a side of the first doping region close to the surface of the substrate;

[0008] A first trench is provided in the substrate and opens from a surface of the substrate and extends to the first doped region to expose a portion of the first doped region;

[0009] A drain region, disposed in the exposed portion of the first doped region;

[0010] A source region, disposed in the substrate;

[0011] A gate, disposed on a side of the source region away from the drain region;

[0012] A well region is provided in the substrate; the well region extends from the surface of the substrate toward the first doping region and is adjacent to the second doping region; the well region is located between the gate and the drain region.

[0013] In one of the embodiments, the doping concentration of the well region gradually decreases from an end close to the source region to an end close to the drain region.

[0014] In one of the embodiments, the width of the well region gradually decreases from one end close to the source region to one end close to the drain region; the width is the dimension from one side of the well region close to the drain region to one side of the well region close to the gate.

[0015] In one of the embodiments, a gate trench is provided in the substrate, and the gate trench extends from the surface of the substrate toward the second doping region; the gate is located in the gate trench.

[0016] In one embodiment, the LDMOS device further includes a split gate, the gate trench extends into the second doped region, and the split gate is disposed in the gate trench and adjacent to the second doped region.

[0017] In one embodiment, the source region is at least located on both sides of the gate along a first direction; the first trench is at least located on both sides of the gate along the first direction; the drain region is at least located on both sides of the gate along the first direction; and the first direction is perpendicular to the thickness direction of the substrate.

[0018] In one embodiment, there are multiple gates, and the multiple gates are arranged at intervals along the first direction;

[0019] The source region is disposed on both sides of each gate along the first direction, and the first trench and the drain region are disposed on both sides of each gate along the first direction;

[0020] Two source regions, one first trench and one drain region are arranged between two adjacent gates; one first trench and one drain region are arranged between the two source regions.

[0021] In one embodiment, the laterally diffused metal oxide semiconductor device further includes an isolation structure, which is disposed on the substrate and encloses a device region;

[0022] The first doped region, the second doped region, the first trench, the drain region, the source region, the gate and the well region are all located in the device region.

[0023] In one of the embodiments, the first doped region is a buried layer, and the second doped region is a drift region;

[0024] The laterally diffused metal oxide semiconductor device also includes a body region, which is arranged in the substrate and extends from the surface of the substrate to the second doped region; the body region is located on the side of the gate close to the drain region and is adjacent to the gate; the source region is located in the body region; the orthographic projection of the body region on the first doped region covers the orthographic projection of the well region on the first doped region.

[0025] In a second aspect, an embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device, specifically comprising:

[0026] A substrate having a first doping region, a second doping region and a well region is provided; the second doping region is located on a side of the first doping region close to a surface of the substrate; the well region is located on a side of the first doping region close to a surface of the substrate and is adjacent to the second doping region;

[0027] forming a gate and a source region; the source region is located in the substrate;

[0028] forming a first trench in the substrate, wherein the first trench opens from a surface of the substrate and extends to the first doped region to expose a portion of the first doped region;

[0029] A drain region is formed in the first doped region, and the drain region is located in the exposed portion of the first doped region; wherein the gate is located on a side of the source region away from the drain region, and the well region is located between the gate and the drain region.

[0030] In one embodiment, the step of providing a substrate having a first doped region, a second doped region and a well region comprises:

[0031] Providing a base layer having a first doping region;

[0032] forming an epitaxial layer on the base layer;

[0033] The second doped region and the well region are sequentially formed in the epitaxial layer.

[0034] In one embodiment, the step of forming the gate and the source region includes:

[0035] forming a gate trench in the substrate, wherein the gate trench extends from the surface of the substrate to the second doped region;

[0036] forming a split gate and the gate in sequence in the gate trench; the split gate is adjacent to the second doped region;

[0037] The source region is formed in the substrate.

[0038] The laterally diffused metal oxide semiconductor device and the preparation method thereof provided in the embodiment of the present application are provided by providing a first trench on the substrate, providing the drain region in the first doped region at the bottom of the first trench, and providing a well region adjacent to the second doped region between the drain region and the gate. In this way, on the one hand, the well region can provide a depletion layer to achieve charge balance with the second doped region and improve the withstand voltage of the device; on the other hand, the structure of the source region and the well region can shield the Cgd capacitance between the drain region and the gate, thereby effectively reducing the Cgd capacitance between the drain region and the gate and improving the operating frequency of the device; in summary, the embodiment of the present application can reduce the Cgd capacitance while improving the withstand voltage of the device, thereby reducing the adverse effect on the FOM value. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1A It is a schematic diagram of the cross-sectional structure of a laterally diffused metal oxide semiconductor device provided in one embodiment of the present application.

[0041] Figure 1B It is a schematic diagram of the cross-sectional structure of another laterally diffused metal oxide semiconductor device provided in one embodiment of the present application.

[0042] Figure 1C It is a schematic diagram of the cross-sectional structure of another laterally diffused metal oxide semiconductor device provided in one embodiment of the present application.

[0043] Figure 2 A preparation flow chart of a method for preparing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application.

[0044] Figure 3 for Figure 2 A preparation flow chart of S100 in the preparation method shown.

[0045] Figure 4 for Figure 2 A preparation flow chart of S200 in the preparation method shown.

[0046] Figure 5-Figure 15 for Figure 2 Schematic diagram of the cross-sectional structure of the device structure during the preparation method shown.

[0047] Description of reference numerals:

[0048] 1. Laterally diffused metal oxide semiconductor device; 10. substrate; 11. base layer; 111. first doped region; 12. epitaxial layer; 121. drain region; 122. source region; 123. second doped region; 124. well region; 125. body region; 126. body lead-out region; 13. first trench; 14. gate trench; 20. gate; 21. gate dielectric layer; 22. gate conductive layer; 30. split gate; 31. split gate dielectric layer; 32. split gate conductive layer; 40. conductive layer; 51. first dielectric layer; 52. second dielectric layer; 61. drain lead-out structure; 62. source lead-out structure; 63. gate lead-out structure; 71. first mask layer; 72. first gate dielectric material layer; 73. first gate conductive material layer; 74. second gate dielectric material layer; 75. second mask layer. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0055] As described in the background technology, in the relevant LDMOS technology, LDMOS usually adopts the structure of the lateral drift region. In order to improve the withstand voltage of the device, the length of the drift region and the Poly field plate is usually increased. However, the applicant has found that the increase in the length of the drift region will increase the Rsp on-resistance, and the increase in the length of the drift region will increase the device area, further leading to an increase in the Rsp on-resistance. At the same time, the Poly field plate increases the parasitic capacitance between the gate and the drain, resulting in an increase in the Cgd capacitance. Therefore, the superposition of the above factors causes the device FOM value to deteriorate sharply with the increase in withstand voltage. How to reduce the adverse effects on the FOM value while improving the withstand voltage of the device has become the direction of the designers' efforts.

[0056] In view of this, the embodiment of the present application provides a laterally diffused metal oxide semiconductor device and a method for preparing the same, by setting a first trench on the substrate, setting the drain region in the first doped region at the bottom of the first trench, and setting a well region adjacent to the second doped region between the drain region and the gate. In this way, on the one hand, the well region can provide a depletion layer to achieve charge balance with the second doped region and improve the withstand voltage of the device; on the other hand, the structure of the source region and the well region can shield the Cgd capacitance between the drain region and the gate, thereby effectively reducing the Cgd capacitance between the drain region and the gate and improving the operating frequency of the device; in summary, the embodiment of the present application can reduce the Cgd capacitance while improving the withstand voltage of the device, thereby reducing the adverse effect on the FOM value.

[0057] First, refer to Figure 1A As shown, the present application provides a laterally diffused metal oxide semiconductor device 1, and the laterally diffused metal oxide semiconductor device 1 takes an N-type laterally diffused metal oxide semiconductor device 1 as an example, and the first doping type is P-type and the second doping type is N-type. In other embodiments, the laterally diffused metal oxide semiconductor device 1 may also be a P-type laterally diffused metal oxide semiconductor device 1, and the first doping type is N-type and the second doping type is P-type.

[0058] Specifically, the lateral diffusion metal oxide semiconductor device 1 includes: a substrate 10, a first doping region 111, a second doping region 123, a first trench 13, a drain region 121, a source region 122, a gate 20 and a well region 124. The first doping region 111 is provided in the substrate 10. The second doping region 123 is provided in the substrate 10 and is located on a side of the first doping region 111 close to the surface of the substrate 10. The first trench 13 is provided in the substrate 10 and is opened from the surface of the substrate 10 and extends to the first doping region 111 to expose a portion of the first doping region 111. The drain region 121 is provided in the exposed portion of the first doping region 111. The source region 122 is provided in the substrate 10. The gate 20 is provided on a side of the source region 122 away from the drain region 121. The well region 124 is provided in the substrate 10, and the well region 124 is located on a side of the first doping region 111 close to the surface of the substrate 10 and is adjacent to the second doping region 123. The well region 124 is located between the gate 20 and the drain region 121 .

[0059] Here, the drain region 121 being disposed in the exposed portion of the first doping region 111 can be understood as: the drain region 121 is located in the first doping region 111 at the bottom of the first trench 13 .

[0060] In one example, the substrate 10 includes a base layer 11 and an epitaxial layer 12 which are stacked, and the first doping region 111 is disposed in the base layer 11. The second doping region 123 is disposed in the epitaxial layer 12. Specifically, the base layer 11 and the well region 124 are of the first doping type, and the first doping region 111, the second doping region 123, the drain region 121, and the source region 122 are of the second doping type.

[0061] It should be noted that the material of the base layer 11 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), etc., or other materials known to those skilled in the art, and the base layer 11 can provide a supporting foundation for the structural layer on the base layer 11. In the embodiment of the present application, the drain region 121 is a drain terminal, and the source region 122 is a source terminal.

[0062] It can be understood that the cross-sectional shape of the first groove 13 can be an inverted trapezoid, a rectangle, a semicircle, etc., and the embodiment of the present application does not limit the shape of the first groove 13.

[0063] The lateral diffused metal oxide semiconductor device 1 provided in the embodiment of the present application is provided with a first trench 13 on the substrate 10, a drain region 121 is provided in the first doped region 111 at the bottom of the first trench 13, and a well region 124 adjacent to the second doped region 123 is provided between the drain region 121 and the gate 20. In this way, on the one hand, the well region 124 can provide a depletion layer to achieve charge balance with the second doped region 123, thereby improving the device withstand voltage; on the other hand, the embodiment of the present application adopts the Drain / Source / Gate port arrangement, and the structure of the source region 122 and the well region 124 can shield the Cgd capacitance between the drain region 121 and the gate 20, thereby effectively reducing the Cgd capacitance between the drain region 121 and the gate 20, and improving the operating frequency of the device; in summary, the embodiment of the present application can reduce the Cgd capacitance while improving the device withstand voltage, thereby reducing the adverse effect on the FOM value.

[0064] Further, refer to Figure 1A As shown, the dotted arrow in the figure indicates the path through which the current flows from the source region 122 to the drain region 121. As can be seen from the figure, on the one hand, the second doping region 123 in the embodiment of the present application adopts a vertical structure. When increasing the withstand voltage of the device, it is only necessary to increase the size of the second doping region 123 in the vertical direction, so that the device area will not be increased; on the other hand, the path through which the current flows through the first doping region 111 is shorter, so that the on-resistance (Rsp) of the device can be made smaller; on the other hand, the drain region 121 is closer to the center of the first doping region 111, which is conducive to the potential conduction of the drain region 121, and is conducive to a more uniform opening of the body diode, thereby facilitating the improvement of the device's ability to discharge current.

[0065] In one embodiment, the first trench 13 is a deep trench.

[0066] In one embodiment, referring to Fig.14 As shown, the dimension H of the first groove 13 along the thickness direction of the substrate 10 is greater than or equal to 0.5 μm. In one example, the dimension H of the first groove 13 along the thickness direction of the substrate 10 is between 0.5 μm and 20 μm. Exemplarily, the dimension H can be 0.5 μm, 1 μm, 5 μm, 7.5 μm, 9 μm, 12 μm, 16 μm, 19 μm or 20 μm. Here, the dimension H can be understood as the depth of the first groove 13. By making the depth of the first groove 13 within the above range, it can be ensured that the device has a lower Cgd capacitance under the premise of stable operation.

[0067] In one embodiment, the doping concentration of the well region 124 gradually decreases from an end close to the source region 122 to an end close to the drain region 121 .

[0068] In this way, linear ion doping can be formed from the source region 122 to the drain region 121 , which is beneficial to optimizing the electric field distribution of the second doping region 123 , thereby improving the breakdown voltage of the device.

[0069] In one embodiment, referring to Figure 1B and Figure 1C As shown, the width W of the well region 124 gradually decreases from the end close to the source region 122 to the end close to the drain region 121. The width W is the dimension from the side of the well region 124 close to the drain region 121 to the side of the well region 124 close to the gate 20.

[0070] In this way, linear ion doping can be formed from the source region 122 to the drain region 121 , which is beneficial to optimizing the electric field distribution of the second doping region 123 , thereby improving the breakdown voltage of the device.

[0071] In one example, the well region 124 is a deep well, which is beneficial for optimizing the electric field distribution of the second doping region 123 and thus improving the breakdown voltage of the device.

[0072] In one embodiment, a gate trench 14 is provided in the substrate 10, and the gate trench 14 extends from the surface of the substrate 10 toward the second doping region 123. The gate 20 is located in the gate trench 14. This is beneficial to assist the depletion of the second doping region 123, thereby improving the device withstand voltage.

[0073] It can be understood that the gate 20 includes a gate dielectric layer 21 and a gate conductive layer 22 . The gate dielectric layer 21 is disposed on the sidewall of the gate trench 14 , and the gate conductive layer 22 is disposed on a side of the gate dielectric layer 21 away from the sidewall.

[0074] In one example, the gate dielectric layer 21 is a gate oxide layer, and the material of the gate dielectric layer 21 may be silicon dioxide. The material of the gate conductive layer 22 may be polysilicon or metal.

[0075] In one embodiment, the LDMOS device 1 further includes a split gate 30, the gate trench 14 extends into the second doping region 123, and the split gate 30 is disposed in the gate trench 14 and adjacent to the second doping region 123. Further, the split gate 30 is located on a side of the gate 20 close to the first doping region 111.

[0076] In this way, the device in the embodiment of the present application utilizes the structure of the source region 122 and the well region 124 to shield the capacitance Cgd between the drain region 121 and the gate 20, thereby effectively reducing the parasitic capacitance Cgd between the drain region 121 and the gate 20. By adopting a trench split gate structure at the gate 20 end, on the one hand, the Cgd capacitance can be further shielded; on the other hand, the second doping region 123 can also be assisted in being depleted, thereby further improving the device's withstand voltage.

[0077] It can be understood that the split gate 30 includes a split gate dielectric layer 31 and a split gate conductive layer 32 . The split gate dielectric layer 31 is disposed on the sidewall of the gate trench 14 , and the split gate conductive layer 32 is disposed on a side of the split gate dielectric layer 31 away from the sidewall.

[0078] In one example, the split gate dielectric layer 31 is a split gate oxide layer, and the material of the split gate oxide layer may be silicon dioxide. The material of the split gate conductive layer 32 may be polysilicon or metal.

[0079] In one embodiment, the source region 122 is at least located on both sides of the gate 20 along the first direction X. The first trench 13 is at least located on both sides of the gate 20 along the first direction X. The drain region 121 is at least located on both sides of the gate 20 along the first direction X. The first direction X is perpendicular to the thickness direction of the substrate 10. In this way, the device structure types can be more abundant, and different device structure types can be realized.

[0080] In one example, the source region 122 is disposed around the periphery of the gate 20. Here, it can also be understood that the source region 122 is disposed around the periphery of the positive projection of the gate 20 on the substrate 10. The drain region 121 is disposed around the periphery of the source region 122. Here, it can also be understood that the drain region 121 is disposed around the periphery of the positive projection of the gate 20 on the substrate 10. The first trench 13 is disposed around the periphery of the source region 122. Here, it can also be understood that the first trench 13 is disposed around the periphery of the positive projection of the gate 20 on the substrate 10.

[0081] In this way, the source region 122 and the drain region 121 are arranged in a ring shape, and this structure is beneficial to improving the withstand voltage of the device.

[0082] In another example, the source region 122 is located on both sides of the gate 20 along the first direction X. The drain region 121 is located on both sides of the gate 20 along the first direction X. The source region 122 is located between the drain region 121 and the gate 20. In this way, the source region 122 and the drain region 121 are arranged in a strip shape. In this structure, two cells share the same gate 20.

[0083] In one embodiment, there are multiple gates 20, and the multiple gates 20 are arranged at intervals along the first direction X. Each gate 20 is provided with source regions 122 on both sides along the first direction X, and each gate 20 is provided with first trenches 13 and drain regions 121 on both sides along the first direction X. Two source regions 122, one first trench 13 and one drain region 121 are provided between two adjacent gates 20. One first trench 13 and one drain region 121 are provided between two source regions 122.

[0084] Thus, the laterally diffused metal oxide semiconductor device 1 provided in the embodiment of the present application includes at least one unit cell, and each unit cell includes at least a drain region 121 , a source region 122 and a gate 20 .

[0085] In one embodiment, the lateral diffused metal oxide semiconductor device 1 further includes an isolation structure (not shown), which is disposed on the substrate 10 and surrounds a device region (not shown). The first doped region 111, the second doped region 123, the first trench 13, the drain region 121, the source region 122, the gate 20 and the well region 124 are all located in the device region.

[0086] The embodiment of the present application sets the first trench 13 in the device area. On the one hand, it avoids setting the first trench 13 on the isolation structure, reduces the adverse effect of the first trench 13 on the setting and performance of the isolation structure, makes the setting of the isolation structure more flexible, and thus reduces the difficulty of device manufacturing. On the other hand, compared with the method of setting the first trench 13 on the isolation structure, the embodiment of the present application will not increase the area of ​​the cell, which is beneficial to reducing the on-resistance.

[0087] In one embodiment, the first doped region 111 is a buried layer, and the second doped region 123 is a drift region. The laterally diffused metal oxide semiconductor device 1 further includes a body region 125, which is disposed in the substrate 10 and extends from the surface of the substrate 10 to the second doped region 123. The body region 125 is located on a side of the gate 20 close to the drain region 121 and is adjacent to the gate 20. The source region 122 is located in the body region 125. The orthographic projection of the body region 125 on the first doped region 111 covers the orthographic projection of the well region 124 on the first doped region 111. Specifically, the body region 125 is of the first doping type.

[0088] It is understandable that the body region 125 can also shield the Cgd capacitance between the drain region 121 and the gate 20 , thereby effectively reducing the Cgd capacitance between the drain region 121 and the gate 20 and improving the operating frequency of the device.

[0089] In the embodiment of the present application, on the one hand, the well region 124 can provide a depletion layer to achieve charge balance with the drift region and improve the device's withstand voltage; on the other hand, the drift region adopts a vertical structure. When increasing the device's withstand voltage, it is only necessary to increase the drift region size in the vertical direction. In this way, the device area will not be increased.

[0090] In one embodiment, the LDMOS device 1 further includes: a conductive layer 40 , a first dielectric layer 51 , a second dielectric layer 52 , a drain lead-out structure 61 , a source lead-out structure 62 and a gate lead-out structure 63 .

[0091] The conductive layer 40 is disposed in the first trench 13, one end of the conductive layer 40 is in electrical contact with the drain region 121, and the other end is located on the surface of the substrate 10. The first dielectric layer 51 is filled in the first trench 13. The second dielectric layer 52 covers the surface of the substrate 10. The drain region lead-out structure 61 is electrically connected to the conductive layer 40 and penetrates to the surface of the second dielectric layer 52. The source region lead-out structure 62 is electrically connected to the source region 122 and penetrates to the surface of the second dielectric layer 52. The gate lead-out structure 63 is electrically connected to the gate 20 and penetrates to the surface of the second dielectric layer 52.

[0092] In this way, the first dielectric layer 51 plays an insulating role, which can reduce the electrical interference of the conductive layer 40 on other structures. The second dielectric layer 52 can protect the cell structure of the device, and the drain lead structure 61, the source lead structure 62 and the gate lead structure 63 can electrically connect the source region 122, the drain region 121 and the gate 20 of the device to the external circuit. Furthermore, in addition, the source lead structure 62 is located between the drain region 121 and the gate 20, and the source lead structure 62 can shield the Cgd capacitance between the drain region 121 and the gate 20, thereby effectively reducing the Cgd capacitance between the drain region 121 and the gate 20, and improving the operating frequency of the device.

[0093] In one example, the first conductive layer 40 and the second conductive layer 40 are made of silicon dioxide. The conductive layer 40 is made of polysilicon or metal.

[0094] In one example, a body lead-out region 126 is further disposed in the body region 125 , and the body lead-out region 126 is of the first doping type. The body lead-out region 126 may be led out through the source region lead-out structure 62 .

[0095] Second, refer to Figure 2 , and combined with Figure 5-Figure 15 As shown, the embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device 1, which specifically includes:

[0096] S100: Provide a substrate 10 having a first doping region 111, a second doping region 123 and a well region 124. The second doping region 123 is located on a side of the first doping region 111 close to the surface of the substrate 10. The well region 124 is located on a side of the first doping region 111 close to the surface of the substrate 10 and is adjacent to the second doping region 123.

[0097] In one embodiment, referring to Figure 3 As shown, S100 specifically includes the following steps:

[0098] S110: Provide a base layer 11 having a first doping region 111. Figure 5As shown, the base layer 11 is a P-type semiconductor, and N-type ions are implanted into the base layer 11 by ion implantation to form a first doped region 111 .

[0099] Exemplarily, the material of the base layer 11 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), or other materials known to those skilled in the art.

[0100] S120: forming an epitaxial layer 12 on the base layer 11. Specifically, the epitaxial layer 12 may be grown on the base layer 11 by vapor phase epitaxy or molecular beam epitaxy.

[0101] S130: sequentially forming a second doping region 123 and a well region 124 in the epitaxial layer 12. Figure 6 and Figure 7 As shown, first, N-type ions are implanted into the epitaxial layer 12 to form a second doped region 123 , and the second doped region 123 is adjacent to the first doped region 111 . Next, P-type ions are implanted into the epitaxial layer 12 to form a well region 124 .

[0102] After the well region 124 is formed, the following steps are performed:

[0103] S200: forming a gate 20 and a source region 122. The source region 122 is located in the substrate 10. The source region 122 may be formed by implanting N-type ions by ion implantation.

[0104] S300 : forming a first trench 13 in the substrate 10 , wherein the first trench 13 opens from the surface of the substrate 10 and extends to the first doping region 111 to expose a portion of the first doping region 111 .

[0105] S400: forming a drain region 121 in the first doping region 111, wherein the drain region 121 is located in the exposed portion of the first doping region 111. The gate 20 is located on a side of the source region 122 away from the drain region 121, and the well region 124 is located between the gate 20 and the drain region 121. Specifically, N-type ions may be implanted into the substrate 10 by ion implantation to form the drain region 121.

[0106] It should be noted that since ion implantation will damage the substrate 10, the mobility and life of the electron-hole pairs will be greatly reduced. In addition, most of the implanted ions are not in the lattice position in a substitutional form. In order to activate the ions and restore the original mobility, the substrate 10 must be annealed at an appropriate temperature. Annealing can repair lattice defects and move impurity atoms to lattice points to activate impurities. Generally, it takes about 450-550°C to repair lattice defects and 900-1000°C to activate impurities. The activation of impurities is related to time and temperature. The longer the time and the higher the temperature, the more fully the impurities are activated. Commonly used annealing methods for the substrate 10 are high-temperature thermal annealing and rapid thermal annealing (RTA). In one example, a high-temperature thermal annealing process can be used for annealing. Specifically, a high-temperature furnace is used to heat the silicon wafer to 800-1000°C and maintain it for 20-40 minutes. In another example, a rapid thermal annealing process may be used for annealing. Compared with a high temperature thermal annealing process, the rapid thermal annealing process has a shorter annealing time, can avoid diffusion of doped ions caused by long-term high temperature, and reduce instantaneous enhanced diffusion of doped ions.

[0107] The method for preparing the lateral diffused metal oxide semiconductor device 1 provided in the embodiment of the present application is to set the first trench 13 on the substrate 10, set the drain region 121 in the first doped region 111 at the bottom of the first trench 13, and set the well region 124 adjacent to the second doped region 123 between the drain region 121 and the gate 20. In this way, on the one hand, the well region 124 can provide a depletion layer to achieve charge balance with the drift region (the second doped region 123) and improve the device withstand voltage; on the other hand, the structure of the source region 122 and the well region 124 can shield the Cgd capacitance between the drain region 121 and the gate 20, thereby effectively reducing the Cgd capacitance between the drain region 121 and the gate 20 and improving the operating frequency of the device; in summary, the embodiment of the present application can reduce the Cgd capacitance while improving the device withstand voltage, thereby reducing the adverse effect on the FOM value.

[0108] It should be noted that before performing S200, the following steps are also included:

[0109] S140: forming a body region 125 in the substrate 10. Figure 8 As shown, P-type ions are implanted into the substrate 10 by ion implantation to form the body region 125 .

[0110] In one embodiment, referring to Figure 4 As shown, S200 specifically includes the following steps:

[0111] S210 : forming a gate trench 14 in the substrate 10 , wherein the gate trench 14 extends from the surface of the substrate 10 to the second doping region 123 .

[0112] In one example, referring to Fig. 9 and Fig.10 As shown, S210 specifically includes the following steps:

[0113] S211: forming a first mask layer 71 on the substrate 10. Specifically, the material of the first mask layer 71 may be silicon dioxide. Exemplarily, the first mask layer 71 may be formed by magnetron sputtering, chemical vapor deposition (CVD), electroplating, atomic layer deposition (ALD), and the like.

[0114] S212 : etching the first mask layer 71 and the substrate 10 to form a gate trench 14 .

[0115] After the gate trench 14 is formed, the following steps are performed:

[0116] S220 : forming a split gate 30 and a gate 20 in sequence in the gate trench 14 . The split gate 30 is adjacent to the second doping region 123 .

[0117] In one example, referring to Fig.10 , Fig.11 and Fig.12 As shown, S220 specifically includes the following steps:

[0118] S221: forming a first gate dielectric material layer 72 in the gate trench 14. The first gate dielectric material layer 72 covers the sidewalls and the bottom wall of the gate trench 14. Exemplarily, the first gate dielectric material layer 72 may be formed by magnetron sputtering, chemical vapor deposition (CVD), electroplating, atomic layer deposition (ALD), and the like. In one example, the material of the first gate dielectric material layer 72 is oxide, and further, the material of the first gate dielectric material layer 72 may be silicon dioxide.

[0119] S222: Fill the gate trench 14 with a first gate conductive material layer 73. Exemplarily, the first gate conductive material layer 73 may be formed by magnetron sputtering, chemical vapor deposition (CVD), electroplating, atomic layer deposition (ALD), etc. In one example, the first gate conductive material layer 73 is made of polysilicon or metal.

[0120] S223 : etching back the first gate conductive material layer 73 , and leaving a portion of the first gate conductive material layer 73 in the gate trench 14 .

[0121] S224 : removing the first gate dielectric material layer 72 located above the remaining first gate conductive material layer 73 and on the sidewall of the gate trench 14 .

[0122] S225: Fill the gate trench 14 with a second gate dielectric material layer 74 to cover the surface of the first gate conductive material layer 73. In one example, the second gate dielectric material layer 74 is made of oxide, and further, the second gate dielectric material layer 74 may be made of silicon dioxide.

[0123] S226 : removing the second gate dielectric material layer 74 on the sidewall of the gate trench 14 to form a split gate 30 .

[0124] S227: forming a gate dielectric layer 21 in the gate trench 14. In one example, the gate dielectric layer 21 is made of oxide, and further, the gate dielectric layer 21 may be made of silicon dioxide.

[0125] S228: forming a gate conductive layer 22 in the gate trench 14 to form a gate 20. In one example, the gate conductive layer 22 may be made of polysilicon or metal.

[0126] Next, refer to Fig.13 As shown, perform the following steps:

[0127] S230 : forming a source region 122 in the substrate 10 . Specifically, N-type ions are implanted into the body region 125 by ion implantation to form the source region 122 , and P-type ions are implanted into the body region 125 to form the body extraction region 126 .

[0128] In one embodiment, referring to Fig.14 and Fig.15 As shown, S300 specifically includes the following steps:

[0129] S310: forming a second mask layer 75 on the substrate 10, and patterning the second mask layer 75 to define the shape and position of the first trench 13. Specifically, the patterning of the second mask layer 75 includes photolithography and etching. Exemplarily, the material of the second mask layer 75 can be silicon dioxide or silicon nitride.

[0130] S320 : etching the substrate 10 based on the patterned second mask layer 75 to form a first trench 13 .

[0131] In one embodiment, after S400, the following steps are also included:

[0132] S500: forming a first dielectric material layer in the first trench 13. In one example, the first dielectric material layer may be formed by a chemical vapor deposition (CVD) process. The material of the first dielectric material layer may be silicon dioxide.

[0133] S600 : removing a portion of the first dielectric material layer to expose a portion of the first doped region 111 at the bottom of the first trench 13 .

[0134] S700: Fill the first trench 13 with a conductive material layer to form a conductive layer 40. Exemplarily, the conductive material layer can be formed by magnetron sputtering, chemical vapor deposition (CVD), electroplating, atomic layer deposition (ALD), etc. The conductive material layer can be made of copper, tungsten, aluminum, etc.

[0135] S800 : forming a second dielectric layer 52 on the substrate 10 .

[0136] S900: forming a drain lead-out structure 61, a source lead-out structure 62, and a gate lead-out structure 63 on the substrate 10. The drain lead-out structure 61 is electrically connected to the conductive layer 40 and penetrates to the surface of the second dielectric layer 52. The source lead-out structure 62 is electrically connected to the source region 122 and penetrates to the surface of the second dielectric layer 52. The gate lead-out structure 63 is electrically connected to the gate 20 and penetrates to the surface of the second dielectric layer 52.

[0137] It should be understood that, in the embodiments of the present application, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0138] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0139] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A laterally diffused metal oxide semiconductor device, characterized in that: include: substrate; A first doped region is disposed in the substrate; A second doping region is disposed in the substrate and is located on a side of the first doping region close to the surface of the substrate; A first trench is provided in the substrate and opens from a surface of the substrate and extends to the first doped region to expose a portion of the first doped region; A drain region, disposed in the exposed portion of the first doped region; A source region, disposed in the substrate; A gate, disposed on a side of the source region away from the drain region; A well region is provided in the substrate; the well region is located on a side of the first doping region close to the surface of the substrate and is adjacent to the second doping region; the well region is located between the gate and the drain region.

2. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The doping concentration of the well region gradually decreases from an end close to the source region to an end close to the drain region.

3. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The width of the well region gradually decreases from one end close to the source region to one end close to the drain region; the width is the dimension from one side of the well region close to the drain region to one side of the well region close to the gate.

4. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: A gate trench is arranged in the substrate, and the gate trench extends from the surface of the substrate toward the second doping region; the gate is located in the gate trench.

5. The laterally diffused metal oxide semiconductor device according to claim 4, characterized in that: The LDMOS device further includes a split gate. The gate trench extends into the second doping region. The split gate is disposed in the gate trench and is adjacent to the second doping region.

6. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The source region is at least located on both sides of the gate along a first direction; the first trench is at least located on both sides of the gate along the first direction; the drain region is at least located on both sides of the gate along the first direction; and the first direction is perpendicular to the thickness direction of the substrate.

7. The laterally diffused metal oxide semiconductor device according to claim 6, characterized in that: There are multiple gates, and the multiple gates are arranged at intervals along the first direction; The source region is disposed on both sides of each gate along the first direction, and the first trench and the drain region are disposed on both sides of each gate along the first direction; Two source regions, one first trench and one drain region are arranged between two adjacent gates; one first trench and one drain region are arranged between the two source regions.

8. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The laterally diffused metal oxide semiconductor device further comprises an isolation structure, which is disposed on the substrate and surrounds a device region; The first doped region, the second doped region, the first trench, the drain region, the source region, the gate and the well region are all located in the device region.

9. The laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The first doped region is a buried layer, and the second doped region is a drift region; The laterally diffused metal oxide semiconductor device also includes a body region, which is arranged in the substrate and extends from the surface of the substrate to the second doped region; the body region is located on the side of the gate close to the drain region and is adjacent to the gate; the source region is located in the body region; the orthographic projection of the body region on the first doped region covers the orthographic projection of the well region on the first doped region.

10. A method for preparing a laterally diffused metal oxide semiconductor device, characterized in that: include: Providing a substrate having a first doping region, a second doping region and a well region; wherein the second doping region is located on a side of the first doping region close to a surface of the substrate; The well region is located on a side of the first doping region close to the surface of the substrate and is adjacent to the second doping region; forming a gate and a source region; the source region is located in the substrate; forming a first trench in the substrate, wherein the first trench opens from a surface of the substrate and extends to the first doped region to expose a portion of the first doped region; A drain region is formed in the first doped region, and the drain region is located in the exposed portion of the first doped region; wherein the gate is located on a side of the source region away from the drain region, and the well region is located between the gate and the drain region.

11. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 10, characterized in that: The step of providing a substrate having a first doping region, a second doping region and a well region comprises: Providing a base layer having a first doping region; forming an epitaxial layer on the base layer; The second doped region and the well region are sequentially formed in the epitaxial layer.

12. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 10, characterized in that: The step of forming the gate and the source region comprises: forming a gate trench in the substrate, wherein the gate trench extends from the surface of the substrate to the second doped region; forming a split gate and the gate in sequence in the gate trench; the split gate is adjacent to the second doped region; The source region is formed in the substrate.

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