Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a semiconductor layer and a trench gate, the semiconductor layer has a first surface and a second surface opposite to each other, the trench gate is located in a trench of the first surface of the semiconductor layer, and the semiconductor layer comprises a first buried layer located at the bottom of the trench gate and connected with the trench gate; the body region is connected with the side wall of the trench gate; the source region is connected with the side wall of the trench gate, and the source region extends from the first surface to the body region and is connected with the body region; at least part of the drift region is located between the body region and the second surface and connected with the first buried layer and the body region, the width of the trench gate is not smaller than the depth of the trench gate, and the width of the trench gate is larger than the width of the first buried layer. By widening the width of the trench gate and arranging the narrower buried layer at the bottom of the trench gate, the barrier of the buried layer to the flow of current carriers is reduced, and the overall voltage endurance capability of the device is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more specifically, to a semiconductor device with a trench gate structure and a manufacturing method thereof. Background Art

[0002] In a vertical transistor with a trench gate, the drain of the transistor needs to be able to withstand high voltage. Since there is a PN junction between the drain and the source, the ability to withstand high voltage is better.

[0003] However, due to the presence of the gate dielectric layer between the drain and the trench gate, it is not conducive to withstanding high voltage. Especially at the bottom and corners of the trench gate, the high voltage resistance is poor, which reduces the overall withstand voltage of the device. Therefore, it is necessary to improve the device to improve the above problems. Summary of the invention

[0004] In view of the above problems, the purpose of the present disclosure is to provide a semiconductor device and a manufacturing method thereof, which reduces the obstruction of the buried layer to the flow of carriers and improves the overall voltage resistance of the device by widening the width of the trench gate and setting a narrower buried layer at its bottom.

[0005] According to one aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising a semiconductor layer and a trench gate, wherein the semiconductor layer has a first surface and a second surface opposite to each other, and the trench gate is located in a trench on the first surface of the semiconductor layer.

[0006] The semiconductor layer comprises:

[0007] A first buried layer, located at the bottom of the trench gate and connected to the trench gate;

[0008] A body region connected to a sidewall of the trench gate;

[0009] a source region connected to a sidewall of the trench gate, the source region extending from the first surface toward the body region and connected to the body region; and

[0010] a drift region, at least a portion of which is located between the body region and the second surface and connected to the first buried layer and the body region,

[0011] Wherein, the width of the trench gate is not less than the depth of the trench gate, and the width of the trench gate is greater than the width of the first buried layer.

[0012] Optionally, the source region and the drift region are of a first conductivity type, the first buried layer and the body region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

[0013] Optionally, the semiconductor layer further includes a second buried layer, which is separated from the trench gate and the first buried layer respectively, and the second buried layer has the same conductivity type as the first buried layer.

[0014] The body region is located between the second buried layer and the first surface and is connected to the second buried layer, and the drift region is connected to the second buried layer.

[0015] Optionally, the bottom of the first buried layer is flush with the bottom of the second buried layer.

[0016] Optionally, both the first buried layer and the second buried layer extend along a length direction of the trench gate.

[0017] Optionally, along the width direction of the trench gate, the body region, the source region and the second buried layer are all located on two sides of the trench gate.

[0018] Optionally, the semiconductor layer further includes a third buried layer, which is located between the first buried layer and the second buried layer and connected to the first buried layer, the second buried layer and the body region, and the conductivity type of the third buried layer is the same as that of the first buried layer.

[0019] Optionally, a plurality of the third buried layers are spaced apart along the length direction of the trench gate.

[0020] Optionally, along the length direction of the trench gate, a spacing distance between adjacent third buried layers is greater than a length of the third buried layer.

[0021] Optionally, the third buried layer is flush with a bottom of the first buried layer.

[0022] Optionally, along the length direction of the trench gate, a plurality of the trench gates are arranged at intervals.

[0023] Along the length direction of the trench gates, the body region and the source region are also located between adjacent trench gates.

[0024] Optionally, along the length direction of the trench gates, a spacing region between adjacent trench gates corresponds to a portion of the third buried layer.

[0025] Optionally, along the length direction of the trench gate, the trench gate extends continuously.

[0026] According to another aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:

[0027] forming a first buried layer in a semiconductor layer, the semiconductor layer having a first surface and a second surface opposite to each other, the first buried layer being at a preset distance from the first surface;

[0028] forming a well region in the semiconductor layer, wherein the well region extends from the first surface toward the first buried layer and is connected to the first buried layer;

[0029] forming a doped region in the well region, the doped region extending from the first surface into the well region; and

[0030] forming a trench extending from the first surface to the first buried layer, and forming a trench gate in the trench,

[0031] Wherein, the width of the trench gate is not less than the depth of the trench gate, and the width of the trench gate is greater than the width of the first buried layer.

[0032] Optionally, the method further comprises forming a second buried layer in the semiconductor layer.

[0033] The second buried layer is separated from the trench gate and the first buried layer respectively, and the well region is located between the second buried layer and the first surface and is connected to the second buried layer.

[0034] Optionally, the method further comprises forming a third buried layer in the semiconductor layer.

[0035] The third buried layer is located between the first buried layer and the second buried layer, and is connected to the first buried layer, the second buried layer and the well region.

[0036] Optionally, the first buried layer, the second buried layer and the third buried layer are formed simultaneously by an ion implantation process.

[0037] One of the above technical solutions has the following beneficial effects:

[0038] By setting a first buried layer at the bottom of the trench gate, the voltage resistance of the bottom of the trench gate is increased, and the width of the trench gate is set to be no less than the depth of the trench gate. Compared with a narrow trench solution in which the width of the trench gate is less than the depth, this solution widens the width of the trench gate, so that the first buried layer can only contact the bottom of the trench gate without wrapping the corners of the trench gate, which greatly reduces the obstruction of the first buried layer to the flow of carriers, thereby reducing the on-resistance of the device.

[0039] In some embodiments, the body region and the source region are disposed on both sides of the trench gate and connected to the sidewalls of the trench gate, so that both sides of the trench gate can be used as conductive channels, thereby reducing the resistance of the device in the on state.

[0040] In some embodiments, a second buried layer is provided on both sides of the trench gate, thereby improving the problem of electric field concentration at the corners of the trench gate and increasing the voltage resistance at the corners of the trench gate.

[0041] In some embodiments, the electrical connection between the first buried layer and the source region is achieved by providing a third buried layer, so that the first buried layer will no longer be in a floating state, making the electric field shielding function of the first buried layer on the bottom of the trench gate more stable.

[0042] In some embodiments, third buried layers are spaced along the length direction of the trench gate, which can not only stabilize the electric field shielding function of the first buried layer on the bottom of the trench gate, but also utilize the spacing area between adjacent third buried layers to layout the current distribution between the source and the drain.

[0043] In some embodiments, an ion implantation process is used to simultaneously form a first buried layer, a second buried layer, and a third buried layer in the semiconductor layer, thereby saving the number of masks and eliminating the need for additional alignment of the patterns of the first to third buried layers, thereby reducing process difficulty and saving costs.

[0044] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0046] Figure 1 A schematic top view of the structure of a semiconductor device according to a first embodiment of the present disclosure is shown.

[0047] Figure 2 Shown along Figure 1 Schematic diagram of the cross-sectional structure taken along line AA.

[0048] Figure 3 Shown along Figure 1 Schematic diagram of the cross-sectional structure taken along line BB.

[0049] Figure 4 A schematic top view of the structure of a semiconductor device according to a second embodiment of the present disclosure is shown.

[0050] Figures 5 to 9 A three-dimensional structural schematic diagram showing a part of the stages in the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0051] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0052] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0053] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".

[0054] The power device generally includes an active component region, an edge termination region, and a crack-stop or shielding region. The active component region includes an active component array. The present disclosure relates to an active component structure. The size of the active component may vary depending on product requirements, and there may be a body region between active components in the active component region.

[0055] Many specific details of the present disclosure are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0056] In vertical transistors, such as SiC MOSFET, it is necessary to be able to withstand a high voltage applied to the drain. Since there is a PN junction between the drain and the source, the ability to withstand high voltage is better. However, between the drain and the trench gate, due to the presence of the gate dielectric layer, it is not conducive to withstanding high voltage. Especially at the bottom and corners of the trench gate, the gate dielectric layer has poor high-voltage resistance and a shielding structure needs to be designed separately. In order to improve the above problems, the purpose of the present disclosure is to provide a semiconductor device, which improves the overall voltage resistance of the device and reduces the obstruction of the buried layer to the flow of carriers by widening the width of the trench gate and providing a narrow buried layer at the bottom thereof.

[0057] Figure 1 FIG. 1 is a schematic diagram showing a top view of a semiconductor device according to a first embodiment of the present disclosure. Figure 2 Shown along Figure 1 Schematic diagram of the cross-section structure cut by line AA. Figure 3 Shown along Figure 1 Schematic diagram of the cross-section structure cut by line BB, where: Figure 1 Only the buried layer and the trench gate are shown, and other structures are omitted in order to more clearly express the positional relationship between the various structures.

[0058] like Figures 1 to 3As shown, the semiconductor device of the first embodiment of the present disclosure includes a semiconductor layer, a plurality of trench gates 150, an interlayer dielectric layer 160, a first conductive layer 171 and a second conductive layer 172. The semiconductor layer has a first surface 101 and a second surface 102 relative to each other and a plurality of grooves, and the grooves extend from the first surface 101 to the second surface 102 into the semiconductor layer. The plurality of trench gates 150 are located in the corresponding grooves. Among them, the semiconductor layer is, for example, a SiC, GaN, Ga2O3, Al2O3 substrate or a stacked structure consisting of a substrate and an epitaxial layer. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art can make other settings for the material and number of layers of the semiconductor layer as needed, such as other wide bandgap semiconductor materials.

[0059] The semiconductor layer includes a drift region 110, a first buried layer 121, a second buried layer 122, a third buried layer 123, a body region 131, a source region 141, and a body contact region 142. The source region 141 and the drift region 110 are of the first conductivity type, the first buried layer 121, the second buried layer 122, the third buried layer 123, the body region 131, and the body contact region 142 are of the second conductivity type, and the doping concentration of the body contact region 142 is greater than the doping concentration of the body region 131. The first conductivity type is opposite to the second conductivity type. The first conductivity type is one of the P type and the N type, and the second conductivity type is the other of the P type and the N type.

[0060] The semiconductor device of this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and can also be used as an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), for example, a drain contact region is set on the second surface 102 of the semiconductor layer, and the conductivity type of the drain contact region is set to the first conductivity type or the second conductivity type. However, the embodiments of the present disclosure are not limited to this, and those skilled in the art can perform other settings on the conductivity type of each region in the semiconductor layer as needed to use the semiconductor device as a MOSFET or an IGBT.

[0061] The trench gate 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers the inner surface of the trench, and the gate conductor 152 is located in the trench. The gate dielectric layer 151 is located between the semiconductor layer and the gate conductor 152, and is used to separate the semiconductor layer from the gate conductor 152. The width direction of the trench gate 150 is the X-axis direction, the depth direction is the Z-axis direction, and the length direction is the Y-axis direction. Optionally, the X-axis, Y-axis, and Z-axis directions are perpendicular to each other.

[0062] The first buried layer 121 is located at the bottom of the trench gate 150. Along the X-axis direction, the second buried layer 122, the body region 131, the source region 141 and the body contact region 142 are all located on both sides of the trench gate 150.

[0063] The first buried layer 121 is connected to the trench gate 150, wherein the trench gate 150 is a wide trench structure, and the width of the trench gate 150 is not less than the depth of the trench gate 150, so that in an actual manufacturing process, the width of the first buried layer 121 can be smaller than the width of the trench gate 150, and the first buried layer 121 is only located at the bottom of the trench gate 150 and does not wrap the corner of the trench gate 150. In some specific embodiments, the depth of the trench gate 150 is less than the width of the trench gate 150, and the depth of the first buried layer 121 is greater than the depth of the trench gate 150.

[0064] The first buried layer 121 and the second buried layer 122 both extend along the Y-axis direction and are separated from each other. The second buried layer 122 is not connected to the trench gate 150. Along the X-axis direction, the third buried layer 123 is located between the first buried layer 121 and the second buried layer 122, and connects the first buried layer 121 and the second buried layer 122 respectively. Along the Y-axis direction, multiple third buried layers 123 are arranged at intervals. Optionally, the spacing distance Sp between adjacent third buried layers 123 is greater than the length Wp of the third buried layer 123. Optionally, the bottoms of the first buried layer 121, the second buried layer 122 and the third buried layer 123 are flush. Optionally, in the XY plane, the third buried layer 123 can extend along the X-axis or at a preset angle to the X-axis.

[0065] Along the X-axis direction, the body region 131 is respectively connected to the two side walls of the trench gate 150 and the second buried layer 122. The source region 141 extends from the first surface 101 of the semiconductor layer toward the body region 131 and is connected to the body region 131. The body contact region 142 extends from the first surface 101 of the semiconductor layer toward the body region 131 and is connected to the body region 131. Optionally, the source region 141 and the body contact region 142 can be connected or separated by the body region 131. At least part of the drift region 110 is located between the body region 131 and the second surface 102 of the semiconductor layer, and is connected to the first buried layer 121, the second buried layer 122, the third buried layer 123 and the body region 131.

[0066] The interlayer dielectric layer 160 is located on the first surface 101 of the semiconductor layer and covers the trench gate 150. The first conductive layer 171 serves as a source electrode, covering the first surface 101 of the semiconductor layer and the interlayer dielectric layer 160. The second conductive layer 172 serves as a drain electrode, covering the second surface 102 of the semiconductor layer.

[0067] In this embodiment, along the Y-axis direction, a plurality of trench gates 150 are arranged at intervals, and along the Y-axis direction, the body region 131 and the source region 141 are also located between adjacent trench gates 150. Optionally, along the Y-axis direction, the interval region between adjacent trench gates 150 corresponds to a portion of the third buried layer 123.

[0068] In this embodiment, when the device is turned on, the body region 131 and the part adjacent to the side wall of the trench gate 150 are inverted to form a channel, and carriers flow in from the source (first conductive layer 171), then flow through the source region 141 and the channel to the drift region 110, and finally flow out from the drain (second conductive layer 172), see Figure 1 The carrier flow path is shown by the dashed line.

[0069] By setting the first buried layer 121 at the bottom of the trench gate 150, the first buried layer 121 forms a PN junction with the drift region 110, thereby increasing the voltage resistance of the bottom of the trench gate 150, and setting the trench gate 150 as a wide trench structure with a width not less than the depth. Compared with the narrow trench solution in which the trench gate width is less than the depth, this embodiment widens the width of the trench gate 150, so that the first buried layer 121 can only contact with the bottom of the trench gate 150 without wrapping the corners of the trench gate 150, which greatly reduces the obstruction of the first buried layer 121 to the flow of carriers, thereby reducing the on-resistance of the device.

[0070] Furthermore, by arranging the body region 131 and the source region 141 on both sides of the trench gate 150 and connecting to the side walls of the trench gate 150 , both sides of the trench gate 150 can be used as conductive channels, thereby reducing the resistance of the device in the on state.

[0071] Furthermore, by disposing the second buried layer 122 on both sides of the trench gate 150 , the problem of electric field concentration at the corners of the trench gate 150 is improved, and the voltage resistance at the corners of the trench gate 150 is increased.

[0072] Furthermore, the third buried layer 123 is provided to electrically connect the first buried layer 121 to the source region 141 , so that the first buried layer 141 will no longer be in a floating state, making the electric field shielding function of the first buried layer 121 on the bottom of the trench gate 150 more stable.

[0073] Furthermore, the third buried layers 123 are arranged at intervals along the Y-axis direction, which can not only stabilize the electric field shielding function of the first buried layer 121 on the bottom of the trench gate 150, but also utilize the interval area between adjacent third buried layers 123 to lay out the current distribution between the source and the drain. Figure 1 and Figure 2The carriers flowing out of the conductive channels on both sides of the trench gate 150 are uniformly diffused to the entire drift region 110 through the individual regions surrounded by the first buried layer 121, the second buried layer 122 and the third buried layer 123, thereby presenting a lower on-resistance.

[0074] Figure 4 A schematic top view of the structure of a semiconductor device according to a second embodiment of the present disclosure is shown.

[0075] like Figure 4 As shown, the similarities between the semiconductor device of the second embodiment of the present disclosure and the first embodiment are not described in detail here, and reference may be made to Figures 1 to 3 The difference is that, in this embodiment, the trench gate 150 extends continuously along the Y-axis direction.

[0076] Figures 5 to 9 A three-dimensional structural schematic diagram showing a part of the stages in the method for manufacturing a semiconductor device according to the first embodiment of the present disclosure is shown.

[0077] See also Figure 5 An epitaxial layer 104 is formed on the substrate 103 using an epitaxial process, wherein the epitaxial layer 104 and the substrate 103 constitute a semiconductor layer 100 .

[0078] Furthermore, a high energy ion implantation process is used to simultaneously form a first buried layer 121, a second buried layer 122 and a third buried layer 123 in the epitaxial layer 104, such as Figure 6 The first buried layer 121 , the second buried layer 122 and the third buried layer 123 have a preset distance from the first surface of the semiconductor layer 100 .

[0079] The first buried layer 121, the second buried layer 122 and the third buried layer 123 are formed in the semiconductor layer 100 simultaneously by adopting the ion implantation process, thereby saving the number of masks, eliminating the need for additional alignment of the patterns of the first to third buried layers, reducing the process difficulty and saving costs.

[0080] Furthermore, a well region 130 is formed in the semiconductor layer 100. The well region 130 extends from the first surface of the semiconductor layer 100 toward the first buried layer 121 and is connected to the top of the first buried layer 121, the second buried layer 122 and the third buried layer 123, respectively. Figure 7 shown.

[0081] Furthermore, a doping region 140 and a body contact region 142 are formed in the well region 130, and the doping region 140 and the body contact region 142 extend from the first surface of the semiconductor layer 100 to the well region 130, as shown in FIG. Figure 8 shown.

[0082] Furthermore, a trench extending from the first surface of the semiconductor layer 100 to the first buried layer 121 is formed, and a trench gate 150 is formed in the trench. Fig. 9 The depth of the trench is less than the depth of the first buried layer 121 , the doped region 140 serves as the source region 141 , the undoped well region 130 serves as the body region 131 , and the undoped epitaxial layer 104 and the substrate 103 serve as the drift region 110 .

[0083] In this step, a plurality of trenches arranged at intervals are formed along the Y-axis direction, so that a plurality of trench gates 150 are arranged at intervals.

[0084] Furthermore, an interlayer dielectric layer 160 and a first conductive layer 171 are formed on the first surface of the semiconductor layer 100, and a second conductive layer 172 is formed on the second surface of the semiconductor layer 100, thereby forming Figures 1 to 3 The semiconductor device shown.

[0085] The manufacturing method of the semiconductor device of the second embodiment of the present disclosure is substantially similar to that of the semiconductor device of the first embodiment, and reference may be made to the relevant description of the first embodiment. The difference is that when forming the groove, a continuously extending groove needs to be formed along the Y-axis direction so that the trench gate 150 extends continuously.

[0086] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising a semiconductor layer and a trench gate, wherein the semiconductor layer has a first surface and a second surface opposite to each other, and the trench gate is located in a trench on the first surface of the semiconductor layer. The semiconductor layer comprises: A first buried layer, located at the bottom of the trench gate and connected to the trench gate; A body region connected to a sidewall of the trench gate; A source region connected to a sidewall of the trench gate, the source region extending from the first surface toward the body region and connected to the body region; as well as a drift region, at least a portion of which is located between the body region and the second surface and connected to the first buried layer and the body region, Wherein, the width of the trench gate is not less than the depth of the trench gate, and the width of the trench gate is greater than the width of the first buried layer.

2. The semiconductor device according to claim 1, wherein The source region and the drift region are of a first conductivity type, the first buried layer and the body region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

3. The semiconductor device according to claim 1, wherein The semiconductor layer further includes a second buried layer, which is separated from the trench gate and the first buried layer respectively, and the second buried layer has the same conductivity type as the first buried layer. The body region is located between the second buried layer and the first surface and is connected to the second buried layer, and the drift region is connected to the second buried layer.

4. The semiconductor device according to claim 3, wherein: The bottom of the first buried layer is flush with the bottom of the second buried layer.

5. The semiconductor device according to claim 3, wherein: The first buried layer and the second buried layer both extend along the length direction of the trench gate.

6. The semiconductor device according to claim 3, wherein: Along the width direction of the trench gate, the body region, the source region and the second buried layer are all located on two sides of the trench gate.

7. The semiconductor device according to any one of claims 3 to 6, wherein: The semiconductor layer also includes a third buried layer, which is located between the first buried layer and the second buried layer and connected to the first buried layer, the second buried layer and the body region. The conductivity type of the third buried layer is the same as that of the first buried layer.

8. The semiconductor device according to claim 7, wherein: Along the length direction of the trench gate, a plurality of the third buried layers are spaced apart.

9. The semiconductor device according to claim 8, wherein: Along the length direction of the trench gate, the spacing distance between adjacent third buried layers is greater than the length of the third buried layer.

10. The semiconductor device according to claim 7, wherein: The third buried layer is flush with the bottom of the first buried layer.

11. The semiconductor device according to claim 7, wherein: Along the length direction of the trench gate, a plurality of the trench gates are arranged at intervals. Along the length direction of the trench gates, the body region and the source region are also located between adjacent trench gates.

12. The semiconductor device according to claim 11, wherein Along the length direction of the trench gates, the spacing region between adjacent trench gates corresponds to a portion of the third buried layer.

13. The semiconductor device according to claim 7, wherein: The trench gate extends continuously along the length direction of the trench gate.

14. A method for manufacturing a semiconductor device, comprising: forming a first buried layer in a semiconductor layer, the semiconductor layer having a first surface and a second surface opposite to each other, the first buried layer being at a preset distance from the first surface; forming a well region in the semiconductor layer, wherein the well region extends from the first surface toward the first buried layer and is connected to the first buried layer; forming a doped region in the well region, wherein the doped region extends from the first surface into the well region; as well as forming a trench extending from the first surface to the first buried layer, and forming a trench gate in the trench, Wherein, the width of the trench gate is not less than the depth of the trench gate, and the width of the trench gate is greater than the width of the first buried layer.

15. The manufacturing method according to claim 14, further comprising forming a second buried layer in the semiconductor layer, in, The second buried layer is separated from the trench gate and the first buried layer respectively, and the well region is located between the second buried layer and the first surface and connected to the second buried layer.

16. The manufacturing method according to claim 15, further comprising forming a third buried layer in the semiconductor layer, in, The third buried layer is located between the first buried layer and the second buried layer, and is connected to the first buried layer, the second buried layer and the well region.

17. The manufacturing method according to claim 16, wherein: The first buried layer, the second buried layer and the third buried layer are formed simultaneously by an ion implantation process.

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