Chip structure and packaging structure thereof

Abstract

The application relates to a chip structure and a packaging structure thereof. The chip structure comprises a substrate, a first semiconductor layer, an active layer and a second semiconductor layer arranged on the substrate in sequence, the number of the second semiconductor layer and the active layer is at least three groups, the first semiconductor layer, the active layer and the second semiconductor layer form three groups of protruding structures, corresponding recessed structures are arranged between adjacent protruding structures, the surface of one group of the protruding structures is provided with a third insulating layer, and the surface of the third insulating layer is connected with a heat diffusion layer; the chip structure and the packaging structure thereof are matched with a high-efficiency heat-conducting substrate, heat can be effectively released, system thermal resistance can be reduced, and device stability can be improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor structures, and particularly relates to a chip structure and a packaging structure thereof. BACKGROUND

[0002] The stability of the device is closely related to the LED chip structure and the packaging form. Generally, the LED packaging substrate usually adopts an aluminum substrate or a copper substrate, which is convenient for processing, but needs to be insulated and heat-conductive to achieve heat dissipation. However, this packaging method has a significant problem, that is, the insulating and heat-conductive material will reduce the thermal conductivity, thereby limiting the heat dissipation efficiency of the device. Especially in the case of high-power LEDs or high-frequency PCBs that require strong heat dissipation performance, the traditional packaging substrate obviously cannot meet the requirements. Therefore, we urgently need a new type of packaging substrate that can realize thermal-electric separation and has high-efficiency heat conduction performance.

[0003] Once the packaging form is determined, the stability of the device mainly depends on the influence of the structure of the LED chip on the stability of heat. Reducing the thermal resistance of the chip structure can significantly improve the thermal stability of the light-emitting device. Therefore, when designing the LED chip, special attention should be paid to how to reduce the thermal resistance to ensure that the device can maintain stability under long-time work and high-temperature environment. This is crucial for the further development and application of LED technology. SUMMARY

[0004] The purpose of the present application is to provide a chip structure and a packaging structure thereof that can effectively release heat, reduce system thermal resistance, and improve device stability to solve the above problems.

[0005] The application achieves the above-mentioned purpose through the following technical solutions:

[0006] The first aspect of the present application provides a chip structure, which comprises a substrate, a first semiconductor layer, an active layer and a second semiconductor layer are sequentially arranged on the substrate, the number of the second semiconductor layer and the active layer is at least three groups, the first semiconductor layer, the active layer and the second semiconductor layer form three groups of protruding structures, corresponding recessed structures are arranged between adjacent protruding structures, the surface of one group of the protruding structures is provided with a third insulating layer, and the surface of the third insulating layer is connected with a heat diffusion layer.

[0007] As a further optimization scheme of the present application, the surface of the second semiconductor layer is ohmically contacted with a first conductive layer, the surface of the first conductive layer is connected with a reflective layer, the surface of the reflective layer is connected with a second conductive layer, the second conductive layer is connected with a first pad, and the first pad is located at the top of any one of the other two groups of the protruding structures.

[0008] As a further optimization scheme of the present application, a part of the surface of the second semiconductor layer is connected with a part of the first conductive layer, and a first insulating layer is connected with the part of the first conductive layer, and the first insulating layer covers the recess structure.

[0009] As a further optimization scheme of the present application, a part of the surface of the first insulating layer is connected with a second insulating layer, and a third conductive layer is arranged on the surface of the second insulating layer, and the third conductive layer is in communication with the first semiconductor layer, and the top positions of a group of the protruding structures in the protruding structure are provided with a second pad, and the second pad is in communication with the third conductive layer, and a third insulating layer covers the surface of the third conductive layer.

[0010] As a further optimization scheme of the present application, the distance between the heat diffusion layer and the first pad or / and the second pad is greater than 10 um.

[0011] The second aspect of the present application provides a packaging structure of a chip structure, which comprises a positive electrode, a negative electrode, a fourth insulating layer, a heat dissipation pad and a metal substrate base material, the positive electrode is connected with the first pad, the negative electrode is connected with the second pad, one end surface of the heat dissipation pad covers the surface of the heat diffusion layer, the other end surface of the heat dissipation pad is connected with the metal substrate base material, the fourth insulating layer is arranged between the metal substrate base material and the positive electrode and the negative electrode, and the fourth insulating layer is also arranged between the positive electrode and the heat dissipation pad or / and between the negative electrode and the heat dissipation pad.

[0012] The present application has the beneficial effects that: the heat diffusion layer arranged in the present application can effectively reduce the risk of local thermal expansion rupture caused by heat accumulation; the structure used by the heat diffusion layer can be consistent with the pad structure, so that no additional process and cost are needed; the introduction of the heat diffusion layer can reduce the force borne by the unit area of the chip and improve the stability of the light emitting device; the line part and the heat layer part of the thermoelectric separation substrate are on different line layers, and the heat layer part directly contacts the heat dissipation part of the lamp bead, so that the best heat dissipation (zero thermal resistance) effect can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a structural schematic diagram of a chip structure of the present application;

[0014] Figure 2 is a structural schematic diagram of a packaging structure of a chip structure of the present application.

[0015] In the figure: 1, substrate; 2, first semiconductor layer; 3, second semiconductor layer; 4, active layer; 5, first conductive layer; 6, reflective layer; 7, second conductive layer; 8, first pad; 9, first insulating layer; 10, second insulating layer; 11, third conductive layer; 12, second pad; 13, third insulating layer; 14, heat diffusion layer; 15, positive electrode; 16, negative electrode; 17, fourth insulating layer; 18, heat dissipation pad; 19, metal substrate base material. DETAILED DESCRIPTION

[0016] The following detailed description of the application is made with reference to the accompanying drawings, it is necessary to point out here that the following detailed description is only used to further illustrate the application, and cannot be understood as limiting the scope of protection of the application, and those skilled in the art can make some non-essential improvements and adjustments to the application according to the above application content.

[0017] Reference Figure 1 The chip structure shown in the structure is mainly an LED chip structure, which mainly includes:

[0018] Substrate 1, first semiconductor layer 2, second semiconductor layer 3, active layer 4 (between the first and second semiconductors);

[0019] The first semiconductor layer 2, the active layer 4, and the second semiconductor layer 3 are sequentially grown on the substrate 1;

[0020] The first conductive layer 5 forms ohmic contact with the second semiconductor layer 3, the reflective layer 6 (which can include a multi-layer structure) forms electrical connection with the first conductive layer 5, the second conductive layer 7 (which can include a multi-layer metal structure) forms electrical connection with the reflective layer 6, and the first pad 8 (which can include a multi-layer metal structure) forms electrical connection with the second conductive layer 7; The first conductive layer 5, the reflective layer 6, the second conductive layer 7, and the first pad 8 together form a first electrical connection layer;

[0021] The recess penetrates the second semiconductor layer 3 and the active layer 4 and extends into the first semiconductor layer 2;

[0022] The first insulating layer 9 covers part of the surface of the second semiconductor layer 3 and part of the surface of the first conductive layer 5, the second insulating layer 10 covers the side wall of the recess, part of the surface of the first insulating layer 9, and one side of the first electrical connection layer;

[0023] The third conductive layer 11 (which can include a multi-layer structure) is mostly in contact with the surface of the second insulating layer 10 and forms electrical connection with the first semiconductor layer 2, and the third conductive layer 11 and the second pad 12 together form a second electrical connection layer;

[0024] The third insulating layer 13 covers most of the surface of the third conductive layer 11 and isolates the first electrical connection layer and the second electrical connection layer from direct conduction.

[0025] The heat diffusion layer 14 covers the surface of the third insulating layer 13 and is not electrically connected with the semiconductor layer or other conductive layer; the heat diffusion layer 14 is a series of regular high-thermal-conductivity material distributed between the first pad 8 and the second pad 12, and the spacing between the heat diffusion layer 14 and the pad is greater than 10 um.

[0026] In this embodiment, a structure as shown in Figure 2 is also provided, and the structure of the chip structure includes a positive electrode 15, a negative electrode 16, a fourth insulating layer 17, a heat dissipation pad 18 (high-thermal-conductivity metal material), and a metal substrate base material 19 (copper substrate, etc.); the heat dissipation pad 18 is directly connected with the metal substrate base material 19, and the materials of the two can be the same or different, but are both high-thermal-conductivity metal materials.

[0027] The positive electrode 15 of the package is connected with the first electrically connecting layer of the chip; the negative electrode 16 is connected with the second electrically connecting layer of the chip; and the positive electrode and the negative electrode of the package are isolated from the metal substrate base material 19 by the fourth insulating layer 17.

[0028] It should be noted that, in use, the chip structure and the packaging structure thereof can effectively reduce the risk of local thermal expansion rupture caused by heat accumulation by the heat diffusion layer 14; the structure of the heat diffusion layer 14 can be consistent with the pad structure, so that no additional process and cost are needed; the introduction of the heat diffusion layer 14 can reduce the force borne by the unit area of the chip and improve the stability of the light-emitting device; the thermoelectric separation substrate, i.e., the substrate combining the heat dissipation pad 18 and the metal substrate base material 19, has the circuit part and the heat layer part on different circuit layers, and the heat layer part directly contacts the heat dissipation part of the lamp bead, so that the best heat dissipation (zero thermal resistance) effect can be achieved.

[0029] The advantages of the present application are as follows:

[0030] The heat diffusion layer adopts a material with high thermal conductivity (such as a metal material, etc., and the thermal conductivity of the metal is much greater than that of air), so that a large amount of heat generated in the eutectic process can be quickly diffused to the adjacent area, effectively relieving the problem of excessively high local temperature.

[0031] The introduction of the heat diffusion layer increases the force-bearing area of the chip and the package, thereby reducing the force borne by the unit area of the chip and further improving the stability of the light-emitting device. The number of the heat diffusion layers is greater than or equal to 1, and the spacing between the heat diffusion layer and the pad is greater than or equal to 10 um.

[0032] The present application adopts a high-efficiency heat-conducting substrate with thermoelectric separation, and the substrate contains a heat dissipation pad which can be directly connected with the metal substrate for heat dissipation.

[0033] Further, in order to improve the heat dissipation efficiency of the heat diffusion layer 14 and the heat dissipation pad 18 and the heat dissipation pad 18 and the metal substrate base material, the bottom of the heat diffusion layer 14 and the top and bottom of the heat dissipation pad 18 can also be provided in the form of a multi-layer gap plate. The bottom of the heat diffusion layer 14, i.e. the connecting part of the heat diffusion layer 14 and the heat dissipation pad 18, is the top of the heat dissipation pad 18. Any straight plate of the bottom of the heat diffusion layer 14 is contacted by two wave-shaped plates on the top of the heat dissipation pad 18. The two wave-shaped plates are respectively arranged on both sides of the straight plate of the bottom of the heat diffusion layer 14, and the end of the wave-shaped plate is inserted into the two straight plates of the bottom of the heat diffusion layer 14. The heat layer of the heat diffusion layer 14 can be directly contacted by the wave-shaped plate, and the side surface of the wave-shaped plate is also contacted with the side surface of the straight plate. The wave-shaped plate improves the corresponding heat dissipation area and reduces the heat dissipation error as much as possible. The wave-shaped plates between the two straight plates can also be in two groups. One is that the two wave-shaped plates are directly contacted and matched to improve the heat exchange efficiency, and the other is that a certain gap is left between the two wave-shaped plates, and a forced air cooling component can be introduced to improve the heat dissipation efficiency.

[0034] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it cannot be understood as limiting the scope of the patent of the present application. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which belong to the protection scope of the present application.

Claims

1. A chip structure, characterized in that, The chip structure includes a substrate (1), on which a first semiconductor layer (2), an active layer (4) and a second semiconductor layer (3) are sequentially disposed. The number of the second semiconductor layer (3) and the active layer (4) is at least three. The first semiconductor layer (2), the active layer (4) and the second semiconductor layer (3) form three sets of protrusion structures. A corresponding recess structure is disposed between adjacent protrusion structures. A third insulating layer (13) is disposed on the surface of one set of protrusion structures. A heat diffusion layer (14) is connected to the surface of the third insulating layer (13). The surface of the second semiconductor layer (3) is ohmically contacted with a first conductive layer (5), the surface of the first conductive layer (5) is connected to a reflective layer (6), the surface of the reflective layer (6) is connected to a second conductive layer (7), the second conductive layer (7) is connected to a first pad (8), and the first pad (8) is the top position of any one of the other two sets of protrusion structures; A portion of the surface of the second semiconductor layer (3) is connected to a portion of the first conductive layer (5) by a first insulating layer (9), which covers the recessed structure. A second insulating layer (10) is connected to a portion of the surface of the first insulating layer (9). A third conductive layer (11) is also provided on the surface of the second insulating layer (10). The third conductive layer (11) is connected to the first semiconductor layer (2). A second pad (12) is provided at the top of a set of protrusions in the protrusion structure. The second pad (12) is connected to the third conductive layer (11). The third insulating layer (13) covers the surface of the third conductive layer (11). The heat diffusion layer (14) is located between the second pad (12) and the first pad (8).

2. The chip structure according to claim 1, characterized in that: The distance between the heat diffusion layer (14) and the first pad (8) or / and the second pad (12) is greater than 10 μm.

3. A chip packaging structure, characterized in that, The chip structure described in any of claims 1-2 is used for packaging. The structure includes a positive electrode (15), a negative electrode (16), a fourth insulating layer (17), a heat dissipation pad (18), and a metal substrate (19). The positive electrode (15) is connected to the first pad (8), and the negative electrode (16) is connected to the second pad (12). One end face of the heat dissipation pad (18) covers the surface of the heat diffusion layer (14), and the other end face of the heat dissipation pad (18) is connected to the metal substrate (19). The fourth insulating layer (17) is disposed between the metal substrate (19) and the positive electrode (15) and the negative electrode (16), and the fourth insulating layer (17) is also disposed between the positive electrode (15) and the heat dissipation pad (18) and / or between the negative electrode (16) and the heat dissipation pad (18).

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