Fixed-Point and Floating-Point Fusion Multi-Precision Addition, Subtraction, and Multiplication Operation Methods

Abstract

The present invention discloses a method for multi-precision addition, subtraction and multiplication operations with fixed-point and floating-point fusion. The method for multi-precision addition and subtraction operations with fixed-point and floating-point fusion includes: a control logic module determines an operation mode of an arithmetic unit according to input operands, and the operation mode includes: a floating-point operation mode and a fixed-point operation mode, and an operation result is output according to the operation mode. This method supports both fixed-point and floating-point operations with a set of hardware resources. Compared with traditional independent fixed-point and floating-point arithmetic components, it uses fewer computing resources and can obtain a smaller chip area.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and more particularly, to a method for multi-precision addition and subtraction operations and a method for multiplication operations with fixed-point and floating-point fusion. Background Art

[0002] Floating-point arithmetic units and fixed-point / integer arithmetic units are necessary computing units in various chips. In high-performance and high-computing-power chips, the number of them is very large and the area occupancy ratio is very high. In traditional chip hardware design, floating-point and fixed-point / integer arithmetic units are usually designed and implemented separately, and they respectively occupy private computing resources independently, resulting in the inability to share core computing resources and too large chip area. Summary of the Invention

[0003] Aiming at the deficiencies of the prior art, the present invention provides a method for multi-precision addition and subtraction operations and a method for multiplication operations with fixed-point and floating-point fusion.

[0004] According to one aspect of the present invention, a method for multi-precision addition and subtraction operations with fixed-point and floating-point fusion is provided, including:

[0005] The control logic module determines the operation mode of the arithmetic unit according to the input operands, and the operation mode includes: floating-point operation mode and fixed-point operation mode;

[0006] In the case where the operation mode is the floating-point operation mode, two input operands are received and sent to the unpacking module to decode the sign, exponent, and mantissa information of the two operands, obtain the sign, exponent, and mantissa of each operand, and restore the mantissa including the implied bit to a significant number;

[0007] The signs of the two operands obtained by the unpacking module enter the control logic module, and the control logic module selectively takes the complement of the significant numbers of the two operands according to the signs of the operands;

[0008] The exponents of the two operands enter the subtractor for subtraction operation to obtain the exponent difference of the operands, and according to the exponent difference of the two operands, the significant numbers of the two operands are aligned to obtain the aligned significant numbers;

[0009] The control logic module sends the aligned significant numbers to the fixed-point adder through the input mux module to obtain the floating-point significant number addition result and sends it to the control logic module;

[0010] The floating-point significant number addition result of the two operands enters the normalization module to normalize the floating-point significant number addition result, the first shift value of the normalization shift is sent to the control logic module, and the normalized result enters the rounding and complement-taking module to obtain the rounded significant number;

[0011] Normalize the rounded significand again, determine the mantissa of the output result floating-point number, and send the second shift value of the normalization shift to the control logic module;

[0012] The control logic module adds the first shift value, the second shift value, and the larger exponent among the input operands to obtain the exponent of the output result floating-point number;

[0013] The control logic module obtains the sign of the output result floating-point number according to the positive or negative of the significand sum result;

[0014] Pack the sign of the output result floating-point number, the exponent of the output result floating-point number, and the mantissa of the output result floating-point number into a standard floating-point identifier format, and output the floating-point operation result.

[0015] Optionally, it further includes: when the sign of the output result floating-point number is negative, perform a two's complement operation on the significand of the output result.

[0016] Optionally, it further includes:

[0017] When the operation mode is the fixed-point operation mode, the control logic module controls the input mux module to directly input the operand into the fixed-point adder;

[0018] The fixed-point adder adds the two input operands to obtain the fixed-point calculation addition result;

[0019] The control logic module controls the output mux module to directly output the fixed-point calculation addition result to complete the fixed-point operation.

[0020] According to another aspect of the present invention, there is provided a fixed-point floating-point fused multi-precision addition and subtraction arithmetic unit for implementing any one of the above-mentioned fixed-point floating-point fused multi-precision addition and subtraction arithmetic methods.

[0021] According to another aspect of the present invention, there is provided a fixed-point floating-point fused multi-precision multiplication arithmetic method, including:

[0022] The control logic module determines the operation mode of the arithmetic unit according to the input operand, and the operation mode includes: floating-point operation mode and fixed-point operation mode;

[0023] When the operation mode is the floating-point operation mode, the input operand enters the unpacking module, and the unpacking module decodes the sign, exponent, and mantissa information of the operand to obtain the sign, exponent, and mantissa of each operand;

[0024] The mantissas of the two operands obtained by the unpacking module pass through the restore significand logic module to restore the hidden bits to obtain the complete significand;

[0025] The significands of the two operands enter the fixed-point multiplier through the input mux module for multiplication operation;

[0026] The exponents of the two input operands enter the fixed-point adder to calculate the output result exponent;

[0027] The control logic module determines the output result sign according to the signs of the two input operands;

[0028] Normalize and round the output mantissa of the fixed-point multiplier to determine the output result mantissa, and synchronously adjust the output result exponent;

[0029] Pack the output result sign, output result exponent, and output result mantissa into a floating-point format to obtain the output floating-point result.

[0030] Optionally, the control logic determines the output result sign according to the signs of the two input operands, including:

[0031] The control logic module determines the output result sign according to the signs of the two input operands and the principle that the same sign is positive and the different sign is negative.

[0032] Optionally, synchronously adjusting the output result exponent includes:

[0033] Adjust the output result exponent according to the normalized shift value and whether the rounding generates a carry, where the carry is the output result exponent minus the shift value plus the carry generated by the rounding.

[0034] Optionally, it further includes:

[0035] When the operation mode is the fixed-point calculation mode, the control logic module controls the input mux module to directly send the two input operands to the fixed-point multiplier;

[0036] The fixed-point multiplier performs a multiplication operation on the input operands to obtain a fixed-point calculation multiplication result;

[0037] The control logic module controls the output MUX module to directly output the fixed-point calculation result to complete the fixed-point operation.

[0038] According to another aspect of the present invention, there is provided a fixed-point and floating-point fused multi-precision multiplier for implementing any one of the above-mentioned fixed-point and floating-point fused multi-precision multiplication operation methods.

[0039] Thus, the present invention provides a set of hardware that supports both fixed-point and floating-point operations. Compared with traditional fixed-point and floating-point independent arithmetic units, it uses fewer computing resources and can obtain a smaller chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] By referring to the following drawings, the exemplary embodiments of the present invention can be more fully understood:

[0041] Figure 1 It is a schematic flowchart of the fixed-point and floating-point fusion multi-precision addition and subtraction operation method provided in the first aspect of the embodiment of the present invention;

[0042] Figure 2 It is a schematic structural diagram of the fixed-point and floating-point fusion multi-precision addition and subtraction arithmetic unit provided in the second aspect of the embodiment of the present invention;

[0043] Figure 3 It is a schematic flowchart of the fixed-point and floating-point fusion multi-precision multiplication operation method provided in the third aspect of the embodiment of the present invention;

[0044] Figure 4 It is a schematic structural diagram of the fixed-point and floating-point fusion multi-precision multiplication arithmetic unit provided in the fourth aspect of the embodiment of the present invention. Detailed implementation manners

[0045] Next, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments of the present invention. It should be understood that the present invention is not limited by the exemplary embodiments described herein.

[0046] It should be noted that: Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and values set forth in these embodiments do not limit the scope of the present invention.

[0047] Those skilled in the art can understand that terms such as "first", "second", etc. in the embodiments of the present invention are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate an inevitable logical order between them.

[0048] It should also be understood that in the embodiments of the present invention, "a plurality of" may mean two or more, and "at least one" may mean one, two or more.

[0049] It should also be understood that for any component, data or structure mentioned in the embodiments of the present invention, unless otherwise clearly defined or given a contrary indication in the context, it can generally be understood as one or more.

[0050] In addition, the term "and / or" in the present invention is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present invention generally represents an "or" relationship between the associated objects before and after.

[0051] It should also be understood that the present invention emphasizes the differences between the various embodiments. The same or similar parts can be referred to each other. For the sake of brevity, they will not be described one by one.

[0052] Meanwhile, it should be understood that, for the convenience of description, the sizes of the various parts shown in the drawings are not drawn in actual proportional relationship.

[0053] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way a limitation on the present invention, its application, or its use.

[0054] Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and devices should be regarded as part of the specification.

[0055] It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0056] Embodiments of the present invention can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate together with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing technology environments including any of the above systems, and so on.

[0057] Terminal devices, computer systems, servers, and other electronic devices can be described in the general context of computer system-executable instructions (such as program modules) executed by a computer system. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. The computer system / server can be implemented in a distributed cloud computing environment where tasks are executed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0058] Figure 1 It is a schematic flowchart of a fixed-point floating-point fusion multi-precision addition and subtraction operation method provided by the first aspect of the embodiments of the present invention. This embodiment can be applied to an electronic device, such as Figure 1 As shown, the fixed-point floating-point fusion multi-precision addition and subtraction operation method 100 includes the following steps:

[0059] Step 101, the control logic module determines the operation mode of the arithmetic unit according to the input operands, and the operation modes include: floating-point operation mode and fixed-point operation mode;

[0060] Step 102, in the case where the operation mode is the floating-point operation mode, receive two input operands, and send them to the unpacking module to decode the sign, exponent, and mantissa information of the two operands, obtain the sign, exponent, and mantissa of each operand, and restore the mantissa including the implied bit to a significant number;

[0061] Step 103, the signs of the two operands obtained by the unpacking module enter the control logic module, and the control logic module selectively takes the complement of the significant numbers of the two operands according to the signs of the operands;

[0062] Step 104, the exponents of the two operands enter the subtractor for subtraction operation to obtain the exponent difference of the operands, and according to the exponent difference of the two operands, align the significant numbers of the two operands to obtain the aligned significant numbers;

[0063] Step 105, the control logic module sends the aligned significant numbers to the fixed-point adder through the input mux module, obtains the floating-point significant number addition result and sends it to the control logic module;

[0064] Step 106, the floating-point significant number addition result of the two operands enters the normalization module to normalize the floating-point significant number addition result, the first shift value of the normalization shift is sent to the control logic module, and the normalized result enters the rounding and complement module to obtain the rounded significant number;

[0065] Step 107, normalize the rounded significant number again to determine the mantissa of the output result floating-point number, and send the second shift value of the normalization shift to the control logic module;

[0066] Step 108, the control logic module adds the first shift value, the second shift value, and the larger exponent among the input operands to obtain the exponent of the output result floating-point number;

[0067] Step 109, the control logic module obtains the sign of the output result floating-point number according to the positive or negative of the significant number addition result;

[0068] Step 110, pack the sign of the output result floating-point number, the exponent of the output result floating-point number, and the mantissa of the output result floating-point number into a standard floating-point identification format, and output the floating-point operation result.

[0069] Optionally, it further includes: in the case where the sign of the output result floating-point number is negative, perform a complement operation on the significant number of the output result.

[0070] Optionally, it further includes:

[0071] In the case where the operation mode is the fixed-point operation mode, the control logic module controls the input mux module to directly input the operands into the fixed-point adder;

[0072] The fixed-point adder adds the two input operands to obtain the fixed-point calculation addition result;

[0073] The control logic module controls the output mux module to directly output the fixed-point calculation addition result, completing the fixed-point operation.

[0074] The structure of the fixed-point and floating-point fused adder-subtractor proposed in the second aspect of the present invention is as Figure 2 shown, and is used to implement the adder-subtraction operation method. The adder-subtractor has 2 input signals and 1 output signal. The input signals x and y respectively receive two operands, and the types of the operands can be in floating-point or fixed-point format. The input signal "fixed-point and floating-point selection signal" is used to control the operation mode of the arithmetic unit to be fixed-point operation or floating-point operation. The output signal s outputs the operation result.

[0075] The operation principle process of the fixed-point and floating-point fused adder-subtractor proposed by the present invention is as follows:

[0076] (1) The control logic receives the input signal of the "fixed-point and floating-point selection signal" to determine the current operation mode of the arithmetic unit. When the operation mode is the floating-point operation mode, the working process is as follows:

[0077] ① The input operands x and y first enter the unpacking module. The unpacking module decodes the sign, exponent, and mantissa information of the floating-point operands to obtain the sign, exponent, and mantissa of each operand. The mantissa including the implied bit is restored to the significand.

[0078] ② The operand sign signals obtained by unpacking enter the control logic, and the control logic module selectively takes the complement of the significand of the operand according to the sign of the operand.

[0079] ③ The exponents of the two operands are subtracted to obtain the exponent difference of the operands. According to the exponent difference of the two floating-point operands, the significands of the two operands are aligned to obtain the aligned significands.

[0080] ④ The control logic module, according to the operation mode being the floating-point mode, sends the aligned significands into the fixed-point adder to obtain the floating-point significand sum result.

[0081] ⑤ The floating-point significand sum result of the floating-point operand enters the normalization module to normalize the sum. The normalization shift value is sent to the control logic module, and the normalized result enters the rounding and complement-taking module. The rounded significand is obtained.

[0082] ⑥Since the significand after normalization may become denormalized due to rounding, the rounded significand needs to be normalized again.

[0083] ⑦The shift values of the two normalizations are sent to the control logic module, and the control logic module adds the shift value and the larger exponent in the input floating-point operand to obtain the exponent of the output result floating-point number;

[0084] ⑧The control logic module obtains the sign of the output result floating-point number according to the positive or negative of the sum result of the significands. If the calculation result is negative, the two's complement operation is performed on the significand of the output result;

[0085] ⑨The sign, exponent, and significand of the floating-point calculation result are packed into the standard floating-point representation format to complete the floating-point operation.

[0086] When the operation mode is fixed-point calculation, the working process is as follows:

[0087] ①The control logic unit controls the input mux module to directly input the fixed-point operand into the fixed-point adder according to the operation mode.

[0088] ②The fixed-point adder performs an addition operation on the input data to obtain the fixed-point calculation addition result.

[0089] ③The control logic unit controls the output MUX module to directly output the fixed-point calculation result to complete the fixed-point operation.

[0090] Figure 3 It is a schematic flowchart of a fixed-point and floating-point fusion multi-precision multiplication operation method provided in the third aspect of the embodiments of the present invention. This embodiment can be applied to electronic devices, such as Figure 3 As shown, the fixed-point and floating-point fusion multi-precision multiplication operation method 300 includes the following steps:

[0091] Step 301, the control logic module determines the operation mode of the arithmetic unit according to the input operand, and the operation mode includes: floating-point operation mode and fixed-point operation mode;

[0092] Step 302, when the operation mode is the floating-point operation mode, the input operand enters the unpacking module, and the unpacking module decodes the sign, exponent, and mantissa information of the operand to obtain the sign, exponent, and mantissa of each operand;

[0093] Step 303, the mantissas of the two operands obtained by the unpacking module pass through the significand restoration logic module to restore the hidden bits to obtain the complete significand;

[0094] Step 304, the significands of the two operands enter the fixed-point multiplier through the input mux module to perform a multiplication operation;

[0095] Step 305: The exponents of the two input operands enter a fixed-point adder to calculate the output result exponent.

[0096] Step 306: The control logic module determines the output result sign according to the signs of the two input operands.

[0097] Step 307: Normalize and round the output mantissa of the fixed-point multiplier to determine the output result mantissa, and synchronously adjust the output result exponent.

[0098] Step 308: Pack the output result sign, output result exponent, and output result mantissa into a floating-point format to obtain the output floating-point result.

[0099] Optionally, the control logic determines the output result sign according to the signs of the two input operands, including:

[0100] The control logic module determines the output result sign according to the signs of the two input operands and the principle that the same sign is positive and the different sign is negative.

[0101] Optionally, synchronously adjusting the output result exponent includes:

[0102] Adjust the output result exponent according to the normalized shift value and whether rounding generates a carry, where the carry is the output result exponent minus the shift value plus the carry generated by rounding.

[0103] Optionally, it further includes:

[0104] When the operation mode is the fixed-point calculation mode, the control logic module controls the input mux module to directly send the two input operands to the fixed-point multiplier;

[0105] The fixed-point multiplier multiplies the input operands to obtain the fixed-point calculation multiplication result;

[0106] The control logic module controls the output MUX module to directly output the fixed-point calculation result to complete the fixed-point operation.

[0107] The structure of the fixed-point and floating-point fused multiplier proposed in the fourth aspect of the present invention is as Figure 4 shown, and is used to implement the multiplication operation method. The multiplier has 2 input signals and 1 output signal. The input signals x and y respectively receive two operands, and the types of the operands can be floating-point or fixed-point formats. The input signal "fixed-point and floating-point selection signal" is used to control the operation mode of the arithmetic unit to be fixed-point operation or floating-point operation. The output signal Z is the output of the operation result.

[0108] The operation principle process of the fixed-point and floating-point fused multiplier proposed by the present invention is as follows:

[0109] (1) The control logic receives the "fixed-point floating-point selection signal" input signal to determine the current operation mode of the arithmetic unit. When the operation mode is the floating-point operation mode, the working process is as follows:

[0110] ① The input operands x and y first enter the unpacking module. The unpacking module decodes the sign, exponent, and mantissa information of the floating-point operands to obtain the sign, exponent, and mantissa of each operand. The mantissa containing the implied bit is restored to a significant number.

[0111] ② The mantissas of the two operands obtained by unpacking pass through the significant number restoration logic to restore the hidden bits and obtain the complete significant numbers;

[0112] ③ The significant numbers of the two operands enter the fixed-point multiplication module for multiplication operation;

[0113] ④ The two input operands enter the fixed-point adder to calculate the exponent operation result;

[0114] ⑤ The control logic determines the sign of the output result according to the signs of the two input operands, "the same sign is positive, and the different sign is negative";

[0115] ⑥ According to the operation mode, the output mantissa of the fixed-point multiplier is normalized and rounded, and the calculation result is directly used as the mantissa of the output result. And the output exponent is adjusted synchronously, that is, adjusted according to the shift value of normalization and whether rounding generates a carry, that is, the exponent is subtracted by the shift value and added with the carry generated by rounding. (If a carry is generated, add it; if no carry is generated, do not add it.);

[0116] ⑦ Pack the calculated sign, exponent, and mantissa into the floating-point format to obtain the output floating-point result.

[0117] When the operation mode is fixed-point calculation, the working process is as follows:

[0118] ① The logic controller controls the input mux to directly enter the fixed-point operand into the fixed-point multiplier according to the operation mode.

[0119] ② The fixed-point multiplier multiplies the input data to obtain the fixed-point calculation multiplication result.

[0120] ③ The logic controller controls the output MUX to directly output the fixed-point calculation result to complete the fixed-point operation.

[0121] Thus, in the present invention, a set of hardware supports both fixed-point and floating-point operations. Compared with the traditional fixed-point and floating-point independent arithmetic units, less computing resources are used, and a smaller chip area can be obtained.

[0122] The basic principles of the present invention have been described in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present invention are merely examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present invention. Additionally, the specific details disclosed above are only for illustrative and easy-to-understand purposes, not limitations. The above details do not limit the present invention to necessarily implementing with the above specific details.

[0123] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the corresponding descriptions in the method embodiments.

[0124] The block diagrams of the devices, systems, equipment, and systems involved in the present invention are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, systems, equipment, and systems can be connected, arranged, and configured in any way. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The word "or" and "and" used here refer to the word "and / or", and can be used interchangeably with each other, unless the context clearly indicates otherwise. The word "such as" used here refers to the phrase "such as but not limited to", and can be used interchangeably with each other.

[0125] The methods and systems of the present invention can be implemented in many ways. For example, the methods and systems of the present invention can be implemented through software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of the steps for the methods is only for illustration. The steps of the methods of the present invention are not limited to the specific order described above, unless otherwise specifically stated. In addition, in some embodiments, the present invention can also be implemented as a program recorded in a recording medium, and these programs include machine-readable instructions for implementing the methods according to the present invention. Therefore, the present invention also covers the recording medium storing the programs for executing the methods according to the present invention.

[0126] It should also be noted that in the systems, devices and methods of the present invention, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations shall be regarded as equivalent solutions of the present invention. The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present invention. Therefore, the present invention is not intended to be limited to the aspects shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

[0127] The above description has been given for purposes of illustration and description. In addition, this description is not intended to limit the embodiments of the present invention to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub - combinations thereof.

Claims

1. A multi-precision addition and subtraction operation method for fixed-point and floating-point fusion, which realizes a set of hardware to support both fixed-point and floating-point operations, and is characterized in that It includes: The control logic module determines the operation mode of the arithmetic unit according to the input operands. The operation modes include: floating-point operation mode and fixed-point operation mode; When the operation mode is the floating-point operation mode, two input operands are received and sent to the unpacking module to decode the sign, exponent, and mantissa information of the two operands, obtaining the sign, exponent, and mantissa of each operand, and restoring the mantissa including the implied bit to a significand; The signs of the two operands obtained by the unpacking module enter the control logic module, and the control logic module selectively takes the complement of the significands of the two operands according to the signs of the operands; The exponents of the two operands enter a subtractor to perform a subtraction operation to obtain the exponent difference of the operands, and according to the exponent difference of the two operands, align the significands of the two operands to obtain the aligned significands; The control logic module sends the aligned significands to the fixed-point adder through the input mux module to obtain the floating-point significand sum result and sends it to the control logic module; The floating-point significand sum result of the two operands enters the normalization module to normalize the floating-point significand sum result. The first shift value of the normalization shift is sent to the control logic module, and the normalized result enters the rounding and complement module to obtain the rounded significand; The rounded significand is normalized again to determine the mantissa of the output result floating-point number, and the second shift value of the normalization shift is sent to the control logic module; The control logic module adds the first shift value, the second shift value, and the larger exponent among the input operands to obtain the exponent of the output result floating-point number; The control logic module obtains the sign of the output result floating-point number according to the positive or negative of the significand sum result; Pack the sign of the output result floating-point number, the exponent of the output result floating-point number, and the mantissa of the output result floating-point number into a standard floating-point identifier format and output the floating-point operation result.

2. The method according to claim 1, wherein It also includes: When the sign of the output result floating-point number is negative, perform a complement operation on the output result significand.

3. The method according to claim 1, characterized in that, It also includes: When the operation mode is the fixed-point operation mode, the control logic module controls the input mux module to directly send the operand into the fixed-point adder; The fixed-point adder adds the two input operands to obtain the fixed-point calculation addition result; The control logic module controls the output mux module to directly output the fixed-point calculation addition result to complete the fixed-point operation.

4. A fixed-point and floating-point fused multi-precision addition and subtraction arithmetic unit, characterized in that, It is used to implement the fixed-point and floating-point fusion multi-precision addition and subtraction operation method described in any one of the above claims 1-3.

5. A multi-precision multiplication operation method for fixed-point and floating-point fusion, which implements a set of hardware to support both fixed-point and floating-point operations, is characterized in that, It includes: The control logic module determines the operation mode of the arithmetic unit according to the input operands. The operation modes include: floating-point operation mode and fixed-point operation mode; When the operation mode is the floating-point operation mode, the input operands enter the unpacking module, and the unpacking module decodes the sign, exponent, and mantissa information of the operands to obtain the sign, exponent, and mantissa of each operand; The mantissas of the two operands obtained by the unpacking module pass through the restore significand logic module to restore the hidden bits to obtain the complete significand; The significands of the two operands enter the fixed-point multiplier through the input mux module for multiplication operation; The exponents of the two input operands enter the fixed-point adder to calculate the output result exponent; The control logic module determines the output result sign according to the signs of the two input operands; Normalize and round the output mantissa of the fixed-point multiplier to determine the output result mantissa, and synchronously adjust the output result exponent; Pack the output result sign, the output result exponent, and the output result mantissa into a floating-point format to obtain the output floating-point result.

6. The method according to claim 5, wherein The control logic determines the output result sign according to the signs of the two input operands, including: The control logic module determines the output result sign according to the signs of the two input operands and the principle that the same sign is positive and the different sign is negative.

7. The method according to claim 5, wherein Synchronously adjust the output result exponent, including: Adjust the output result exponent according to the normalized shift value and whether the rounding generates a carry, where the carry is the output result exponent minus the shift value plus the carry generated by the rounding.

8. The method according to claim 5, wherein It also includes: When the operation mode is the fixed-point calculation mode, the control logic module controls the input mux module to directly send the two input operands to the fixed-point multiplier; The fixed-point multiplier performs a multiplication operation on the input operands to obtain a fixed-point calculation multiplication result; The control logic module controls the output MUX module to directly output the fixed-point calculation result to complete the fixed-point operation.

9. A multi-precision multiplier with fixed-point and floating-point fusion, characterized in that It is used to implement the multi-precision multiplication operation method for fixed-point and floating-point fusion described in any one of claims 5-8 above.

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