CAM-based random local search accelerator for solving constraint satisfaction problems

Abstract

The present disclosure relates to a CAM-based random local search accelerator for solving constraint satisfaction problems. The present disclosure generally provides a method for solving a K-SAT problem. The method includes programming one or more clauses of a Boolean expression written in a negated disjunctive normal form (DNF) for the K-SAT problem into a ternary CAM (TCAM) array, the array including columns and rows of TCAM cells. The method also includes: applying an interpretation including one or more binary variables expected to be used to solve the Boolean expression as input to the TCAM array along the column; returning a binary value for each clause; randomly selecting a matching match line; determining a selected clause from one or more violating clauses; and using the interrupt count of each variable of the selected clause to change one or more literals within the interpretation.

Description

Background Art

[0001] The Boolean satisfiability problem (i.e., propositional satisfiability problem, abbreviated as Satisfiability, SAT or B-SAT) is the problem of determining whether there is an interpretation that satisfies a given Boolean formula. For example, the SAT problem attempts to determine whether the variables of a given Boolean formula can always be replaced with the value true or false so that the formula evaluates to true. If this is the case, the formula is called satisfiable. On the other hand, if there is no such assignment, the function represented by the formula is false for all possible variable assignments, and the formula is unsatisfiable. For example, the formula "a AND NOT b" is satisfiable because the values ​​a = true and b = false will make the formula "a AND NOT b" = true. In contrast, "a AND NOT a" is unsatisfiable. SAT is the first problem that was proven to be NP-complete. All problems in the NP complexity class (which includes a wide range of natural decision and optimization problems) are at most as difficult to solve as SAT.

[0002] One or more clauses of the Boolean expression for the SAT problem can be programmed as corresponding cells of a row of a content-addressable memory ("CAM"). A CAM is a computational memory in which the stored data is accessed not by its location but by its content. A word or "tag" is entered into the CAM. The CAM searches for the tag in its content, and when the tag is found, the CAM returns the address of the location where the found content resides. CAMs are powerful, efficient, and fast. However, CAMs are also relatively large, consume a lot of energy, and are relatively expensive. These drawbacks limit their applicability to select applications where their power, efficiency, and speed are sufficiently efficient. CAMs based on non-volatile memory technology have been used for in-memory computing in a variety of applications such as pattern matching, artificial intelligence, and machine learning. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure is described in detail according to one or more different embodiments with reference to the following drawings. The drawings are provided for illustrative purposes only and depict only typical or example embodiments.

[0004] Figure 1 An example of a K-SAT solver including a K-SAT verification block and a K-SAT optimizer is shown.

[0005] Figure 2 An example ternary content addressable memory (TCAM) that may be used as a k-SAT verification circuit is shown.

[0006] FIG. 3A to FIG. 3B An example of a 3-SAT negated DNF Boolean expression mapped onto a TCAM is illustrated.

[0007] Figure 4 An example memristor-implemented dot product engine is shown that can be used to determine the number of times each variable violates a constraint.

[0008] FIG. 5A to FIG. 5B An example architecture of a K-SAT verification and solution technique according to one embodiment is shown.

[0009] Figure 6 is a method for solving the K-SAT problem according to one embodiment.

[0010] Figure 7 An example architecture of a K-SAT verification and solution technique according to one embodiment is shown.

[0011] Figure 8 An example architecture of a K-SAT verification and solution technique according to one embodiment is shown.

[0012] Fig. 9 are example computing components that may be used to implement various features of the example embodiments of the present invention.

[0013] The drawings are not exhaustive and do not limit the disclosure to the precise forms disclosed. DETAILED DESCRIPTION

[0014] The Boolean satisfiability problem (i.e., propositional satisfiability problem, abbreviated as Satisfiability, SAT or B-SAT) is the problem of determining whether there is an interpretation that satisfies a given Boolean formula. For example, the SAT problem attempts to determine whether the variables of a given Boolean formula can always be replaced with the value true or false so that the formula evaluates to true. If this is the case, the formula is called satisfiable. On the other hand, if there is no such assignment, the function represented by the formula is false for all possible variable assignments, and the formula is unsatisfiable. For example, the formula "a AND NOT b" is satisfiable because the values ​​a = true and b = false will make the formula "a AND NOT b" = true. In contrast, "a AND NOT a" is unsatisfiable. SAT is the first problem that was proven to be NP-complete. All problems in the NP complexity class (which includes a wide range of natural decision and optimization problems) are at most as difficult to solve as SAT.

[0015] The k-SAT problem is characterized by the number of variables V, the number of literals k, and the number of clauses C. A literal is a variable or the negation of a variable. A clause consists of k literals. Conjunctive Normal Form or CNF (especially with k=3 literals per clause) is generally considered to be the canonical representation of SAT formulas. In CNF formation, a clause is a disjunction (logical OR operation) of literals (or a single literal). A formula is a conjunction (logical AND operation) of clauses (or a single clause). A formula can also be represented by Disjunctive Normal Form (DNF), where a clause is a conjunction of literals and a formula is a disjunction of clauses.

[0016] The CAM may be implemented with a technology that allows the CAM to retain its contents even when power is removed or otherwise removed. Thus, the data stored in the CAM may be retained and may act as a "non-volatile memory." These technologies include, for example, resistive memory (i.e., memristor), phase change memory, magnetoresistive memory, ferroelectric memory, and other resistive random access memory devices or a combination of these technologies.

[0017] CAMs can be classified as either "binary" or "tri-state". Binary CAMs ("BCAMs") operate on input patterns containing binary bits zero and one. Tri-state CAMs ("TCAMs") operate (and store data) on input patterns containing not only binary bits zero and one but also "X" values. "X" is sometimes referred to as "don't care" or "wildcard". In a search for input patterns in a TCAM, "X" will return a match for either zero or one bit. Thus, a search for the input pattern "10X1" will return a match for both "1001" and "1011". It is worth noting that both BCAMs and TCAMs use and operate on binary values ​​zero and one. CAMs are digital because data is stored in the CAM as binary values ​​in a memory (e.g., SRAM, memristor, etc.) and the input pattern is represented by zero and one. Each memory cell in the CAM processes one value (0 / 1 or 0 / 1 / X) at a time, which limits memory density and power efficiency.

[0018] Figure 1 1 is an example architecture of a K-SAT verification and solution technique according to one embodiment. The example architecture 100 includes a K-SAT verification block 110 (i.e., a K-SAT verification circuit) and a K-SAT optimizer 115. Figure 1As shown, input 102 is applied to a K-SAT verification block 110. Input 102 includes a formula (e.g., a CNF expression or a DNF expression) 106 and an interpretation (e.g., a conjecture), the formula including multiple clauses, and the clauses including k literals. The interpretation includes a set of variables that can be applied to the K-SAT problem to test / check whether the variables satisfy the clauses. In one embodiment, if the variables do not satisfy each clause, the number of violated clauses can be counted. Output 103 from the K-SAT verification block 110 can include any of the following: a Boolean value 111 (e.g., a value representing true or false); an integer 112; and a Boolean vector 113 of Boolean expressions. Boolean value 111 can be used to indicate whether all clauses are satisfied. Integer 112 can be used to indicate the number of violated clauses of the interpretation. The output can also include a Boolean vector 113 representing the index of the TCAM row storing the violated clauses. As shown Figure 1 As shown, the output of the K-SAT verification block 110 is sent to and received by the K-SAT optimizer 115. The K-SAT optimizer 115 uses the output to generate an updated (i.e., new) interpretation 116, which can be applied as input 102 to the K-SAT verification block 110 to satisfy more clauses than the previous input.

[0019] Figure 2 An example ternary content addressable memory (TCAM) 200 is shown that can be used as a k-SAT verification block 110. The TCAM 200 is programmed consistently with the k-SAT formula 106 so that the TCAM 200 can be used to test the interpretation 107 for the k-SAT formula 106 within a block (i.e., TCAM cell 210). The TCAM 200 is a type of content addressable memory (CAM).

[0020] Specifically, in a typical non-CAM computer memory such as a random access memory (RAM), the content or data stored in the memory is searched by the memory address. In contrast, in a CAM, the memory is content addressable. To search the CAM, the content is provided rather than the memory address. The CAM can be a binary CAM, which can only match binary values, such as logic zero and logic one. In contrast, a TCAM can match and store values ​​based on the following three inputs: logic zero, logic one, and a "don't care" state.

[0021] TCAM 200 includes input column line groups 202A, 202B, . . . , 202L, which are collectively referred to as input column line groups 202. The number of column line groups 202 is equal to the total set of variables x l , x2, ..., x L Inside Figure 1Any formula 106 or interpretation 107 of can be set to (either identically or as its negation) the number of variables V. The column line groups 202 correspond to the variables x l , x2, ..., x L .

[0022] TCAM 200 includes row line pairs 204A, 204B, ..., 204S, which are collectively referred to as row line pairs 204. The number of row line pairs 204 is equal to the number of row line pairs 204. Figure 1 The number S of k-SAT clauses in formula 106 in . The line pairs 204 correspond to the k-SAT clauses constituting formula 106 , respectively.

[0023] Each input column line group 202 includes a search line 206A or SL and a reverse search line 206B or And in some embodiments of the TCAM, a "don't care" line 206C or SX may also be included. Each row line pair 204 includes a match line 208A or ML and a write line 208B or WL. Lines 206A, 206B, and 206C are collectively referred to as lines 206, and lines 208A and 208B are collectively referred to as lines 208.

[0024] The TCAM returns a match (true value) for a given row ML if all the values ​​stored in each TCAM cell on the row are equal to a given value which is input to SL / and SL-negated. Thus, the TCAM performs a bitwise AND operation between the XNOR of the value stored in each TCAM cell and its corresponding input.

[0025] Each TCAM cell 210 may be implemented by a memristor, in which case the TCAM 200 is a memristor-implemented TCAM. For example, each TCAM cell 210 may be implemented by one or two memristors. An example of such a TCAM cell implemented by two memristors using four transistors is described in L. Huang et al., "ReRAM-based 4T2R non-volatile TCAM with a 7x NVM-stress reduction, and 4x improvement in speed word length-capacity for normally-off instant-on filter-based search engines used in big-data processing", VLSI Symposium, June 2014, pp. 99-100. An example of a TCAM implemented by a memristor using three transistors is described in M. Chang et al., "A 3T1R non-volatile TCAM using MLC ReRAM with sub-1ns search time", 2015 IEEE International Solid-State Circuits Conference, 2015, pp. 1-3.

[0026] TCAM unit 210 is programmed to correspond to the variable assignments of the k-SAT clause in equation 106. Figure 2 As shown, the input columns (ie, the input column line groups 202 ) correspond to a total number of variables V. Each TCAM cell 210 is arranged between a corresponding input column line group 202 and a corresponding output row line pair 204 .

[0027] For example, column line group 202B may correspond to a total set of V variables x1, x2, . . . , x V , and thus corresponds to the variable assignment corresponding to the variable x2. For example, row pair 204S may correspond to the last or s-th k-SAT clause, thereby indicating whether the s-th clause is satisfied.

[0028] In one embodiment, the TCAM cell includes a four transistor and two memristors (4T2M) TCAM cell, the first transistor T1 is connected to the first data line SL, and the second transistor T2 is connected to the second data line SL. The first memristor is connected to the first transistor T1, and the second memristor M2 is connected to the second transistor T2. The first memristor M1 and the second memristor M2 are connected in series to form a resistor divider, and the output voltage of the resistor divider (i.e., the voltage on the common node G) is applied to the gate of the match line transistor T4 to control whether to switch the match line transistor T4 to pull down the voltage on the match line ML. The third transistor T3 works in conjunction with the first transistor T1 and / or the second transistor T2 to program the memristors M1 and M2. Further, using a TS memristor according to the technology disclosed herein, the same operation can be achieved with three transistors, thereby reducing the size of the unit and reducing power consumption.

[0029] Although discussed with respect to example CAMS based on memristors, the techniques disclosed herein are not limited to example CAMs based on memristors, but are also directly applicable to CAMs based on conventional static random access memories (SRAMs) implemented with conventional complementary metal oxide semiconductor (CMOS) technology. Conventional SRAM-based CAM cells include a total of sixteen transistors including storage and memory circuits. The problem of subthreshold leakage exists in any situation where a large number of transistors are present and associated with a common match line. The effect of subthreshold leakage in this environment limits the possible size of data words that can be effectively stored and searched to only 8 or 16 bits.

[0030] Assuming that each CAM / TCAM row performs a bitwise AND operation between the XNOR of each stored value in the CAM / TCAM and its corresponding input, the k-SAT problem in the negated DNF formulation can be mapped onto the CAM / TCAM. Therefore, the CAM / TCAM can be used to verify which clauses are satisfied through input interpretation.

[0031] Mapping includes programming the Boolean expression into the CAM. Specifically, each clause of the DNF Boolean expression can be mapped (e.g., programmed) into multiple CAM cells according to a mapping order. Therefore, the inherent AND property of the CAM can be used to help the solver solve the K-SAT problem. For example, because the negated DNF Boolean expression includes multiple clauses connected by OR, each clause (including multiple literals separated by AND) can be mapped to the CAM in rows and can be separated into multiple rows without interfering with the DNF Boolean expression. Once the DNF expression is mapped into rows, each variable in the row can be arranged into columns so that a conjecture can be applied to each variable through each column.

[0032] like FIG. 3A to FIG. 3BAs shown, the TCAM includes a plurality of columns 307 and rows 305. Each clause of the negated DNF Boolean expression can be mapped to the rows 305 of the plurality of CAM cells 306 according to a mapping order. In one embodiment, the mapping order includes programming a first clause including a plurality of literals to a first row 305A, and programming a second clause including a plurality of literals to a second row 305B. Each of the plurality of literals also includes a first value assigned to each non-negated literal (e.g., z), and a first value assigned to each negated literal (e.g., )’s second value.

[0033] like Figure 3A As shown, an exemplary 2-SAT problem is mapped to a TCAM. Here, the 2-SAT problem includes two literals (i.e., k=2), three variables (i.e., V=3), and two clauses (i.e., C=2). In this example, the TCAM includes a cell array comprising two rows and three columns. Each clause is mapped to a row of the TCAM. For example, the first clause is mapped to the first row 305A, and the second clause is mapped to the second row 305B. In addition, each column of the TCAM includes a variable (e.g., 1, 0, or X). Each clause has k literals selected between V variables. In this example, each clause includes two literals. Non-negative literals are programmed as 1 in the corresponding TCAM cell, and negative literals are programmed as 0 in the corresponding TCAM cell. Variables that are not present in a clause are programmed as 'X' (don't care) in the corresponding TCAM cell.

[0034] For example, Figure 3A As shown, the expression: (representing the negation of a given formula) can be programmed (i.e., mapped) onto a CAM. In this example, the first clause is mapped to the first row 305A, and the second clause Mapped to the second row 305B. Each literal within each clause is mapped to its own corresponding column 307A to 307C. For example, x of the first clause and the second clause is mapped to the first column 307A, y of the first clause and the second clause is mapped to the second column 307B, and z is mapped to the third column 307C. In addition, as previously mentioned, each literal is assigned a bit value (three-state 0 or 1 or X) depending on whether the literal is negative, non-negated, or a missing literal that is not present in the clause. Here, negative literals are assigned a bit value of 0, non-negated literals are assigned a bit value of 1, and missing literals are assigned a bit value of 'X' (don't care). For example, the first clause includes literals x, y. The values ​​of x, y are mapped to the CAM such that x is represented as 1 in cell 311, y is represented as 1 in cell 312, and z is represented as "X" in cell 313. As Figure 3A As further shown, the second clause is mapped to the second row 305 of the CAM, so that x is represented as "X" in cell 314, is represented as "0" in cell 315, and z is represented as "1" in cell 316. Therefore, Figure 3A As shown, negate the DNF Boolean expression The first clause is represented by 1 1X in the first line, and the second clause Represented as X 0 1 in the second row.

[0035] like Figure 3A As further shown, each row includes a match line (ML). For example, cells 311 to 313 in a first row 305A include a first ML, and cells 314 to 316 in a second row 305B include a second ML.

[0036] The solver applies each variable (i.e., input) explained in parallel to each column to determine which clause is satisfied. A satisfied clause corresponds to an ML output equal to 0. For example, Figure 3A As shown, if the interpretation [1 1 0] is applied as input, ML1 will return an ML high value (e.g., a high-order bit value of 1). Here, ML1 will return an ML high value because each variable (i.e., input value) of the interpretation matches the values ​​stored in cells 311, 312, and 313, respectively. Additionally, ML2 will return an ML low value (e.g., a low-order bit value of 0) because the interpretation [1 1 0] does not match the values ​​stored in cells 314, 315, and 316. Thus, the first clause is not satisfied, but the second clause is satisfied. Additionally, in another example, if the interpretation [0 0 0] is applied as input, ML1 and ML2 will return an ML low value (e.g., a low-order bit value of 0) because the interpretation does not match the values ​​stored in cells 311, 312, 313, 314, 315, and 316. Because both ML (ML1 and ML2) return low values, both clauses are satisfied.

[0037] The following shows the Figure 3A The complete truth table of the Boolean expression of (i.e., Truth Table 1). When , the given k-SAT problem is solved. To verify that each row of ML can be coupled to an OR gate to verify whether the Boolean expression is satisfied. Figure 3B As shown, the OR gate can accommodate any number of MLs. For example, if three clauses are mapped to three rows of the CAM, three MLs will be coupled to the OR gate.

[0038]

[0039] Truth Table 1

[0040] In an alternative embodiment, the analog values ​​of each ML are passed through an analog adder. The analog adder combines the analog values ​​(i.e., non-binary signals) of each ML to calculate a sum value. The sum of the analog values ​​is returned as an output (e.g., output 103), which can be used by the K-SAT optimizer 115 to solve the K-SAT problem.

[0041] Figure 3B is an example of three clauses mapped to the CAM. As mentioned previously, each clause is mapped to rows, and each literal within each clause is mapped to columns. For example, if the interpretation [0 1 1] is applied to the first clause Second Clause and the third clause At the input of the mapped CAM, ML1 and ML2 will both return low outputs, while ML3 will return high outputs. Since ML3 returns high outputs, the third clause is not satisfied.

[0042] For example, Figure 3B As shown, if interpretation [0 0 1] is applied as input, ML1 will return an ML low value (e.g., a low-order bit value of 0) because interpretation [0 0 1] does not match the values ​​stored in cells 311, 312, and 313. Here, ML2 and ML3 will both return an ML high value because each variable of the interpretation (i.e., input value) matches the values ​​stored in cells 314, 315, 316, 317, 318, and 319, respectively. Thus, in this example, the first clause is satisfied, while the second and third clauses are not satisfied. The following shows the operation for Figure 3B The complete truth table for the Boolean expression of (i.e., Truth Table 2).

[0043]

[0044] Truth Table 2

[0045] Figure 4 An example memristor-implemented dot product engine 400 that can be used to determine the number of clauses violated per variable is shown. The dot product engine 400 has a number M of rows 402A, 402B, ..., 402N, which are collectively referred to as rows 402. The dot product engine 400 has a number N of columns 404A, 404B, ..., 404N, which are collectively referred to as columns 404. At each intersection 406 of a row 402 and a column 404, the dot product engine 400 includes a memristor 408. The memristor 408 at each intersection 406 is more generally referred to as a memristor element, and there may be more than one memristor at each intersection 406 to store a data value.

[0046] The analog input voltages iv1, iv2, ..., iv MApplied to row 402, and constitutes a vector IV of input voltages. Output voltages OV1, OV2, ..., OV are provided at the output of a transimpedance amplifier (TIA) 406 on column 404. N , and form a vector of output voltages OV. The memristor 408 at the intersection of row x and column y has a programmed value, such as an analog conductance corresponding to an analog value, equal to G xy The output voltage of the yth column 404 is OV y Equal to the product iv on the row X = 1..M x ·G xy sum. Right now,

[0047]

[0048] The memristors 408 in column y form a vector {G xy}, X ＝ 1..M. Therefore the output voltage is OV y is the input voltage iv1, iv2, ..., iv M The dot product of the vector IV of {Gxy} and this vector {Gxy}. The memristors in all rows x and all columns y form a matrix {Gxy}, where X = 1..M and y = 1..N.

[0049] Figure 5A An example architecture 500 of a K-SAT verification and solving technique according to one embodiment is shown. The example architecture 500 includes a ternary content addressable memory (TCAM) 505, a random multiple match resolver (SMMR) 510, a counter 525, a static random access memory (SRAM) 515, and a selection block 520. As shown in FIG5 , the TCAM 505, the SMMR 510, the counter 525, the SRAM 515, and the selection block 520 are all electrically coupled to each other through a plurality of buses, respectively, to create a feedback loop.

[0050] The TCAM 505 includes a TCAM array including columns and rows of TCAM cells. One or more clauses of a Boolean expression written in disjunctive normal form (DNF) for a K-SAT problem can be programmed into the TCAM array. Programming each clause of a Boolean expression written in disjunctive normal form (DNF) for a K-SAT problem includes programming a bit value including 0, 1, or X into each cell within each TCAM array, where X represents a don't care value. Each occurring variable of each clause is mapped to a corresponding TCAM cell in a row, and each non-occurring variable is programmed to a don't care value. Specifically, each negation of each literal in each clause is assigned a bit value of 0, each non-negation of each literal in each clause is assigned a bit value of 1, and each missing variable in each clause is assigned a bit value of X. Each row of TCAM cells in the TCAM array includes a match line (ML).

[0051] In one embodiment, the TCAM 505 is configured to receive input 102 from a selection block 520. The input 102 includes an interpretation 107 (e.g., a conjecture) as input along a column to the TCAM array, the interpretation including one or more binary values ​​expected to be used to solve the Boolean expression. The interpretation 107 includes one or more binary variables expected to be used to solve the binary expression. Here, the TCAM 505 uses the interpretation 107 to test / check whether the input variable satisfies the mapping clause. The interpretation 107 is applied as input along the column of the TCAM array to determine whether one or more clauses are satisfied. A satisfied clause corresponds to an ML output 503 equal to 0. A violated clause (i.e., an unsatisfied clause) corresponds to an ML output 503 equal to 1. One or more binary variables may be applied to the K-SAT problem to test / check whether the variable satisfies at least one clause. For example, in one embodiment, the interpretation 107 may include a conjecture applied as input along the column of the TCAM array to determine whether one or more clauses are satisfied. As mentioned previously, the Boolean satisfiability problem (i.e., propositional satisfiability problem, abbreviated as Satisfiability, SAT or B-SAT) is the problem of determining whether there is an interpretation that satisfies a given Boolean formula. In one embodiment, selection block 520 applies interpretation 107 to each column to determine which clause is satisfied.

[0052] As previously mentioned, each row of TCAM cells in the TCAM is connected to a corresponding match line (ML). In one embodiment, if the interpretation matches the value stored in the row, the ML for that row will return a value associated with a true condition (e.g., ML returns TRUE or a high-order value of 1). If the interpretation does not match the value stored in each row, the ML for that row will return a value associated with a false condition (e.g., ML returns FALSE or a low-order value of 0). For example, if all values ​​stored in each TCAM cell on a row are equal to a given value as an interpretation (i.e., input) to the negation of SL / and SL, the TCAM will return a match (true value) on the ML of a given row. Thus, the TCAM performs a bitwise AND operation between the XNOR of the value stored in each TCAM cell and its corresponding input.

[0053] SMMR 510 is configured to receive output 503 from TCAM 505. Here, SMMR 510 uses output 503 from TCAM to randomly select one or more violation clauses. For example, in one embodiment, SMMR 510 can randomly select a violation clause index. The violation clause index is represented by the Boolean value TRUE in Boolean vector 113, which corresponds to output 503 of TCAM. The satisfied (i.e., non-violation) clause index is represented by the Boolean value FALSE in Boolean vector 113, which corresponds to output 503 of TCAM. In one embodiment, SMMR 510 uses output 503 to randomly select one of the high match lines (ML). This randomly selected high ML is sent as a vector via bus to SRAM 515. Specifically, once SMMR 510 randomly selects this high match line, a one-hot vector is returned on the selected match line (SML). The one-hot vector has the same dimensions as ML but only includes one element that is high. For example, if input MLs 1, 7, and 8 are high, the SMMR will randomly select between one of the high MLs and return an SML value of 1 as output 504. All other MLs will be returned as 0s in the SML (i.e., if 1, 7, and 8 are high, and the SMMR randomly selects ML 7, the SML will return a value of 1 for ML7 and a value of 0 for MLs 1 and 8 as output 504). Thus, the SML will have only one high value. As further explained below, each SML is communicatively coupled to each word line (WL) of the SRAM 515.

[0054] The SRAM 515 is configured to receive the output 504 from the SMMR 510. Because each SML is communicatively connected to each word line (WL) of the SRAM 515, the SRAM 515 can use the output 504 to return (e.g., send) one of the violating clauses to the selection block 520. Specifically, the SRAM 515 stores the same clauses as the clauses stored on the TCAM 505. If the variable exists in the clause, the SRAM assigns a value of 1, and if the variable does not exist in the clause, the SRAM assigns a value of 0. For example, for a 3-SAT problem with 10 variables, if the clause includes X1, X7, X8, the corresponding SRAM row will be filled with all 0s (e.g., X2, X3, X4, X5, X6, X9, and X10) except for the three 1s (X1, X7, X8). 10) to be programmed, where there are variables in the clause. The SML vector is directly connected to the SRAM row. The clause stored in SML1 (selected to be high) is retrieved from the SRAM. The retrieved clause is referred to as the "selected clause" hereinafter. For example, since SML has only one valid high value, the high value will be connected to the WL of SRAM 515, and the SRAM will return a "selected clause" as output 505. In one embodiment, the SRAM returns the selected clause itself as the violating clause. The selected clause is sent to the selection block 520 as output 505, where the WalkSat algorithm can be applied to the selected clause to determine which variable to change (i.e., flip). Therefore, the SRAM can then be used to determine the variable of a violating clause randomly selected by the SMMR.

[0055] The selection block 520 is configured to receive the output 505 from the SRAM 515. Here, the selection block 520 includes circuitry configured to use the output 505 to decide which variable to change (i.e., flip) from the selected clause. In one embodiment, the selection block uses a WalkSAT algorithm to determine which variable to change. In one embodiment, changing (i.e., flipping) the variable includes creating a reciprocal value and applying the reciprocal value of the variable to each clause to determine the number of clauses violated.

[0056] The WalkSAT algorithm is a local search algorithm that applies an interpretation to a device (e.g., a TCAM) and changes one variable of the interpretation to see if the output is changed (e.g., whether the clause is satisfied or not satisfied). The WalkSAT search algorithm then changes one or more variables of the interpretation based on the output. For example, the selection block 520 can apply the WalkSAT search algorithm to random clauses to calculate how many clauses each variable violates when flipping the variable. The number of clauses violated by each variable is called an interruption count. The interruption count can be used to indicate how many clauses are violated by flipping the particular variable. Each variable has an interruption count based on the result of the change (i.e., flipping). Here, the interruption count includes an integer 560 (e.g., a number) as an output from a counter 525. The integer 560 includes the number of clauses violated. Therefore, the interruption count for the particularly updated interpretation 116 includes an integer 560 as an output from the counter 525.

[0057] In one embodiment, the selection block 520 changes (i.e., flips) a variable based on an interruption count. Specifically, the WalkSAT algorithm includes starting with a random interpretation, calculating unsatisfied clauses, and picking random clauses. For example, if the interruption count of a variable is equal to zero, the variable is flipped. Otherwise, the selection block 520 randomly selects between flipping the variable with the smallest interruption count or flipping a random variable (e.g., a random value (RND) from 0 to 1). If RND is less than a hyperparameter (P), the random variable is flipped. Otherwise, the variable with the smallest interruption count is flipped. For example, if the 3-SAT problem is encoded, the output of the SRAM is a vector with all zeros except the three values ​​in a specific clause. The selection block 520 will check the interruption counts corresponding to flipping the first variable and querying the three variables of the TCAM 505 to determine the number of violations (i.e., mismatches) of the clause (e.g., how many 0s are there in the ML). Then, the selection block 520 will flip the variable and repeat the process. Repeat the process to determine which variables lead to a closer solution and which variables lead to a farther solution. Thus, once the selection block 520 decides which variable to flip, it generates an updated interpretation 116 that includes the flipped variable. The updated interpretation is then applied as input 102 to the TCAM 505 to satisfy one or more clauses of the formula.

[0058] Figure 5B An example architecture 500 of a K-SAT verification and solution technique according to one embodiment is shown. Figure 5B Including CNF and negate DNF Negate DNF Each clause of is programmed into TCAM 505. For example, the first row includes the clauses corresponding to The second line contains the values ​​corresponding to the clauses [0, X, 1]. The third line includes the value [X, 0, 1] corresponding to the clause As mentioned previously, each row includes ML (i.e., is connected to ML). Figure 5B As shown, the first row includes ML1, the second row includes ML2, and the third row includes ML3. Each ML is connected (e.g., communicatively coupled) to SMMR 510. SMMR 510 is connected to a plurality of SMLs (e.g., SML1, SML2, and SML3). Each SML is electrically coupled to a row of SRAM 515 memory cells. Here, SRAM 515 includes three rows (e.g., a first row, a second row, and a third row). Therefore, as shown in FIG. Figure 5BAs shown, SML1 is electrically coupled to the first row of SRAM 515, SML2 is electrically coupled to the second row of SRAM 515, and SML3 is electrically coupled to the third row of SRAM 515. Each memory cell of SRAM 515 is programmed with a variable (e.g., 0 or 1). Figure 5B As shown, the first row of SRAM is programmed with values ​​[1, 0, 1], the second row of SRAM is programmed with values ​​[0, 1, 1], and the third row of SRAM is programmed with values ​​[1, 1, 0].

[0059] In one example, the interpretation [0, 0, 1] is applied as input 102 to the TCAM. Since the value of the first row matches the interpreted value, ML1 returns a value of 1 (e.g., [0, 0, 1] matches [0, X, 1] because the X value can be 1 or 0). In addition, since the value of the second row matches the interpreted value, ML2 returns a value of 1 (e.g., [0, 0, 1] matches [X, 0, 1] because the X value can be 1 or 0). Since ML1 and ML2 match, the output 503 from the TCAM is a vector ML [1, 1, 0]. Once one or more MLs match, the SMMR 510 randomly selects one of the matching MLs (e.g., ML1) and returns the SML corresponding to the randomly selected ML as a one-hot vector. The one-hot vector is sent as output 504 to the selection block 520. In order to distinguish between the randomly selected and non-selected MLs, the SMMR 510 sets the selected match line (SML) to a value of 1. Here, SML1 is set to 1. The value stored in the row of SRAM 515 electrically coupled to SML1 is returned as the selected clause (eg, the first row value [1, 0, 1]). The selected clause is then used by the WalkSAT algorithm to solve the K-SAT problem.

[0060] Figure 6 600 is a method for solving a K-SAT problem according to one embodiment. The method 600 includes mapping each clause of a Boolean expression in a negated disjunctive normal form (DNF) of the K-SAT problem to a CAM, applying an interpretation, returning a binary value for each violating clause, randomly selecting (i.e., randomly selecting) one or more violating clauses, retrieving the selected violating clauses from an SRAM, and if at least one clause is violated, changing one or more variables within the interpretation according to a WalkSAT algorithm.

[0061] At activity 602, method 600 includes mapping each clause of a Boolean expression written in a negated DNF of a K-SAT problem to a CAM. In one embodiment, the Boolean expression can be mapped to a three-state CAM of four transistors and two memristors (i.e., a 4T2M TCAM). In another embodiment, the Boolean expression can be mapped to a three-state CAM of two transistors and two memristors (i.e., a 2T2M TCAM). In yet another embodiment, the Boolean expression can be mapped to a three-state CAM of three transistors and one memristor (i.e., a 3T1M TCAM). In yet another embodiment, the Boolean expression can be mapped to an analog CAM of six transistors and two memristors (i.e., a 6T2M aCAM). In yet another embodiment, the Boolean expression can be mapped to a multi-bit CAM of 2 ferroelectric FETs (2FeFET mCAM). In yet another embodiment, the Boolean expression can be mapped to a three-terminal aCAM and a 16-transistor TCAM (i.e., SRAM).

[0062] Here each clause of the Boolean expression is mapped to a row of the CAM. Each word within each clause is mapped to its own corresponding column. Each word is further assigned a bit value (binary 0, 1, or X) depending on whether the word is negative, non-negative, or a missing word that does not exist in the clause. Here, negative words are assigned a bit value of 0, non-negative words are assigned a bit value of 1, and missing words are assigned a bit value of 'X' (don't care). In addition, each row is electrically coupled to a match line (ML).

[0063] At activity 604, method 600 includes applying interpretation 107 as input to K-SAT verification block 110. Here, K-solver circuit 101 applies each variable (i.e., input) of the interpretation in parallel to each column to determine which clause is satisfied. A satisfied clause corresponds to an ML output equal to 0. The interpretation includes a set of variables that can be applied to the K-SAT problem to test / check whether the variables satisfy all clauses. As previously mentioned, the Boolean satisfiability problem (i.e., propositional satisfiability problem, abbreviated as Satisfiability, SAT or B-SAT) is the problem of determining whether there is an interpretation that satisfies a given Boolean formula. Therefore, CAM / TCAM is used to verify which clauses are satisfied by input interpretation.

[0064] At activity 606, method 600 includes returning a binary value for each violation clause. As previously mentioned, each row of cells in the CAM is connected to a corresponding match line (ML). In one embodiment, if the interpretation matches the value stored in each row, the ML coupled to the row will return a value associated with a true condition (e.g., ML returns TRUE or a high-order value of 1). If the interpretation does not match the value stored in each row, the ML coupled to the row will return a value associated with a false condition (e.g., ML returns FALSE or a low-order value of 0). For example, if all values ​​stored in each TCAM cell on the row are equal to a given value as an interpretation (i.e., input) of a negation of SL / and SL, the TCAM will return a match (true value) on the ML of a given row. Therefore, the TCAM performs a bitwise AND operation between the XNOR of the value stored in each TCAM cell and its corresponding input.

[0065] In one embodiment, if the variable does not satisfy all clauses, the number of violated clauses can be counted. The output 103 from the K-SAT verification block 110 can include any of the following: a Boolean value 111 (e.g., a value representing true or false); an integer 112; and a Boolean vector (e.g., a vector in which each entry represents true or false) 113. The Boolean value 111 can be used to indicate whether a clause is satisfied. The integer 112 can be used to indicate the total number of violated clauses. The Boolean vector 113 can be used to indicate the index of the violated clause, where a true value in one of the vector entries means that the corresponding TCAM row is storing the violated clause. Figure 1 As shown, the output of TCAM 505 is sent to and received by SMMR 510.

[0066] At activity 608, method 600 includes determining whether a clause is satisfied or violated. In one embodiment, K-SAT optimizer 115 uses output 103 from K-SAT validation block 110 to determine whether a clause is satisfied or violated. If the clause is violated, the method includes proceeding to step 610 to update one or more variables within the interpretation. A violated clause corresponds to an ML output equal to 1. A satisfied clause corresponds to an ML output equal to 0. If the clause is satisfied (i.e., not violated), the method ends.

[0067] At activity 610, method 600 includes randomly selecting one or more violation clauses. SMMR 510 is configured to receive output 103 from TCAM 505. SMMR 510 uses output 103 from TCAM to randomly select one or more violation clauses. In one embodiment, SMMR 510 uses output 103 to randomly select one of the high match lines (ML) to be sent to SRAM 515 as a vector via bus. Specifically, once SMMR 510 randomly selects a high match line, a one-hot vector is returned on the selected match line (SML). A one-hot vector is a vector that is the same as ML but includes only one high value. Therefore, SML will have only one high value. Each SML is electrically coupled to each word line (WL) of SRAM 515 to communicatively couple each SML to each WL.

[0068] At activity 612, method 600 includes obtaining a selected clause from an SRAM. SRAM 515 is configured to receive output 504 from SMMR 510. Because each SML is communicatively coupled to each word line (WL) of SRAM 515, SRAM 515 can use output 504 to return (e.g., send) one of the violating clauses to selection block 520. Specifically, SRAM 515 stores the same clauses as the clauses stored on TCAM 505. If there is a variable in the clause, the SRAM assigns a value of 1, and if there is no variable in the clause, the value of 0 is assigned. Since SML has only one valid high value, the high value will be connected to the WL of SRAM 515. Therefore, the SRAM can be used to determine the variables of the clause randomly selected by the SMMR. Therefore, output 505 includes the selected clause (e.g., a violating clause). Output 505 is sent to selection block 520. In one embodiment, SRAM 515 returns (i.e., sends) output 505 itself as a violating clause.

[0069] At activity 614, method 600 includes changing (i.e., flipping) one or more variables in the interpretation according to the WalkSAT algorithm. Here, selection block 520 is configured to receive output 505 from SRAM 515 and integer 560 from counter 525. Selection block 520 includes circuitry configured to use output 505 to decide which variable to change from the selected clause. In one embodiment, the selection block uses the WalkSAT algorithm to determine which variable to change.

[0070] The WalkSAT search algorithm changes one or more variables of the interpretation based on output 505. In one embodiment, changing one or more variables includes creating a reciprocal value and applying the reciprocal value of the variable to each clause to determine the number of clauses violated. For example, selection block 520 can apply the WalkSAT search algorithm to random clauses to calculate how many clauses each variable violates when flipping the variable. As previously mentioned, each variable has a break count based on the flip result. Therefore, the break count can be used to indicate how many clauses are violated by flipping a particular variable.

[0071] In one embodiment, the selection block 520 flips the variable based on the interruption count. Specifically, the WalkSAT algorithm starts with a random interpretation, calculates unsatisfied clauses, and selects a random clause. For example, if the interruption count of a variable is equal to zero, the variable is flipped. Otherwise, the selection block 520 randomly selects between flipping the variable with the smallest interruption count or flipping a random variable (e.g., a random value (RND) from 0 to 1). If the RND is less than a hyperparameter (P), the random variable is flipped. Otherwise, the variable with the smallest interruption count is flipped. Repeat the process to determine which variables lead to a closer solution and which variables lead to a farther solution. Therefore, once the selection block 520 decides which variable to flip, it generates an updated (i.e., new) interpretation 116 including the flipped variable. The updated interpretation is then applied to the TCAM 505 as input 102 to satisfy one or more clauses of the formula.

[0072] Figure 7 7 shows an example architecture 700 of a K-SAT verification and solution technique according to one embodiment. The example architecture 700 includes a ternary content addressable memory (TCAM) 505, a dot product engine (DPE) 710, and a selection block 520. Figure 7 As shown, the TCAM 505 , the DPE 710 , and the selection block 520 are each electrically coupled to one another via a plurality of buses to create a feedback loop.

[0073] The TCAM 505 includes a cell array including rows and columns. Each clause of the Boolean expression written in negated DNF of the K-SAT problem can be mapped to a row of the TCAM, so that each column of the TCAM includes a variable. In one embodiment, non-negated literals are programmed as 1 in the corresponding TCAM cell, and negated literals are programmed as 0 in the corresponding TCAM cell. All variables not present in the clause are programmed as 'X' (don't care) in the corresponding TCAM cell. Each row is electrically coupled to a match line (ML).

[0074] In one embodiment, the TCAM 505 is configured to receive input 102 from a selection block 520. The input 102 includes an interpretation 107 (e.g., a conjecture). The interpretation includes a set of variables that can be applied to the K-SAT problem to test / check whether the variables satisfy all clauses. Here, the TCAM 505 uses the interpretation 107 to test / check whether the input variables satisfy the mapping clause. Specifically, the selection block 520 applies each variable (i.e., input) of the interpretation in parallel to each column to determine which clause is satisfied. The unsatisfied clause corresponds to an ML high value (e.g., a high-order bit value) because the negated DNF is mapped and all variables in the interpretation are matched. The satisfied clause corresponds to an ML low value (e.g., a low-order bit value) because the last variable in the interpretation does not match. The output 703 may include a Boolean vector 113 representing the index of the TCAM row storing the violation clause.

[0075] DPE 710 is configured to receive output 703 from TCAM 505. DPE 710 uses output 703 from TCAM. In one embodiment, DPE 710 includes Figure 4 DPE 400 of FIG. 400 can be used to determine the number of clauses violated by each variable. Here, DPE 710 includes a resistor or memristor array that can be programmed. DPE 710 receives an input vector (e.g., ML output from a TCAM). The DPE 710 matrix can be used to return an output 705 to selection block 520 that includes a vector indicating the number of clauses violated by each specific variable. For example, if ML is a vector with 3 elements, each element will physically connect a row. Therefore, if Figure 4 As shown, each vector element of the ML will be connected to rows 402A, 402B, 402C. Each row in the DPE 710 is multiplied according to the matrix multiplication to form an output 705 that can be returned (i.e., sent) to the selection block 520. As previously mentioned, each ML will return a high value (e.g., a high-order value of 1) if the clause is violated, and will return a low value (e.g., a low-order value of 0) if the clause is not violated. Similar to the SRAM 515, the DPE assigns a value of 1 if the variable is present in the clause, and a value of 0 if the variable is not present in the clause. For example, for a 3-SAT problem with 10 variables, if the clause includes X1, X7, X8, the corresponding DPE row will be filled with all 0s (e.g., X2, X3, X4, X5, X6, X9, and X10) except for the three 1s (X1, X7, X8). 10) to be programmed, where there are variables in the clauses. By performing a matrix-multi-vector multiplication, using the matrix and the value stored in the RAM (i.e., DPE 710), the DPE 710 can return (i.e., send) a vector having elements (e.g., specific frequencies or frequency ranges) representing the number of times a particular variable violates one or more clauses. For example, if variable V2 violates three clauses, the output will include a vector having the number of violated clauses (e.g., 3) in position 2 of the array. Therefore, the DPE 710 can determine which variable contributes the most to the violation of the clause. Specifically, the DPE 710 can determine which variable has the highest probability of not being able to solve the problem. The DPE 710 can then return (i.e., send) an output 705 including a vector representing the number of clauses violated by each specific variable to the selection block 520. Here, the selection block 520 is configured to receive the output 705 from the DPE 710 and use the output 705 to decide which variable to flip from the selected clause. In one embodiment, the selection block 520 is configured to flip the text of the variable with the highest probability of not being able to solve the problem, thereby forming a possible solution to the K-SAT problem. In one embodiment, the selection block is configured to add a random number to each element of the output 705 to randomly add additional scalars to the vector addition / multiplication. In this way, when performing an optimization operation, it is possible to avoid getting stuck in a local minimum or convergence point that is not a true solution.

[0076] Figure 8 An example architecture 800 of a K-SAT verification and solution technique according to one embodiment is shown. The example architecture 800 includes an early stopping circuit 801 including a ternary content addressable memory (TCAM) 505, a dot product engine (DPE) 710, an encoding block 805, a sensing block 820, and a selection block 520. The TCAM 505, the DPE 710, and the selection block 520 are each electrically coupled to each other via a plurality of buses to create a feedback loop.

[0077] In this embodiment, the early stopping circuit 801 is configured to determine when to stop the K-SAT problem solving operation (i.e., when the iteration of deciding which variable to flip from the selected clause is completed). Figure 7It can be seen that the rows of DPE 710 are used for matrix multi-vector multiplication. However, in this embodiment, each row is programmed with an additional 1 in an additional column. Therefore, an integer 835 representing the total number of violation clauses can be obtained without the need for a new circuit block. For example, by adding only one additional column to DPE 710, an integer 835 representing the total number of violation clauses can be obtained, thereby replacing the need for counter 525 of Figure 5. By applying a sensing operation to the memory cell, the sensing block can determine when the K-SAT problem solving operation should be completed. Here, the encoding block 805 encodes an additional 1 in each row as a mark to indicate the end of the solving process. Calculating the additional (e.g., additional) columns of DPE 710 in each row does not change the operation of other columns of DPE 710. Therefore, the number of violation clauses can be determined without changing the matrix multi-vector multiplication. When integer 835 is equal to 0, the K-SAT problem is solved and the circuit can stop. In one embodiment, the sensing block 820 senses the 0 integer 835 value. For example, if integer 835 is a value of 0, sense block 820 will determine that the K-SAT problem has been solved and stop the circuit. In one embodiment, stopping the circuit includes a process of terminating the feedback loop.

[0078] Fig. 9 A block diagram of an example computer system 900 is depicted in which various embodiments described herein may be implemented. For example, in one embodiment, a k-solver may be implemented as computer system 900. Computer system 900 includes a bus 902 or other communication mechanism for communicating information, one or more hardware processors 904 coupled to bus 902 for processing information. Hardware processor(s) 904 may be, for example, one or more general purpose microprocessors.

[0079] The computer system 900 also includes a main memory 906, such as a random access memory (RAM), cache, and / or other dynamic storage device, coupled to the bus 902 for storing information and instructions to be executed by the processor 904. The main memory 906 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by the processor 904. When stored in a storage medium accessible to the processor 904, such instructions cause the computer system 900 to become a special-purpose machine customized to perform the operations specified in the instructions.

[0080] The computer system 900 further includes a hardware accelerator 908. The hardware accelerator 908 may be configured to execute instructions (i.e., programming code or software code) stored in the main memory 906, the read-only memory (ROM) 912, and / or the storage device 914 to encode a set of logic rules embodied in the data structure into the CAM. In an example implementation, the exemplary hardware accelerator 908 may include a plurality of integrated circuits, which in turn may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other very large scale integrated circuit (VLSI). The integrated circuits of the exemplary hardware accelerator 908 may be specifically optimized to perform a discrete subset of computer processing operations in an accelerated manner, or to execute a discrete subset of computer executable instructions.

[0081] A CAM may include non-volatile memory constructed using technologies including, for example, resistive memory (i.e., memristors), phase change memory, magnetoresistive memory, ferroelectric memory, some other resistive random access memory device (Re-RAM), or a combination of these technologies. More generally, a CAM may be implemented using technologies that allow the CAM to retain its contents when it is powered off or otherwise removed. Thus, the data in the CAM is "persistent," and the CAM may act as so-called "non-volatile memory."

[0082] The computer system 900 also includes a read only memory (ROM) 912 or other static storage device coupled to the bus 902 for storing static information and instructions for the processor 904. A storage device 914, such as a magnetic disk, optical disk, or USB thumb drive (flash drive), is provided and coupled to the bus 902 for storing information and instructions.

[0083] The computer system 900 may be coupled to a display 916, such as a liquid crystal display (LCD) (or touch screen), via the bus 902 for displaying information to a computer user. An input device 918, including alphanumeric and other keys, is coupled to the bus 902 for communicating information and command selections to the processor 904. Another type of user input device is a cursor control 920, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to the processor 904 and for controlling cursor movement on the display 916. In some embodiments, the same direction information and command selections as a cursor control may be implemented by receiving touches on a touch screen without a cursor.

[0084] The computing system 900 may include a user interface module for implementing a GUI, which may be stored in a mass storage device as executable software code executed by the computing device(s). By way of example, this module and other modules may include components (such as software components, object-oriented software components, class components, and task components), processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

[0085] Generally, the words "component", "engine", "system", "database", "data storage", etc. as used herein may refer to logic implemented in hardware or firmware, or to a set of software instructions written in a programming language such as Java, C or C++, which may have entry points and exit points. Software components can be compiled and linked to executable programs, installed in dynamic link libraries, or written in interpretive programming languages ​​such as BASIC, Perl, or Python. It should be understood that software components can be called from other components or from themselves, and / or can be called in response to detected events or interrupts. Software components configured for execution on a computing device can be provided on a computer-readable medium, such as an optical disc, a digital video disc, a flash drive, a disk, or any other tangible medium, or can be provided as a digital download (and can be stored originally in a compressed format or an installable format that needs to be installed, decompressed or decrypted before execution). Such software code can be stored in part or in whole on a memory device of an executing computing device for execution by the computing device. Software instructions can be embedded in firmware such as an EPROM. It will be further understood that hardware components may include connected logic units such as gates and flip-flops, and / or may include programmable units such as programmable gate arrays or processors.

[0086] The computer system 900 may implement the techniques described herein using custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic devices that, in combination with the computer system, enable the computer system 900 to become or be programmed as a special purpose machine. According to one embodiment, the techniques herein are performed by the computer system 900 in response to the processor(s) 904 executing one or more sequences of one or more instructions contained in the main memory 906. Such instructions may be read into the main memory 906 from another storage medium, such as the storage device 914. Execution of the sequences of instructions contained in the main memory 906 causes the processor(s) 904 to perform the process steps described herein. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0087] As used herein, the term "non-transitory media" and similar terms (such as machine-readable storage media) refer to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media may include non-volatile media and / or volatile media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 914. Volatile media include dynamic memory, such as main memory 906. Common forms of non-transitory media include, for example, floppy disks, floppy disks, hard disks, solid-state drives, magnetic tapes or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a pattern of holes, RAM, PROMs and EPROMs, flash EPROMs, NVRAMs, any other memory chips or boxes, and networked versions of these media.

[0088] Non-transient media are distinct from transmission media but can be used in conjunction with transmission media. Transmission media participate in the transfer of information between non-transient media. For example, transmission media include coaxial cables, copper wire, and optical fiber, including the wires that comprise bus 902. Transmission media can also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0089] Computer system 900 also includes a communication interface 922 coupled to bus 902. Communication interface 922 provides a two-way data communication coupled to one or more network links, and the one or more network links are connected to one or more local networks. For example, communication interface 922 can be an integrated services digital network (ISDN) card, a cable modem, a satellite modem or a modem, to provide data communication connection to the telephone line of the corresponding type. As another example, communication interface 922 can be a local area network (LAN) card, to provide data communication connection to a compatible LAN (or a WAN component communicating with a WAN). Wireless links can also be implemented. In any such implementation, communication interface 922 sends and receives an electrical signal, an electromagnetic signal or an optical signal carrying a digital data stream representing various types of information.

[0090] A network link typically provides data communications to other data devices through one or more networks. For example, a network link can provide a connection through a local network to a host computer or to data devices operated by an Internet Service Provider (ISP). The ISP in turn provides data communications services through a global packet data communications network now commonly referred to as the "Internet". Both the local network and the Internet use electrical, electromagnetic, or optical signals that carry digital data streams. Signals through various networks and signals on the network link and through the communication interface 922 (which carry digital data to and from the computer system 900) are example forms of transmission media.

[0091] Computer system 900 may send messages and receive data, including program code, through the network(s), network links, and communications interface 922. In the Internet example, a server may transmit the requested code for an application program through the Internet, an ISP, a local network, and communications interface 922. The received code may be executed by processor 904 as it is received and / or stored in storage device 914, or other non-volatile storage, for later execution.

[0092] Each process, method and algorithm described in the previous sections can be implemented in a code component executed by one or more computer systems or computer processors including computer hardware and automated in whole or in part by these code components. The one or more computer systems or computer processors can also operate to support the carrying out of related operations in a "cloud computing" environment, or operate as "software as a service" (SaaS). These processes and algorithms can be implemented in part or in whole in a dedicated circuit. The various features and processes described above can be used independently of each other, or can be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of the present disclosure, and some method boxes or process boxes can be omitted in some embodiments. The methods and processes described herein are also not limited to any specific order, and the boxes or states related to these methods and processes can be carried out in other appropriate orders, or can be carried out in parallel, or in some other way. Boxes or states can be added to or removed from the disclosed example embodiments. The carrying out of certain operations or processes can be distributed to multiple computer systems or computer processors so that it does not reside only in a single machine, but is deployed across multiple machines.

[0093] As used herein, circuits can be implemented using any form of hardware, software or a combination thereof. For example, one or more processors, controllers, ASIC, PLA, PAL, CPLD, FPGA, logic components, software routines or other mechanisms can be implemented to form circuits. In an embodiment, the various circuits described herein can be implemented as discrete circuits, or the described functions and features can be shared partially or entirely among one or more circuits. Even if various features or functional elements can be described or advocated separately as separate circuits, these features and functions can also be shared between one or more common circuits, and this description should not require or imply that separate circuits are needed to implement such features or functions. In the case of using software to implement circuits in whole or in part, such software can be implemented to operate together with a computing system or processing system (such as computer system 900) that can perform the functions described about the software.

[0094] As used herein, the term "or" may be interpreted in an inclusive or exclusive sense. Furthermore, descriptions of resources, operations, or structures in the singular should not be construed to exclude the plural. Unless expressly stated otherwise, or otherwise understood within the context in which it is used, conditional language (such as, among others, "can," "could," "might," or "may") is generally intended to convey that certain embodiments include and other embodiments do not include certain features, elements, and / or steps.

[0095] Unless otherwise expressly stated, the terms and phrases used in this document and their variations should be interpreted as open-ended rather than restrictive. Adjectives such as "conventional", "traditional", "normal", "standard", "known" and terms of similar meaning should not be interpreted as limiting the items described to items available for a given time period or at a given time, but should be understood to cover conventional, traditional, normal or standard technologies that may be available or known at any time now or in the future. In some cases, the presence of broad words and phrases such as "one or more", "at least", "but not limited to" or other similar phrases should not be understood to mean that narrower situations are intended or required where such broad phrases may not be present.

Claims

1. A computer-implemented method comprising: Programming, by a processor, one or more clauses of a Boolean expression written in negated disjunctive normal form (DNF) for a K-satisfiability (K-SAT) problem into a ternary content addressable memory (TCAM) array, the TCAM array comprising columns and rows of TCAM cells, wherein each clause of the Boolean expression is programmed into a corresponding row of the TCAM array, and wherein each occurring variable of each clause is mapped to a corresponding TCAM cell in the row, and wherein each non-occurring variable is programmed as a don't care value; applying, by the processor as input, to the TCAM array along the columns, an interpretation including one or more binary variables desired for solving the Boolean expression; Returning a binary value for each clause by the processor; randomly selecting a matching match line by the processor; determining, by the processor, a selected clause from one or more violating clauses; and The interrupt count for each variable of the selected clause is used by the processor to change one or more literals within the interpretation.

2. The computer-implemented method of claim 1, wherein: Programming each clause of the Boolean expression written in DNF for the K-SAT problem includes programming a bit value including 0, 1, or X into each cell within each TCAM array, where X represents a don't care value.

3. The computer-implemented method of claim 2, wherein: Each negation of each literal in each clause is assigned a place value of 0, each non-negation of each literal in each clause is assigned a place value of 1, and each missing variable in each clause is assigned a place value of X.

4. The computer-implemented method of claim 1, wherein: Each match line returns a high value if the interpretation violates the clause stored in the corresponding row of the TCAM array, and wherein each match line returns a low value if the interpretation satisfies the clause stored in the corresponding row of the TCAM array.

5. The computer-implemented method of claim 4, wherein: A random multiple match resolver (SMMR) randomly selects a high-order value from a matchline Boolean vector to return a one-hot vector including only one high value, and wherein the SMMR sets all unselected matchlines in the Boolean vector to zero.

6. The computer-implemented method of claim 5, wherein: The one-hot vector is sent to a static random access memory (SRAM).

7. The computer-implemented method of claim 6, wherein: Each row of the SRAM is programmed with each clause of the Boolean expression for the K-SAT problem.

8. The computer-implemented method of claim 1 , further comprising: A Walk-satisfiability (WalkSAT) algorithm is applied by the processor to the selected clauses, wherein the WalkSAT algorithm is used to determine an interruption count for each variable by applying a changed state of each variable as an interpretation to each clause.

9. The computer-implemented method of claim 2, wherein: The interruption count is determined by varying a variable to create a reciprocal value and applying the reciprocal value of the variable to each clause to determine the number of clauses violated.

10. A computer-implemented method for solving a K-satisfiability (K-SAT) problem using a content addressable memory (CAM), comprising: Programming, by a processor, one or more clauses of a Boolean expression written in negated disjunctive normal form (DNF) for a K-SAT problem into a ternary CAM (TCAM) array, the TCAM array comprising columns and rows of TCAM cells, wherein each clause of the Boolean expression is programmed into a corresponding row of the TCAM array, and wherein each occurring variable of each clause is mapped to a corresponding TCAM cell in the row, and wherein each non-occurring variable is programmed as a don't care value; applying, by the processor as input, to the TCAM array along the columns, an interpretation including one or more binary variables desired for solving the Boolean expression; returning, by the processor, a binary value for each violating clause; applying, by the processor, a matrix multi-vector multiplication to one or more values ​​stored in a dot product engine (DPE) to determine which variable contributes most to each violating clause; and One or more literals within the interpretation are changed by the processor based on which variable contributes most to each violating clause.

11. The computer-implemented method of claim 10, wherein: The DPE assigns a value of 1 to each variable present in a clause and a value of 0 to each variable not present in the clause.

12. The computer-implemented method of claim 10, further comprising: A sense operation is used by the processor to determine when to terminate changing one or more words within the interpretation, wherein the sense operation senses the 1's otherwise encoded in each row of the DPE.

13. The computer-implemented method of claim 10, wherein: The one or more literals include a variable or a negation of a variable, and wherein the one or more literals within the interpretation are changed using a selection block configured to use an interrupt count to determine which of the one or more literals within the interpretation to change.

14. The computer-implemented method of claim 10, further comprising: One or more violation clause indexes are randomly selected by the processor, wherein the index corresponds to a Boolean true value in the vector returned from the TCAM.

15. A circuit for solving a K-satisfiability (K-SAT) problem, the circuit comprising: a ternary content addressable memory (TCAM) configured to determine whether an interpretation of one or more clauses comprising a Boolean expression is satisfied, the Boolean expression being written in negated disjunctive normal form (DNF); a random multi-match resolver (SMMR) communicatively coupled to the TCAM, wherein the SMMR is configured to randomly select a high-value match line from one or more high-value match lines communicatively coupled to each row of the TCAM; and A static random access memory (SRAM) is communicatively coupled to the SMMR, wherein the SRAM is configured to return a violating clause to a select block.

16. The circuit of claim 15, wherein: The selection block is configured to apply each variable of the interpretation to each row of the TCAM to determine which clause is satisfied.

17. The circuit of claim 15, wherein: The SMMR is configured to return a one-hot vector that includes only one dimension representing high values.

18. The circuit of claim 15, wherein: Each high value from a matching line indicates a violation of the clause.

19. A non-transitory computer-readable storage medium storing instructions which, when executed by a processor, cause the processor to perform the following operations: One or more clauses of a Boolean expression written in negated disjunctive normal form (DNF) for a K-satisfiability (K-SAT) problem are programmed into a ternary content addressable memory (TCAM) array, the TCAM array comprising columns and rows of TCAM cells, wherein programming each clause of the Boolean expression to a corresponding row of the TCAM array, and wherein each occurring variable of each clause is mapped to a corresponding TCAM cell in the row, and wherein each non-occurring variable is programmed as a don't care value; applying as input a first interpretation including one or more binary variables desired for solving the Boolean expression to the TCAM array along the columns; Returns a binary value for each clause; Randomly select one or more violation clause indexes; determining a break count for each variable of a violation clause; and When at least one clause of the Boolean expression is not satisfied, one or more variables within the first interpretation are changed.

20. The non-transitory computer readable storage medium of claim 19, wherein: One or more literals within the interpretation are changed using a selection block configured to use the interrupt count to determine which variable or negation of a variable to change to an inverse form.

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