A semiconductor device and a method of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a gate electrode, a field plate, and an etch stop layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than a bandgap of the first nitride semiconductor layer. The third nitride semiconductor layer is doped with a dopant and disposed on the second nitride semiconductor layer. The gate electrode is disposed on the third nitride semiconductor layer. The field plate covers a portion of the gate electrode. The etch stop layer is disposed between the gate electrode and the field plate.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a gate electrode having an extension. Background Technology

[0002] Components containing direct bandgap semiconductors, such as semiconductor components containing III-V materials or III-V compounds (category: III-V compounds), can operate or function under a variety of conditions or in a variety of environments (e.g., at different voltages and frequencies).

[0003] Semiconductor components may include heterojunction bipolar transistors (HBTs), heterojunction field effect transistors (HFETs), high-electron-mobility transistors (HEMTs), and modulation-doped field effect transistors (MODFETs), etc. Summary of the Invention

[0004] According to some embodiments of this disclosure, a semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a gate electrode, a field plate, and an etch stop layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer is doped with a dopant and is disposed on the second nitride semiconductor layer. The gate electrode is disposed on the third nitride semiconductor layer. The field plate covers a portion of the gate electrode. The etch stop layer is disposed between the gate electrode and the field plate.

[0005] According to some embodiments of this disclosure, a method of manufacturing a semiconductor device includes providing a substrate. The method also includes forming a first nitride semiconductor layer on the substrate. The method further includes forming a second nitride semiconductor layer on the first nitride semiconductor layer, the second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer. Additionally, the method includes forming a third nitride semiconductor layer on the second nitride semiconductor layer, the third nitride semiconductor layer being doped with a dopant. The method also includes forming a gate electrode on the third nitride semiconductor layer. The method further includes forming an etch stop layer on the gate electrode. The method also includes forming an etch stop layer partially covered by a field plate.

[0006] According to some embodiments of this disclosure, a semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a gate electrode, a dielectric layer, an etch stop layer, and a field plate. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer is doped with a dopant and is disposed on the second nitride semiconductor layer. The gate electrode is disposed on the third nitride semiconductor layer. The dielectric layer covers the gate electrode and the third nitride semiconductor layer. The etch stop layer covers the dielectric layer. The field plate covers the etch stop layer.

[0007] This disclosure provides a semiconductor device having an etch stop layer between a field plate and a gate electrode. The etch stop layer can prevent the dielectric layer beneath the spacers from being damaged during the etching process used to define spacers, thus avoiding performance degradation of the field plate. Furthermore, the etch stop layer can also be used to form an air gap, further resulting in a relatively low dielectric constant for the environment beneath the field plate, thereby further improving the performance of the field plate. Attached Figure Description

[0008] When with attachment Figure 1 When reading the following detailed description, various aspects of this disclosure can be readily understood from it. It has been carefully considered that the various features may not be drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 2 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 3 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 4 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 5 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0014] Figure 6 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0015] Figure 7 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 8This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0017] Figure 9 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E Various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure are illustrated.

[0019] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F Various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure are illustrated.

[0020] Throughout the accompanying drawings and detailed embodiments, common reference numerals are used to indicate the same or similar components. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In this disclosure, references to forming or setting a first feature on or above a second feature may include embodiments where the first and second features are formed or set in direct contact, and may also include embodiments where an additional feature may be formed or set between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and is not intended to limit the relationship between the various embodiments and / or configurations discussed.

[0022] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0023] This disclosure provides a semiconductor device. The semiconductor device has an etch stop layer between a field plate and a gate electrode. The etch stop layer can prevent the dielectric layer under the spacers from being damaged during the etching process used to define spacers, thus avoiding unsatisfactory performance of the field plate. Furthermore, the etch stop layer can also be used to form an air gap, further allowing the environment under the field plate to have a relatively low dielectric constant, thereby further improving the performance of the field plate.

[0024] Figure 1 This is a cross-sectional view of a semiconductor device 1a according to some embodiments of the present disclosure. The semiconductor device 1a may include a substrate 12, a nitride semiconductor layer 14, a nitride semiconductor layer 16, a nitride semiconductor layer 18, a gate electrode 20, a dielectric layer 30, an etch stop layer 41, spacers 51 and 52, an electrode 61 (e.g., a source electrode), an electrode 62 (e.g., a drain electrode), a field plate 611, and an interlayer dielectric layer 70.

[0025] Substrate 12 may comprise, but is not limited to, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. Substrate 12 may comprise, but is not limited to, sapphire, silicon-on-insulator (SOI), or other suitable materials. Substrate 12 may have a surface 12s1 (upper surface). The normal direction of surface 12s1 of substrate 12 may be approximately parallel to the Y-axis.

[0026] Semiconductor device 1a may also include a buffer layer. The buffer layer may be disposed on substrate 12. The buffer layer may be configured to reduce defects caused by lattice mismatch between substrate 12 and nitride semiconductor layer 14.

[0027] A nitride semiconductor layer 14 (or channel layer) may be disposed on the substrate 12. The nitride semiconductor layer 14 may comprise a group III-V layer. The nitride semiconductor layer 14 may comprise, but is not limited to, group III nitrides, such as the compound InaAlbGa1-a-bN, where a+b≦1. The group III nitride may further comprise, but is not limited to, the compound AlaGa(1-a)N, where a≦1. The nitride semiconductor layer 14 may comprise a gallium nitride (GaN) layer. The bandgap of GaN is approximately 3.4 eV.

[0028] A nitride semiconductor layer 16 (or barrier layer) may be disposed on the nitride semiconductor layer 14. The nitride semiconductor layer 16 may comprise a group III-V layer. The nitride semiconductor layer 16 may comprise, but is not limited to, group III nitrides, such as the compound InaAlbGa1-a-bN, where a+b≦1. The group III nitride may further comprise, but is not limited to, the compound AlaGa(1-a)N, where a≦1. The bandgap of the nitride semiconductor layer 16 may be greater than the bandgap of the nitride semiconductor layer 14. The nitride semiconductor layer 16 may comprise an aluminum gallium nitride (AlGaN) layer. The bandgap of AlGaN is approximately 4.0 eV.

[0029] A heterojunction can be formed between the nitride semiconductor layer 16 and the nitride semiconductor layer 14, and the polarization of the heterojunction forms a two-dimensional electron gas (2DEG) region in the nitride semiconductor layer 14.

[0030] A nitride semiconductor layer 18 (or depletion layer) may be disposed on the nitride semiconductor layer 16. The nitride semiconductor layer 18 may be in direct contact with the nitride semiconductor layer 16. The nitride semiconductor layer 18 may be disposed between the gate electrode 20 and the nitride semiconductor layer 16. The nitride semiconductor layer 18 may be doped with dopants. The nitride semiconductor layer 18 may contain p-type dopant. The nitride semiconductor layer 18 may contain a p-type doped GaN layer, a p-type doped AlGaN layer, a p-type doped AlN layer, or other suitable III-V group layers. The p-type dopant may contain magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd). The nitride semiconductor layer 18 may be configured to control the concentration of 2DEG in the nitride semiconductor layer 14. The nitride semiconductor layer 18 may be used to deplete the 2DEG directly beneath the nitride semiconductor layer 18. The nitride semiconductor layer 18 may have a surface 18s1 (or upper surface) and a surface 18s2 (or side surface). The surface 18s2 of the nitride semiconductor layer 18 may extend between the surface 18s1 of the nitride semiconductor layer 18 and the upper surface of the nitride semiconductor layer 16.

[0031] Gate electrode 20 may be disposed on nitride semiconductor layer 16. Gate electrode 20 may be disposed on nitride semiconductor layer 18. Gate electrode 20 may be disposed on surface 18s1 of nitride semiconductor layer 18. Gate electrode 20 may be disposed between electrode 62 and electrode 61. Gate electrode 20 may comprise a metal. Gate electrode 20 may comprise titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and their compounds (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloys (Al-Cu)), or other suitable materials. Gate electrode 20 may have surface 20s1 (or upper surface) and surface 20s2 (or side surface). Surface 20s2 of gate electrode 20 may extend between surface 18s1 of nitride semiconductor layer 18 and surface 20s1 of gate electrode 20. The nitride semiconductor layer 18 and the gate electrode 20 can define a corner c1. The surface 18s1 of the nitride semiconductor layer 18 and the surface 20s2 of the gate electrode 20 can define a corner c1.

[0032] A dielectric layer 30 may be disposed on the gate electrode 20. The dielectric layer 30 may contact the surface 20s1 of the gate electrode 20. The dielectric layer 30 may contact the surface 20s2 of the gate electrode 20. The dielectric layer 30 may be disposed on the nitride semiconductor layer 18. The dielectric layer 30 may contact the surface 18s1 of the nitride semiconductor layer 18. The dielectric layer 30 may contact the surface 18s2 of the nitride semiconductor layer 18. The dielectric layer 30 may be disposed on the nitride semiconductor layer 16. The dielectric layer 30 may contact the nitride semiconductor layer 16. The dielectric layer 30 may be conformally disposed on the nitride semiconductor layer 16, the nitride semiconductor layer 18, and the gate electrode 20. The dielectric layer 30 may cover corner c1. The dielectric layer 30 may extend to electrode 61. The dielectric layer 30 may extend to electrode 62. The dielectric layer 30 may be configured to adjust the dielectric constant between the nitride semiconductor layer 18 and the field plate 611. The dielectric layer 30 may be configured to adjust the dielectric constant between the gate electrode 20 and the field plate 611. The dielectric layer 30 may have a surface 30s1 (or a top surface) and a surface 30s2 (or a side surface). The surface 30s2 of the dielectric layer 30 may extend between the surface 30s1 of the dielectric layer 30 and the surface 18s1 of the nitride semiconductor layer 18. The dielectric layer 30 may contain a nitride. The dielectric layer 30 may contain silicon nitride. The dielectric layer 30 may contain an oxide. The dielectric layer 30 may contain silicon oxide. The dielectric layer 30 may contain oxynitride. The dielectric layer 30 may contain silicon oxynitride. The dielectric layer 30 may contain other suitable materials.

[0033] An etch stop layer 41 may be disposed on the dielectric layer 30. The etch stop layer 41 may contact the surface 30s1 of the dielectric layer 30. The etch stop layer 41 may contact the surface 30s2 of the dielectric layer 30. The etch stop layer 41 may be separated from the gate electrode 20 by the dielectric layer 30. The etch stop layer 41 may be separated from the nitride semiconductor layer 18 by the dielectric layer 30. The etch stop layer 41 may be separated from the nitride semiconductor layer 16 by the dielectric layer 30. The etch stop layer 41 may cover corner c1. The etch stop layer 41 may be separated from corner c1 by the dielectric layer 30. The etch stop layer 41 may be conformally disposed on the dielectric layer 30. The etch stop layer 41 may be configured to protect the surface 30s1 of the dielectric layer 30, preventing thickness loss of the surface 30s1 due to the etching process. The etch stop layer 41 may be configured to adjust the dielectric constant between the field plate 611 and the nitride semiconductor layer 18 within a desired range. The etch stop layer 41 can be configured to adjust the dielectric constant between the field plate 611 and the gate electrode 20 within a desired range. The material of the etch stop layer 41 may be different from the material of the dielectric layer 30. The material of the etch stop layer 41 and the material of the dielectric layer 30 may have different etch selectivity ratios for the same etchant. The material of the etch stop layer 41 may be different from the material of the spacer 51. The material of the etch stop layer 41 and the material of the spacer 51 may have different etch selectivity ratios for the same etchant. The etch stop layer 41 may contain a metal nitride. The etch stop layer 41 may contain aluminum nitride. The etch stop layer 41 may contain a metal oxide. The etch stop layer 41 may contain aluminum oxide. The etch stop layer 41 may contain gallium oxide. The etch stop layer 41 may contain indium oxide. The etch stop layer 41 may contain indium tin oxide.

[0034] Spacer 51 can be disposed on the surface 20s2 of the gate electrode 20. Spacer 51 can be disposed on the surface 30s2 of the dielectric layer 30. Spacer 51 can be disposed on the surface 18s1 of the nitride semiconductor layer 18. Spacer 51 can separate the surface 20s2 of the gate electrode 20 from the field plate 611. Spacer 51 can be disposed between the field plate 611 and the nitride semiconductor layer 18 along the X-axis direction. Spacer 51 can be disposed between the field plate 611 and the nitride semiconductor layer 18 along the Y-axis direction. Spacer 51 can be disposed between the field plate 611 and the gate electrode 20 along the X-axis direction. Spacer 51 can be disposed between the field plate 611 and the dielectric layer 30 along the X-axis direction. Spacer 51 can be disposed between the field plate 611 and the dielectric layer 30 along the Y-axis direction. Spacer 51 can be disposed between the field plate 611 and the etch stop layer 41 along the X-axis direction. Spacer 51 may be disposed between field plate 611 and etch stop layer 41 along the Y-axis. Spacer 51 may be disposed between gate electrode 20 and electrode 61. The height of the top of spacer 51 may be approximately the same as the height of surface 41s1 (or upper surface) of etch stop layer 41. Spacer 51 may be configured to adjust the dielectric constant between nitride semiconductor layer 18 and field plate 611. Spacer 51 may be configured to adjust the dielectric constant between gate electrode 20 and field plate 611. The material of spacer 51 may be different from the material of dielectric layer 30. The dielectric constant of spacer 51 may be different from the dielectric constant of dielectric layer 30. The dielectric constant of spacer 51 may be less than the dielectric constant of dielectric layer 30. Spacer 51 may contain oxide. Spacer 51 may contain silicon oxide. Spacer 51 may contain nitride. Spacer 51 may contain silicon nitride. Spacer 51 may contain oxynitride. Spacer 51 may comprise silicon oxynitride. Spacer 51 may comprise other suitable materials. The difference in etch selectivity between the material of spacer 51 and the material of dielectric layer 30 may be smaller than the difference in etch selectivity between the material of spacer 51 and the material of etch stop layer 41. The magnitude of etch selectivity refers to the rate at which a material is removed by the same etchant. When the difference in etch selectivity between the two materials is small, it means that the difference in the rate at which the two materials are removed by the same etchant is small. When the difference in etch selectivity between the two materials is large, it means that the difference in the rate at which the two materials are removed by the same etchant is large.

[0035] Spacer 52 may be disposed on surface 20s2 of gate electrode 20. Spacer 52 may be disposed on surface 30s2 of dielectric layer 30. Spacer 52 may be disposed on surface 18s1 of nitride semiconductor layer 18. Spacer 52 may be disposed between gate electrode 20 and electrode 62. The material of spacer 52 may be the same as the material of spacer 51.

[0036] Electrode 61 may be disposed on nitride semiconductor layer 16. Electrode 61 may be in contact with nitride semiconductor layer 16. Electrode 61 may comprise, for example, but not limited to, a conductive material. The conductive material may comprise metals, alloys, doped semiconducting materials (e.g., doped crystalline silicon), or other suitable conductive materials such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials. Electrode 61 may comprise a multilayer structure. For example, electrode 61 may comprise a structure of two layers of different materials. Electrode 61 may serve as a source electrode.

[0037] Electrode 61 may have a field plate 611. Field plate 611 may extend toward gate electrode 20. Field plate 611 may be disposed on surface 41s1 of etch stop layer 41. Field plate 611 may contact surface 41s1 of etch stop layer 41. Field plate 611 may be disposed on surface 30s1 of dielectric layer 30. Electrode 61 may be disposed on surface 30s2 of dielectric layer 30. Field plate 611 may be disposed on spacer 51. Field plate 611 may extend from electrode 61 to surface 41s1 of etch stop layer 41. Field plate 611 may cover a portion of nitride semiconductor layer 18. Field plate 611 may cover a portion of gate electrode 20. Field plate 611 may be configured to adjust the electric field distribution of semiconductor device 1a. Field plate 611 may be configured to adjust the electrical parameters of semiconductor device 1a.

[0038] Electrode 62 may be disposed on nitride semiconductor layer 16. Electrode 62 may be in contact with nitride semiconductor layer 16. Electrode 62 may comprise, for example, but not limited to, a conductive material. The conductive material may comprise metals, alloys, doped semiconducting materials (e.g., doped crystalline silicon), or other suitable conductive materials such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials. Electrode 62 may comprise a multilayer structure. For example, electrode 62 may comprise a structure of two layers of different materials. Electrode 62 may serve as a drain electrode.

[0039] An interlayer dielectric layer 70 may be disposed on the nitride semiconductor layer 16. The interlayer dielectric layer 70 may cover the gate electrode 20. The interlayer dielectric layer 70 may contain a high-k dielectric material. The k-value of the high-k dielectric material may be greater than about 5. The interlayer dielectric layer 70 may contain a low-k dielectric material. The k-value of the low-k dielectric material may be less than about 5. The interlayer dielectric layer 70 may contain oxides, nitrides, oxynitrides, or other suitable materials. The interlayer dielectric layer 70 may comprise multiple dielectric layers. The materials of the dielectric layers may be partially the same. The materials of the dielectric layers may be partially different. There may be incomplete boundaries between adjacent dielectric layers (e.g., the boundary of one part of the interface can be confirmed by a scanning electron microscope (SEM), while the boundary of another part of the interface cannot be observed by SEM). There may be substantially no boundary between adjacent dielectric layers. There may be no boundary between the interlayer dielectric layer 70 and the spacer 52.

[0040] In this embodiment, an etch stop layer 41 may be disposed between the field plate 611 and the dielectric layer 30. The etch stop layer 41 can protect the dielectric layer 30 from being damaged by the etching process during the etching process used to define the contour of the spacer 51, thereby affecting the performance of the field plate 611.

[0041] Figure 2 This is a cross-sectional view of a semiconductor device 1b according to some embodiments of the present disclosure. Figure 2 The semiconductor device 1b can be used with Figure 1 It is similar to the semiconductor device 1a, except as described below.

[0042] Semiconductor device 1b may include an etch stop layer 42. The etch stop layer 42 may not cover the surface 30s1 of the dielectric layer 30. The etch stop layer 42 may have a surface 42s1 (or an upper surface). The surface 42s1 of the etch stop layer 42 may contact the interlayer dielectric layer 70. The height of the surface 42s1 of the etch stop layer 42 may be substantially the same as the height of the surface 30s1 of the dielectric layer 30. The height of the surface 42s1 of the etch stop layer 42 may be substantially the same as the height of the top of the spacer 51. The roughness of the surface 30s1 of the dielectric layer 30 may be different from the roughness of the surface 42s1 of the etch stop layer 42.

[0043] Figure 3 This is a cross-sectional view of a semiconductor device 1c according to some embodiments of the present disclosure. Figure 3 The semiconductor device 1c can be with Figure 1 It is similar to the semiconductor device 1a, except as described below.

[0044] Semiconductor device 1c may include an etch stop layer 43. The etch stop layer 43 may not cover the surface 30s1 of the dielectric layer 30. The etch stop layer 43 may have a surface 43s1 (or an upper surface). The surface 43s1 of the etch stop layer 43 may contact the interlayer dielectric layer 70. The height of the surface 43s1 of the etch stop layer 43 may be lower than the height of the surface 30s1 of the dielectric layer 30. The height of the surface 43s1 of the etch stop layer 43 may be lower than the height of the top of the spacer 51.

[0045] The field plate 611 may have a protrusion 611e1. The protrusion 611e1 may protrude from the field plate 611 toward the substrate 12 along the Y-axis direction. The protrusion 611e1 of the field plate 611 may contact the surface 43s1 of the etch stop layer 43. The field plate 611 may contact the surface 30s2 of the dielectric layer 30. The protrusion 611e1 of the field plate 611 may contact the surface 30s2 of the dielectric layer 30.

[0046] The interlayer dielectric layer 70 may have protrusions 70e. The protrusions 70e may protrude toward the substrate 12 along the Y-axis direction. The protrusions 70e of the interlayer dielectric layer 70 may contact the surface 43s1 of the etch stop layer 43. The protrusions 70e of the interlayer dielectric layer 70 may contact the surface 30s2 of the dielectric layer 30.

[0047] Figure 4 This is a cross-sectional view of a semiconductor device 1d according to some embodiments of the present disclosure. Figure 4 The semiconductor device 1d can be with Figure 1 It is similar to the semiconductor device 1a, except as described below.

[0048] Semiconductor device 1d may include an etch stop layer 44. The etch stop layer 44 may not cover the surface 30s1 of the dielectric layer 30. The etch stop layer 44 may have a surface 44s1 (or an upper surface). Field plate 611 may be spaced apart from the surface 44s1 of the etch stop layer 44.

[0049] The semiconductor device 1d may include an air gap 81. The air gap 81 may be located between the field plate 611 and the surface 44s1 of the etch stop layer 44. The field plate 611 may be separated from the surface 44s1 of the etch stop layer 44 by the air gap 81.

[0050] The air gap 81 has a relatively small dielectric constant. The dielectric constant between the field plate 611 and the nitride semiconductor layer 18 can be adjusted by adjusting the length of the air gap 81 along the Y-axis. The dielectric constant between the field plate 611 and the gate electrode 20 can also be adjusted by adjusting the length of the air gap 81 along the Y-axis. Because the air gap 81 has a relatively small dielectric constant, the field plate 611 can relatively better adjust the electric field of the semiconductor device 1d, thereby improving the performance of the semiconductor device 1d.

[0051] Figure 5 This is a cross-sectional view of a semiconductor device 1e according to some embodiments of the present disclosure. Figure 5 The semiconductor device 1e can be used with Figure 1 It is similar to the semiconductor device 1a, except as described below.

[0052] The semiconductor device 1e may include an etch stop layer 45. The etch stop layer 45 may not cover the surface 30s1 of the dielectric layer 30. The etch stop layer 45 may have a surface 45s1 (or an upper surface).

[0053] The field plate 611 may have a protrusion 611e2. The protrusion 611e2 may protrude from the field plate 611 toward the substrate 12 along the Y-axis direction. The protrusion 611e2 of the field plate 611 may be spaced apart from the surface 45s1 of the etch stop layer 45. The protrusion 611e2 of the field plate 611 may contact the surface 30s2 of the dielectric layer 30.

[0054] Semiconductor device 1e may include an air gap 82. The air gap 82 may be located between the field plate 611 and the surface 45s1 of the etch stop layer 45. The protrusion 611e2 of the field plate 611 may be separated from the surface 45s1 of the etch stop layer 45 by the air gap 82.

[0055] The air gap 82 has a relatively small dielectric constant. The dielectric constant between the field plate 611 and the nitride semiconductor layer 18 can be adjusted by adjusting the length of the air gap 82 along the Y-axis. The dielectric constant between the field plate 611 and the gate electrode 20 can also be adjusted by adjusting the length of the air gap 82 along the Y-axis. Because the air gap 82 has a relatively small dielectric constant, the field plate 611 can relatively better adjust the electric field of the semiconductor device 1e, thereby improving the performance of the semiconductor device 1e.

[0056] Figure 6 This is a cross-sectional view of a semiconductor device 1f according to some embodiments of the present disclosure. Figure 6 The semiconductor device 1f can be with Figure 1 It is similar to the semiconductor device 1a, except as described below.

[0057] The semiconductor device 1f may include an etch stop layer 46. The etch stop layer 46 may be spaced apart from the surface 30s2 of the dielectric layer 30. A portion of the surface 30s3 may not be covered by the etch stop layer 46.

[0058] Semiconductor device 1f may include an air gap 83. An etch stop layer 46 may be separated from the surface 30s2 of dielectric layer 30 via the air gap 83. A protrusion 611e2 of field plate 611 may be exposed to the air gap 83. The surface 30s2 of dielectric layer 30 may be exposed to the air gap 83. Dielectric layer 30 may have a surface 30s3 substantially parallel to surface 30s1. The height of surface 30s3 may be lower than the height of surface 30s1. The surface 30s3 of dielectric layer 30 may be exposed to the air gap 83. The air gap 83 may have a length L1 along the Y-axis direction.

[0059] Semiconductor device 1f may include an air gap 84. A protrusion 70e of the interlayer dielectric layer 70 may be exposed to the air gap 84. The air gap 84 may have a length L2 along the Y-axis. The length L1 may be different from the length L2. The length L1 may be greater than the length L2. The length of the protrusion 611e2 of the field plate 611 along the Y-axis may be different from the length of the protrusion 70e of the interlayer dielectric layer 70.

[0060] Figure 7 This is a cross-sectional view of a semiconductor device 1g according to some embodiments of the present disclosure. Figure 7 1g of semiconductor device can be used with Figure 1 It is similar to the semiconductor device 1a, except as described below.

[0061] The semiconductor device 1g may include an etch stop layer 47. The etch stop layer 47 may have a surface 47s1 (or an upper surface).

[0062] The semiconductor device 1g may include spacers 51'. The height of the top of spacer 51' may differ from the height of the surface 30s1 of dielectric layer 30. The height of the top of spacer 51' may differ from the height of the surface 47s1 of etch stop layer 47. The height of the top of spacer 51' may be lower than the height of the surface 47s1 of etch stop layer 47. A portion of etch stop layer 47 may not be covered by spacers 51'.

[0063] The semiconductor device 1g may include spacers 52'. The height of the top of the spacers 52' may be lower than the height of the surface 47s1 of the etch stop layer 47.

[0064] Electrode 61 may have a stepped structure 61p. The stepped structure 61p may be disposed on spacer 51'.

[0065] Figure 8 This is a cross-sectional view of a semiconductor device 1h according to some embodiments of the present disclosure. Figure 8 The semiconductor device can be connected to the semiconductor device in 1 hour. Figure 1 It is similar to the semiconductor device 1a, except as described below.

[0066] The semiconductor device 1h may include an etch stop layer 48. The etch stop layer 48 may have a surface 48s1. The surface 48s1 of the etch stop layer 48 may be substantially parallel to the surface 30s2 of the dielectric layer 30. The surface 48s1 of the etch stop layer 48 may be recessed from the edge of the spacer 51 along the X-axis toward the gate electrode 20.

[0067] The field plate 611 may have a protrusion 611e3. The protrusion 611e3 may extend from the electrode 61 along the X-axis toward the nitride semiconductor layer 18. The protrusion 611e3 may contact the surface 48s1 of the etch stop layer 48.

[0068] Figure 9 This is a cross-sectional view of a semiconductor device 1i according to some embodiments of the present disclosure. Figure 9 The semiconductor device 1i can be used with Figure 1 It is similar to the semiconductor device 1a, except as described below.

[0069] Semiconductor device 1i may include an etch stop layer 49. The etch stop layer 49 may have a surface 49s1. The surface 49s1 of the etch stop layer 49 may be substantially parallel to the surface 30s2 of the dielectric layer 30. The surface 49s1 of the etch stop layer 49 may be recessed from the edge of the spacer 51 along the X-axis toward the gate electrode 20.

[0070] Semiconductor device 1i may include an air gap 85. The air gap 85 may be located between the surface 49s1 of the etch stop layer 49 and the field plate 611. The field plate 611 may be separated from the surface 49s1 of the etch stop layer 49 by the air gap 85.

[0071] Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E Various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure are illustrated.

[0072] See Figure 10AA substrate 12 may be provided. Nitride semiconductor layers 14, 16, and 18, and a gate electrode 20 are formed on the substrate 12. The nitride semiconductor layers 14, 16, and 18, and the gate electrode 20 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable techniques. The patterns of the nitride semiconductor layers 14, 16, and 18, and the gate electrode 20 may be formed using photolithography, etching, and other suitable processes.

[0073] See Figure 10B A dielectric layer 30 is formed, which covers the nitride semiconductor layer 16, the nitride semiconductor layer 18, and the gate electrode 20. An etch stop layer 41 is formed on the dielectric layer 30. The dielectric layer 30 and the etch stop layer 41 can be formed by ALD, CVD, PVD, or other suitable processes.

[0074] See Figure 10C Dielectric material 50 is formed on etch stop layer 41. Dielectric material 50 can be formed by CVD, PVD, ALD or other suitable processes.

[0075] See Figure 10D An etching process is performed to remove a portion of the dielectric material 50 to form spacers 51 and 52. During this stage, the etch stop layer 41 protects the dielectric layer 30 from damage caused by the etching process. The etching process may include dry etching or other suitable processes.

[0076] See Figure 10E Electrodes 61 and 62 and an interlayer dielectric layer 70 are formed to obtain, as shown in the figure. Figure 1 The semiconductor device 1a shown. Electrodes 61, 62 and interlayer dielectric layer 70 can be formed by CVD, PVD, ALD or other suitable processes.

[0077] In the comparative example semiconductor device, no etch stop layer was formed. During the execution of... Figure 10DDuring the etching process, because the difference in etch selectivity between the materials of the spacer layer and the dielectric layer is relatively small, the dielectric layer will suffer losses due to the etching process when an etch stop layer is not formed. This affects the electric field distribution between the field plate and the depletion layer, resulting in the semiconductor device's electrical performance not meeting requirements. In this embodiment, the difference in etch selectivity between the materials of the etch stop layer 41 and the dielectric material 50 is relatively large. Therefore, the etch stop layer 41 has relatively low losses during the process of defining the contour of the spacer 51. Thus, the dielectric layer 30, when performing the process as described above... Figure 10D There is no loss during the process. Therefore, the field plate 611 can have better performance in controlling the electric field distribution of the semiconductor device 1a.

[0078] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F Various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure are illustrated.

[0079] See Figure 11A A substrate 12 may be provided. Nitride semiconductor layers 14, 16, and 18, and a gate electrode 20 are formed on the substrate 12. The nitride semiconductor layers 14, 16, and 18, and the gate electrode 20 may be formed using CVD, PVD, ALD, or other suitable techniques. The patterns of the nitride semiconductor layers 14, 16, and 18, and the gate electrode 20 may be formed using photolithography, etching, and other suitable processes.

[0080] See Figure 11B A dielectric layer 30 is formed, which covers the nitride semiconductor layer 16, the nitride semiconductor layer 18, and the gate electrode 20. An etch stop layer 42 is formed on the dielectric layer 30. The dielectric layer 30 and the etch stop layer 42 can be formed by ALD, CVD, PVD, or other suitable processes.

[0081] See Figure 11C Dielectric material 50 is formed on etch stop layer 42. Dielectric material 50 can be formed by CVD, PVD, ALD or other suitable processes.

[0082] See Figure 11DAn etching process is performed to remove a portion of the dielectric material 50 to form spacers 51 and 52. The etchant used in the etching process can be controlled, as can the amount of dielectric material 50 removed. The execution time of the etching process can also be controlled, further controlling the amount of dielectric material 50 removed. The top height of spacer 51 can be lower than the height of the surface 42s1 of the etch stop layer 42. The top height of spacer 52 can also be lower than the height of the surface 42s1 of the etch stop layer 42. During this stage, the etch stop layer 42 can protect the dielectric layer 30, preventing damage to the dielectric layer 30 due to the etching process. The etching process may include dry etching or other suitable processes.

[0083] See Figure 11E An etching process is performed to remove a portion of the etch stop layer 42, exposing the surface 30s1 of the dielectric layer 30. The height of the surface 30s1 of the dielectric layer 30 can be approximately the same as the height of the surface 42s1 of the etch stop layer 42. Because the difference in etch selectivity between the materials of the etch stop layer 42 and the dielectric layer 30 is relatively large, the loss of the dielectric layer 30 in this step is relatively small.

[0084] See Figure 11F Electrodes 61 and 62 and an interlayer dielectric layer 70 are formed to obtain, as shown in the figure. Figure 2 The semiconductor device 1b shown. Electrodes 61, 62 and interlayer dielectric layer 70 can be formed by CVD, PVD, ALD or other suitable processes.

[0085] In this embodiment, the etch stop layer 42 has relatively low loss during the process of defining the contour of the spacer 51. Therefore, the dielectric layer 30 performs as follows: Figure 11D There is no loss during the process. Therefore, the field plate 611 can have better performance in controlling the electric field distribution of the semiconductor device 1b.

[0086] After careful consideration, Figure 11E During this stage, a portion of the surface 42s1 of the etch stop layer 42 can be removed to form a shape such as Figure 3 The semiconductor device 1c shown.

[0087] After careful consideration, Figure 11E During this stage, a portion of the surface 42s1 of the etch stop layer 42 can be removed to form an air gap 81, thereby forming a structure as described above. Figure 4 The semiconductor device 1d shown.

[0088] After careful consideration, Figure 11E During this stage, a portion of the surface 42s1 of the etch stop layer 42 can be removed to form an air gap 82, and a protrusion 611e2 can be formed protruding toward the air gap 82 to form a shape such as Figure 5 The semiconductor device 1e shown.

[0089] After careful consideration, Figure 11E During this stage, a portion of the surface 42s1 of the etch stop layer 42 can be removed to form air gaps 83 and 84, thereby forming a structure as described above. Figure 6 The semiconductor device 1f shown.

[0090] After careful consideration, Figure 10D During this stage, more dielectric material 50 can be removed to form spacer layers 51' and 52', to form a structure like... Figure 7 The semiconductor device shown is 1g.

[0091] After careful consideration, Figure 11E During this stage, a portion of the surface 42s1 of the etch stop layer 42 and a portion near the electrode 61 can be removed, and protrusions 611e2 and 611e3 can be formed to create a shape as shown in the figure. Figure 8 The semiconductor device shown is 1h.

[0092] After careful consideration, Figure 11E During this stage, a portion of the surface 42s1 of the etch stop layer 42 and a portion near the electrode 61 can be removed to form air gaps 81 and 85, thereby forming a structure as described above. Figure 9 The semiconductor device 1i shown.

[0093] According to some embodiments of this disclosure, a semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a gate electrode, a field plate, and an etch stop layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer is doped with a dopant and is disposed on the second nitride semiconductor layer. The gate electrode is disposed on the third nitride semiconductor layer. The field plate covers a portion of the gate electrode. The etch stop layer is disposed between the gate electrode and the field plate.

[0094] The semiconductor device may further include a dielectric layer disposed between the etch stop layer and the third nitride semiconductor layer.

[0095] An etch stop layer can cover the upper surface of the dielectric layer.

[0096] The upper surface of the etch stop layer and the upper surface of the dielectric layer can be approximately coplanar.

[0097] The upper surface of the etch stop layer is recessed by the upper surface of the dielectric layer.

[0098] The field plate may have protrusions that project toward the substrate.

[0099] The semiconductor device may further include an air gap located between the field plate and the etch stop layer.

[0100] The plate may have a protrusion that faces the air gap.

[0101] The semiconductor device may further include a first electrode, a field plate extending from the first electrode to the gate electrode, wherein an etch stop layer extends to the first electrode.

[0102] The semiconductor device may further include a first electrode, a field plate extending from the first electrode to the gate electrode, wherein the field plate has a protrusion extending in a direction substantially perpendicular to the normal direction of the upper surface of the substrate.

[0103] The semiconductor device may further include an air gap located between the first electrode and the etch stop layer.

[0104] The semiconductor device may further include spacers disposed between the field plate and the etch stop layer.

[0105] The top of the spacer is located at a first height, and the upper surface of the dielectric layer is located at a second height, which is higher than the first height.

[0106] The field plate may have a stepped structure, which is located above the interface between the spacer and the etch stop layer.

[0107] According to some embodiments of this disclosure, a method of manufacturing a semiconductor device includes providing a substrate. The method also includes forming a first nitride semiconductor layer on the substrate. The method further includes forming a second nitride semiconductor layer on the first nitride semiconductor layer, the second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer. Additionally, the method includes forming a third nitride semiconductor layer on the second nitride semiconductor layer, the third nitride semiconductor layer being doped with a dopant. The method also includes forming a gate electrode on the third nitride semiconductor layer. The method further includes forming an etch stop layer on the gate electrode. The method also includes forming an etch stop layer partially covered by a field plate.

[0108] The method may further include: forming a first dielectric layer on a third nitride semiconductor layer, wherein an etch stop layer is formed on the dielectric layer; forming a second dielectric layer on the etch stop layer; and removing a portion of the second dielectric layer to form a spacer, wherein a field plate is formed on the spacer.

[0109] The method may further include: removing the upper surface of the etch stop layer to expose the first dielectric layer.

[0110] The forming field plate may include a protrusion that protrudes toward the substrate.

[0111] According to some embodiments of this disclosure, a semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a gate electrode, a dielectric layer, an etch stop layer, and a field plate. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a band gap larger than that of the first nitride semiconductor layer. The third nitride semiconductor layer is doped with a dopant and is disposed on the second nitride semiconductor layer. The gate electrode is disposed on the third nitride semiconductor layer. The dielectric layer covers the gate electrode and the third nitride semiconductor layer. The etch stop layer covers the dielectric layer. The field plate covers the etch stop layer.

[0112] The upper surface of the dielectric layer and the upper surface of the etch stop layer can be roughly coplanar.

[0113] The upper surface of the dielectric layer is located at the first height, and the upper surface of the etch stop layer is located at the second height. The first height is higher than the second height.

[0114] The semiconductor device may further include an air gap located between the field plate and the etch stop layer.

[0115] Unless otherwise specified, spatial descriptions such as “above,” “below,” “upward,” “left,” “right,” “downward,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper part,” “above,” and “below” are relative to the orientation indicated in the drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not deviated from by such arrangements.

[0116] As used in this article, the term "vertical" refers to the upward and downward directions, while the term "horizontal" refers to the direction that is transverse to the vertical direction.

[0117] As used herein, the terms “approximately,” “generally,” “roughly,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples of events or situations that occurred precisely or very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value may be considered “generally” the same as or equal to the second value. For example, "generally" vertical can refer to an angular variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0118] If the displacement between two surfaces does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0119] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators.

[0120] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials generally indicate those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than about 10⁴ S / m (e.g., at least 10⁵ S / m or at least 10⁶ S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0121] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly specified.

[0122] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in this disclosure and actual equipment. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A first nitride semiconductor layer is disposed on the substrate; A second nitride semiconductor layer is disposed on the first nitride semiconductor layer and its band gap is larger than that of the first nitride semiconductor layer; A third nitride semiconductor layer is doped with a dopant and disposed on the second nitride semiconductor layer; A gate electrode is disposed on the third nitride semiconductor layer; A field plate that covers a portion of the gate electrode; as well as An etch stop layer is disposed between the gate electrode and the field plate; Including: An interlayer dielectric layer covers the field plate; The first air gap is covered by the field plate; and The second air gap is covered by the interlayer dielectric layer. The first air gap has a first length along a first direction, the second air gap has a second length along the first direction, the first length and the second length are different, and the first direction is parallel to the normal direction of the upper surface of the substrate.

2. The semiconductor device according to claim 1, characterized in that, Including: A dielectric layer is disposed between the etch stop layer and the third nitride semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that, The etch stop layer covers the upper surface of the dielectric layer.

4. The semiconductor device according to claim 1, characterized in that, The field plate has a protrusion that extends toward the substrate.

5. The semiconductor device according to claim 1, characterized in that, The field plate has a protrusion that extends toward the first air gap.

6. The semiconductor device according to claim 2, characterized in that, Including: A first electrode, wherein the field plate extends from the first electrode to the gate electrode, and wherein the etch stop layer extends to the first electrode.

7. The semiconductor device according to claim 2, characterized in that, Including: A spacer is disposed between the field plate and the etch stop layer.

8. The semiconductor device according to claim 7, characterized in that, The top of the spacer is located at a first height, and the upper surface of the dielectric layer is located at a second height, which is higher than the first height.

9. The semiconductor device according to claim 1, characterized in that, The interlayer dielectric layer has a protrusion that extends toward the second air gap.

10. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; A first nitride semiconductor layer is formed on the substrate; A second nitride semiconductor layer is formed on the first nitride semiconductor layer, and its band gap is larger than that of the first nitride semiconductor layer; A third nitride semiconductor layer is formed on the second nitride semiconductor layer, and the third nitride semiconductor layer is doped with a dopant. A gate electrode is formed on the third nitride semiconductor layer; An etch stop layer is formed on the gate electrode; as well as A field plate is formed on a portion of the etch stop layer; The semiconductor device further includes: An interlayer dielectric layer covers the field plate; The first air gap is covered by the field plate; and The second air gap is covered by the interlayer dielectric layer. The first air gap has a first length along a first direction, the second air gap has a second length along the first direction, the first length and the second length are different, and the first direction is parallel to the normal direction of the upper surface of the substrate.

11. The method according to claim 10, characterized in that, Including: A first dielectric layer is formed on the third nitride semiconductor layer, wherein the etch stop layer is formed on the first dielectric layer; A second dielectric layer is formed on the etch stop layer; and A portion of the second dielectric layer is removed to form a spacer, wherein the field plate is formed on the spacer.

12. The method according to claim 11, characterized in that, Including: Remove the upper surface of the etch stop layer to expose the first dielectric layer.

13. The method according to claim 12, characterized in that, Forming the field plate includes forming protrusions that project toward the substrate.

14. A semiconductor device, characterized in that, include: Substrate; A first nitride semiconductor layer is disposed on the substrate; A second nitride semiconductor layer is disposed on the first nitride semiconductor layer and its band gap is larger than that of the first nitride semiconductor layer; A third nitride semiconductor layer is doped with a dopant and disposed on the second nitride semiconductor layer; A gate electrode is disposed on the third nitride semiconductor layer; A dielectric layer covering the gate electrode and the third nitride semiconductor layer; Etch a stop layer to cover the dielectric layer; as well as A field plate covering the etch stop layer; Including: An interlayer dielectric layer covers the field plate; The first air gap is covered by the field plate; and The second air gap is covered by the interlayer dielectric layer. The first air gap has a first length along a first direction, the second air gap has a second length along the first direction, the first length and the second length are different, and the first direction is parallel to the normal direction of the upper surface of the substrate.

15. The semiconductor device according to claim 14, characterized in that, The upper surface of the dielectric layer is located at a first height, and the upper surface of the etch stop layer is located at a second height, with the first height being higher than the second height.

16. The semiconductor device according to claim 14, characterized in that, The field plate has a protrusion that extends toward the air gap.

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