Hardware management implementation methods, devices, and computer equipment for RAID buffers

Abstract

The application relates to a hardware management implementation method, device, computer equipment and storage medium of a RAID buffer, wherein the method comprises the following steps: informing hardware of the starting address and the RAID buffer size of the RAID buffer corresponding to the RAID buffer through a register in a starting process; an FTL module processes according to a conventional strategy in a data writing process; when an NFI module issues a descriptor to hardware, the stripe ID corresponding to a RAID strip is filled in the descriptor, and the RAID buffer is no longer managed; and hardware performs allocation and management of the RAID buffer according to the acquired stripe ID. According to the application, the RAID buffer is managed by using hardware, the operation process of FW is simplified while the speed of the RAID process is improved, and the efficiency of the RAID process is improved.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive technology, and in particular to a hardware management implementation method, apparatus, computer device, and storage medium for RAID buffer. Background Technology

[0002] Redundant Arrays of Independent Disks (RAID) is a technology that combines multiple independent physical hard drives into a single group to provide higher storage performance and data redundancy than a single hard drive. Typical user-grade solid-state drives (SSDs) use RAID 5 technology to provide redundancy protection for user data and improve reliability. When read operations on user data fail after hard decode, read retry, and soft decode LDPC operations, and the user data cannot be recovered, RAID is needed to recover the data. A single RAID recovery requires reading the corresponding positions in the same band, performing an XOR operation with the hardware, and then obtaining the desired data.

[0003] In the current RAID process, buffer management is done by software. For the use case of RAID buffer: when the RAID buffer management is implemented by the FW software and the NFI module is implemented by dual cores, the mutual exclusion lock problem of dual cores managing software resources at the same time needs to be considered. At the same time, when the FW software manages the RAID buffer resources, the software process is relatively complex. When issuing descriptors to the hardware, it is also necessary to calculate and fill in the fields corresponding to the RAID buffer, which leads to low efficiency of the RAID process. Summary of the Invention

[0004] Therefore, it is necessary to provide a hardware management implementation method, apparatus, computer equipment, and storage medium for RAID buffer to address the aforementioned technical problems.

[0005] A hardware management implementation method for RAID buffers, the method comprising:

[0006] During the power-on process, the starting address and size of the RAID buffer corresponding to the RAID buffer are notified to the hardware via registers;

[0007] During the data writing process, the FTL module processes the data according to the conventional strategy;

[0008] When the NFI module issues descriptors to the hardware, it simply fills the stripe ID corresponding to the RAID stripe into the descriptor and no longer manages the RAID buffer.

[0009] The hardware allocates and manages the RAID buffer based on the obtained stripe ID.

[0010] In one embodiment, the step of the FTL module processing data according to a conventional strategy during the data writing process includes:

[0011] The FTL module calculates the actual location where user data and RAID parity data are written. When a new block slot is allocated for writing user data, the FTL module updates the actual RAID size of the current RAID stripe based on the bad block situation of the current block slot.

[0012] In one embodiment, the step of the FTL module processing data according to a conventional strategy during the data writing process further includes:

[0013] The FTL module updates the RAID pos when writing user data. The RAID pos is used to record the position of user data being written in the stripe. When the RAID pos records that the current stripe of user data has been written and the next position needs to be written with parity data, it sends a notification to the NFI module to write the parity data to the NAND.

[0014] In one embodiment, after the step of the hardware allocating and managing the RAID buffer based on the acquired stripe ID, the method further includes:

[0015] The hardware performs corresponding write operations based on the contents of the descriptor.

[0016] A hardware management implementation device for a RAID buffer, the device comprising:

[0017] The notification module is used to notify the hardware of the starting address and size of the RAID buffer corresponding to the RAID buffer through a register during the power-on process.

[0018] The FTL processing module is used to process data according to a conventional strategy during the data writing process.

[0019] The descriptor distribution module is used by the NFI module to fill the stripe ID corresponding to the RAID stripe into the descriptor when the hardware is distributed descriptor, and no longer manages the RAID buffer.

[0020] The hardware management module is used by the hardware to allocate and manage RAID buffers based on the obtained stripe ID.

[0021] In one embodiment, the FTL processing module is further configured to:

[0022] The FTL module calculates the actual location where user data and RAID parity data are written. When a new block slot is allocated for writing user data, the FTL module updates the actual RAID size of the current RAID stripe based on the bad block situation of the current block slot.

[0023] In one embodiment, the FTL processing module is further configured to:

[0024] The FTL module updates the RAID pos when writing user data. The RAID pos is used to record the position of user data being written in the stripe. When the RAID pos records that the current stripe of user data has been written and the next position needs to be written with parity data, it sends a notification to the NFI module to write the parity data to the NAND.

[0025] In one embodiment, the device further includes:

[0026] A write operation processing module is used by the hardware to perform corresponding write operations based on the content of the descriptor.

[0027] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.

[0028] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.

[0029] The aforementioned hardware management method, apparatus, computer device, and storage medium for RAID buffers, during the power-on process, notify the hardware of the starting address and size of the RAID buffer via registers; during data writing, the FTL module processes data according to a conventional strategy; when the NFI module issues descriptors to the hardware, it simply fills in the stripe ID corresponding to the RAID stripe and no longer manages the RAID buffer; the hardware allocates and manages the RAID buffer based on the obtained stripe ID. This invention improves the efficiency of the RAID process by using hardware management to manage the RAID buffer, thereby increasing the speed of the RAID process and simplifying the FW operation process. Attached Figure Description

[0030] Figure 1 This is a diagram illustrating the writing of parity data into a RAID stripe.

[0031] Figure 2 This is a flowchart illustrating the hardware management implementation method of the RAID buffer in one embodiment;

[0032] Figure 3 This is a flowchart illustrating the hardware management implementation method of the RAID buffer in another embodiment;

[0033] Figure 4 This is a structural block diagram of a hardware management implementation device for a RAID buffer in one embodiment;

[0034] Figure 5 This is a structural block diagram of the hardware management implementation device for the RAID buffer in another embodiment;

[0035] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0037] When the RAID size of the entire stripe is N+1, N user data requests generate one set of parity data. The parity data for each stripe is stored in the parity page. To ensure that data is not lost when a block fails, each stripe unit in the RAID stripe should ideally come from a different block.

[0038] Taking RAID size 63+1 as an example, such as Figure 1 As shown, each vbank selects a block, and then the same pages of each block form a stripe. Taking the SLC block as an example, the size of each page is 16K. After the user data of vbank0 to vbank62 is written, the corresponding check data will be written to the corresponding page of vbank63.

[0039] Currently, in traditional technology, the NFI module checks if a corresponding RAID buffer already exists for the current stripe ID. If a RAID buffer has been allocated, the corresponding RAID buffer ID is entered into the descriptor; otherwise, a corresponding RAID buffer is allocated to the current stripe ID. Furthermore, the NFI module records the mapping between stripe IDs and RAID buffer IDs. After the parity data recorded in the current RAID buffer is written to the NAND, NFI resets the management structure of the corresponding RAID buffer for use by subsequent RAID stripes.

[0040] Therefore, in the current operation, when the RAID buffer management is implemented by the FW software and the NFI module is implemented by dual cores, the mutual exclusion lock problem of dual cores managing software resources at the same time also needs to be considered. At the same time, when the FW software manages the RAID buffer resources, the software process is relatively complex, and when issuing descriptors to the hardware, the fields corresponding to the RAID buffer also need to be calculated and filled in.

[0041] Based on this, the present invention proposes a hardware management implementation method for RAID buffers, which aims to simplify the software operation process of FW and improve the efficiency of RAID process.

[0042] In one embodiment, such as Figure 2 As shown, a hardware management implementation method for RAID buffers is provided, which includes:

[0043] Step 202: During the power-on process, the starting address and size of the RAID buffer corresponding to the RAID buffer are notified to the hardware via registers;

[0044] Step 204: During the data writing process, the FTL module processes the data according to the conventional strategy.

[0045] Step 206: When the NFI module sends the descriptor to the hardware, it can fill in the stripe ID corresponding to the RAID stripe into the descriptor and no longer manage the RAID buffer.

[0046] Step 208: The hardware allocates and manages the RAID buffer based on the obtained stripe ID.

[0047] In this embodiment, a hardware management implementation method for RAID buffer is proposed. This method is designed for the current RAID process and RAID buffer usage scenarios. It proposes that RAID buffer can be managed by hardware. Hardware management can improve the speed of the RAID process while simplifying the software operation process of the firmware, thereby improving the efficiency of the RAID process.

[0048] In one embodiment, after the step of the hardware allocating and managing the RAID buffer based on the obtained stripe ID, the method further includes: the hardware performing a corresponding write operation based on the content of the descriptor.

[0049] Specifically, the optimized RAID process can be found by referring to [reference needed]. Figure 3 The steps are as follows:

[0050] Step 1: During the power-on process, the RAID buffer start addr and RAID buffer size are communicated to the hardware via registers.

[0051] Step 2: During the process of writing user data, the processing strategy of the FTL module remains unchanged;

[0052] Step 3: The NFI module no longer manages the RAID buffer. When filling in the descriptor, the NFI module only needs to fill in the stripe ID corresponding to the RAID stripe.

[0053] Step 4: The allocation and management of the RAID buffer are handled by the corresponding hardware modules. Specifically, the hardware modules perform allocation and reclamation based on the stripe ID, and then perform corresponding write operations based on the descriptor content.

[0054] In the above embodiment, during the power-on process, the starting address and size of the RAID buffer corresponding to the RAID buffer are notified to the hardware via registers; during data writing, the FTL module processes the data according to the conventional strategy; when the NFI module issues a descriptor to the hardware, it simply fills in the stripe ID corresponding to the RAID stripe and no longer manages the RAID buffer; the hardware allocates and manages the RAID buffer based on the obtained stripe ID. This solution improves the efficiency of the RAID process by using hardware management to manage the RAID buffer, thereby increasing the speed of the RAID process and simplifying the FW operation process.

[0055] In one embodiment, the steps of the FTL module processing data according to the conventional strategy during the data writing process include: the FTL module calculating the actual writing positions of user data and RAID parity data; and when the FTL module is allocated a new block slot for writing user data, updating the actual RAID size of the current RAID stripe according to the bad block situation of the current block slot.

[0056] In one embodiment, the step of the FTL module processing data according to the conventional strategy during the data writing process further includes: the FTL module updates the RAID pos when writing user data. The RAID pos is used to record the position of the user data being written in the stripe. When the RAID pos records that the current stripe of user data has been written and the next position needs to be written with parity data, it sends a notification to the NFI module to write the parity data to the NAND.

[0057] For specific details, please refer to Figure 3 As shown, in this embodiment, the FTL module is managed by software according to the conventional processing strategy, while the NFI module no longer manages the RAID buffer. The management of the RAID buffer is transferred to hardware to simplify the operation process of software management.

[0058] Specifically, the FTL module calculates the actual writing positions of user data and RAID parity data. When the FTL module allocates a new block slot for writing user data, it updates the actual RAID size of the current RAID stripe based on the bad block situation of the current block slot. The RAID size represents the sum of the number of user data entries that can be written in a stripe and the total number of RAID parity data entries. Each stripe corresponds to a stripe ID, which is used to identify different stripes.

[0059] The FTL module updates the RAID position when writing user data. The RAID position is used to record the position of user data being written in the stripe. When the RAID position records that the current stripe of user data has been written and the next position needs to write parity data, FTL will issue the corresponding ctrl_node to notify NFI to write the parity data to the NAND.

[0060] Then, when filling in the descriptor, the NFI module only needs to fill in the stripe ID corresponding to the RAID stripe; the allocation and management of the RAID buffer are completed by the corresponding hardware module.

[0061] In this embodiment, user data can also be successfully written to NAND, and corresponding RAID parity data can be generated simultaneously. When the management of the RAID buffer is implemented in hardware, the firmware process can be effectively simplified, and the efficiency of the RAID process can be improved.

[0062] It should be understood that, although Figures 1-3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-3 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0063] In one embodiment, such as Figure 4 As shown, a hardware management implementation device 400 for RAID buffers is provided, the device comprising:

[0064] Notification module 401, the notification module is used to notify the hardware of the starting address of the RAID buffer and the size of the RAID buffer through a register during the power-on process;

[0065] FTL processing module 402, the FTL processing module is used to process data according to the conventional strategy during the data writing process;

[0066] The descriptor distribution module 403 is used to fill the stripe ID corresponding to the RAID stripe into the descriptor when the NFI module distributes the descriptor to the hardware, and no longer manages the RAID buffer.

[0067] Hardware management module 404 is used for hardware to allocate and manage RAID buffers based on the obtained stripe ID.

[0068] In one embodiment, the FTL processing module 402 is further configured to:

[0069] The FTL module calculates the actual location where user data and RAID parity data are written. When a new block slot is allocated for writing user data, the FTL module updates the actual RAID size of the current RAID stripe based on the bad block situation of the current block slot.

[0070] In one embodiment, the FTL processing module 402 is further configured to:

[0071] The FTL module updates the RAID pos when writing user data. The RAID pos is used to record the position of user data being written in the stripe. When the RAID pos records that the current stripe of user data has been written and the next position needs to be written with parity data, it sends a notification to the NFI module to write the parity data to the NAND.

[0072] In one embodiment, such as Figure 5 As shown, a hardware management implementation device 400 for RAID buffers is provided, the device further comprising:

[0073] The write operation processing module 405 is used by the hardware to perform corresponding write operations based on the content of the descriptor.

[0074] For specific limitations on the hardware management implementation of the RAID buffer, please refer to the limitations on the hardware management implementation method of the RAID buffer mentioned above, which will not be repeated here.

[0075] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 6 As shown, the computer device includes a processor, memory, and a network interface connected via a device bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores operating devices, computer programs, and a database. The internal memory provides an environment for the operation of the operating devices and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a hardware management method for a RAID buffer.

[0076] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0077] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.

[0078] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.

[0079] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A hardware management implementation method for a RAID buffer, the method comprising: During the power-on process, the starting address and size of the RAID buffer corresponding to the RAID buffer are notified to the hardware via registers; During the data writing process, the FTL module processes the data according to the conventional strategy; When the NFI module issues descriptors to the hardware, it simply fills the stripe ID corresponding to the RAID stripe into the descriptor and no longer manages the RAID buffer. The hardware allocates and manages the RAID buffer based on the obtained stripe ID; The steps for the FTL module to process data according to the conventional strategy during the data writing process include: The FTL module calculates the actual location where user data and RAID parity data are written. When a new block slot is allocated for writing user data, the FTL module updates the actual RAID size of the current RAID stripe based on the bad block situation of the current block slot. The steps for the FTL module to process data according to the conventional strategy during the data writing process also include: The FTL module updates the RAID pos when writing user data. The RAID pos is used to record the position of user data being written in the stripe. When the RAID pos records that the current stripe of user data has been written and the next position needs to be written with parity data, it sends a notification to the NFI module to write the parity data to the NAND.

2. The hardware management implementation method for the RAID buffer according to claim 1, characterized in that, Following the step of the hardware allocating and managing the RAID buffer based on the acquired stripe ID, the following is also included: The hardware performs corresponding write operations based on the contents of the descriptor.

3. A hardware management implementation device for a RAID buffer, characterized in that, The device includes: The notification module is used to notify the hardware of the starting address and size of the RAID buffer corresponding to the RAID buffer through a register during the power-on process. The FTL processing module is used to process data according to a conventional strategy during the data writing process. The descriptor distribution module is used by the NFI module to fill the stripe ID corresponding to the RAID stripe into the descriptor when the hardware is distributed descriptor, and no longer manages the RAID buffer. The hardware management module is used by the hardware to allocate and manage RAID buffers based on the obtained stripe ID. The FTL processing module is also used for: The FTL module calculates the actual location where user data and RAID parity data are written. When a new block slot is allocated for writing user data, the FTL module updates the actual RAID size of the current RAID stripe based on the bad block situation of the current block slot. The FTL processing module is also used for: The FTL module updates the RAID pos when writing user data. The RAID pos is used to record the position of user data being written in the stripe. When the RAID pos records that the current stripe of user data has been written and the next position needs to be written with parity data, it sends a notification to the NFI module to write the parity data to the NAND.

4. The hardware management implementation device for the RAID buffer according to claim 3, characterized in that, The device further includes: A write operation processing module is used by the hardware to perform corresponding write operations based on the content of the descriptor.

5. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 2.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 2.

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