A method, device and storage medium for locating errors in logic system design

Abstract

An embodiment of the present application provides a method for locating errors in a logic system design, comprising: simulating the logic system design to obtain a reference waveform file; generating multiple errors in the logic system design; simulating the logic system design based on the multiple errors to generate multiple error outputs; training a positioning model corresponding to the logic system based on the logic system design, the reference waveform file, the multiple errors, and the multiple error outputs; and locating the errors in the logic system design using the positioning model.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer software technology, and in particular, to a method, device, and storage medium for locating errors in logic system design. Background Art

[0002] With the development of electronic technology, logic system design (e.g., chip design) has been widely used. The debugging of logic system design usually involves the debugging of simulation waveforms. For example, for a logic system design, a simulation waveform diagram of multiple signals within a certain period of time can be obtained through a simulation tool. The simulation waveform is stored as a waveform database, and the waveform database can be read by a debugging tool to reproduce the simulation waveform, and the debugging work of the logic system design is carried out accordingly.

[0003] In the daily development of chip design, the source code of the logic system design will be constantly modified and iterated, which will inevitably introduce errors. The traditional positioning method is to manually find the abnormal point by viewing the simulation waveform, and then manually trace the signal step by step until the source of the error is found. This method mainly relies on manual experience and is time-consuming and labor-intensive. In addition, the source of the error can be located by tracing back the source code and re-simulating the logic system design. However, these methods cannot solve the problem of changes in the verification simulation environment. Manually tracing the signal cannot accurately locate the source of the error. Therefore, how to quickly locate the source of the error is the key to improving verification efficiency. Summary of the invention

[0004] A first aspect of the present application provides a method for quickly locating errors in a logic system design, comprising: simulating a first logic system design and a second logic system design to obtain a first waveform file and a second waveform file respectively, wherein the first logic system includes a first design to be tested, the second logic system design includes a second design to be tested, and the second waveform file includes a second input stimulus for the design to be tested; applying the second input stimulus to the first design to be tested to obtain a reference waveform file of multiple signals of the first design to be tested under the second input stimulus; and comparing the reference waveform file and the second waveform file to locate errors in the second logic system design.

[0005] The second aspect of the present application provides an electronic device, which includes a memory for storing a group of instructions and at least one processor configured to execute the group of instructions so that the electronic device executes the method according to the first aspect.

[0006] A third aspect of the present application provides a non-transitory computer-readable storage medium, which stores a set of instructions for a computer, and when the set of instructions is executed, causes the computer to perform the method as described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0008] Figure 1 A schematic diagram of a host according to an embodiment of the present application is shown.

[0009] Figure 2 A schematic diagram of a simulation tool and a debugging tool according to an embodiment of the present application is shown.

[0010] Figure 3 A schematic diagram of a method for simulating logic system design is shown.

[0011] Figure 4 A schematic diagram of a method for locating errors in logic system design using a machine learning model according to an embodiment of the present application is shown.

[0012] Figure 5 A schematic diagram of a process for generating simulation data for an erroneous logic system design according to an embodiment of the present application is shown.

[0013] Figure 6 A schematic diagram of another process of generating simulation data for an erroneous logic system design according to an embodiment of the present application is shown.

[0014] Figure 7 A flow chart of a method for quickly locating errors in logic system design according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0016] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0017] Simulation testing is to apply various stimuli to the logic system design on the host running the simulation test system to detect whether the logic system design can achieve the predetermined functions.

[0018] Figure 1 FIG. 1 is a schematic diagram of a host 100 according to an embodiment of the present application. The host 100 may be an electronic device running a simulation system. Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other in communication within the host through the bus 110.

[0019] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0020] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). In some embodiments, the simulation test system for simulation test design may be a computer program stored in the memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method for locating logic system design errors of the present application) and data to be processed (e.g., the memory may store temporary codes generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0021] The network interface 106 can be configured to provide communication with other external devices to the host 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC) etc.), a cellular network, the Internet or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0022] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0023] The bus 110 may be configured to transmit information between various components of the host 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (e.g., a USB port, a PCI-E bus), etc.

[0024] It should be noted that, although the above host architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the host architecture may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above host architecture may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0025] Figure 2 The schematic diagram of the simulation tool 202 and the debugging tool 200 according to the embodiment of the present application is shown. The simulation tool 202 and the debugging tool 200 may be computer programs running on the host 100.

[0026] In the field of chip design, a design can usually be simulated using a simulation tool, such as the GalaxSim simulation tool produced by Xinhuazhang Technology Co., Ltd. Figure 2 The exemplary simulation tool 202 shown may include a compiler 120 and a simulator 220. The compiler 120 may compile a design (e.g., a verification system 210) into a target code 204, and the simulator 220 may perform simulation according to the target code 204 and output a simulation result 206. For example, the simulation tool 202 may output the simulation result (e.g., a simulation waveform) via Figure 1 The verification system 210 may include a logic system design 210a and a verification environment 210b. The verification environment 210b may also be referred to as a testbench. For example, the verification environment 210b may be a UVM environment.

[0027] The simulation result 206 may also be stored in the form of a waveform database. The waveform database storing the waveform data may also be referred to as a waveform file.

[0028] The debugging tool 200 can also read the simulation result 206. The debugging tool 200 can be, for example, the Fusion Debug debugging tool produced by Xinhuazhang Technology Co., Ltd. For example, the debugging tool 200 can read the simulation result 206 stored in a waveform file, and generate a corresponding simulation waveform for debugging. The debugging tool 200 can also read the description of the verification system 210 (usually SystemVerilog and Verilog code) and display it to the user. The debugging tool 200 can also generate various graphical interfaces (for example: debugging window) to facilitate the user's debugging work. The user can issue a debugging command to the debugging tool 200 (for example, run the verification system 210 to a certain moment), and the debugging tool 200 applies the debugging command to the simulation tool 202 to execute accordingly. The debugging tool 200 can also read a log file. The log file can include various information of the simulation process, including information of the simulation error, the line number of the error, the time when the simulation error occurred, etc.

[0029] It is understandable that, in addition to being connected to the simulation tool 202 , the debugging tool 200 may also be connected to a hardware emulator.

[0030] Before the logic system design is put into actual operation, the compiled logic system design needs to be run and debugged using the aforementioned debugging tool 200. The debugging tool 200 can receive user instructions 212 from the user and make corresponding debugging actions. In some embodiments, the user can issue user instructions 212 by clicking the mouse in the graphical interface; in some embodiments, the user can enter a command line in the command line interface to issue a user instruction 212. If an abnormality is found in the logic system design during the debugging process, it is necessary to further diagnose the abnormality found, find out the cause and the specific source location of the abnormality, and make corrections to ensure the robustness of the logic system design.

[0031] In the field of integrated circuits, simulation can refer to compiling a logical system design and then running it with a simulation tool to simulate and test various functions of the design. It is used for the design of application-specific integrated circuits (ASIC) or system-on-chips (SOC). Therefore, the design tested or verified in the simulation can also be called the design under test (DUT).

[0032] In the daily development of chip design, the source code of the design to be tested will be constantly modified and iterated, which will inevitably introduce errors. Traditional positioning methods can be to check the simulation waveform, find the abnormal point manually, and then manually track the signal step by step until the source of the error is found. In addition, the source of the error can be located by backtracking the source code and re-simulating the logic system design. These methods mainly rely on manual experience and are time-consuming and labor-intensive.

[0033] However, errors in the design to be tested tend to spread step by step, and manually tracking signals step by step often cannot effectively and timely locate the source of the error. Moreover, it is too dependent on manual experience and cannot quickly locate errors in the logic system design. Therefore, how to reduce the reliance on manual experience and locate errors in the logic system design more quickly and accurately is an urgent problem to be solved.

[0034] Figure 3 A schematic diagram of a method for simulating logic system design is shown.

[0035] like Figure 3 As shown, the logic system design 302 may include a DUT 3022 and a TB 3024. The DUT 3022 may be a complete chip design or a portion of a complete chip design. The TB 3024 may be used to provide test stimulus to the DUT 3022, determine test results, and generate test feedback (e.g., test logs, error reports, etc.).

[0036] The simulation tool 202 may read and compile the description (eg, source code) of the logical system design 302 and generate an executable file for simulation.

[0037] Simulating the logic system design 302 usually requires initializing the logic system design 302. In some embodiments, initialization is used to assign initial values ​​to multiple signals of the DUT 3022. Initialization is usually performed before 0 o'clock in the simulation time, so it is often not considered as part of the actual test, but it will take up a long period of simulation time.

[0038] TB 3024 can apply multiple stimulus signals to DUT 3022. Multiple stimulus signals are generally applied to respective ports of DUT. DUT 3022 running in simulator 220 processes multiple stimulus signals in sequence.

[0039] When the simulation is finished, the DUT 3022 will store the simulation data in the memory 104. Subsequently, the simulator 220 can generate a waveform file based on the simulation data in the memory 104. The waveform file can include a test log, an output waveform of each port of the DUT, and multiple stimulus signals received by the DUT.

[0040] Figure 4 A schematic diagram of a method 400 for locating errors in logic system design using a machine learning model according to an embodiment of the present application is shown.

[0041] As mentioned above, most of the existing methods for locating errors in logic system design rely on manual experience. Moreover, since errors in logic system design will spread step by step, most of the locating methods cannot locate errors quickly and effectively. Therefore, this application proposes a method for locating errors in logic system design using a machine learning model.

[0042] like Figure 4 As shown, an error 406 is injected into the logic system design 302, and a data set 404 is obtained by simulation. The error 406 may be an error in the TB 3024 or an error in the DUT 3022. Both the injected error 406 and the location of the error 406 may be known.

[0043] The positioning model 402 is trained based on the error 406 , the location of the error 406 , and the data set 404 , and each parameter in the positioning model 402 is improved so that the positioning model 402 can output the error 406 and the location of the error 406 .

[0044] In some embodiments, the logic system design 302 code may be manually modified to inject errors 406. However, the errors manually modified are often relatively single and cannot fully take into account the locations where errors may occur in the logic system design 302. Therefore, the inventor of the present application proposes a method for generating a simulation data set of an erroneous logic system design using a tool.

[0045] Figure 5 A schematic diagram of a process 500 for generating simulation data of an erroneous logic system design according to an embodiment of the present application is shown.

[0046] Injecting errors into the logic system design may include injecting errors into a test bench in the logic system design or injecting errors into a design under test in the logic system design. Flow 500 is a flow of injecting errors into a design under test in a logic system design.

[0047] like Figure 5 As shown, the logic system design 302 includes a TB 3024 and a DUT 3022. The TB 3024 generates a stimulus signal a, and the DUT 3022 includes a module 1. Figure 3 , the logic system design 302 is simulated. TB 3024 applies a stimulus signal a to the input terminal of DUT 3022. The output terminal of DUT 3022 can output a waveform file A, and the waveform file A can include the stimulus signal a accordingly.

[0048] By modifying logic module 1, an erroneous logic module 2 can be obtained. By replacing logic module 1 with erroneous logic module 2, DUT 3044 is obtained. Figure 5 As shown, tool 502 can be used to inject errors into DUT 3022 to generate DUT 3044. In other words, tool 502 can be used to inject errors into logic module 1 in DUT 3022 to generate error logic module 2. Tool 502 can be error injection software, such as ChatGPT.

[0049] It is easy to understand that DUT 3044 is different from DUT 3022. Therefore, before simulating DUT 3044, multiple signals of DUT 3044 need to be reassigned, that is, initialized.

[0050] After the initialization is completed, as in process 500, the stimulus signal a is extracted from the waveform file A and applied to the input terminal of the DUT 3044, and finally the error waveform B is obtained. The error waveform B may include Figure 4 In some embodiments, the DUT 3044 may also be re-simulated to obtain the error waveform B.

[0051] In summary, directly injecting errors into the DUT 3022 in the logic system design 302 will change the internal modules of the logic system design 302, so the logic system design 302 needs to be reinitialized and re-simulated. This will take a long time. Even just reinitialization will be very time-consuming.

[0052] Therefore, when using tool 502 (e.g., ChatGPT) to inject errors into the design under test in the logic system design, a large amount of data sets cannot be obtained in a short time due to the long time of re-simulation / initialization. In view of this, the inventor of the present application has proposed a method for generating simulation data of an erroneous logic system design.

[0053] Figure 6 A schematic diagram of a process 600 for generating simulation data of an erroneous logic system design according to an embodiment of the present application is shown.

[0054] like Figure 6 As shown, process 600 is a process for injecting errors into a test bench in a logic system design.

[0055] In order to avoid excessive time consumption caused by re-simulation / initialization, injecting errors into the test bench can be injecting errors into the stimulus signal in the test bench. It is understandable that the stimulus signal is associated with the upstream module that generates the stimulus signal and the downstream module that receives the stimulus signal. The value of the stimulus signal must be related to the upstream module of the stimulus signal. In other words, the stimulus signal injected with an error must reflect the error of its upstream module compared to the original stimulus signal. Therefore, even if the upstream module is not modified but only the stimulus signal it generates is modified to an error signal, the behavior of the entire design under test is as if there is an error in the upstream module.

[0056] like Figure 6 As shown, in some embodiments, injecting an error into a logic module (e.g., logic module 1 of DUT 3022) may be equivalent to injecting an error into a stimulus signal associated with the module (e.g., Figure 6 Errors are injected into the stimulus signal a).

[0057] The excitation signal a is generated by the logic module 1. The excitation signal a can be Figure 6 As shown, including the signal value "0100100100101" with a length of Length. Extract the excitation signal a from the waveform file A, and change the signal value in the excitation signal a to "01001001 1 0101", the error excitation signal b can be obtained.

[0058] In the process 600, for example, the error stimulus signal b can be applied to the input terminal of the DUT 3022, and the error waveform C can be obtained through simulation. The error waveform C may include Figure 4 Chinese data set 404.

[0059] It is understandable that the modified excitation signal may also be an input signal of the logic module 1 .

[0060] Therefore, the errors generated by modifying the excitation signal a and modifying the logic module 1 can be consistent. Therefore, in the case of error equivalence, Figure 5 Error waveform B and Figure 6 The error waveform C in can be equivalent.

[0061] Process 600 of the embodiment of the present application overcomes the problem that changing the design to be tested will increase the initialization time. The error injected into the design to be tested is converted into the error injected into the stimulus signal, thereby avoiding the problem of extra time consumption caused by modifying the design to be tested. Therefore, a large number of error data sets can be quickly generated in a short time to meet the needs of training the positioning model. At the same time, the positioning model corresponding to the logic system design trained in a short time can help users quickly locate the errors in the logic system design, greatly improving the efficiency of locating the errors in the logic system design.

[0062] The embodiment of the present application also provides a method for quickly locating errors in logic system design.

[0063] Figure 7 FIG. 7 is a flowchart of a method 700 for quickly locating errors in a logic system design according to an embodiment of the present application. The method 700 may be Figure 1 The method 700 may include the following steps.

[0064] In step 702, the logic system design is simulated (eg, Figure 5 or Figure 6 302 in the logic system design to obtain a reference waveform file (eg, Figure 5 or Figure 6 Wave file A).

[0065] At step 704, a plurality of errors (eg, Figure 5 Error in module 2 or Figure 6 The wrong excitation in b).

[0066] In some embodiments, generating the plurality of errors in the logic system design may be generating a test bench in the logic system design (eg, Figure 6 Multiple errors in TB 3024).

[0067] In some other embodiments, generating the plurality of errors in the logic system design may be generating a design to be tested in the logic system design (eg, Figure 5 For example, Figure 5 As shown, the logic module 1 in the DUT 3022 in the logic system design 302 is changed to the wrong logic module 2, and the logic module 1 is replaced by the wrong logic module 2. For another example, Figure 6 As shown, the stimulus signal a in the logic system design 302 is changed into an erroneous stimulus signal b, and the erroneous stimulus signal b replaces the stimulus signal a.

[0068] In step 706, based on the plurality of errors (eg, Figure 5 Error in module 2 or Figure 6 b) simulating the logic system design to generate multiple error outputs (e.g., Figure 5 Error waveform B or Figure 6 Error waveform in C).

[0069] In some embodiments, the plurality of error outputs may include error waveform files or error logs. For example, the plurality of error outputs may include Figure 5 Error waveform B or Figure 6 Error waveform C in .

[0070] In some other embodiments, based on multiple errors in the test bench in the logic system design (e.g., Figure 6 b) simulating the logic system design to generate multiple error outputs (e.g., Figure 6 The error waveform in C). Figure 6 As shown in method 600, an error excitation signal b is applied to the DUT 3022 or the input end of module 1 of the DUT 3022, and an error waveform C can be obtained through simulation.

[0071] In some other embodiments, based on multiple errors of the design to be tested in the logic system design (for example, Figure 5 2) emulates the logic system design to generate multiple error outputs (e.g., Figure 5 Error waveform in B).

[0072] In step 708, based on the logic system design (e.g., Figure 5 or Figure 6 302), the reference waveform file (eg, Figure 5 or Figure 6 The waveform file A in the embodiment of the present invention), the plurality of errors (for example, Figure 5 Error in module 2 or Figure 6 The error stimulus b) and the plurality of error outputs (eg, Figure 5 Error waveform B or Figure 6 The error waveform C in the training and the positioning model corresponding to the logic system (for example, Figure 4 Positioning model 402 in ).

[0073] In some embodiments, the positioning model can be selected according to the specific embodiment. Different logic system designs, error types, and complexity of waveform files, etc. can affect the selection of the positioning model.

[0074] In some embodiments, based on Figure 6The process 600 in the embodiment generates an error stimulus and simulates an error waveform C. The error location corresponding to the error waveform C is determined, that is, the logic module 1. Based on the logic system design 302, the reference waveform file 304, the error waveform C and the location of the logic module 1, the positioning module 402 is trained.

[0075] In step 710, the errors in the logic system design are located using the location model.

[0076] In some embodiments, the user can use the simulation waveform of the erroneous logic system design (including erroneous waveforms and / or logs) and the erroneous logic system design itself as inputs to the positioning model, and the positioning model provides possible errors and error locations, thereby accelerating the user's positioning of design errors.

[0077] Process 700 of the embodiment of the present application overcomes the problem that changing the design to be tested will increase the initialization time. The error injected into the design to be tested is converted into the error injected into the stimulus signal, thereby avoiding the problem of extra time consumption caused by modifying the design to be tested. Therefore, a large number of error data sets can be quickly generated in a short time to meet the needs of training the positioning model. At the same time, the positioning model corresponding to the logic system design trained in a short time can help users quickly locate the errors in the logic system design, greatly improving the efficiency of locating the errors in the logic system design.

[0078] The present application also provides a computing device for locating errors in the design of a logic system. The computing device may be Figure 1 The computing device may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the computing device performs the method 700.

[0079] The embodiment of the present application further provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of computer instructions, and the set of instructions is used to make the computer perform method 700 when executed.

[0080] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0081] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0082] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0083] This application is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A method for locating an error in a logic system design, comprising: simulating the logic system design to obtain a reference waveform file; generating a plurality of errors of the logic system design; simulating the logic system design based on the plurality of errors respectively to generate a plurality of error outputs; Training a positioning model corresponding to the logic system based on the logic system design, the reference waveform file, the plurality of errors, and the plurality of error outputs; as well as Using the positioning model to locate errors in the logic system design; The logic system design includes a design to be tested, the design to be tested includes a first module, the multiple errors include a first error of the first module, the reference waveform file includes a first stimulus corresponding to the first module, and generating the multiple errors of the logic system design further includes: determining a first error stimulus corresponding to the first error; and Using the first error stimulus to replace the first stimulus in the reference waveform file; Wherein, simulating the logic system design based on the multiple errors to generate multiple error outputs further comprises: The logic system design is simulated based on the first error stimulus to generate a first error output, wherein the first error output includes a first error waveform file or a first error log.

2. The method according to claim 1, wherein: Simulating the logic system design based on the first error stimulus to generate a first error output further comprises: The first error stimulus is applied to an input terminal of the design to be tested in the logic system design.

3. The method according to claim 1, wherein: Generating a plurality of errors in the logic system design further includes: determining a first error module corresponding to the first error stimulus; and The first error module is used to replace the first module in the design to be tested to generate an error design to be tested.

4. The method according to claim 1, wherein: Training a positioning model corresponding to the logic system based on the logic system design, the reference waveform file, the multiple errors, and the multiple error outputs further includes: determining a location of the first error, the location being the first module; and The localization model is trained based on the logic system design, the reference waveform file, the plurality of errors, the locations of the plurality of errors, and the plurality of error outputs.

5. The method according to claim 1, wherein: Using the positioning model to locate the error of the logic system design further includes: simulating an erroneous logic system design to generate an erroneous output, the erroneous logic system design being modified based on the logic system design; and Based on the error output and the error logic system design, the error corresponding to the error output and the location of the error are determined using the positioning model.

6. A computing device for locating errors in a logic system design, comprising: A memory for storing a plurality of instructions; as well as At least one processor is configured to execute the plurality of instructions so that the computing device performs the method according to any one of claims 1 to 5.

7. A non-transitory computer-readable storage medium storing a set of instructions for a computing device, the set of instructions being used to cause the computing device to execute the method according to any one of claims 1 to 5.

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