A low-noise large full-well TDI-CMOS image sensor readout circuit

Abstract

The invention relates to a low-noise large full-well TDI-CMOS image sensor readout circuit, which belongs to the field of CMOS image sensors; the circuit comprises a buried-channel CCD structure and a readout module; the buried-channel CCD structure comprises a p-type substrate, an n-type buried channel, four CCD electrodes and a transmission gate TG; the n-type buried channel is arranged on the upper surface of the p-type substrate; the four CCD electrodes are evenly distributed on the upper surface of the n-type buried channel; the transmission gate TG is arranged on the upper surface of the n-type buried channel and is located on the outside of the four CCD electrodes; a groove is arranged on the upper surface of the n-type buried channel; the readout module comprises an FD node and an analog readout front-stage circuit; the FD node is connected to the analog readout front-stage circuit; the FD node extends into the groove to realize the connection between the readout module and the n-type buried channel; the invention is suitable for a CCD-CMOS fusion type TDI image sensor, and in particular can improve the noise performance of the sensor under the premise of high buried channel depletion potential, high charge transfer efficiency and large full-well buried channel CCD pixel design.

Description

Technical Field

[0001] The invention belongs to the field of CMOS image sensors and relates to a low-noise large full-well TDI-CMOS image sensor readout circuit. Background Art

[0002] Time Delay Integration (TDI) CMOS image sensors can be divided into digital TDI, CCD-CMOS fusion TDI (CCD, Charge Coupled Device), TDI based on avalanche mechanism pixels, etc. According to the type of pixels, CCD-CMOS fusion TDI takes into account the advantages of traditional CCD image sensor signal noise-free accumulation and traditional CMOS image sensor high integration, and has unparalleled line frequency performance, so it is the TDI CMOS image sensor with the most performance advantages.

[0003] However, for CCD-CMOS fusion TDI image sensors, their voltage swing is naturally limited. Therefore, the CCD buried channel design needs to balance performance indicators such as full well, charge transfer efficiency, and noise, which greatly restricts the further improvement of the performance of CCD-CMOS fusion TDI image sensors. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and propose a low-noise large full-well TDI-CMOS image sensor readout circuit, which is suitable for CCD-CMOS fusion TDI image sensors, and can especially improve the noise performance of the sensor under the premise of high buried channel depletion potential, high charge transfer efficiency, and large full-well buried channel CCD pixel design.

[0005] The solution of the present invention is:

[0006] A low-noise large full-well TDI-CMOS image sensor readout circuit comprises a buried-channel CCD structure and a readout module; wherein the buried-channel CCD structure comprises a p-type substrate, an n-type buried channel, four CCD electrodes and a transmission gate TG; wherein the p-type substrate is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is arranged on the upper surface of the p-type substrate; the four CCD electrodes are evenly distributed on the upper surface of the n-type buried channel; the transmission gate TG is arranged on the upper surface of the n-type buried channel and is located outside the four CCD electrodes; a groove is arranged on the upper surface of the n-type buried channel; the readout module comprises an FD node and an analog readout pre-stage circuit; the FD node is connected to the analog readout pre-stage circuit; the FD node extends into the groove to realize the connection between the readout module and the n-type buried channel.

[0007] In the above-mentioned low-noise large full-well TDI-CMOS image sensor readout circuit, the analog readout pre-stage circuit is a direct reset FIR analog readout pre-stage circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2 and capacitor C1;

[0008] Among them, the switch SW RST One end is connected to the external power supply V DD-RST ; Switch SW RST The other end is connected to the FD node and the gate of the PMOS tube M1 respectively; the source of the PMOS tube M1 is connected to the external power supply V DD-AMP The drain of PMOS tube M1 is connected to the source of PMOS tube M2; the gate of PMOS tube M2 is connected to the external power supply V B2 The drain of the PMOS tube M2 is connected to one end of the switch SW1 and the drain of the NMOS tube M3; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is connected to one end of the capacitor C1 and one end of the switch SW2 respectively, and serves as an output at the same time; the other end of the capacitor C1 is grounded; the other end of the switch SW2 is connected to the external power supply V0.

[0009] In the above-mentioned low-noise large full-well TDI-CMOS image sensor readout circuit, the analog readout pre-stage circuit is an automatic zero reset FIR analog readout pre-stage circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2 and capacitor C1;

[0010] Among them, the source of PMOS tube M1 is connected to the external power supply V DD-AMP The gate of the PMOS tube M1 is connected to the FD node and the switch SW RST The drain of the PMOS tube M1 is connected to the source of the PMOS tube M2; the gate of the PMOS tube M2 is connected to the external power supply V B2 Connection; the drain of PMOS tube M2 is connected to the switch SW RST The other end of the switch SW1 is connected to the drain of the NMOS tube M3; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is connected to one end of the capacitor C1 and one end of the switch SW2 respectively, and serves as an output at the same time; the other end of the capacitor C1 is grounded; the other end of the switch SW2 is connected to the external power supply V0.

[0011] In the above-mentioned low-noise large full-well TDI-CMOS image sensor readout circuit, the PMOS tube M1 and the PMOS tube M2 together constitute a transconductance amplifier to convert the voltage of the front-stage FD node into current; the NMOS tube M3 and the NMOS tube M4 together constitute a current source; the charging process of the rear-stage capacitor C1 by the currents of the PMOS tube M1, the PMOS tube M2, the NMOS tube M3, and the NMOS tube M4 is controlled by the switch SW1; and the resetting of the capacitor C1 is controlled by the switch SW2.

[0012] In the above-mentioned low-noise large full-well TDI-CMOS image sensor readout circuit, the analog readout pre-stage circuit is a direct reset FIR+IIR analog readout circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2, switch SW3, capacitor C1 and capacitor C2;

[0013] Among them, the switch SW RST One end of the switch SW is connected to the FD node; RST The other end is connected to the ground and the gate of the PMOS tube M1; the source of the PMOS tube M1 is connected to the external power supply V DD-AMP The drain of PMOS tube M1 is connected to the source of PMOS tube M2; the gate of PMOS tube M2 is connected to the external power supply V B2 The drain of the PMOS tube M2 is connected to one end of the switch SW1 and the drain of the NMOS tube M3; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is respectively connected to one end of the capacitor C1 and one end of the switch SW3; the other end of the capacitor C1 is grounded; the other end of the switch SW3 is respectively connected to one end of the switch SW2 and one end of the capacitor C2, and serves as an output at the same time; the other end of the switch SW2 is connected to the external power supply V0; the other end of the capacitor C2 is grounded.

[0014] In the above-mentioned low-noise large full-well TDI-CMOS image sensor readout circuit, the analog readout pre-stage circuit is an automatic zero reset FIR+IIR analog readout pre-stage circuit, including a switch SW RST, PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2, switch SW3, capacitor C1 and capacitor C2;

[0015] Among them, the source of PMOS tube M1 is connected to the external power supply V DD-AMP The gate of the PMOS tube M1 is connected to the FD node and the switch SW RST The drain of PMOS tube M1 is connected to the source of PMOS tube M2; the gate of PMOS tube M2 is connected to the external power supply V B2 The drain of the PMOS tube M2 is connected to the switch SW RST The other end of the NMOS tube M3, the drain of the NMOS tube M3, and one end of the switch SW1; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is respectively connected to one end of the capacitor C1 and one end of the switch SW3; the other end of the capacitor C1 is grounded; the other end of the switch SW3 is respectively connected to one end of the switch SW2 and one end of the capacitor C2, and serves as an output at the same time; the other end of the switch SW2 is connected to the external power supply V0; the other end of the capacitor C2 is grounded.

[0016] In the above-mentioned low-noise large full-well TDI-CMOS image sensor readout circuit, PMOS tube M1 and PMOS tube M2 together constitute a transconductance amplifier to convert the voltage of the front-stage FD node into current; NMOS tube M3 and NMOS tube M4 together constitute a current source; the charging process of the rear-stage capacitor C1 and capacitor C2 by the current of PMOS tube M1, PMOS tube M2, NMOS tube M3, and NMOS tube M4 is controlled by switch SW1; the reset of capacitor C1 and capacitor C2 is controlled by switch SW2; switch SW3 controls capacitor C1 and capacitor C2 to form IIR filtering.

[0017] In the above-mentioned low-noise large full-well TDI-CMOS image sensor readout circuit, when the analog readout pre-stage circuit is a direct reset FIR analog readout pre-stage circuit or an automatic zero reset FIR analog readout pre-stage circuit, the timing control method is the same, specifically:

[0018] External power supply V B2 The high and low levels of the PMOS tube M1 and the PMOS tube M2 are controlled to close and open the current; through the switch SW RST Control the reset of the FD node; control the reset of the capacitor C1 by turning on the switch SW2; RSTAfter closing, that is, after the FD node is reset, when the switch SW2 is still turned on, the drains of the PMOS tube M2 and the NMOS tube M3 are reset by turning on the switch SW1; then the switch SW2 is turned off to filter and sample the signal; then the switch SW1 is turned off to end the first sampling of the signal and output the signal 1 to the next stage; then the transmission gate TG is turned on to transfer the charge of the buried channel CCD structure to the FD node;

[0019] Repeat the above operations of switch SW1 and switch SW2, filter the changed FD node signal, and output signal 2 to the next stage;

[0020] Signal 1 is the signal value of the FD node in the reset state, and signal 2 is the signal value of the FD node after receiving the CCD photogenerated charge.

[0021] In the above-mentioned low-noise large full-well TDI-CMOS image sensor readout circuit, when the analog readout front-stage circuit is a direct reset FIR+IIR analog readout circuit or an automatic zero reset FIR+IIR analog readout front-stage circuit, the timing control method is the same, specifically:

[0022] External power supply V B2 The high and low levels of the PMOS tube M1 and the PMOS tube M2 are controlled to close and open the current; through the switch SW RST Control the reset of the FD node; control the reset of capacitors C1 and C2 by turning on switch SW2; RST After closing, that is, after the FD node is reset, when the switch SW2 is still turned on, the drains of the PMOS tube M2 and the NMOS tube M3 are reset by turning on the switch SW1; then the switch SW2 is turned off to filter and sample the signal; during the next period, the switches SW2 and SW3 are turned on alternately; then the switch SW1 is turned off to end the first sampling of the signal and output the signal 1 to the next stage; then the transmission gate TG is turned on to transfer the charge of the buried channel CCD structure to the FD node;

[0023] Repeat the above operations of switch SW1, switch SW2, and switch SW3 to filter the changed FD node signal and output signal 2 to the next stage;

[0024] Signal 1 is the signal value of the FD node in the reset state, and signal 2 is the signal value of the FD node after receiving the CCD photogenerated charge.

[0025] In the above-mentioned low-noise large full-well TDI-CMOS image sensor readout circuit, the gate area value of the PMOS tube M1 and the PMOS tube M2 is 0.3-3 μm 2 ; Switch SW RSTThe capacitance value formed by the gate of the PMOS tube M1 and the FD node is 2-20fF; the reset voltage of the FD node is 2.5-3V; the current value of the NMOS tube M3 and the NMOS tube M4 is 1-10μA; the capacitance value of the capacitor C1 is 500fF-3pF; the capacitance value of the capacitor C2 is 100-500fF.

[0026] The beneficial effects of the present invention compared with the prior art are:

[0027] (1) The present invention proposes a low-noise large full-well TDI-CMOS image sensor readout circuit, which is suitable for CCD-CMOS fusion TDI image sensors, and can especially improve the noise performance of the sensor under the premise of high buried channel depletion potential, high charge transfer efficiency, and large full-well buried channel CCD pixel design;

[0028] (2) The present invention uses simple components and realizes four types of circuits through different circuit configurations, namely, a direct reset FIR analog readout pre-stage circuit, an automatic zero reset FIR analog readout pre-stage circuit, a direct reset FIR+IIR analog readout circuit, and an automatic zero reset FIR+IIR analog readout pre-stage circuit, which can be selected according to needs;

[0029] (3) The present invention sets the direct reset FIR analog readout pre-stage circuit and the automatic zero reset FIR analog readout pre-stage circuit to the same timing control; sets the direct reset FIR+IIR analog readout circuit and the automatic zero reset FIR+IIR analog readout pre-stage circuit to the same timing control; and achieves the improvement of the noise performance of the sensor under the premise of high buried channel depletion potential, high charge transfer efficiency, and large full well buried channel CCD pixel design. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a circuit diagram of the front stage of the direct reset form FIR analog readout of the present invention;

[0031] Figure 2 This is the circuit diagram of the front stage of the automatic zero reset FIR analog readout of the present invention;

[0032] Figure 3 This is a direct reset form FIR+IIR analog readout circuit diagram of the present invention;

[0033] Figure 4 This is the circuit diagram of the front stage of the automatic zero reset form FIR+IIR analog readout of the present invention;

[0034] Figure 5 This is a schematic diagram of timing control of the FIR analog readout front-stage circuit of the present invention;

[0035] Figure 6This is a schematic diagram of the timing control of the FIR+IIR analog readout front-stage circuit of the present invention. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with the embodiments.

[0037] The present invention provides a low-noise large full-well TDI-CMOS image sensor readout circuit, which is suitable for a CCD-CMOS fusion type TDI image sensor, and can especially improve the noise performance of the sensor under the premise of high buried channel depletion potential, high charge transfer efficiency, and large full-well buried channel CCD pixel design.

[0038] The invention discloses a low-noise large full-well TDI-CMOS image sensor readout circuit, which specifically comprises a buried-channel CCD structure and a readout module; wherein the buried-channel CCD structure comprises a p-type substrate, an n-type buried channel, four CCD electrodes and a transmission gate TG; wherein the p-type substrate is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is arranged on the upper surface of the p-type substrate; the four CCD electrodes are evenly distributed on the upper surface of the n-type buried channel; the transmission gate TG is arranged on the upper surface of the n-type buried channel and is located on the outside of the four CCD electrodes; a groove is arranged on the upper surface of the n-type buried channel; the readout module comprises an FD node and an analog readout front-stage circuit; the FD node is connected to the analog readout front-stage circuit; the FD node extends into the groove to realize the connection between the readout module and the n-type buried channel.

[0039] like Figure 1 As shown, the analog readout pre-stage circuit is a direct reset FIR analog readout pre-stage circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2 and capacitor C1; wherein, switch SW RST One end is connected to the external power supply V DD-RST ; Switch SW RST The other end is connected to the FD node and the gate of the PMOS tube M1 respectively; the source of the PMOS tube M1 is connected to the external power supply V DD-AMP The drain of PMOS tube M1 is connected to the source of PMOS tube M2; the gate of PMOS tube M2 is connected to the external power supply V B2 The drain of the PMOS tube M2 is connected to one end of the switch SW1 and the drain of the NMOS tube M3; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is connected to one end of the capacitor C1 and one end of the switch SW2 respectively, and serves as an output at the same time; the other end of the capacitor C1 is grounded; the other end of the switch SW2 is connected to the external power supply V0.

[0040] like Figure 2 As shown, the analog readout pre-stage circuit is an automatic zero reset FIR analog readout pre-stage circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2 and capacitor C1;

[0041] Among them, the source of PMOS tube M1 is connected to the external power supply V DD-AMP The gate of the PMOS tube M1 is connected to the FD node and the switch SW RST The drain of the PMOS tube M1 is connected to the source of the PMOS tube M2; the gate of the PMOS tube M2 is connected to the external power supply V B2 Connection; the drain of PMOS tube M2 is connected to the switch SW RST The other end of the switch SW1 is connected to the drain of the NMOS tube M3; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is connected to one end of the capacitor C1 and one end of the switch SW2 respectively, and serves as an output at the same time; the other end of the capacitor C1 is grounded; the other end of the switch SW2 is connected to the external power supply V0.

[0042] The PMOS tube M1 and the PMOS tube M2 together form a transconductance amplifier, which converts the voltage of the front-stage FD node into current; the NMOS tube M3 and the NMOS tube M4 together form a current source; the charging process of the rear-stage capacitor C1 by the currents of the PMOS tube M1, the PMOS tube M2, the NMOS tube M3, and the NMOS tube M4 is controlled by the switch SW1; the resetting of the capacitor C1 is controlled by the switch SW2.

[0043] like Figure 3 As shown, the analog readout front stage circuit is a direct reset FIR+IIR analog readout circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2, switch SW3, capacitor C1 and capacitor C2; wherein, switch SW RST One end of the switch SW is connected to the FD node; RST The other end is connected to the ground and the gate of the PMOS tube M1; the source of the PMOS tube M1 is connected to the external power supply V DD-AMP The drain of PMOS tube M1 is connected to the source of PMOS tube M2; the gate of PMOS tube M2 is connected to the external power supply V B2The drain of the PMOS tube M2 is connected to one end of the switch SW1 and the drain of the NMOS tube M3; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is respectively connected to one end of the capacitor C1 and one end of the switch SW3; the other end of the capacitor C1 is grounded; the other end of the switch SW3 is respectively connected to one end of the switch SW2 and one end of the capacitor C2, and serves as an output at the same time; the other end of the switch SW2 is connected to the external power supply V0; the other end of the capacitor C2 is grounded.

[0044] like Figure 4 As shown, the analog readout pre-stage circuit is an automatic zero reset FIR+IIR analog readout pre-stage circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2, switch SW3, capacitor C1 and capacitor C2; wherein the source of PMOS tube M1 is connected to the external power supply V DD-AMP The gate of the PMOS tube M1 is connected to the FD node and the switch SW RST The drain of PMOS tube M1 is connected to the source of PMOS tube M2; the gate of PMOS tube M2 is connected to the external power supply V B2 The drain of the PMOS tube M2 is connected to the switch SW RST The other end of the NMOS tube M3, the drain of the NMOS tube M3, and one end of the switch SW1; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is respectively connected to one end of the capacitor C1 and one end of the switch SW3; the other end of the capacitor C1 is grounded; the other end of the switch SW3 is respectively connected to one end of the switch SW2 and one end of the capacitor C2, and serves as an output at the same time; the other end of the switch SW2 is connected to the external power supply V0; the other end of the capacitor C2 is grounded.

[0045] The PMOS tube M1 and the PMOS tube M2 together form a transconductance amplifier, which converts the voltage of the front-stage FD node into current; the NMOS tube M3 and the NMOS tube M4 together form a current source; the switch SW1 controls the charging process of the PMOS tube M1, the PMOS tube M2, the NMOS tube M3, and the NMOS tube M4 currents on the rear-stage capacitors C1 and C2; the switch SW2 controls the resetting of the capacitors C1 and C2; the switch SW3 controls the capacitors C1 and C2 to form an IIR filter.

[0046] like Figure 5As shown, when the analog readout front-stage circuit is a direct reset FIR analog readout front-stage circuit or an automatic zero reset FIR analog readout front-stage circuit, the timing control method is the same, specifically:

[0047] External power supply V B2 The high and low levels of the PMOS tube M1 and the PMOS tube M2 are controlled to close and open the current; through the switch SW RST Control the reset of the FD node; control the reset of the capacitor C1 by turning on the switch SW2; RST After closing, that is, after the FD node is reset, when the switch SW2 is still turned on, the drains of the PMOS tube M2 and the NMOS tube M3 are reset by turning on the switch SW1; then the switch SW2 is turned off to filter and sample the signal; then the switch SW1 is turned off to end the first sampling of the signal and output the signal 1 to the next stage; then the transmission gate TG is turned on to transfer the charge of the buried channel CCD structure to the FD node;

[0048] Repeat the above operations of switch SW1 and switch SW2, filter the changed FD node signal, and output signal 2 to the next stage;

[0049] Signal 1 is the signal value of the FD node in the reset state, and signal 2 is the signal value of the FD node after receiving the CCD photogenerated charge.

[0050] like Figure 6 As shown, when the analog readout front stage circuit is a direct reset FIR+IIR analog readout circuit or an automatic zero reset FIR+IIR analog readout front stage circuit, the timing control method is the same, specifically:

[0051] External power supply V B2 The high and low levels of the PMOS tube M1 and the PMOS tube M2 are controlled to close and open the current; through the switch SW RST Control the reset of the FD node; control the reset of capacitors C1 and C2 by turning on switch SW2; RST After closing, that is, after the FD node is reset, when the switch SW2 is still turned on, the drains of the PMOS tube M2 and the NMOS tube M3 are reset by turning on the switch SW1; then the switch SW2 is turned off to filter and sample the signal; during the next period, the switches SW2 and SW3 are turned on alternately; then the switch SW1 is turned off to end the first sampling of the signal and output the signal 1 to the next stage; then the transmission gate TG is turned on to transfer the charge of the buried channel CCD structure to the FD node;

[0052] Repeat the above operations of switch SW1, switch SW2, and switch SW3 to filter the changed FD node signal and output signal 2 to the next stage;

[0053] Signal 1 is the signal value of the FD node in the reset state, and signal 2 is the signal value of the FD node after receiving the CCD photogenerated charge.

[0054] The gate area of ​​PMOS tube M1 and PMOS tube M2 is 0.3-3μm 2 ; Switch SW RST The capacitance value formed by the gate of the PMOS tube M1 and the FD node is 2-20fF; the reset voltage of the FD node is 2.5-3V; the current value of the NMOS tube M3 and the NMOS tube M4 is 1-10μA; the capacitance value of the capacitor C1 is 500fF-3pF; the capacitance value of the capacitor C2 is 100-500fF.

[0055] Specifically, when the CCD electrode is at a high level, the typical maximum potential VCCD-MAX of the buried channel in the depletion state is between 1.5V and 2.5V, the typical junction depth of the n-type buried channel is between 200nm and 500nm, and the typical distance from the surface at the maximum potential when the buried channel is depleted is between 100nm and 300nm.

[0056] In the column-level analog front-stage readout circuit structure, M1 and M2 use PMOS transistors with normal threshold or low threshold, and the gate area of ​​the M1 transistor is typically between 0.3um2 and 3um2.

[0057] Figure 2 Figure 3 Figure 4 Figure 5 In the column-level analog pre-stage readout circuit structure shown in FIG. RST The typical value of the capacitance formed by the gate of the PMOS tube M1 and the FD node is between 2fF and 20fF, and the typical reset voltage of the FD node is between 2.5V and 3V.

[0058] In the column-level analog front-stage readout circuit structure, the current source formed by M3 and M4 has a typical current value between 1-10 μA.

[0059] In the column-level analog front-stage readout circuit structure, switch SW RST , SW1, SW2 can be composed of a single NMOS transistor, a single PMOS transistor, a transmission gate composed of NMOS and PMOS, or a dummy switch.

[0060] In the column-level analog front-stage readout circuit structure, the typical capacitance value of C1 is between 500fF and 3pF, and the typical capacitance value of C2 is between 100fF and 500fF.

[0061] In the column-level analog front-stage readout circuit structure, the analog front-stage output Vout can be connected to a single-slope ADC with a digital correlated double sampling function, or to a programmable gain amplifier with analog correlated double sampling.

[0062] In the present invention, Figure 5 Given Figure 1 and Figure 2 A typical timing control method for the column-level FIR analog pre-stage circuit, V B2 The high and low levels of SW control the current closing and opening of M1 and M2; RST Responsible for controlling the reset of the FD node. When it is turned on, it resets the FD. At the same time, the reset of capacitor C1 is controlled by turning on SW2. RST After closing, that is, after FD is reset and SW2 is still on, switch SW1 is turned on to reset the drains of M2 and M3; then switch SW2 is turned off to filter and sample the signal; then switch SW1 is turned off to end the first sampling of the signal and output signal 1 to the next stage; then TG is turned on to transfer the charge in the CCD buried channel to the FD node; repeat the related operations of SW1 and SW2, filter and sample the changed FD signal, and output signal 2 to the next stage. Finally, each pixel and each frame signal forms two outputs, signal 1 and signal 2. Signal 1 represents the signal value of the FD node in the reset state, and signal 2 represents the signal value of the FD node after receiving the CCD photogenerated charge.

[0063] Figure 6 Given Figure 3 and Figure 4 A typical timing control method for the mid-level FIR+IIR analog pre-stage circuit, V B2 The high and low levels of SW control the current closing and opening of M1 and M2; RST Responsible for controlling the reset of the FD node. When it is turned on, it resets the FD. At the same time, the reset of capacitors C1 and C2 is controlled by turning on SW2. RST After closing, that is, after FD is reset and SW2 is still on, switch SW1 is turned on to reset the drains of M2 and M3; then switch SW2 is turned off to filter and sample the signal; during this sampling period, SW2 and SW3 are turned on alternately; then switch SW1 is turned off to end the first sampling of the signal and output signal 1 to the next stage; then TG is turned on to transfer the charge in the CCD buried channel to the FD node; repeat the related operations of switch SW1, switch SW2, and switch SW3, filter and sample the changed FD signal, and output signal 2 to the next stage. Finally, each pixel and each frame of the signal forms two outputs, signal 1 and signal 2, signal 1 represents the signal value of the FD node in the reset state, and signal 2 represents the signal value of the FD node after receiving the CCD photogenerated charge.

[0064] The present invention proposes a low-noise large full-well TDI-CMOS image sensor readout circuit, which is suitable for CCD-CMOS fusion TDI image sensors, and can especially improve the noise performance of the sensor under the premise of high buried channel depletion potential, high charge transfer efficiency, and large full-well buried channel CCD pixel design.

[0065] Only simple components are used, and through different circuit configurations, four types of circuits are realized: direct reset FIR analog readout pre-stage circuit, automatic zero reset FIR analog readout pre-stage circuit, direct reset FIR+IIR analog readout circuit, and automatic zero reset FIR+IIR analog readout pre-stage circuit, which can be selected according to needs;

[0066] The present invention sets a direct reset FIR analog readout pre-stage circuit and an automatic zero reset FIR analog readout pre-stage circuit to the same timing control; sets a direct reset FIR+IIR analog readout circuit and an automatic zero reset FIR+IIR analog readout pre-stage circuit to the same timing control; and improves the noise performance of the sensor under the premise of high buried channel depletion potential, high charge transfer efficiency, and large full well buried channel CCD pixel design.

[0067] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A low-noise large full-well TDI-CMOS image sensor readout circuit, characterized in that: The invention comprises a buried channel CCD structure and a readout module; wherein the buried channel CCD structure comprises a p-type substrate, an n-type buried channel, four CCD electrodes and a transmission gate TG; wherein the p-type substrate is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is arranged on the upper surface of the p-type substrate; the four CCD electrodes are evenly spaced and distributed on the upper surface of the n-type buried channel; the transmission gate TG is arranged on the upper surface of the n-type buried channel and is located outside the four CCD electrodes; a groove is arranged on the upper surface of the n-type buried channel; the readout module comprises an FD node and an analog readout pre-stage circuit; the FD node is connected to the analog readout pre-stage circuit; the FD node extends into the groove to realize the connection between the readout module and the n-type buried channel; The analog readout pre-stage circuit is a direct reset FIR analog readout pre-stage circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2 and capacitor C1; Among them, the switch SW RST One end is connected to the external power supply V DD-RST ; Switch SW RST The other end is connected to the FD node and the gate of the PMOS tube M1 respectively; the source of the PMOS tube M1 is connected to the external power supply V DD-AMP The drain of PMOS tube M1 is connected to the source of PMOS tube M2; the gate of PMOS tube M2 is connected to the external power supply V B2 The drain of the PMOS tube M2 is connected to one end of the switch SW1 and the drain of the NMOS tube M3; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is connected to one end of the capacitor C1 and one end of the switch SW2 respectively, and serves as an output at the same time; the other end of the capacitor C1 is grounded; the other end of the switch SW2 is connected to the external power supply V0.

2. A low-noise large full-well TDI-CMOS image sensor readout circuit, characterized in that: The invention comprises a buried channel CCD structure and a readout module; wherein the buried channel CCD structure comprises a p-type substrate, an n-type buried channel, four CCD electrodes and a transmission gate TG; wherein the p-type substrate is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is arranged on the upper surface of the p-type substrate; the four CCD electrodes are evenly spaced and distributed on the upper surface of the n-type buried channel; the transmission gate TG is arranged on the upper surface of the n-type buried channel and is located outside the four CCD electrodes; a groove is arranged on the upper surface of the n-type buried channel; the readout module comprises an FD node and an analog readout pre-stage circuit; the FD node is connected to the analog readout pre-stage circuit; the FD node extends into the groove to realize the connection between the readout module and the n-type buried channel; The analog readout pre-stage circuit is an automatic zero reset FIR analog readout pre-stage circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2 and capacitor C1; Among them, the source of PMOS tube M1 is connected to the external power supply V DD-AMP The gate of the PMOS tube M1 is connected to the FD node and the switch SW RST The drain of the PMOS tube M1 is connected to the source of the PMOS tube M2; the gate of the PMOS tube M2 is connected to the external power supply V B2 Connection; the drain of PMOS tube M2 is connected to the switch SW RST The other end of the switch SW1 is connected to the drain of the NMOS tube M3; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is connected to one end of the capacitor C1 and one end of the switch SW2 respectively, and is used as an output at the same time; the other end of the capacitor C1 is grounded; the other end of the switch SW2 is connected to the external power supply V0; The PMOS tube M1 and the PMOS tube M2 together form a transconductance amplifier, which converts the voltage of the front-stage FD node into current; the NMOS tube M3 and the NMOS tube M4 together form a current source; the charging process of the rear-stage capacitor C1 by the currents of the PMOS tube M1, the PMOS tube M2, the NMOS tube M3, and the NMOS tube M4 is controlled by the switch SW1; the resetting of the capacitor C1 is controlled by the switch SW2.

3. A low-noise large full-well TDI-CMOS image sensor readout circuit, characterized in that: The invention comprises a buried channel CCD structure and a readout module; wherein the buried channel CCD structure comprises a p-type substrate, an n-type buried channel, four CCD electrodes and a transmission gate TG; wherein the p-type substrate is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is arranged on the upper surface of the p-type substrate; the four CCD electrodes are evenly spaced and distributed on the upper surface of the n-type buried channel; the transmission gate TG is arranged on the upper surface of the n-type buried channel and is located outside the four CCD electrodes; a groove is arranged on the upper surface of the n-type buried channel; the readout module comprises an FD node and an analog readout pre-stage circuit; the FD node is connected to the analog readout pre-stage circuit; the FD node extends into the groove to realize the connection between the readout module and the n-type buried channel; The analog readout pre-stage circuit is a direct reset FIR+IIR analog readout circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2, switch SW3, capacitor C1 and capacitor C2; Among them, the switch SW RST One end is connected to the external power supply V DD-RST ; Switch SW RST The other end is connected to the FD node and the gate of the PMOS tube M1 respectively; the source of the PMOS tube M1 is connected to the external power supply V DD-AMP The drain of PMOS tube M1 is connected to the source of PMOS tube M2; the gate of PMOS tube M2 is connected to the external power supply V B2 The drain of the PMOS tube M2 is connected to one end of the switch SW1 and the drain of the NMOS tube M3; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is respectively connected to one end of the capacitor C1 and one end of the switch SW3; the other end of the capacitor C1 is grounded; the other end of the switch SW3 is respectively connected to one end of the switch SW2 and one end of the capacitor C2, and serves as an output at the same time; the other end of the switch SW2 is connected to the external power supply V0; the other end of the capacitor C2 is grounded.

4. A low-noise large full-well TDI-CMOS image sensor readout circuit, characterized in that: The invention comprises a buried channel CCD structure and a readout module; wherein the buried channel CCD structure comprises a p-type substrate, an n-type buried channel, four CCD electrodes and a transmission gate TG; wherein the p-type substrate is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is a horizontally placed rectangular parallelepiped structure; the n-type buried channel is arranged on the upper surface of the p-type substrate; the four CCD electrodes are evenly spaced and distributed on the upper surface of the n-type buried channel; the transmission gate TG is arranged on the upper surface of the n-type buried channel and is located outside the four CCD electrodes; a groove is arranged on the upper surface of the n-type buried channel; the readout module comprises an FD node and an analog readout pre-stage circuit; the FD node is connected to the analog readout pre-stage circuit; the FD node extends into the groove to realize the connection between the readout module and the n-type buried channel; The analog readout pre-stage circuit is an automatic zero reset FIR+IIR analog readout pre-stage circuit, including a switch SW RST , PMOS tube M1, PMOS tube M2, NMOS tube M3, NMOS tube M4, switch SW1, switch SW2, switch SW3, capacitor C1 and capacitor C2; Among them, the source of PMOS tube M1 is connected to the external power supply V DD-AMP The gate of the PMOS tube M1 is connected to the FD node and the switch SW RST The drain of PMOS tube M1 is connected to the source of PMOS tube M2; the gate of PMOS tube M2 is connected to the external power supply V B2 The drain of the PMOS tube M2 is connected to the switch SW RST The other end of the NMOS tube M3, the drain of the NMOS tube M3, and one end of the switch SW1; the gate of the NMOS tube M3 is connected to the external power supply V B3 ; The source of NMOS tube M3 is connected to the drain of NMOS tube M4; The gate of NMOS tube M4 is connected to the external power supply V B4 ; The source of the NMOS tube M4 is grounded; the other end of the switch SW1 is respectively connected to one end of the capacitor C1 and one end of the switch SW3; the other end of the capacitor C1 is grounded; the other end of the switch SW3 is respectively connected to one end of the switch SW2 and one end of the capacitor C2, and serves as an output at the same time; the other end of the switch SW2 is connected to the external power supply V0; the other end of the capacitor C2 is grounded.

5. The low-noise large full-well TDI-CMOS image sensor readout circuit according to claim 4, characterized in that: The PMOS tube M1 and the PMOS tube M2 together form a transconductance amplifier, which converts the voltage of the front-stage FD node into current; the NMOS tube M3 and the NMOS tube M4 together form a current source; the switch SW1 controls the charging process of the PMOS tube M1, the PMOS tube M2, the NMOS tube M3, and the NMOS tube M4 currents on the rear-stage capacitors C1 and C2; the switch SW2 controls the resetting of the capacitors C1 and C2; the switch SW3 controls the capacitors C1 and C2 to form an IIR filter.

6. A low-noise large full-well TDI-CMOS image sensor readout circuit according to claim 1 or 2, characterized in that: External power supply V B2 The high and low levels of the PMOS tube M1 and the PMOS tube M2 are controlled to close and open the current; through the switch SW RST Control the reset of the FD node; control the reset of the capacitor C1 by turning on the switch SW2; RST After closing, that is, after the FD node is reset, when the switch SW2 is still turned on, the drains of the PMOS tube M2 and the NMOS tube M3 are reset by turning on the switch SW1; then the switch SW2 is turned off to filter and sample the signal; Then, the switch SW1 is turned off to end the first sampling of the signal and output signal 1 to the next stage; Then the transfer gate TG is turned on to transfer the charges of the buried-channel CCD structure to the FD node; Repeat the above operations of switch SW1 and switch SW2, filter the changed FD node signal, and output signal 2 to the next stage; Signal 1 is the signal value of the FD node in the reset state, and signal 2 is the signal value of the FD node after receiving the CCD photogenerated charge.

7. A low-noise large full-well TDI-CMOS image sensor readout circuit according to claim 3 or 4, characterized in that: External power supply V B2 The high and low levels of the PMOS tube M1 and the PMOS tube M2 are controlled to close and open the current; through the switch SW RST Control the reset of the FD node; control the reset of capacitors C1 and C2 by turning on switch SW2; RST After closing, that is, after the FD node is reset, when the switch SW2 is still turned on, the drains of the PMOS tube M2 and the NMOS tube M3 are reset by turning on the switch SW1; then the switch SW2 is turned off to filter and sample the signal; during this period, the switches SW2 and SW3 are turned on alternately; then the switch SW1 is turned off to end the first sampling of the signal and output the signal 1 to the next stage; Then the transfer gate TG is turned on to transfer the charges of the buried-channel CCD structure to the FD node; Repeat the above operations of switch SW1, switch SW2, and switch SW3 to filter the changed FD node signal and output signal 2 to the next stage; Signal 1 is the signal value of the FD node in the reset state, and signal 2 is the signal value of the FD node after receiving the CCD photogenerated charge.

8. The low-noise large full-well TDI-CMOS image sensor readout circuit according to claim 4, characterized in that: The gate area of ​​PMOS tube M1 and PMOS tube M2 is 0.3-3μm 2 ; Switch SW RST The capacitance value formed by the gate of the PMOS tube M1 and the FD node is 2-20fF; the reset voltage of the FD node is 2.5-3V; the current value of the NMOS tube M3 and the NMOS tube M4 is 1-10μA; the capacitance value of the capacitor C1 is 500fF-3pF; the capacitance value of the capacitor C2 is 100-500fF.

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