Integrated circuit and system having integrated circuit

Abstract

The present disclosure relates to a layout of an integrated resistor with current sensing functionality. One or more layout techniques can be used to balance a current sense circuit. The current sense circuit can include an upper layer resistor of an amplifier formed of polysilicon material. The upper layer resistor can be symmetrically arranged with respect to one or more stress gradients to improve accuracy of the current sense circuit. The stress gradients can include a stress gradient with respect to an axis and a stress gradient with respect to a die edge.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to wireless power, and more specifically to current sensing. BACKGROUND

[0002] Current sensing is one block in a wireless power system. The sensed current, along with a voltage measurement, provides a power measurement of the system. The power measurement is critical to know how much power is actually received from the transmitter and delivered to the load, such as a battery. In particular, a wireless power system must measure power very accurately to help foreign object detection. It is undesirable for a foreign object to receive power from the transmitter and start to overheat. The receiver can include current sensing functionality to measure the received power to determine the power loss caused by the foreign object. The power loss caused by the foreign object can be predicted by more accurately determining the received current. Thus, it is desirable to determine the received current at a given level of accuracy. However, the current sensing functionality of a wireless power system can include inaccuracies introduced by one or more sources.

[0003] In view of the above, one or more embodiments of the present disclosure provide an integrated circuit including improved current sensing capabilities. SUMMARY

[0004] According to one or more illustrative embodiments of the disclosure, an integrated circuit is described. In some embodiments, the integrated circuit includes a current sensing circuit including a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. In some embodiments, the first resistor includes a first resistance (Rs), the second and third resistors each include a second resistance (Rt), and the fourth and fifth resistors each include a third resistance (Rb). In some embodiments, the first resistor is configured to carry a first current (Isns) that is based on the first resistance (Rs) and a voltage difference between a first voltage (Vrect) and a second voltage (Vmid). In some embodiments, the first amplifier is configured to output a third voltage (Vo) based on the current (Isns). In some embodiments, a gain of the first amplifier is based on the second resistance (Rt) and the third resistance (Rb). In some embodiments, the first resistor is formed from a first plurality of polysilicon slices. In some embodiments, the second resistor is formed from a second plurality of polysilicon slices. In some embodiments, the third resistor is formed from a third plurality of polysilicon slices. In some embodiments, the first, second, and third pluralities of polysilicon slices are disposed on a layer of the integrated circuit. In some embodiments, the second plurality of polysilicon slices is arranged symmetrically with respect to the third plurality of polysilicon slices about an axis to reduce a stress difference between the second and third pluralities of polysilicon slices.

[0005] According to one or more illustrative embodiments of the disclosure, a wireless power system is described. In some embodiments, the wireless power system includes a coil. In some embodiments, the wireless power system includes an integrated circuit. In some embodiments, the integrated circuit includes a rectifier circuit configured to receive an alternating current from the coil and generate a first voltage (Vrect). In some embodiments, the integrated circuit includes a current sense circuit including a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. In some embodiments, the first resistor includes a first resistance (Rs), the second and third resistors each include a second resistance (Rt), and the fourth and fifth resistors each include a third resistance (Rb). In some embodiments, the first resistor is configured to carry a first current (Isns) that is based on the first resistance (Rs) and a voltage difference between the first voltage (Vrect) and a second voltage (Vmid). In some embodiments, the first amplifier is configured to output a third voltage (Vo) based on the current (Isns). In some embodiments, a gain of the first amplifier is based on the second resistance (Rt) and the third resistance (Rb). In some embodiments, the first resistor is formed from a first plurality of polysilicon slices, the second resistor is formed from a second plurality of polysilicon slices, and the third resistor is formed from a third plurality of polysilicon slices. In some embodiments, the first, second, and third pluralities of polysilicon slices are disposed on a layer of the integrated circuit. In some embodiments, the second plurality of polysilicon slices is symmetrically arranged relative to the third plurality of polysilicon slices about an axis to reduce a stress difference between the second and third pluralities of polysilicon slices. In some embodiments, the integrated circuit includes a voltage regulator circuit configured to regulate the second voltage (Vmid). In some embodiments, the integrated circuit includes a processor. In some embodiments, the processor is configured to receive one or more digital signals of the third voltage (Vo) and determine the current (Isns) based on the third voltage (Vo). In some embodiments, the wireless power system includes a battery charging system. BRIEF DESCRIPTION OF DRAWINGS

[0006] Embodiments of the concepts disclosed herein can be better understood with regard to the following detailed description. This description references the drawings, which are not necessarily to scale and are provided to clearly describe some features and to illustrate some embodiments. Identical reference numbers in the figures can represent and refer to the same or similar elements, features, or functions throughout the figures. In the figures:

[0007] Figures 1A to 1Ca top view depicting a layout of components of a current sense circuit according to one or more embodiments of the present disclosure.

[0008] Figures 2A to 2B a side view depicting a layout of components of a current sense circuit according to one or more embodiments of the present disclosure.

[0009] Figure 3 a top view depicting a layout of components of a current sense circuit according to one or more embodiments of the present disclosure.

[0010] Figure 4 a circuit diagram depicting a current sense circuit according to one or more embodiments of the present disclosure.

[0011] Figures 5A to 5B a circuit diagram depicting a current sense circuit according to one or more embodiments of the present disclosure.

[0012] Figure 6 a top view depicting a layout of components of a current sense circuit according to one or more embodiments of the present disclosure.

[0013] Figure 7 a simplified block diagram depicting an integrated circuit including a current sense circuit according to one or more embodiments of the present disclosure.

[0014] Figure 8 a simplified schematic diagram depicting a wireless power system according to one or more embodiments of the present disclosure.

[0015] Figure 9 a simplified communication device including one or more components of a wireless power system according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Before one or more embodiments of the present disclosure are explained in detail, it is to be understood that the application of the embodiments is not limited to the details of construction and the arrangement of components or steps or methods set forth in the following description or illustrated in the drawings. In the following detailed description of the embodiments, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art, having the benefit of the present disclosure, that the embodiments disclosed herein can be practiced without these specific details. In other instances, well-known features are not described in detail to avoid obscuring the present disclosure.

[0017] As used herein, letters following reference numerals are intended to refer to embodiments of features or elements that can be similar but not necessarily identical to the preceding elements or features having the same reference numeral (e.g., 1, 1a, 1b). Such shorthand notations are merely for convenience and are not to be construed as limiting the present disclosure in any way, unless expressly so stated.

[0018] Also, "or" means "inclusive or" and not "exclusive or", unless expressly stated otherwise. For example, a condition A or B is satisfied by either of the following: A is true (or present) and B is false (or not present); A is false (or not present) and B is true (or present); and both A and B are true (or present).

[0019] Also, "a" or "an" can be used to describe elements and components of the embodiments disclosed herein. This is only for convenience and is not intended to invoke a limiting choice of singular v. plural with respect to the present disclosure.

[0020] Finally, as used herein any reference to "one embodiment" or "some embodiments" means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, and the

[0021] Reference will now be made to the detailed description of the disclosure.

[0022] Integrated circuits include current sense circuits having resistors formed of polysilicon material. The resistors can suffer from internal stress, which can be generated during fabrication of the integrated circuit. When stress is applied to the resistors, a piezoresistive effect can cause the resistivity of the resistors to change. Variations in the resistivity are undesirable, causing errors in the resistors, particularly in high accuracy environments. For high accuracy current sense circuits operating at 1 amp of current, 1 milliamp corresponds to 0.1% error. In some examples, the current sense circuits can be designed to achieve an accuracy of 0.5% within, such that a 1 milliamp error caused by the piezoresistive effect consumes 20% of the 0.5% error. Therefore, compensating for the offset between the resistors is critical to achieving the desired accuracy level.

[0023] Embodiments of the present disclosure generally relate to one or more layouts of an integrated circuit for compensating for piezoresistivity of resistors formed of polysilicon material. When physically implementing a resistor within an integrated circuit, the resistor can undesirably suffer from stress caused by pressure. The resistor can be laid out on the integrated circuit with respect to a stress gradient to reduce the stress, and similarly reduce resistance variation caused by piezoresistivity. In particular, a pair of matched resistors (e.g., each having a 1 kilo-ohm resistance) can be disposed the same distance from a chip edge and / or symmetrically about an axis. The pair of matched resistors can be inputs to an amplifier. A second pair of matched resistors can be outputs of the amplifier and can similarly be arranged to reduce resistance variation. In this regard, the amplifier can include an offset and a gain, the percentage error of which can be improved by reducing error corresponding to resistance variation caused by piezoresistivity. Thus, the piezoresistive effect of the stress gradient can be compensated for without requiring post-fabrication software calibration of each integrated circuit.

[0024] Referring generally to Figures 1A to 6 , a current sense circuit 100 is described. The current sense circuit 100 can be configured to measure current across a wide range of voltages, such as up to 24 volts or higher. The current sense circuit 100 can be configured to measure current with a relatively large dynamic range, such as (but not limited to) between 1 milliamp to up to 2.5 amps or greater. Through one or more layout configurations, a switching matrix for determining offset, and a dual channel approach for analog and digital control loops, the accuracy of the current sense circuit 100 is expected to be within 0.5% of the actual current across the dynamic range of the current. Although the current sense circuit 100 is depicted as including various components included in respective layouts, this is not intended to be a limitation of the present disclosure. It is further expected that the current sense circuit 100 can include various additional components not depicted. It is noted herein, for purposes of the present disclosure, that "coupled" can mean one or more of "communicatively coupled to," "electrically coupled to," and / or "physically coupled to." As used herein, coupled can refer to either a direct or indirect coupling. An indirect coupling can refer to a connection through another functional element. A direct coupling can refer to a connection without an intermediate element. It is noted herein that "coupled between" can be understood with respect to movement or flow of a signal between two or more components, and can additionally include intervening components.

[0025] Referring now to Figures 1A to 1C , layouts of one or more components of the current sense circuit 100 are described in accordance with one or more embodiments of the present disclosure.

[0026] The current sense circuit 100 can include one or more of resistor 102, resistor 104, and resistor 106. Resistor 102 can also be referred to herein as a sense resistor having a resistance (Rs). For example, the resistance (Rs) can be 20 milli-ohms, but this is not intended to be limiting. The value range of resistor 102 is contemplated to be around the exemplary 20 milli-ohm resistor. In this regard, the resistance value can be selected to be about 1 to 100 milli-ohms or greater. Resistor 104 and resistor 106 can be connected to the input of amplifier 108, such that resistor 104 and resistor 106 can also be referred to herein as upper layer resistors. Resistor 104 and resistor 106 can each include a resistance (Rt), such that resistor 104 and resistor 106 can also be referred to as a pair of matched resistors. For example, the resistance (Rt) can be 1 kilo-ohm (e.g., 1 kΩ resistor), but this is not intended to be limiting. The current sense circuit 100 can further include one or more dummy resistors 124. The current sense circuit 100 can further include one or more switches 122 (e.g., switches (Ml), (M2), (M3), and (M4)). The switches (Ml-M4) can be provided to measure the offset of the current sense circuit, which is caused by resistor 104, resistor 106, resistor 110, resistor 112, and amplifier 108, as will be further described herein.

[0027] As Figure 1A The resistors 102, 104, 106, and dummy resistors 124 are depicted with different hatching, which is not intended to be limiting. Rather, the resistors 102, 104, 106, and dummy resistors 124 are depicted with hatching to illustrate the number of array elements that each resistor includes. The layout of resistors 102, 104, and 106 is contemplated to be beneficial for any number of current sense circuits that sense current in the milli-amp to amp range.

[0028] In an embodiment, the resistors 102, 104, and 106 each include a poly-silicon resistor formed onto a substrate. The poly-silicon resistor can also be referred to herein as a poly-resistor or an internal poly-resistor. In an embodiment, the poly-silicon resistor is formed as an array of array elements each including a piece of poly-silicon. Figure 1AThe resistor 102 is depicted as containing 140 array elements, the resistor 104 is depicted as containing 7 array elements, the resistor 106 is depicted as containing 7 array elements, and the dummy resistor 124 is depicted as containing 6 array elements, but this is not intended to be limiting. Further, although not depicted, the array elements of each of the resistor 102, the resistor 104, and the resistor 106 can be coupled in various series or parallel arrangements to achieve a desired resistance value. As further depicted in FIG. 2, each array element can contain a number of polysilicon slices. For example, an array element can also be referred to as a 10x resistor, such that each array element contains 10 polysilicon slices (also referred to as fingers), but this is not intended to be limiting. Thus, the resistor 102 can contain 1400 polysilicon slices and the resistor 104 and the resistor 106 can each contain 70 polysilicon slices.

[0029] Thus, the resistor 102, the resistor 104, and the resistor 106 can each be formed from a plurality of polysilicon slices. The polysilicon slices can comprise any polysilicon material known in the art, such as, but not limited to, doped or undoped polysilicon films. The polysilicon slices can be disposed on the same layer of an integrated circuit, such as below a metallization layer. The polysilicon slices can include a resistance that varies with temperature. Using polysilicon slices can facilitate a reduced temperature coefficient compared to implementing the resistor 102, the resistor 104, and the resistor 106 in a metallization layer of an integrated circuit. For example, the polysilicon slices can include a temperature coefficient of resistance (TCR) of between 150 and 160 parts per million per degree Celsius, but this is not intended to be limiting. The polysilicon slices can each include a resistance value. For example, the polysilicon slices can each include a slice resistance of 300 ohms per square, but this is not intended to be limiting. The polysilicon slices can be arranged in parallel and / or in series. The parallel and / or series arrangement of the polysilicon slices can be used to form a resistor array of polysilicon resistors having a selected resistance value. The resistance of the sense resistor (Rs), the resistance of the upper resistor (Rt), and the resistance of the lower resistor (Rb) are based on the number and arrangement of the array of polysilicon slices. The number of resistor elements used to form the array of the resistor 102 can be substantially more than the number of resistor elements used to form the upper resistor. Providing substantially more resistor elements 102 than the upper resistor can result in the resistance (Rs) being substantially less than the resistance (Rt). Consider an example in which the resistor 102 has 140 array elements, with each array element containing 10 polysilicon slices. In this example, the resistor 102 can be composed of 1400 parallel polysilicon slices to achieve a resistance value of 20 milliohms for the resistance (Rs), but this is not intended to be limiting.

[0030] It is desirable to ensure that resistors 104 and 106 are as close as possible to their matched resistance values, for example, to ensure the gain of one or more amplifiers suitable for a current sensing circuit. One challenge in implementing resistors 102, 104, and 106 is due to the piezoresistive nature of polysilicon. In this respect, the resistance (Rs) and the anti-resistance (Rt) can change when the polysilicon wafer is subjected to pressure. Each of resistors 104 and 106 can be subjected to stress due to pressure. In some examples, the stress on resistor 104 may differ from the stress on resistor 106, which may also be referred to herein as stress difference.

[0031] like Figure 1B As depicted, the stress gradient plot 130 of the integrated circuit can decrease away from axis 126 and can be further symmetrical about axis 126. Similarly, the resistance plot (not depicted) varying with distance shows the change in resistance away from the axis. Figure 1C As further described, the stress gradient plot 131 of the integrated circuit can vary away from the die edge 128. For example, the stress gradient may be highest at the die edge 128 and decrease non-linearly across the die, making the stress gradient across the integrated circuit from the die edge 128 non-linear. Similarly, a resistance plot (not depicted) varying with distance shows the change in resistance away from the die edge 128. It should be understood that plots 130 and 131 are not intended to be limiting. In this respect, plots 130 and 131 may include batch-to-batch and / or portion-to-part variations.

[0032] In an embodiment, resistors 104 and 106 may be arranged symmetrically about the stress gradient to minimize the resistance variation caused by piezoresistive properties.

[0033] In this embodiment, resistors 104 and 106 comprise an array of polysilicon wafers symmetrically arranged about an axis 126. Axis 126 may include a central axis. In this respect, the stress difference between the polysilicon wafers of resistors 104 and 106 can be reduced, thereby causing the matching resistor pair to experience similar stress and similar resistance changes caused by piezoresistive properties. This resulting in similar resistance changes in the matching resistor pair can be particularly advantageous, where each resistor is coupled to the input of a differential amplifier, thereby improving the accuracy of the differential amplifier.

[0034] In an embodiment, resistors 104 and 106 include array elements having polysilicon pieces arranged the same distance from a die edge 128 of an integrated circuit. Resistors 104 and 106 can be piezoresistive and change resistance due to pressure. The change in resistance due to pressure can affect the offset and gain of downstream amplifiers. By arranging resistors 104 and 106 the same distance from axis 126 and die edge 128, the stress difference between the resistors can be reduced. Reducing the stress difference can result in the resistors experiencing similar resistance changes. Thus, arranging the resistors the same distance from the chip edge can minimally affect the offset and gain of downstream amplifiers (e.g., where resistors 104 and 106 are inputs to the amplifiers) compared to arranging resistors 104 and 106 different distances from die edge 128.

[0035] Resistors 104 and 106 can also be placed a distance from the die edge in a portion of the stress gradient that is flatter than the area closer to the die edge. In this regard, the resistance of the matched resistor pair can minimally change, thereby minimizing the effect on the gain of the amplifier. For example, one or more array elements of resistor 102 and one or more of switches (M1-M4) can be placed between die edge 128 and resistors 104, 106, thereby spacing resistors 104, 106 from die edge 128.

[0036] As depicted, the layout can include a resistor array. The array can be separated based on one or more deep n-well (DNW) regions 132 of the integrated circuit, but this is not intended to be limiting. In this regard, the resistors can be placed in a layer above DNW regions 132. For example, Figure 1AA 2x4 array of DNW regions 132 is depicted, where each of the DNW regions 132 includes two rows and each row has 10 array elements. As further depicted, a first 1x4 array of DNW regions 132 is separated from a second 1x4 array of DNW regions 132 by switches (M1-M4). Although DNW regions 132 are depicted as including 20 array elements, this is not intended to be a limitation of the present disclosure. DNW regions 132 can generally include any suitable number for achieving a desired resistance. For example, DNW regions 132 can include 22 array elements per DNW region 22 (i.e., a row of 11 array elements). In this example, the total number of array elements can be 176 elements (i.e., a 2x4 array of DNW regions, each including 22 elements). When each element includes 10 fingers or polysilicon pieces, the array can include 1760 polysilicon pieces. To achieve a 20 milli-ohm resistance for resistor 102, 1400 of the 1760 polysilicon pieces can be used for a total of 140 array elements. To achieve a 1 kOhm resistance for each of resistor 104 and resistor 106, 70 array elements can be used. The remaining layout can include 12 unused array elements (e.g., dummy resistor 124).

[0037] In an embodiment, both resistor 104 and resistor 106 are symmetrically arranged about axis 126 and disposed the same distance from die edge 128, as depicted. The resistors will still experience stress to cause resistance variation. Advantageously, the resistivity of resistor 104 and resistor 106 changes at a similar rate. The resistivity can change at a similar rate because both resistors are the same distance from edge 128 and in the same orientation about axis 126. Thus, the resistance (Rt) of each resistor can be more closely matched. For example, the array elements of resistor 104 and resistor 106 are depicted as disposed in separate DNW regions 132 that are closest to axis 126 and separated from die edge 128 by a second group of DNW regions 132.

[0038] Resistor 102 can include one or more rows of array elements, including polysilicon pieces. The one or more rows of resistor 102 are disposed between die edge 128 and the polysilicon pieces of resistor 104. Similarly, one or more rows of resistor 102 are disposed between die edge 128 and the polysilicon pieces of resistor 106. The rows can be considered closer to die edge 128 and can also be disposed within a region that experiences a higher concentration of stress. Thus, resistor 102 can experience relatively more variation caused by piezoresistance than resistor 104 or resistor 106. For example, resistor 102 is depicted as including 14 rows of array elements, where each row has 10 array elements. Resistor 102 is further depicted as including 8 rows between die edge 128 and resistor 104 or resistor 124.

[0039] The resistor 102 can additionally include one or more rows of array elements arranged at the same distance from the die edge 128 as the resistor 104 or the resistor 106. The rows arranged at the same distance can also be arranged symmetrically about the axis 126. The polysilicon pieces of the resistor 104 and the resistor 106 can also be disposed between one or more rows of the first resistor 102. For example, the resistor 104 and the resistor 106 are depicted as being disposed between three rows of the resistor 102 arranged symmetrically about the axis, which are disposed at the same distance from the die edge 128. Thus, the resistor 102 can include a layout that reduces the space between the resistor 104 and the resistor 106 for better matching.

[0040] The resistor 102, the resistor 104, and the resistor 106 can be disposed in the same layer of the circuit to reduce temperature differences. In an embodiment, the resistor 104 and the resistor 106 can be fingered to reduce temperature differences between the resistor 104 and the resistor 106. Reducing temperature differences is valuable to minimize errors caused by temperature-induced resistance variations.

[0041] Fingered can refer to interleaving one or more subcomponents of a first component with one or more subcomponents of a second component. For example, an array can include polysilicon pieces of a first component that are fingered with polysilicon pieces of a second component. By way of another example, a switch matrix can include a first switch that is fingered with a second switch on a layer to match channel resistance. Channel resistance can refer to resistance from drain to source.

[0042] The integrated circuit can be further configured to directly measure offset. The current sensing circuit 100 can further include one or more switches. For example, the switches can include four switches (M1-M4). The switches (M1-M4) can be provided to measure offset. The switches (M1-M4) can also be arranged symmetrically about the stress gradient. For example, the switch (M2) and the switch (M3) can be symmetric about the axis 126 relative to the switch (M1) and the switch (M4).

[0043] The switches (M1-M4) can be disposed on the same layer as the resistor 102, the resistor 104, and the resistor 106. In an embodiment, the switch (M1) can be fingered with the switch (M4). Similarly, the switch (M2) can be fingered with (M3). Fingered switches can be beneficial to match channel resistance of the switch (M1) and the switch (M4) and similarly match channel resistance of the switch (M2) and the switch (M3). Alternative ways are contemplated for laying out the switches (M1-M4). For example, the switch (M1) and the switch (M4) can be separate and can be arranged in any order with the switch (M2) and the switch (M3). The switch (M1) and the switch (M4) can also be arranged symmetrically about the axis relative to the switch (M2) and the switch (M3).

[0044] Reference is made generally to Figures 2A to 2B, describing an array element of a polysilicon resistor. The polysilicon resistor can include one or more of resistor 102, resistor 104, or resistor 106. The array element can include one or more polysilicon slices 134 and one or more metallization layers 136. The array element can further include one or more vias 138 connecting the polysilicon slices 134 to the metallization layers 136.

[0045] The array element can include any number of polysilicon slices 134. For example, the array element can include 12 polysilicon slices 134 (e.g., two dummy slices and slices 1 through 10), but this is not intended to be limiting. As depicted, array element 201 and array element 203 each include 10 coupled polysilicon slices (1 through 10) and 2 dummy polysilicon slices (Dmy). The polysilicon slices 134 can include a suitable size range. For example, the polysilicon slices 134 can be relatively wide, such as (but not limited to) 50 microns wide. The polysilicon slices 134 can further include a length, such as (but not limited to) 4 microns long. Thus, the aspect ratio of the polysilicon slices 134 can be 50 microns x 4 microns, but this is not intended to be limiting. Polysilicon slices having an aspect ratio of 50 microns x 4 microns have been experimentally determined to include a temperature coefficient of 150 PPM / C. Setting the size of the polysilicon slices to have the same aperture and similar same temperature coefficient can be beneficial to offset the temperature coefficient of resistance (Rs) and resistance (Rt).

[0046] The connections between the plurality of polysilicon slices 134 are routed between one or more of the metallization layers 136. In addition to the polysilicon slices 134, the metallization layers 136 of the integrated circuit can also be resistive. Thus, the resistance value of the array element can be based on the array itself as well as the metallization layers used to get current in and out of the polysilicon slices 134. The metallization layers can be formed of one or more materials, such as (but not limited to) copper. The layers can include a resistivity inversely proportional to thickness. As depicted, the array element can include four metallization layers. Although the array element is depicted as including four metallization layers, this is not intended to be limiting. For example, each array element can include six metallization layers (m1 through m6). The layers (m1 through m5) can be relatively thin and include a surface resistivity (e.g., 300 milli-ohms per square). The layers (m1 through m5) can be high density metal interconnects for various digital signals. In comparison, the layer (m6) can be relatively thicker than the layers (m1 through m5) and include a relatively lower surface resistivity (e.g., 4 milli-ohms per square). The layer (m6) can be provided for an analog path for high current. The layer (m6) can also be described as a top layer or a package layer. The metallization layers (m1 through m6) can be provided as one or more parallel layers. The parallel layers can be disposed on top of the polysilicon slice layers. The polysilicon slice layers can be disposed on top of one or more deep n-well (DNW) layers.

[0047] When designing a current sense circuit, parasitic resistance caused by routing between polysilicon slices 134 results in an error term. Mismatch between upper layer resistors of the current sense circuit can result in a significant percentage error. For example, when resistors 104 and 106 are 1 kQ resistors, a 1 ohm resistor mismatch results in a 0.1% error. 3 square metal in layers (m1 to m5) can result in this error. In an embodiment, connections between polysilicon slices 134 can be routed between metallization layers 136 that include a lower sheet resistivity. Routing through layers with a lower sheet resistivity can minimally affect the resistance of resistor 102, resistor 104, or resistor 106. For example, layer (m6) can be used to route connections between polysilicon slices 134 due to the lower sheet resistivity. In this regard, connecting polysilicon slices 134 through layer (m6) can reduce the ohmic resistance caused by metallization layers.

[0048] Layers (m1 to m5) can be disposed between layer (m6) and polysilicon slices 134. Vias 138 can be coupled between polysilicon slices 134 and metallization layers 136. For example, vias 138 can be provided to couple polysilicon slices 134 with layer (m6). Vias 138 can pass vertically through layers (m1 to m6) to route current laterally through layer (m6). Vias 138 can also be referred to as stack vias. Vias 138 can also include a resistivity. The resistance of vias 138 can result in an additional error term. In an embodiment, the resistance of vias 138 is matched between array element 201 and array element 203. Each of array element 201 and array element 203 can be passed through the same number of vias to match the resistance. Current can then flow through the stack vias to the polysilicon slices, flow along the polysilicon slices, and then to layer (m6) through a second set of stack vias to a different portion of metal 6 layer.

[0049] Referring now to Figure 2A , array element 201 of resistor 102 is described. Array element 201 of resistor 102 can include one or more of polysilicon slices 134 coupled in parallel, such as 10 polysilicon slices 134 through vias 138 and metallization layers 136. As depicted, the resistance of the array element can be based on the resistance of the polysilicon slices (Rpoiy) and the resistance of the vias (Rcontact). In some examples, each of the polysilicon slices 134 of each array element of resistor 102 are coupled in parallel. By coupling each of polysilicon slices 134 in parallel, the resistance (Rs) of resistor 102 can be very low resistance. Providing very low resistance is beneficial to minimize power loss across resistor 102. Each of polysilicon slices 1 to 10 can be coupled in parallel. For example, the resistance (Rs) of resistor 102 can be 20 milli-ohms, but this is not intended to be limiting. The resistance can be defined by the following equation:

[0050] R = [Rpoiy + (2 * Rcontact)] / 10

[0051] Resistor 102 can further include any number of array elements 201 to achieve a desired resistance, for example Figure 1A 140 array elements 201 of the layout depicted in FIG. 1.

[0052] Referring now to Figure 2B , array elements 203 of resistor 104 and resistor 106 are described. Array elements 203 can include one or more polysilicon slices coupled in series. As depicted, the resistance of an array element can be based on the resistance of a polysilicon slice (Rpoly) and the resistance of a via (Rcontact). Array element 203 can include a via 138 that rises and passes through resistor slice 9, rises through the via, and falls. Resistor slice 8 can then be skipped. The pattern can continue with slices 1, 3, 5, 7, and 9 coupled in series and resistor slices 2, 4, 6, and 8 skipped. In this regard, array elements 201 and array elements 203 can include matching via resistances. For example, the resistance can be defined by the following equation:

[0053] R = (5 * Rpoly) + (10 * Rcontact)

[0054] = 5 * [Rpoly + (2 * Rcontact)]

[0055] Resistor 104, 106 can further include any number of array elements 203 to achieve a desired resistance, for example Figure 1B 7 array elements 203 of the layout depicted in FIG. 1.

[0056] Referring now to Figure 3 , layouts of current sense circuit 100 are further described in accordance with one or more embodiments of the disclosure. Current sense circuit 100 can additionally include resistor 110 and resistor 112. Resistor 110 and resistor 112 can be connected to the output of an amplifier such that resistor 110 and resistor 112 can also be referred to herein as lower layer resistors. Resistor 110 and resistor 112 can each include a resistance (Rb) such that resistor 110 and resistor 112 can also be referred to as a pair of matching resistors. For example, the resistance (Rb) can be 17.5 kilo-ohms (e.g., a 17.5 kΩ resistor), but this is not intended to be limiting.

[0057] Although not depicted, resistor 110 and resistor 112 can each include a number of array elements arranged from polysilicon slices and arranged to form a resistance (Rb). The array elements can be arranged in a checkerboard pattern in order to improve matching. As depicted, resistor 110 and resistor 112 are laid out in a symmetric matrix.

[0058] The current sense circuit 100 can further include one or more of a package pin 140 and a package pin 142. The package pin 140 and the package pin 142 can be centrally disposed about the axis 126 to reduce stress gradients of array elements disposed thereunder, thereby improving matching between the resistor 104 and the resistor 106. Package pins can be provided for coupling an integrated circuit package with external components. Package pins can also be referred to as pins or leads.

[0059] The current sense circuit 100 can further include one or more resistors 144 for a secondary amplifier path (e.g., an analog path), as will be described with reference to Figures 5A to 6 Further described. For example, the resistors 144 can include a pair of integrated 1 kQ resistors and 17K resistors arranged in a checkerboard pattern.

[0060] Referring now to Figure 4 , a circuit diagram of the current sense circuit 100 is described in accordance with one or more embodiments of the disclosure. The current sense circuit 100 can provide a structure to measure current across a resistor with a selected level of accuracy and across a wide range of current values. The current sense circuit 100 can be configured to output a voltage (Vo). The voltage (Vo) can be provided to an analog-to-digital converter, which produces a digital signal that is then used by a processor to determine a current (Isns). The current sense circuit 100 can include one or more components for generating the voltage (Vo). For example, the current sense circuit 100 can include the resistor 102, the resistor 104, the resistor 106, the amplifier 108, the resistor 110, the resistor 112, the transistor 114, and the transistor 116. The current sense circuit 100 can additionally include one or more switches 122 (i.e., switch (Ml), switch (M2), switch (M3), and switch (M4)).

[0061] The resistor 102 can be coupled between a node having a first voltage (Vrect) and a node having a voltage (Vmid). A node can refer to a point of connection between one or more elements of a circuit and / or between one or more branches of a circuit. A node can be represented by a wire connecting various elements and / or branches. The resistor 102 can include a resistance (Rs). The resistance (Rs) can include a relatively small resistance value. Due to an inverse relationship between resistance and power loss, the resistance (Rs) can be relatively small to reduce the amount of power dissipated across the resistor 102. For example, the resistor 102 can be a 20 milli-ohm resistor, but this is not intended to be limiting. The resistor 102 can be configured to carry a current (Isns) across the resistor, which is based on the resistance (Rs) and a voltage difference between the voltage (Vrect) and the voltage (Vmid). Providing a low resistance resistor presents challenges to circuit design, especially when the resistance (Rs) is reduced and the current is measured across a wide dynamic range (e.g., between the milli-amp range to the 2.5 amp range). There are many challenges to integrating the resistor 102 into an integrated circuit (IC).

[0062] In an embodiment, the current sense circuit 100 is designed to output a voltage (Vo) for sensing a current (Isns). In this regard, the ability to detect a current (Isns) can be advantageous for sensing received or transmitted power. Since it is desirable to detect a current (Isns) across the resistor 102, the resistor 102 can also be referred to as a sense resistor.

[0063] The resistor 104 can be coupled between a node having a voltage (Vrect) and an input of the amplifier 108. Similarly, the resistor 106 can be coupled between a node having a voltage (Vmid) and an input of the amplifier 108. In this regard, the resistor 104 and the resistor 106 can also be referred to herein as upper resistors or input resistors of the amplifier 108. In an embodiment, the resistor 104 and the resistor 106 each include a matching resistance value (Rt). In this regard, the resistor 104 and the resistor 106 can also be referred to herein as a pair of matching resistors. The resistance (Rt) can increase as the resistor 104 and the resistor 106 age.

[0064] The resistor 110 can be coupled between an output of the amplifier 108 and ground. Similarly, the resistor 112 can be coupled between the output of the amplifier 108 and ground. For example, the resistor 110 is depicted as being coupled between a node of the transistor 114 and ground, and the resistor 112 is depicted as being coupled between a node of the transistor 116 and ground. In this regard, the resistor 110 and the resistor 112 can also be referred to herein as lower resistors of the amplifier 108. In an embodiment, the resistor 110 and the resistor 112 each include a matching resistance value (Rb). In this regard, the resistor 110 and the resistor 112 can also be referred to herein as a pair of matching resistors. Through the arrangement of the resistor 110 and the resistor 112, the voltage (Vo) output from the current sense circuit 100 is proportional to the resistance (Rb).

[0065] The amplifier 108 can be configured to output a voltage (Vo). The amplifier 108 can output the voltage (Vo) by amplifying the voltage drop across the resistor 102. Thus, the voltage (Vo) can be based on the current (Isns). The amplifier 108 can also be referred to as an operational amplifier, a differential amplifier, or a high-gain amplifier. The amplifier 108 can sense an input voltage on the upper resistor and drive an output such that the voltage from the left and right sides are equal. Providing equal voltages on the left and right sides can provide a current that is proportional to the current (Isns). The amplifier 108 can include a gain that is based on a resistance (Rb) of the lower resistor divided by a resistance (Rt) of the upper resistor. For example, the resistance (Rt) of the upper resistor can be 1 kilo-ohm (1 kQ resistor), but this is not intended to be limiting. Continuing the example, the resistance (Rb) of the lower resistor can be 17.5 kilo-ohm (17.5 kQ resistor), but this is not intended to be limiting. When the upper resistor is a 1 kQ resistor and the lower resistor is a 17.5 kQ resistor, the gain of the amplifier can be 17.5 times (e.g., a gain of about 24.86 dB), but this is not intended to be limiting. In some examples, the gain of the amplifier 108 can be selected based on the capabilities of a downstream ADC.

[0066] In embodiments, each of the resistors 102, 104, 106, 110, and 112 are included within the integrated circuit 700, such that the resistors can be considered “internal.” Each of the resistors can be formed from one or more polysilicon elements that define a resistance value (Rs), a resistance value (Rt), and a resistance value (Rb). It is further contemplated that the resistors 102, 104, and 106 can include substantially similar temperature coefficients and similar aging coefficients.

[0067] In embodiments, the resistor 102 is an internal resistor. The current sense circuit can internally sense current without the use of external components, such as an external sense resistor. The resistor 102 is part of the integrated circuit provided within the chip and combined with the amplifier 108 to form the current sense circuit 100. The current measured across the resistor 102 can be referred to herein as the sense current (Isns) and can be based on a resistance value of the sense resistor (Rs) and a voltage drop between the rectified voltage (Vrect) and the mid voltage (Vmid).

[0068] The current sense circuit 100 includes a node 118 between the resistor 102 and the resistor 104. The node 118 can be provided for a voltage (Vrect) to loop back through a rectifier, but this is not intended to be limiting. The current sense circuit 100 can also include a node 120 between the resistor 102 and the resistor 104. The node 120 can be provided for a voltage (Vmid) to loop back through a voltage regulator, but this is not intended to be limiting.

[0069] In an embodiment, the resistor 102 and the amplifier 108 are assembled into an integrated circuit. The upper resistors (e.g., resistor 104, resistor 106) and the lower resistors (e.g., resistor 110, resistor 112) can also be part of the integrated circuit. By incorporating the amplifier components and the resistor 102 onto the integrated circuit, the temperature coefficient of the resistor 102 and the upper resistors can be substantially similar. In an embodiment, the integrated circuit includes the upper resistors and the current sense resistor integrated into the layout.

[0070] In an embodiment, one or more of the resistor 102, the resistor 104, the resistor 106, the resistor 110, or the resistor 112 comprise a polysilicon resistor formed below a metallization layer onto an integrated circuit. The polysilicon resistor can also be referred to herein as a poly resistor, an internal poly resistor. In an embodiment, the polysilicon resistor is formed as an array of polysilicon elements. The polysilicon elements can also be referred to herein as poly slices. The polysilicon elements can comprise any polysilicon material known in the art. The polysilicon material can include a resistance that varies with temperature. Using a polysilicon material can facilitate reducing the temperature coefficient as compared to implementing a resistor in a metallization layer of an integrated circuit.

[0071] The polysilicon elements can include a wide range of dimensions. For example, the polysilicon elements used to form the resistor 102, the resistor 104, or the resistor 106 can be relatively wide. For example, the polysilicon elements can be 50 microns wide. The polysilicon elements can further include a length, such as (but not limited to) 4 microns long. Thus, the polysilicon elements can have an aspect ratio of 50 microns x 4 microns. Polysilicon elements having an aspect ratio of 50 microns x 4 microns have been experimentally determined to include a temperature coefficient of 150 PPM / C. By way of another example, the polysilicon elements used to form the resistor 110 or the resistor 112 can be relatively narrow as compared to the polysilicon elements of the upper resistors and the sense resistor. For example, the polysilicon elements of the lower resistors can be 1 micron wide. The polysilicon elements of the lower resistors can change over time due to aging. In an embodiment, the resistance change of the lower resistors is further calibrated by a calibration circuit (not depicted).

[0072] One challenge in implementing the resistor 102 within an integrated circuit is the temperature coefficient of the resistor 102. Integrating an upper layer resistor into the array of the resistor 102 can allow for cancellation of the temperature coefficients of the resistance (Rs) and the resistance (Rt). Cancellation of the temperature coefficients can eliminate inaccuracies associated with the temperature of the upper layer resistor and the current sense resistor. The voltage (Vo) can be proportional to the current (Isns), the resistance (Rs), and the resistance (Rb). The voltage (Vo) can be further inversely proportional to the resistance (Rt).

[0073] The transistors 114 and 116 can act as a gain stage from the amplifier. For example, if the amplifier 108 starts to detect a different voltage on the input, the output from the amplifier can pull up or down the gates of the transistors 114 and 116 to cause the transistors 114 and 116 to act as current sources. It should be understood that the transistors 114 and 116 can generally include any transistor, such as but not limited to a field effect transistor, such as a metal oxide semiconductor field effect transistor (MOSFET or M). As depicted, the transistors 114 and 116 can be N-channel MOS (NMOS), but this is not intended to be limiting.

[0074] The current sense circuit 100 can also include a switching matrix. The switching matrix can include one or more switches 122, such as but not limited to switch (Ml), switch (M2), switch (M3), and switch (M4). The switches (Ml-M4) can be selectively opened and closed to configure the current sense circuit in a receive mode, a transmit mode, and one or more offset calibration modes. The switching matrix can allow for transmit and receive gain inversion. The switching matrix can also allow for measurement of the offset of the input voltage of the amplifier. Advantageously, the current sense circuit 100 includes a current sense accuracy within 0.5% of the actual current across the resistor 102. The switching matrix can provide direct offset measurement and minimally introduce parasitic effects that can affect temperature performance.

[0075] The switches (Ml-M4) can be arranged between the resistor 102, the resistor 104, and the resistor 106. The switch (Ml) is coupled between the node 118 and the resistor 104. The switch (M2) is coupled between the node 120 and the resistor 106. The switch (M3) is coupled between the node 120 and the resistor 104. The switch (M4) is coupled between the node 118 and the resistor 106.

[0076] The switches (M1-M4) allow for measuring current transfer from the node 118 having voltage (Vrect) to the node 120 having voltage (Vmid), measuring current transfer from voltage (Vmid) to voltage (Vrect), and measuring offset of the current sense circuit. The processor can receive one or more digital signals of voltage (Vo) and determine current (Isns) based on voltage (Vo). Voltage (Vo) can also indicate offset contributed by resistor 104, resistor 106, resistor 110, resistor 112, and amplifier 108, depending on which of the switches (M1-M4) are closed.

[0077] When switches (M1) and (M2) are closed and switches (M3) and (M4) are open, the current sense circuit 100 is configured in a receive mode. In the receive mode, the processor can measure current transfer from voltage (Vrect) to voltage (Vmid). In the receive mode, the current sense circuit can measure current received by an integrated circuit of a wireless power system. For example, the receive mode can correspond to communications and / or wireless power received from a transmitter. Thus, the wireless power system can be configured in the receive mode based on configuration of the switches.

[0078] When switches (M3) and (M4) are closed and switches (M1) and (M2) are open, the current sense circuit 100 is configured in a transmit mode. In the transmit mode, the processor can measure current from voltage (Vmid) to voltage (Vrect). In this regard, the switches (M1-M4) provide a way to reverse between transmit (Tx) and receive (Rx). In the transmit mode, the current sense circuit can measure current transmitted from an integrated circuit of a wireless power system. For example, the transmit mode can correspond to communications transmitted from a wireless power system. Thus, the wireless power system can be configured in the transmit mode based on configuration of the switches.

[0079] When switches (M1) and (M4) are closed and switches (M2) and (M3) are open, the current sense circuit 100 is configured in a first offset mode to measure offset of the current sense circuit 100. When switches (M1) and (M4) are on, the input of the current sense circuit 100 can be shorted at node 118. When switches (M1) and (M4) are closed and switches (M2) and (M3) are open, the processor can be configured to measure offset of the current sense circuit 100 (e.g., offset of various resistors and amplifier together) based on one or more digital signals of voltage (Vo).

[0080] Alternatively, when switches (M2) and (M3) are closed and switches (Ml) and (M4) are open, the current sense circuit 100 is configured in a second offset mode to measure an offset of the current sense circuit 100. When switches M2 and M3 are on, the input of the current sense circuit 100 can be shorted at node 120. When switches (M2) and (M3) are closed and switches (Ml) and (M4) are open, the processor can be configured to measure the offset of the current sense circuit 100 based on one or more digital signals of the voltage (Vo).

[0081] Next, the processor can use the offset to calibrate the measured current (Isns). For example, when in the offset mode, any voltage received from the ADC is a zero current reference. The zero current reference can be subtracted from the voltage during the calibration phase. By implementing switches in the upper resistor array, the current sense circuit 100 can have both transmit and receive power modes and also perform a direct offset measurement of the resistor structure. Thus, the processor measures the offset of the current sense circuit 100 based on the voltage (Vo) and then compensates for the offset when determining the current (Isns).

[0082] The switches (Ml-M4) can be controlled by one or more processors executing program instructions. The processor can include firmware that causes the processor to control the switches (Ml-M4). The firmware can cause the processor to control the switches to make an offset measurement of a current offset. The firmware can make the offset measurement to detect what the current offset of the structure is and then use the offset information for calibration purposes.

[0083] It should be understood that the switches (Ml-M4) can generally include any switch, such as a transistor. The transistor can include, but is not limited to, a field effect transistor, such as a metal oxide semiconductor field effect transistor (MOSFET or M). As depicted, the switches (Ml-M4) can be P-channel MOS (PMOS), but this is not intended to be limiting.

[0084] Referring now to Figures 5A to 5B , a current sense circuit 100 is described in accordance with one or more embodiments of the disclosure. In an embodiment, the current sense circuit 100 includes one or more channels. The current sense circuit 100 can include a digital channel and an analog channel. The current sense circuit 100 can include an amplifier 108 for the digital channel that is in parallel with an amplifier 146 for the analog channel. The amplifier 108 and the amplifier 146 can each include an input coupled to a node 118 and a node 120.

[0085] The digital channel can provide one or more digital control loops using the first current (Isns). The digital channel can output a voltage (Vo) from the amplifier 108 to the ADC. The ADC can then provide one or more digital signals of the voltage (Vo) to the processor. The processor can be configured to receive the one or more digital signals of the third voltage (Vo) and further configured to determine the current (Isns) based on the voltage (Vo). The processor can also measure the offset of the current sense circuit contributed by the resistor 104, the resistor 106, the resistor 110, the resistor 112, and the amplifier 108 by switching one or more switches 122. The processor can then compensate for the offset when determining the current (Isns) of the one or more digital control loops. When the processor switches the switches 122, the digital channel can be offline such that the processor cannot determine the current (Isns) when the one or more switches 122 are switched to determine the offset. The loss of the current (Isns) measurement is not desirable, resulting in a period where the current (Isns) cannot be measured. However, it can be desirable to provide the offset measurement to improve the accuracy of the current (Isns) measurement of the digital control loops.

[0086] The analog channel can provide one or more analog control loops using the first current (Isns). The analog channel can output a voltage (Van) from the amplifier 146 to one or more circuits. The circuits can use the current (Isns) in the one or more analog control loops for wireless power control. For example, the analog control loops of an integrated circuit can include, but are not limited to, a load modulation circuit (ILOAD), a main voltage regulator (MVR), and the like. The voltage regulator can regulate the voltage output of the integrated circuit. Regulating the voltage output can be beneficial to allow a battery charging system to charge a battery. The voltage regulator circuit can generally include any circuit for regulating a voltage based on the analog control loops.

[0087] By providing the analog channel and the digital channel, the amplifier 146 can remain on when the node 118 includes the voltage (Vrect) and the node 120 includes the voltage (Vmid), thereby ensuring that the analog channel continuously receives the current (Isns). The amplifier 146 can remain on regardless of the state of the switches 122, such that the switches can be switched to determine the offset and not affect the analog control loops. Thus, the analog channel can operate independently of the digital channel, thereby allowing the digital channel to be calibrated while the analog control loops are in operation. In this regard, the amplifier 108 can also be referred to herein as a switching amplifier and the amplifier 146 can also be referred to herein as a constant-on amplifier.

[0088] The current sense circuit 100 can additionally include any number of elements coupled to the amplifier 146. Although not depicted, the current sense circuit 100 can include one or more resistors (e.g., see resistor 104, resistor 106) coupled between the node 118 or the node 120 and an input of the amplifier 146. The current sense circuit 100 can include one or more elements coupled to an output of the amplifier 146. For example, the current sense circuit 100 can include a transistor 148, a transistor 150, a resistor 152, and a resistor 154. The transistor 148 and the transistor 150 can each be coupled to the output of the amplifier 146. Thus, a voltage (Van) can be based on an input voltage of the amplifier 146 and one or more resistances of the analog channel. For example, the amplifier 146 can be a differential amplifier with a gain based on the resistances of the input and the output.

[0089] The transistor 148 and the transistor 150 can generally include any transistor, such as (but not limited to) a field effect transistor, such as a metal oxide semiconductor field effect transistor (MOSFET or M). As depicted, the transistor 148 and the transistor 150 can be P-channel MOS (PMOS), but this is not intended to be limiting.

[0090] The resistor 152 can be coupled between the transistor 148 and ground. Similarly, the resistor 154 can be coupled between the transistor 150 and ground. The resistor 152 and the resistor 154 can each include a resistance (Rt). For example, the resistor 152 and the resistor 154 can each include a 17 kilo-ohm (17 kQ) resistance, but this is not intended to be limiting. The resistor 152 and the resistor 154 can also be referred to as a pair of matched lower layer resistors.

[0091] The current sense circuit 100 can include one or more elements coupled between an output and an input of the amplifier 146. The one or more elements can include a resistor 156 and a resistor 158. The resistor 156 and the resistor 158 can each include a matching resistance value. For example, the resistor 156 and the resistor 158 can each include a 1 kilo-ohm (1 kQ) resistance, but this is not intended to be limiting. The resistor 156 can be coupled between the transistor 148 and a first input of the amplifier 146. Similarly, the resistor 158 can be coupled between the transistor 150 and a second input of the amplifier 146.

[0092] The current sense circuit 100 can include one or more offset correction features. For example, the amplifier 146 can include a chopper switch 151. The chopper switch 151 can also be referred to as chopper clock feedback or the like. The chopper feedback loop can provide choppering for offset correction of the amplifier 146. The offset correction of the amplifier 146 can improve the accuracy of the analog channel. For example, the chopper feedback loop can include a first chopper switch at the input of the amplifier 146. The first chopper switch can be configured to switch the input of the amplifier. By way of another example, the chopper feedback loop can include a second chopper switch at the output of the amplifier 146. The second chopper switch can be configured to switch the output of the amplifier.

[0093] It should be appreciated that the depiction of the switches 122 is not intended to be limiting. For example, the current sense circuit 100 can include any number of switches for measuring offset, such as (but not limited to) Figure 4 a four-switch configuration of Figure 5A a three-switch configuration of

[0094] Referring now to Figure 6 , the layout of one or more components of the current sense circuit 100 is described in accordance with one or more embodiments of the disclosure. As depicted, dummy resistor 124, resistor 152, resistor 154, resistor 156, and resistor 158 are depicted with different hatching, which is not intended to be limiting. Rather, the resistors are depicted with hatching to illustrate the number of array elements that each resistor includes. The layout of the resistors 152, 154, 156, and 158 is contemplated to be beneficial for any number of current sense circuits that sense current in the milliamp to amp range.

[0095] In an embodiment, the resistors 152, 154, and 156 each include a polysilicon resistor formed onto a substrate. The polysilicon resistor can also be referred to herein as a poly resistor or an internal poly resistor. In an embodiment, the polysilicon resistor is formed as an array of array elements each including a piece of polysilicon. The piece of polysilicon can be disposed on a layer of an integrated circuit. As depicted, the resistors 152 and 154 each include 17 array elements. Similarly, the resistors 156 and 158 are each depicted as including 9 array elements. Further, although not depicted, the array elements of each of the resistors can be coupled in various series or parallel arrangements to achieve a desired resistance value. Each array element can include a number of pieces of polysilicon. The discussion of the pieces of polysilicon in Figures 1A to 2B is hereby incorporated by reference. In this regard, the array elements can be formed from any number of pieces of polysilicon having any aperture, resistivity, and temperature coefficient.

[0096] It can be desirable to ensure that resistors 152 and 154 match resistance values as closely as possible, for example, to ensure a gain of one or more amplifiers of a current sense circuit. In an embodiment, resistors 152 and 154 include array elements of polysilicon pieces arranged symmetrically about axis 160. Similarly, resistors 156 and 158 include array elements of polysilicon pieces arranged symmetrically about axis 160. In this regard, stress differences between polysilicon pieces can be reduced. Reducing stress differences can result in matching resistor pairs experiencing similar stresses. Experiencing similar stresses can result in the resistors experiencing similar resistance changes caused by piezoresistivity. Polysilicon pieces of resistor 152 can be fingered with resistor 154. Similarly, polysilicon pieces of resistor 156 can be fingered with resistor 158. As depicted, polysilicon pieces of resistor 152 are mirrored about axis 160 with resistor 154. Additionally, pieces of resistor 156 are mirrored about axis 160 with resistor 158. This arrangement can also be referred to as a checkerboard pattern, but this is not intended to be limiting.

[0097] Referring now to Figure 7 An exemplary embodiment of an integrated circuit 700 is described in accordance with one or more embodiments of the present disclosure. Integrated circuit 700 can also be referred to herein as a transceiver unit, a mixed signal chip, a wireless power chip, a wireless power receiver (Rx), a receiver (Rx) integrated circuit, or the like. Integrated circuit 700 can be configured to receive and regulate alternating current and output a regulated DC voltage. For example, the alternating current can be received from a coil of a wireless power system and the regulated DC voltage can be provided to a battery for charging the battery, but this is not intended to be limiting. In an embodiment, integrated circuit 700 can include one or more of a rectifier 702, a current sense circuit 704 (such as current sense circuit 100), a processor 706, a power unit 708, a voltage regulator 710, an analog / digital converter 712, and the like. It is further contemplated that integrated circuit 700 can include any number of additional components not depicted herein for the sake of clarity. For example, integrated circuit 700 can further include various un-depicted traces between one or more of rectifier 702, current sense circuit 704, embedded processor 706, power unit 708, voltage regulator 710, and analog / digital converter 712.

[0098] Rectifier 702 can be configured to receive alternating current having a voltage (Vin). For example, the alternating current can be received from a coil of a wireless power system, but this is not intended to be limiting. Rectifier 702 can be further configured to generate direct current having a voltage (Vrect). Voltage (Vrect) can not be regulated to a desired supply power. Rectifier 702 can generally include any circuit suitable for rectifying current. For example, rectifier 702 can include a bridge circuit, such as an H-type bridge circuit.

[0099] When the integrated circuit is configured in a receive mode, the rectifier 702 can convert an AC input voltage to a rectified DC voltage. When the integrated circuit is configured in a transmit mode, the rectifier can also convert a DC input voltage to an AC output voltage. For example, the integrated circuit can be configured in a receive mode for receiving wireless power. By way of another example, the integrated circuit can be configured in a receive mode and / or a transmit mode for wirelessly communicating with a transmitter.

[0100] The current sense circuit 704 incorporates herein by reference the discussion of the current sense circuit 100. The current sense circuit 704 can include a voltage from the node (Vrect) and a voltage from the node (Vmid). Depending on whether the integrated circuit 700 is receiving or transmitting, the voltage (Vrect) can be higher or lower than the voltage (Vmid). The current sense circuit 704 can further output a voltage (Vo) that can be used to determine a current (Isns).

[0101] The processor 706 can generally include any suitable processor. For example, the embedded processor 706 can be a microprocessor, although this is not intended to be a limitation. The processor 706 can further include one or more memory blocks by which the processor 706 can be configured to perform any of the various methods described herein. For example, the processor 706 can include, but is not limited to, read only memory (ROM) for performing boot-up operations, one-time programmable (OTP) memory for boot code, and / or random access memory (e.g., static RAM) for saving program instructions, communications (e.g., FSK communications, ASK communications, etc.), and the like.

[0102] The processor 706 can generally be configured to perform various program functions that can be saved in firmware. For example, the processor 706 can be configured to receive various bits from the analog-to-digital converter 712. The processor 706 can be further configured to determine a current (Isns) across the current sense circuit 704.

[0103] The power unit 708 can be configured to power various components of the integrated circuit, such as, but not limited to, the embedded processor 706 or another component of the integrated circuit 700. The power unit 708 can generally provide any level of power, such as, but not limited to, 1.2 volts, 1.8 volts, 3.3 volts, or 5 volts. The power unit 708 can draw power from any number of sources, such as, but not limited to, a main power rail of a communication device.

[0104] The voltage regulator 710 can be configured to receive the voltage (Vmid) from the current sense circuit 704. The voltage regulator 710 can be further configured to regulate the voltage to a desired output. The regulated voltage can then be provided to a battery or battery charging system for charging a battery. The regulated voltage can generally include any suitable output voltage for wireless charging, such as (but not limited to) 15 volts or 30 volts.

[0105] The analog-to-digital converter 712 can be configured to receive various voltages and / or currents from any one or more of the components of the integrated circuit and generate a digital signal of bits. For example, the analog-to-digital converter 712 can receive the voltage (Vo) from the current sense circuit 704 and generate a digital signal based on the voltage (Vo). The analog-to-digital converter 712 can then provide the digital signal to the processor 706 for processing. It should be understood that the analog-to-digital converter 712 can generally include any analog-to-digital converter (ADC) and can further include a plurality of various other converters for handling various other signals, which are not depicted herein.

[0106] Although the current sense circuit 704 is described as a component of the integrated circuit 700, this is not intended to be a limitation of the present disclosure. It is contemplated that the current sense circuit 100 and / or the current sense circuit 704 can be integrated into any number of integrated circuits. In this regard, reducing pressure variations caused by pressure resistance can be beneficial for providing accurate current measurements over a wide dynamic range in any number of integrated circuits. Applications can include any type of accurate current measurement on-chip, whether it is from wireless power or for any type of power management type of integrated circuit.

[0107] In some examples, the integrated circuit 700 can achieve a 0.5% or better current sense accuracy, which can be an improvement over existing current sense accuracy of 1.0%. Improving the current sense accuracy can be beneficial for allowing higher levels of power transfer while still meeting one or more safety requirements, such as (but not limited to) requirements regarding foreign object detection.

[0108] Reference is now made to Figure 8According to one or more embodiments of the present disclosure, a wireless power system 800 is described. The wireless power system 800 can include one or more components such as, but not limited to, a transmitter unit 802, a transmitter coil 804, a receiver coil 806, an integrated circuit 700, and a battery charger 808. The transmitter unit 802 and the integrated circuit 700 can be inductively coupled through the transmitter coil 804 and the receiver coil 806. In this regard, the integrated circuit 700 can wirelessly receive power from the transmitter unit 802 and provide the power to the battery charger 808 for charging one or more batteries. The integrated circuit 700 and the transmitter unit 802 can wirelessly communicate through any number of communication protocols. For example, the integrated circuit 700 can receive transmissions and receive communications of the transmitter unit 802 to establish a transmission through one or more handshaking protocols. A current sense circuit can be configured to sense a current (Isns) in a transmission mode or a receive mode.

[0109] Providing high accuracy current measurements from a current sense circuit within the integrated circuit 700 is advantageous to help with foreign object detection. The more accurate the current sensing, the more accurate the power transfer that can be performed in the system 800. The level of power transfer of the wireless power system 800 improves over time. As the level of power improves, accurate current detection becomes more and more important. It is also advantageous to sense the current internally without using external resistors within the current sense circuit.

[0110] Referring now to Figure 9 According to one or more embodiments of the present disclosure, a communication device 900 is described. The communication device 900 can generally include one or more components of the wireless power system 800 through which a battery can be wirelessly charged. The peak wireless power transfer level of the communication device 900 can be in a range from 15 to 30 Watts or higher, and can further improve as wireless power transfer protocols and hardware develop. As the peak wireless power transfer level improves, it becomes more and more important to improve the ability to accurately sense current within the wireless power system 800. The communication device 900 can generally include any type of device configured to communicate by transmitting or receiving signals (e.g., digital, analog, etc.) over a medium (e.g., wired, wireless, etc.), such as, but not limited to, a cellular phone, a modem, a network interface, and the like. In some examples, the communication device 900 is configured to communicate over a wireless power system, such as for communicating between a transmitter and a receiver.

[0111] Referring again to Figures 1A to 9For the purposes of this disclosure, the term "processor" or "processing element" can be broadly defined to encompass any device (such as one or more microprocessor devices, one or more application specific integrated circuit (ASIC) devices, one or more field programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)) having one or more processing or logic elements. In this sense, the one or more processors can include any device configured to execute algorithms and / or instructions (such as program instructions stored in a memory). Further, the memory can include any storage media suitable for storing program instructions that can be executed by the associated processor(s). For example, the storage media can include non-transitory memory media. By way of further example, the memory media can include, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical memory devices (such as a disk), solid-state drives, and the like. It is further noted that the memory media can be located remotely with respect to the physical location of the processor(s), in embodiments.

[0112] In the present disclosure, the disclosed methods, operations, and / or functionalities can be implemented as sets of instructions readable by a device or as software. Moreover, it is to be understood that the particular order or hierarchy of steps in the methods, operations, and / or functionalities disclosed is an example of exemplary approaches. Based upon design preferences, it is understood that the particular order or hierarchy of steps in the methods, operations, and / or functionalities can be rearranged while remaining within the scope of the inventive concepts disclosed herein. The accompanying claims can present elements of the various steps in a sample order, and are not necessarily meant to be limited to the specific order or hierarchy presented.

[0113] It is to be understood that embodiments in accordance with the inventive concepts disclosed herein can include one or more of the steps described herein. Further, such steps can be implemented in any desired order and two or more steps can be implemented simultaneously with one another. Two or more steps disclosed herein can be combined into a single step, and in some embodiments, one or more steps can be implemented as two or more sub-steps. Moreover, other steps or sub-steps can be implemented in addition to or in replacement of one or more steps disclosed herein.

[0114] From the above description, it is clear that the inventive concepts disclosed herein are well adapted to attain the ends and advantages mentioned as well as those inherent in the inventive concepts disclosed herein. While the presently preferred embodiments of the inventive concepts disclosed herein have been described for the purposes of this disclosure, it is to be understood that numerous changes can be made which will readily suggest themselves to those skilled in the art and which are accomplished within the broad scope and coverage of the inventive concepts disclosed and claimed herein.

Claims

1. An integrated circuit comprising: a first circuit including a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; wherein the first resistor has a first resistance (Rs); wherein the second resistor and the third resistor each have a second resistance (Rt); wherein the fourth resistor and the fifth resistor each have a third resistance (Rb); wherein the first resistor is configured to carry a first current (Isns) that is based on the first resistance (Rs) and a voltage difference between a first voltage (Vrect) and a second voltage (Vmid); wherein the first amplifier is configured to output a third voltage (Vo) based on the first current (Isns); wherein a gain of the first amplifier is based on the second resistance (Rt) and the third resistance (Rb); wherein the first resistor is formed from a first plurality of polysilicon slices; wherein the second resistor is formed from a second plurality of polysilicon slices; wherein the third resistor is formed from a third plurality of polysilicon slices; wherein the first, second, and third pluralities of polysilicon slices are disposed on a layer of the integrated circuit; wherein the second plurality of polysilicon slices is symmetrically arranged about an axis relative to the third plurality of polysilicon slices to reduce a stress difference between the second and third pluralities of polysilicon slices.

2. The integrated circuit of claim 1, wherein the second and third pluralities of polysilicon slices are arranged a first distance from a die edge to reduce the stress difference between the second and third pluralities of polysilicon slices.

3. The integrated circuit of claim 2, wherein the first resistor includes a first row and a second row of polysilicon slices; wherein the first row is disposed between the die edge and the second plurality of polysilicon slices; wherein the second row is disposed between the die edge and the third plurality of polysilicon slices.

4. The integrated circuit of claim 3, wherein the first resistor includes a third row and a fourth row of polysilicon slices, both of which are arranged the first distance from the die edge; wherein the third row is symmetrically arranged about the axis relative to the fourth row.

5. The integrated circuit of claim 4, wherein the second and third pluralities of polysilicon slices are disposed between the third and fourth rows.

6. The integrated circuit of claim 5, wherein the integrated circuit has a stress gradient; wherein the stress gradient decreases away from the die edge and away from the axis.

7. The integrated circuit of claim 1, further comprising a metallization layer; wherein the first plurality of polysilicon slices are coupled through the metallization layer; wherein the second plurality of polysilicon slices are coupled through the metallization layer; wherein the third plurality of polysilicon slices are coupled through the metallization layer; wherein at least some of the first plurality of polysilicon slices are coupled in parallel such that the first resistance (Rs) is less than the second resistance (Rt).

8. The integrated circuit of claim 7, wherein the first plurality of polysilicon slices are coupled to the metallization layer through a first plurality of vias; wherein the second plurality of polysilicon slices are coupled to the metallization layer through a second plurality of vias.

9. The integrated circuit of claim 8, wherein a via resistance matches between the first resistor and the second resistor.

10. The integrated circuit of claim 9, wherein the via resistance matches by skipping one or more vias of the second resistor.

11. The integrated circuit of claim 1, the first circuit further comprising a first switch (Ml), a second switch (M2), a third switch (M3), and a fourth switch (M4); wherein the first switch (Ml) and the fourth switch (M4) are symmetrically arranged with respect to the axis relative to the second switch (M2) and the third switch (M3).

12. The integrated circuit of claim 11, wherein the first switch (Ml) and the fourth switch (M4) are fingered on the layer to reduce channel resistance.

13. The integrated circuit of claim 12, wherein the first switch (Ml), the second switch (M2), the third switch (M3), and the fourth switch (M4) are provided to measure offset of the first circuit.

14. The integrated circuit of claim 1, wherein the first plurality of polysilicon slices, the second plurality of polysilicon slices, and the third plurality of polysilicon slices each include a first aperture.

15. The integrated circuit of claim 14, wherein the first aperture is 50 microns x 4 microns.

16. The integrated circuit of claim 1, wherein the first resistor is coupled between a first node having the first voltage (Vrect) and a second node having the second voltage (Vmid). wherein the second resistor is coupled between the first node and a first input of the amplifier; wherein the third resistor is coupled between the second node and a second input of the amplifier; wherein the fourth resistor is coupled between a first output of the amplifier and ground; wherein the fifth resistor is coupled between a second output of the amplifier and ground.

17. The integrated circuit of claim 1, wherein the amplifier is a differential amplifier.

18. The integrated circuit of claim 1, further comprising one or more package pins disposed centrally with respect to the axis.

19. A system comprising: a coil configured to receive wireless power; an integrated circuit comprising: a rectifier configured to receive alternating current from the coil and generate a first voltage (Vrect); a first resistor (Rs) coupled between the first voltage (Vrect) and a first node; a second resistor (Rt) coupled between the first node and a second node; a third resistor (Rt) coupled between the second node and a second voltage (Vdd); a fourth resistor (Rs) coupled between the second voltage (Vdd) and a third node; a fifth resistor (Rs) coupled between the third node and a third voltage (Vss); a sixth resistor (Rs) coupled between the third voltage (Vss) and a fourth node; a seventh resistor (Rs) coupled between the fourth node and a fourth voltage (Vdd); an amplifier having a first input, a second input, a first output, and a second output; wherein the first input is coupled to the first node; wherein the second input is coupled to the second node; wherein the first output is coupled to the third node; wherein the second output is coupled to the fourth node; and a third resistor (Rs) coupled between the first voltage (Vrect) and the first input of the amplifier; wherein the fourth resistor (Rs) is coupled between the second voltage (Vdd) and the second input of the amplifier. a current sense circuit including a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; wherein the first resistor has a first resistance (Rs); wherein the second resistor and the third resistor each have a second resistance (Rt); wherein the fourth resistor and the fifth resistor each have a third resistance (Rb); wherein the first resistor is configured to carry a first current (Isns) that is based on the first resistance (Rs) and a voltage difference between a first voltage (Vrect) and a second voltage (Vmid); wherein the first amplifier is configured to output a third voltage (Vo) based on the current (Isns); wherein a gain of the first amplifier is based on the second resistance (Rt) and the third resistance (Rb); wherein the first resistor is formed from a first plurality of polysilicon slices; wherein the second resistor is formed from a second plurality of polysilicon slices; wherein the third resistor is formed from a third plurality of polysilicon slices; wherein the first, second, and third pluralities of polysilicon slices are disposed on a layer of the integrated circuit; wherein the second plurality of polysilicon slices is arranged symmetrically relative to the third plurality of polysilicon slices about an axis to reduce a stress difference between the second and third pluralities of polysilicon slices; a voltage regulator configured to regulate the second voltage (Vmid); and a processor; wherein the processor is configured to receive one or more digital signals of the third voltage (Vo); wherein the processor is configured to determine the current (Isns) based on the third voltage (Vo); and a battery charging system.

20. The system of claim 19, wherein the system is configurable between a receive mode and a transmit mode; wherein when the system is in the receive mode, the first current (Isns) is provided from the rectifier across the first resistor to the voltage regulator; wherein the processor is configured to determine the first current (Isns) when the system is in the receive mode.

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