Edram and method of forming the same

Abstract

The present application relates to eDRAM and a method for forming the same. In the method, a pad oxide layer and a pad nitride layer formed on a substrate surface are removed after forming an active region and a polysilicon filled deep trench, and then a re-deposited oxide layer and a re-deposited nitride layer are formed. The re-deposited nitride layer has better uniformity than the pad nitride layer after a deep trench manufacturing process. When forming an isolation groove and an extension groove on one side of the deep trench and filling an isolation medium, the re-deposited nitride layer can be used to control the height and flatness of the top surface of the isolation medium, ensuring effective isolation between the polysilicon and the word line, which helps to improve the performance and yield of the eDRAM. The eDRAM is formed by the above method, in which the top surface of the isolation medium is flat and the thickness of different regions is relatively uniform, which helps to improve the performance and yield of the eDRAM.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an eDRAM and a method for forming the same. Background Technology

[0002] Deep trench capacitors can be formed before the MOSFET without affecting the MOSFET's characteristics. Therefore, DRAM (Dynamic Random Access Memory) and logic circuits using deep trench capacitors can be integrated on the same wafer, called eDRAM (embedded DRAM). The memory cell of eDRAM typically includes a deep trench capacitor and a conventional two-dimensional MOSFET or FinFET coupled to it.

[0003] Figure 1 The diagram shows a cross-sectional structure of a deep trench (DT) filled with polysilicon (PS) in a substrate 100 using a conventional process. (Refer to...) Figure 1 In existing processes, before forming the deep trench DT in the substrate 100, a pad oxide layer 101 and a pad nitride layer 102 are typically stacked on the surface of the substrate 100. After forming the active region 110 and the deep trench DT in the substrate 100, a dielectric layer 103 and polysilicon PS are filled in the deep trench DT. A barrier layer 103a (such as titanium nitride (TiN)) can also be formed between the dielectric layer 103 and the polysilicon layer PS. Then, the polysilicon PS is etched to make it lower than the top surface of the active regions 110 on both sides, and a photoresist PR is used as a mask to etch the active region 110 and polysilicon PS on one side of the deep trench DT. (Refer to...) Figure 2 After etching, an isolation groove 10 is formed on one side of the deep trench DT. Then, an isolation medium 120 is formed in the isolation groove 10 and on the top surface of the polysilicon PS and CMP planarization is performed. The pad nitride layer 102 is used as the grinding endpoint, and then the pad nitride layer 102 is removed.

[0004] Figure 3A and Figure 3B The diagram shows cross-sectional structures of different regions after word lines WL are formed on substrate 100 using existing processes. (Refer to...) Figure 3A and Figure 3B Multiple word lines WL are formed on substrate 100. These word lines WL form the gates of transistors on active region 110 and pass-word lines (PWL) on isolation dielectric 120. However, during the formation of isolation dielectric 120, due to the poor uniformity and absence of the pad nitride layer 102, after CMP, as... Figure 3A and Figure 3BThe height of the isolation medium 120 varies in different regions of the substrate 100 shown. This not only causes performance differences and instability of memory cells in different regions, but also, in the thinner regions of the isolation medium 120, the polysilicon PS is too close to the through word line (PWL) formed on the isolation medium 120, which can easily lead to serious parasitic capacitance or even short circuit problems, affecting the overall performance and yield of eDRAM. Summary of the Invention

[0005] To improve the uniformity of the isolation medium filled in the isolation groove formed on the side of the deep trench and to ensure effective isolation between the polysilicon in the deep trench and the word lines passing through the isolation medium, the present invention provides a method for forming eDRAM and an eDRAM.

[0006] On one hand, the present invention provides a method for forming eDRAM, the method comprising:

[0007] A pad oxide layer and a pad nitride layer are stacked on the substrate surface;

[0008] At least one active region extending along a first direction and at least one deep trench filled with polysilicon are formed in the substrate. Each deep trench divides an active region into a first active region and a second active region located on both sides of the deep trench. The polysilicon above the deep trench is connected to the first active region and the second active region. The top surface of the polysilicon is lower than the top surface of the active region.

[0009] Remove the pad nitride layer and the pad oxide layer, and stack and redeposit an oxide layer and a nitride layer on the substrate;

[0010] Etching the second active region and the polysilicon connected to the second active region forms an isolation groove on the side of the deep trench opposite to the first active region;

[0011] The redeposited nitride layer and the redeposited oxide layer are contracted in the first direction to form an expansion groove on top of the isolation groove, the expansion groove exposing the top surface of the polysilicon and part of the top surface of the first active region;

[0012] An isolation medium is filled in the isolation recess and the expansion groove, the isolation medium covering the top surface of the exposed first active region and the top surface of the polysilicon; and

[0013] At least one word line extending in a second direction is formed on the substrate, the word line crossing the isolation medium.

[0014] On the other hand, the present invention provides an eDRAM, which is formed using the above-described eDRAM forming method, the eDRAM comprising:

[0015] A substrate, wherein a first active region extending along a first direction is formed in the substrate;

[0016] At least one polysilicon-filled deep trench is located in the substrate, the first active region is located on one side of the deep trench, the polysilicon is connected to the first active region, and the top surface of the polysilicon is lower than the top surface of the first active region.

[0017] An isolation groove formed on the other side of the deep trench and an extension groove located on top of the isolation groove, the isolation groove and the extension groove being filled with an isolation medium, the isolation medium covering a portion of the top surface of the first active region and the top surface of the polysilicon; and

[0018] Word lines formed on the substrate and extending in a second direction, the word lines crossing the isolation medium.

[0019] In the eDRAM formation method provided by this invention, the pad oxide layer and pad nitride layer formed on the substrate surface are removed after forming the active region and the deep trench filled with polysilicon. A re-deposited oxide layer and a re-deposited nitride layer are then formed. The uniformity of the re-deposited nitride layer is better than that of the pad nitride layer after the deep trench fabrication process. When forming isolation grooves and extension grooves on one side of the deep trench and filling them with isolation dielectric, the height and flatness of the top surface of the isolation dielectric can be controlled by the re-deposited nitride layer, ensuring effective isolation between the polysilicon and the word lines, which helps improve the performance and yield of the eDRAM. The eDRAM claimed in this invention is formed using the eDRAM formation method provided by this invention, wherein the top surface of the isolation dielectric is flat and the thickness of different regions is relatively uniform, and the polysilicon and the word lines are effectively isolated, which helps improve the performance and yield of the eDRAM. Attached Figure Description

[0020] Figure 1 This is a schematic cross-sectional view of a deep trench filled with polysilicon formed in a substrate using existing processes.

[0021] Figure 2 This is a cross-sectional schematic diagram showing the formation of an isolation groove on one side of a deep trench using existing technology and the filling of an isolation medium.

[0022] Figure 3A and Figure 3B These are cross-sectional schematic diagrams of different regions after word lines are formed on the substrate using existing processes.

[0023] Figure 4 This is a schematic flowchart of the method for forming eDRAM according to an embodiment of the present invention.

[0024] Figure 5AThis is a planar schematic diagram of the active region and the deep trench filled with polysilicon in a method for forming eDRAM according to an embodiment of the present invention.

[0025] Figure 5B It is along Figure 5A A cross-sectional view of line AA' in the middle.

[0026] Figures 6 to 9 This is a cross-sectional schematic diagram of a method for forming eDRAM according to an embodiment of the present invention.

[0027] Figure 10A This is a cross-sectional schematic diagram of the second mask layer formed according to an embodiment of the present invention.

[0028] Figure 10B This is a planar schematic diagram of the second mask layer in a method for forming eDRAM according to an embodiment of the present invention.

[0029] Figures 11 to 15 This is a cross-sectional schematic diagram of a method for forming eDRAM according to an embodiment of the present invention.

[0030] Figure 16A This is a planar schematic diagram of a method for forming eDRAM according to an embodiment of the present invention, after word lines have been formed on a substrate.

[0031] Figure 16B It is along Figure 16A A cross-sectional view of line AA' in the middle. Detailed Implementation

[0032] The eDRAM and its formation method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the drawings in this specification are all in a very simplified form and use non-precise scales, and are only used to facilitate clarity in illustrating the embodiments of the present invention. Furthermore, spatial relative terms are intended to include different orientations in use or operation besides the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or positioned in other different ways (e.g., rotated), the exemplary term "on" may also include "below" and other orientational relationships.

[0033] This invention relates to a method for forming eDRAM and the eDRAM formed using this method. The eDRAM manufactured using this method employs deep trench capacitors, which can provide large capacitance. More specifically, the eDRAM manufactured by this method may include a two-dimensional MOSFET coupled to the deep trench capacitor. The eDRAM formation method of this invention can improve various problems caused by poor uniformity and deficiencies in the pad nitride layer in the prior art. The following describes the method in conjunction with… Figures 4 to 16B The method for forming eDRAM according to an embodiment of the present invention will be described.

[0034] Figure 5A and Figure 5B Planar and cross-sectional structures of the deep trench DT filled with active region 110 and polysilicon PS in substrate 100 are shown, respectively. (Refer to...) Figure 4 , Figure 5A as well as Figure 5B According to the method for forming eDRAM according to an embodiment of the present invention, step S1 is performed to stack a pad oxide layer 101 and a pad nitride layer 102 on the surface of a substrate 100, and step S2 is performed to form at least one active region 110 extending along a first direction and at least one deep trench DT filled with polysilicon PS in the substrate.

[0035] The substrate 100 is, for example, an SOI substrate, which includes a doped substrate layer 100a, a buried oxide layer 100b on the doped substrate layer 100a, and a device layer 100c on the buried oxide layer 100b. The doped substrate layer 100a is, for example, a p-type heavily doped silicon substrate, the buried oxide layer 100b is, for example, a silicon oxide layer, and the device layer 100c is, for example, a p-type doped silicon layer.

[0036] The active region 110 can be defined by forming an isolation structure (such as shallow trench isolation (STI)) in the substrate 100. The isolation structure can be formed using a disclosed method. In the etching process forming the isolation structure, the pad oxide layer 101 and the pad nitride layer 102 can serve as hard masks. In embodiments where the device layer 100c is made of silicon, the pad oxide layer 101 is, for example, a silicon oxide layer, and the pad nitride layer 102 is, for example, a silicon nitride layer.

[0037] by Figure 5A The direction of line AA' in the diagram is the first direction. Figure 5B It is along Figure 5A A schematic cross-sectional view of line AA'. (Refer to...) Figure 5A and Figure 5B The deep trench DT is fabricated, for example, after the active region 110 is formed. The deep trench DT penetrates the device layer 100c and the buried oxide layer 100b and extends into the doped substrate layer 100a. The deep trench DT can be formed using a disclosed method. In the etching process forming the deep trench DT, the pad oxide layer 101 and the pad nitride layer 102 can serve as hard masks. Each deep trench DT, for example, traverses an active region 110. As an example, each active region 110 is separated by a plurality of deep trench DTs. Each deep trench DT divides an active region 110 into a first active region 110a and a second active region 110b located on either side of the deep trench DT. Figure 5AAs shown, as an example, in a plurality of deep trenches DT formed in substrate 100, two adjacent deep trenches DT separate the same active region 110 and share the second active region 110b.

[0038] The deep trench DT is used to form a deep trench capacitor, and the first active region 110a is used to form a MOSFET coupled to the deep trench capacitor located at the corresponding deep trench DT. After forming the deep trench DT, a dielectric layer 103 can be formed on the inner surface of the deep trench DT and filled with polysilicon PS. The dielectric layer 103 conformally covers the surface of the doped substrate layer 100a exposed by the deep trench DT, and may also cover a portion of the surface of the buried oxide layer 100b exposed by the deep trench DT. Optionally, before filling the polysilicon PS, a barrier layer 103a (e.g., including titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN)) is formed on the surface of the dielectric layer 103. The barrier layer 103a can prevent dopant ions in the polysilicon PS from diffusing into the dielectric layer 103. When filling the deep trench DT with polysilicon PS, polysilicon material is first deposited to fill the deep trench DT and cover the surface of the pad nitride layer 102 outside the deep trench DT. Then, etching is performed so that the top surface of the polysilicon PS is lower than the top surface of the active region 110. Figure 5B As shown, the polycrystalline silicon PS on the upper part of the deep trench DT is connected to the first active region 110a and the second active region 110b located on both sides of the deep trench DT. The polycrystalline silicon PS can be electrically doped by in-situ doping or ion implantation.

[0039] Since the pad nitride layer 102 is formed before the active region 110, the thickness uniformity and integrity of the pad nitride layer 102 are poor after the formation of the deep trench DT filled with polysilicon PS, so it is removed. Figure 6 The diagram shows the cross-sectional structure after removing the pad oxide layer 101 and the pad nitride layer 102. Figure 7 The diagram shows the cross-sectional structure after the formation of the redeposited oxide layer 104 and the redeposited nitride layer 105. (Refer to...) Figure 4 , Figure 6 and Figure 7 According to the method for forming eDRAM according to an embodiment of the present invention, step S3 is performed to remove the pad nitride layer 102 and the pad oxide layer 101, and to deposit again on the substrate 100 to form a stacked redeposited oxide layer 104 and a redeposited nitride layer 105.

[0040] The redeposited oxide layer 104 is, for example, silicon oxide, which can be formed by atomic layer deposition (ALD). The redeposited nitride layer 105 is, for example, silicon nitride, which can be formed by chemical vapor deposition (CVD). Figure 7As shown, a stack of redeposited oxide layer 104 and redeposited nitride layer 105 conformally covers the surface of substrate 100 after forming a deep trench DT filled with polysilicon PS.

[0041] Figure 8 The image shows a cross-sectional structure of the redeposited nitride layer 105 after CMP treatment. Figure 8 As shown, optionally, a CMP process is performed to make the top surface of the redeposited nitride layer 105 smooth.

[0042] Reference Figure 4 Step S4 is executed to etch the second active region 110b and the polysilicon PS connected to the second active region 110b, and to form an isolation groove on the side of the deep trench DT opposite to the first active region 110a (that is, the formed isolation groove and the first active region 110a are located on opposite sides of the deep trench DT).

[0043] Figure 9 The cross-sectional structure after the isolation groove 10 is formed is shown. (Refer to...) Figure 9 In step S4, firstly, a first mask layer is formed on the surface of the redeposited nitride layer 105, such that the first mask layer has a pattern defining the isolation trench. Exemplarily, the first mask layer includes an OPL layer (Organic Planarization Layer) covering the redeposited nitride layer 105, a BARC layer (Bottom Anti-Reflection Coating) covering the OPL layer, and a photoresist layer located on the BARC layer. Then, using the first mask layer as a mask, etching (e.g., dry etching) is performed to etch the second active region 110b on one side of the deep trench DT and the polysilicon PS in the deep trench DT connected to the second active region 110b. In this embodiment, the second active region 110b located between two adjacent deep trenches DT is removed by etching, and a portion of the polysilicon PS in the two adjacent deep trenches DT facing the second active region 110b is also removed, forming an isolation groove 10 between the two adjacent deep trenches DT, wherein the polysilicon PS surface exposed by the isolation groove 10 is L-shaped; then, the first mask layer is removed.

[0044] The isolation groove 10 is used for subsequent filling with an isolation medium to isolate the polysilicon PS in the deep trench DT from the word lines (i.e., passing word lines (PWL)) that will subsequently pass over the deep trench DT. In this embodiment, the isolation groove 10 is formed by forming the first mask layer on the redeposited nitride layer 105 and etching the second active region 110b and the polysilicon PS in the deep trench DT. The isolation groove 10 can be formed to a corresponding depth as needed.

[0045] The isolation groove 10 exposes the buried oxide layer 100b located below the second active region 110b and the side surface of the polysilicon PS above the deep trench DT, which is connected to the first active region 110a. A stack of redeposited oxide layer 104 and redeposited nitride layer 105 covers the surface of the first active region 110a and the top surface of the polysilicon PS above the deep trench DT.

[0046] Reference Figure 4 Step S5 is executed to pull back the redeposited nitride layer 105 and the redeposited oxide layer 104 in the first direction (i.e., the length direction of the active region 110 (i.e., the direction of the AA' line)) to form an expansion groove on the top of the isolation groove 10. The expansion groove exposes the top surface of the polysilicon PS and part of the top surface of the first active region 110a.

[0047] Specifically, a second mask layer can first be formed on the top surface of the redeposited nitride layer 105 to define the pattern of the extended trench. The second mask layer serves as an etching mask and can employ various mask structures; for example, the second mask layer may include photoresist and / or a hard mask. (See reference...) Figure 10A As an example, a first line oxide layer 106 can be formed along the top surface of the redeposited nitride layer 105 and the inner surface of the isolation groove 10 using atomic layer deposition or chemical vapor deposition; then, a photoresist layer is formed on the first line oxide layer 106, the photoresist layer having a pattern for defining the expansion groove to be fabricated; subsequently, etching is performed to transfer the pattern of the photoresist layer to the first line oxide layer 106, and the photoresist layer is removed, using methods such as... Figure 10A The patterned first line oxide layer 106 shown serves as the second mask layer.

[0048] Figure 10B The planar structure of the second mask layer is shown. (Refer to...) Figure 10A and Figure 10B In this embodiment, a patterned first line oxide layer 106 is used as the second mask layer. The opening in the first line oxide layer 106 is located above the isolation groove 10. The opening is widened relative to the isolation groove 10 in the first direction (i.e., the direction of the AA' line) and is substantially the same size as the isolation groove 10 in the direction perpendicular to the first direction.

[0049] After forming the patterned first line oxide layer 106, the first line oxide layer 106 is used as a mask to etch and redeposit the nitride layer 105, such as by wet etching, using a phosphoric acid solution as an example. After etching, the first line oxide layer 106 is removed, and the exposed redeposited oxide layer 104 is also removed.

[0050] Figure 11 The cross-sectional structure after the expansion groove 11 is formed is shown. (Refer to...) Figure 11 After step S5, the expansion groove 11 formed at the top of the isolation groove 10 exposes the top surface of the polysilicon PS connecting the first active region 110a, and also exposes the top surface of the portion of the first active region 110a adjacent to the polysilicon PS. The exposed top surface of the first active region 110a has a height difference from the top surface of the redeposited nitride layer 105, and the exposed top surface of the first active region 110a has a height difference from the top surface of the polysilicon PS, and the top surface of the polysilicon PS has a height difference from the bottom surface of the isolation groove 10, that is, multiple steps are formed on the inner walls of the isolation groove 10 and the expansion groove 11.

[0051] Reference Figure 4 Step S6 is executed, in which an isolation medium is filled in the isolation groove 10 and the expansion groove 11, the isolation medium covering the top surface of the exposed first active region 110a and the top surface of the polysilicon PS.

[0052] As an example, filling the isolation medium in the isolation groove 10 and the expansion groove 11 may include: firstly, as... Figure 12 As shown, a second linear oxide layer 107 can be formed on the polysilicon PS surface exposed in the isolation trench 10 and the expansion trench 11, as well as on the surface of the first active region 110a, using processes such as thermal oxidation; then, as... Figure 13 As shown, high-density plasma chemical vapor deposition (HDP-CVD) or other suitable processes can be used to deposit dielectric material 108 in the isolation groove 10, the expansion groove 11, and on the redeposited nitride layer 105, and CMP planarization can be performed to remove the dielectric material 108 on the redeposited nitride layer 105, so that the top surface of the dielectric material 108 in the isolation groove 10 and the expansion groove 11 is flush with the surface of the redeposited nitride layer 105. To avoid the dielectric material 108 protruding too much above the first active region 110a, optionally, such as Figure 14 As shown, the dielectric material 108 is then etched, lowering its top surface to a predetermined position. The dielectric material 108 and the second line oxide layer 107 constitute an isolation dielectric STI, which fills the isolation recess 10 and the expansion groove 11 and covers a portion of the top surface of the first active region 110a. Figure 15 As shown, the redeposited nitride layer 105 can then be removed. After etching, the top surface of the isolation medium STI is higher than the top surface of the first active region 110a and has a height difference of about 1 nm to 5 nm with the top surface of the first active region 110a, but it is not limited to this, and the specific value of the height difference can be controlled as needed.

[0053] In this embodiment, step S5 causes the redeposited nitride layer 105 and redeposited oxide layer 104 to shrink in the first direction, forming an extension groove 11 on the top of the isolation groove 10, exposing the top surface of the polysilicon PS in the deep trench DT and part of the top surface of the first active region 110a. In step S6, after filling the isolation groove 10 and the extension groove 11 with the isolation medium STI, the isolation medium STI covers the exposed top surface of the first active region 110a and the top surface of the polysilicon PS, which can form effective isolation between the polysilicon PS and the pass-through word line (PWL) subsequently formed above the isolation medium STI.

[0054] Figure 16A and Figure 16B The planar structure and cross-sectional structure after the word line WL is formed on the substrate 100 are shown respectively. (Refer to...) Figure 4 , Figure 16A and Figure 16B Step S7 is performed to form at least one ray along a second direction (e.g., ...) on the substrate 100. Figure 16A The word line WL extends in the direction of the BB' line in the isolation groove 10 and the expansion groove 11, and the word line WL crosses the isolation medium STI filled in the isolation groove 10 and the expansion groove 11.

[0055] The word line WL is used to form the gate of a transistor in eDRAM on the first active region 110a, and the word line WL forms a pass-through word line (PWL) on the isolation medium STI. The word line WL may include at least one conductive material selected from metal, polysilicon, metal silicide, metal nitride, etc. A gate dielectric layer 109 may be formed between the word line WL and the substrate 100, and the gate dielectric layer 109 may include at least one selected from silicon oxide, silicon oxynitride, and high-k material. A function metal layer may also be formed between the gate dielectric layer 109 and the word line WL.

[0056] In the eDRAM formation method described in the above embodiments, the pad oxide layer 101 and the pad nitride layer 102 are removed after the formation of the active region 110 and the deep trench DT filled with polysilicon PS, and a redeposited oxide layer 104 and a redeposited nitride layer 105 are deposited. The uniformity of the redeposited nitride layer 105 is better than that of the pad nitride layer 102 after the deep trench fabrication process. When the isolation groove 10 and the extension groove 11 are formed on one side of the deep trench DT and the isolation medium STI is filled, the redeposited nitride layer 105 can be used to control the top surface of the isolation medium STI to remain flat and to control the thickness of the isolation medium STI covering the surface portion of the first active region 110a. This ensures that effective isolation is formed between the polysilicon PS in the deep trench DT and the pass-through word line (PWL) above the isolation medium STI, which helps to improve the performance of the eDRAM.

[0057] This invention also relates to an eDRAM, which is formed using the eDRAM formation method described in the above embodiments, with reference to... Figure 16A and Figure 16B The eDRAM includes:

[0058] Substrate 100, wherein a first direction (e.g., Figure 16A The first active region 110a extends from the direction of line AA' in the middle;

[0059] A deep trench DT filled with at least one polysilicon PS in the substrate 100, the first active region 110a being located on one side of the deep trench DT, the polysilicon PS being connected to the first active region 110a, and the top surface of the polysilicon PS being lower than the top surface of the first active region 110a.

[0060] An isolation groove 10 is formed on the other side of the deep trench DT, and an expansion groove 11 is located on top of the isolation groove 10. The isolation groove 10 and the expansion groove 11 are filled with an isolation medium STI, which covers part of the top surface of the first active region 110a and the top surface of the polysilicon PS.

[0061] Formed on the substrate 100 and along the second direction (e.g.) Figure 16A A word line WL extending in the direction of the middle BB' line, the word line WL crossing the isolation medium STI. The word line WL forms a through word line PWL above the isolation medium STI.

[0062] The eDRAM is formed using the eDRAM formation method described in the above embodiments, wherein the top surface of the isolation medium STI is flat and the thickness of different regions is relatively uniform, which helps to improve the performance and yield of the eDRAM.

[0063] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Relevant details can be understood by referring to these examples.

[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming eDRAM, characterized in that, include: A pad oxide layer and a pad nitride layer are stacked on the substrate surface; At least one active region extending along a first direction and at least one deep trench filled with polysilicon are formed in the substrate. Each deep trench divides an active region into a first active region and a second active region located on both sides of the deep trench. The polysilicon above the deep trench is connected to the first active region and the second active region. The top surface of the polysilicon is lower than the top surface of the active region. Remove the pad nitride layer and the pad oxide layer, and stack and redeposit an oxide layer and a nitride layer on the substrate; Etching the second active region and the polysilicon connected to the second active region forms an isolation groove on the side of the deep trench opposite to the first active region; The redeposited nitride layer and the redeposited oxide layer are contracted in the first direction to form an expansion groove on top of the isolation groove, the expansion groove exposing the top surface of the polysilicon and part of the top surface of the first active region; An isolation medium is filled in the isolation groove and the expansion groove, the isolation medium covering the top surface of the exposed first active region and the top surface of the polysilicon; as well as At least one word line extending in a second direction is formed on the substrate, the word line crossing the isolation medium.

2. The forming method as described in claim 1, characterized in that, The substrate is an SOI substrate, which includes a doped substrate layer, a buried oxide layer on the doped substrate layer, and a device layer on the buried oxide layer. The bottom surface of the isolation trench exposes the buried oxide layer.

3. The forming method as described in claim 1, characterized in that, Two adjacent deep trenches separate the same active area and share the second active area, and the isolation groove and the expansion groove are formed between the two adjacent deep trenches.

4. The forming method as described in claim 1, characterized in that, After forming the redeposited nitride layer on the substrate, the method further includes: The top surface of the redeposited nitride layer is treated using a CMP process.

5. The forming method as described in claim 1, characterized in that, Etching the second active region and the polysilicon within the deep trench connected to the second active region includes: A first mask layer is formed on the surface of the redeposited nitride layer, the first mask layer having a pattern defining the isolation grooves; Using the first mask layer as a mask, the second active region on one side of the deep trench and the polysilicon within the deep trench connected to the second active region are etched to form the isolation groove, wherein the exposed polysilicon surface of the isolation groove is L-shaped; and Remove the first mask layer.

6. The forming method as described in claim 1, characterized in that, The process of shrinking the redeposited nitride layer and the redeposited oxide layer in the first direction to form an expansion groove on top of the isolation groove includes: A second mask layer is formed on the top surface of the redeposited nitride layer, the second mask layer having a pattern defining the expansion groove; Using the second mask layer as a mask, the re-deposited nitride layer is etched; and Remove the exposed redeposited oxide layer and form the extended groove on top of the isolation groove.

7. The forming method as described in claim 6, characterized in that, Forming a second mask layer on the top surface of the redeposited nitride layer includes: A first line oxide layer is formed along the top surface of the redeposited nitride layer and the inner surface of the isolation groove; A photoresist layer is formed on the first line oxide layer, the photoresist layer having a pattern defining the extended groove; and Etching is performed to transfer the pattern of the photoresist layer to the first line oxide layer, and the patterned first line oxide layer is used as the second mask layer. Specifically, after etching the redeposited nitride layer, the first line oxide layer and the exposed redeposited oxide layer are removed.

8. The forming method as described in claim 1, characterized in that, The insulating medium filling the insulating groove and the expansion groove includes: A second line oxide layer is formed on the polysilicon surface exposed along the isolation groove and the expansion groove, as well as on the surface of the first active region; Deposit dielectric material within the isolation groove, the expansion groove, and on the redeposited nitride layer; CMP is performed to remove the dielectric material on the redeposited nitride layer, so that the top surfaces of the isolation groove and the expansion groove are flush with the surface of the redeposited nitride layer; The dielectric material is etched so that the top surface of the dielectric material is lowered to a set position on the first active region, and the second line oxide layer and the dielectric material form the isolation dielectric.

9. The forming method as described in claim 1, characterized in that, After the isolation medium is filled into the isolation groove and before the word line is formed, the redeposited nitride layer is removed.

10. An eDRAM, characterized in that, The eDRAM is formed using the formation method according to any one of claims 1 to 9, and comprises: A substrate, wherein a first active region extending along a first direction is formed in the substrate; At least one polysilicon-filled deep trench is located in the substrate, the first active region is located on one side of the deep trench, the polysilicon is connected to the first active region, and the top surface of the polysilicon is lower than the top surface of the first active region. An isolation groove formed on the other side of the deep trench and an extension groove located on top of the isolation groove, the isolation groove and the extension groove being filled with an isolation medium, the isolation medium covering a portion of the top surface of the first active region and the top surface of the polysilicon; and Word lines formed on the substrate and extending in a second direction, the word lines crossing the isolation medium.

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