Balancing switch circuit for a balancing system and balancing system

Abstract

The application discloses a balancing switch circuit and a balancing system for the balancing system, the balancing switch circuit comprises a first transistor and a second transistor arranged reversely, a first resistor and a capacitor for controlling the conduction of the first transistor and the second transistor, and a protection unit, the protection unit is used for monitoring the second end voltage of the capacitor when the balancing switch circuit is disabled, and the gate of the first transistor and the second transistor is pulled to the ground when the voltage of the second end of the capacitor is less than a set threshold value, the false conduction of the balancing switch can be avoided when any external interference causes the body diode of the first transistor or the second transistor to be conducted, the plurality of power supplies in the balancing system can be protected from being damaged due to short circuit, and the safety and stability of the balancing system are improved.

Description

Technical Field

[0001] This invention relates to the field of power balancing technology, and more specifically, to a balancing switch circuit and a balancing system for use in a balancing system. Background Technology

[0002] Battery packs are widely used in applications such as laptops, electric vehicles, and uninterruptible power supplies (UPS). A battery pack consists of multiple individual cells connected in series; however, due to manufacturing processes and usage conditions, the voltage of each cell can vary. This imbalance can occur during charging and discharging, leading to overcharging or over-discharging of individual cells, thus affecting the performance and safety of the battery pack. To address this inconsistency and extend battery life, an equalization circuit needs to be incorporated into the battery pack.

[0003] Existing equalization circuits mainly include passive equalization circuits and active equalization circuits. Passive equalization circuits use energy-consuming components such as resistors to dissipate the excess energy in the high-voltage battery as heat, achieving voltage equalization within the battery pack. While passive equalization circuits have advantages such as low cost and small size, they also have limitations such as significant energy waste and difficulty in heat dissipation. Active equalization circuits mainly utilize non-energy-consuming components such as capacitors, inductors, and transformers as intermediate energy transfer elements to transfer energy from the high-voltage battery to the low-voltage battery, achieving voltage equalization between batteries. They have advantages such as high efficiency and strong equalization capability.

[0004] In the application of the equalization circuit, the voltage of each individual cell in the battery pack needs to be collected via a data acquisition switch to monitor the status of each cell. However, existing equalization circuits typically use two back-to-back MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistors to implement this data acquisition switch. In actual use, when the voltage of a particular cell experiences a significant drop, it can easily cause the switch connected to that cell to malfunction and turn on other switches, leading to a short circuit and affecting the performance of the battery pack. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide an equalization switch circuit and equalization system for an equalization system, which can prevent the equalization switch from being mis-activated when any external interference causes the body diode of the first transistor or the second transistor to conduct, and can protect multiple power supplies in the equalization system from being damaged by short circuits, thereby improving the safety and stability of the equalization system.

[0006] According to one aspect of the present invention, an equalization switching circuit for an equalization system is provided, the equalization system being used to equalize the voltages across multiple power supplies, wherein the equalization switching circuit includes: a first transistor, a first terminal of the first transistor serving as a first connection terminal of the equalization switching circuit; a second transistor, a first terminal of the second transistor serving as a second connection terminal of the equalization switching circuit, the second terminals of both the first transistor and the second transistor being electrically connected to a first node, and the control terminals of both the first transistor and the second transistor being electrically connected to a second node; a first resistor, the first resistor being electrically connected between the first node and the second node; a capacitor, the first terminal of the capacitor being electrically connected to the second node, and the second terminal of the capacitor being electrically connected to a third node; and a protection unit, the protection unit being configured to monitor the voltage at the third node, and, when the equalization switching circuit is in an off state, if the voltage at the third node is detected to be less than a set threshold, to pull the voltage at the second node down to a reference ground, thereby preventing the first transistor and the second transistor from being mis-energized.

[0007] Optionally, the second terminal of the capacitor is further configured to receive a conduction signal for charging the capacitor in order to control the conduction of the first transistor and the second transistor, wherein the conduction signal is a pulse signal, and the first transistor and the second transistor are turned on during the effective pulse of the conduction signal.

[0008] Optionally, it further includes: a conduction control module for generating the conduction signal; and a driver electrically connected between the output of the conduction control module and the second terminal of the capacitor.

[0009] Optionally, the protection unit includes: a comparator for comparing the voltage at the third node with a reference voltage, the reference voltage being used to characterize the set threshold, the comparator being used to generate a valid protection signal when the voltage at the third node is less than the reference voltage; a third transistor, a first terminal of the third transistor being electrically connected to the second node, and a second terminal of the third transistor being electrically connected to the reference ground; and a protection control module, the protection control module being electrically connected to the control terminal of the third transistor, for turning on the third transistor according to the valid protection signal, wherein the protection control module is further used to receive the turn-on signal and enable or disable it according to the turn-on signal.

[0010] Optionally, when the first transistor and the second transistor are turned off, the voltage value of the reference voltage is set such that the turn-on time of the third transistor is earlier than the time when the voltage between the first node and the second node is equal to the turn-on threshold of the first transistor and the second transistor.

[0011] Optionally, it further includes a pre-charge unit for pre-charging the control terminals of the first transistor and the second transistor according to the bias voltage.

[0012] Optionally, the pre-charge unit includes: a fourth transistor, the first terminal of which is connected to the bias voltage, and the second terminal of which is connected to the control terminals of the first transistor and the second transistor; and a second resistor, the first terminal of which is connected to the bias voltage, and the second terminal of which is connected to the control terminal of the fourth transistor and the first terminal of the capacitor.

[0013] Optionally, the bias voltage is set to be equal to the sum of the voltage at the first connection and a set voltage, wherein the set voltage is equal to the voltage across the power supply.

[0014] Optionally, it further includes a transient voltage suppressor diode connected between the first node and the second node.

[0015] According to another aspect of the present invention, a balancing system is provided for balancing the voltages across multiple power sources, comprising: an energy storage element configured to store or release energy; a first power node; a second power node; a balancing switch array including multiple balancing switch circuits, wherein a first connection terminal of each balancing switch circuit is electrically connected to the positive or negative terminal of a corresponding power source, and a second connection terminal of each balancing switch circuit is electrically connected to the first power node or the second power node; a commutation switch array connected between the first power node and the second power node and the energy storage element, configured to switch such that a selected power source is electrically connected to the energy storage element according to a preset polarity; a voltage sampling circuit configured to acquire voltage values ​​of the multiple power sources by acquiring voltage values ​​on the energy storage element; and a controller for controlling the switching of the balancing switch array and the commutation switch array according to the voltage values ​​of the multiple power sources to balance the voltage values ​​of the multiple power sources.

[0016] Optionally, the controller is configured to: obtain a strong power source with the maximum voltage value and a weak power source with the minimum voltage value from the voltage values ​​of the plurality of power sources; electrically connect the strong power source to the energy storage element such that the strong power source charges the energy storage element; and enable control of the energy storage element to charge the weak power source, wherein the energy storage element includes at least one flying capacitor.

[0017] In summary, the equalization switch circuit for an equalization system provided in this embodiment of the invention includes a first transistor and a second transistor configured in reverse order, and a first resistor and a capacitor for controlling the conduction of the first transistor and the second transistor. The first resistor is electrically connected between the source and gate of the first transistor and the second transistor, and the first end of the capacitor is connected to the gate of the first transistor and the second transistor. A narrow pulse conduction signal is applied to the second end of the capacitor to charge it, thereby controlling the conduction of the equalization switch. This equalization switch circuit uses a narrow pulse combined with capacitor driving to control the conduction of the first transistor and the second transistor, allowing the equalization switch to be turned on for only half a resonant cycle each time, reducing the power consumption of the circuit. Attached Figure Description

[0018] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0019] Figure 1 This is a schematic diagram of the structure of a series battery pack balancing system provided by existing technology in a specific application.

[0020] Figure 2 This is a schematic diagram of the working principle of a series battery pack balancing system provided by existing technology.

[0021] Figure 3 This is a schematic diagram of the structure of an equalization switching circuit for an equalization system according to the first embodiment of the present invention.

[0022] Figure 4 This is a schematic diagram of an equalization switching circuit for an equalization system according to a second embodiment of the present invention.

[0023] Figure 5 This is a schematic diagram of the structure of the equalization system according to the third embodiment of the present invention. Detailed Implementation

[0024] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0025] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0026] This invention can be presented in various forms, some of which will be described below.

[0027] Figure 1 This is a schematic diagram of the structure of a series battery pack balancing system provided by existing technology in a specific application. For example... Figure 1 As shown, the prior art series battery pack balancing system 100 includes a balancing switch array 102, a controller 103, a voltage sampling module 104, and an energy storage module 105. The voltage sampling module 104 collects the voltage value of each individual battery cell in the battery pack 101 and provides the collected voltage value to the controller 103. The controller 103 compares the voltage values ​​of each individual battery cell and, based on the comparison results, controls the balancing switch array 102 to connect the individual battery cell with the highest voltage value to the energy storage module 105. When the energy level of the individual battery cell with the highest voltage value is balanced with that of the energy storage module 105, the balancing switch array 102 disconnects the electrical connection between the individual battery cell with the highest voltage value and the energy storage module 105. Simultaneously, the equalization switch array 102 is controlled to connect the individual battery with the lowest voltage value to the energy storage module 105. When the charge in the individual battery with the lowest voltage value and the energy storage module 105 reaches equilibrium, the isolation switch array 102 is controlled to disconnect the electrical connection between the individual battery with the lowest voltage value and the energy storage module 105, and the voltage values ​​of each individual battery collected by the voltage sampling module 104 are compared again until the charge in all individual batteries in the series battery pack 101 reaches equilibrium.

[0028] Figure 2 This is a schematic diagram illustrating the working principle of a series battery pack balancing system based on existing technology. Figure 2As shown, the series battery pack 101 is composed of individual cells BT1, BT2, BT3, ..., BTn-1, BTn connected in series. The resulting output differential voltage points are BIT0, BIT1, BIT2, BIT3, ..., BITn-1, BIT1n, respectively. The voltage across voltage node BIT0 and voltage node BIT1 is the voltage of individual cell BT1; the voltage across voltage node BIT1 and voltage node BIT2 is the voltage of individual cell BT2; and the voltage across voltage node BITn-1 and voltage node BITn is the voltage of individual cell BTn. The connection nodes between the series battery pack 101 and the equalization switch array 102 are these voltage nodes BIT0, BIT1, BIT2, BIT3, ..., BITn-1, BIT1n. Furthermore, the energy storage module 105 is a capacitor Cfly, and the equalization switch array 102 includes multiple equalization switches S1, S2, S3...Sn-1, Sn. The first voltage terminals of the equalization switches S1, S2, S3...Sn-1, Sn are electrically connected to the voltage nodes BIT0, BIT1, BIT2, BIT3...BITn-1, BIT1n in the series battery pack 101, respectively. The second voltage terminals of the equalization switches S1, S2, S3...Sn-1, Sn are electrically connected to the capacitor Cfly. The second voltage terminals of the equalization switches S1, S3, S5...Sn-1 are electrically connected to the second terminal of the capacitor Cfly, and the second voltage terminals of the equalization switches S2, S4, S6...Sn are electrically connected to the first terminal of the capacitor Cfly. As mentioned earlier, existing equalization switches are usually implemented using two back-to-back MOSFETs. In actual use, when the voltage of a battery drops significantly, it can easily cause the switch connected to that battery to turn on falsely, which in turn causes other switches to turn on falsely, leading to short circuits and affecting the performance of the battery pack.

[0029] Figure 3 This is a schematic diagram of a balancing switching circuit for a balancing system according to a first embodiment of the present invention. The balancing system is used to balance the voltages across multiple power sources. It should be noted that the term "power source" as used herein can refer to virtually any type of component or circuit location capable of generating voltage across its terminals. In one exemplary embodiment, a battery cell can be used as a power source; for example, the battery cell includes a rechargeable battery, such as a lithium-ion battery, a nickel-cadmium battery, a nickel-metal cyanide battery, a lead-acid battery, a nickel-zinc battery, or other rechargeable batteries. In another exemplary embodiment, circuits including single or multiple capacitor circuits, diode circuits, transistor circuits, etc., can also be used as a power source. Of course, the power source can also include circuit combinations such as resistor / capacitor networks or semiconductor networks capable of generating voltage and balancing according to the systems and methods described herein.

[0030] like Figure 3 As shown, the equalization switching circuit 200 of this embodiment includes a first transistor 201, a second transistor 202, a resistor Rpd, and a capacitor Cdrv.

[0031] It should be noted that the aforementioned transistors can be Insulated Gate Bipolar Transistors (IGBTs) or Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). For ease of explanation, the following description uses a MOSFET as an example. In some embodiments of this application, the MOSFET can be an N-type MOSFET. In this case, the first terminal of the transistor is called the drain, the second terminal is called the source, and the control terminal is called the gate. Alternatively, in other embodiments of this application, the MOSFET can be a P-type MOSFET. In this case, the first terminal of the switching transistor is called the source, the second terminal is called the drain, and the control terminal is called the gate. For ease of explanation, the following description uses an N-type MOSFET as an example.

[0032] exist Figure 3 In this circuit, the first transistor 201 and the second transistor 202 can be connected in series as an equalization switch. The first terminal (e.g., drain) of the first transistor 201 serves as the first connection terminal VBN of the equalization switch circuit 200, which is used to electrically connect to the positive or negative terminal of the corresponding power supply. Furthermore, since the first transistor 201 and the second transistor 202 are reverse-biased, the second terminal (e.g., source) of the first transistor 201 is electrically connected to the second terminal (e.g., source) of the second transistor 202. The first terminal (e.g., drain) of the second transistor 202 serves as the second connection terminal VBP of the equalization switch circuit 200, which is used to electrically connect to either the first or second terminal of the flying capacitor Cfly.

[0033] For example, both the first transistor 201 and the second transistor 202 are driven by capacitors. When not driven, the first transistor 201 and the second transistor naturally enter the switching off state, which facilitates protection design and enables negative voltage stress design. Figure 3As shown, the first terminal of resistor Rpd is electrically connected to the second terminals of the first transistor 201 and the second transistor 202 at node A, and the second terminal of resistor Rpd is electrically connected to the control terminal (e.g., gate) of the first transistor 201 and the second transistor 202 at node B. The first terminal of capacitor Cdrv is electrically connected to the second terminal of resistor Rpd and node B, and the second terminal of capacitor Cdrv (i.e., node C) is used to receive a conduction signal ENA.

[0034] In this embodiment, a conduction signal ENA is applied to the second terminal of capacitor Cdrv, which charges capacitor Cdrv, causing the voltage across capacitor Cdrv to rise. This forms a voltage across resistor Rpd (i.e., between node A and node B), controlling the conduction of the first transistor 201 and the second transistor 202. Further, the conduction signal ENA is a pulse signal. This driving pulse signal is coupled through capacitor Cdrv to turn on the first transistor 201 and the second transistor 202. The first transistor 201 and the second transistor 202 are briefly turned on during the effective pulse of the conduction signal ENA. Furthermore, the holding time of the conduction state of the first transistor 201 and the second transistor 202 is determined by the settling time of the Rpd-Cdrv network together with the switching threshold.

[0035] Furthermore, the equalization switching circuit 200 also includes a turn-on control module 206 and a driver 207. The output terminal of the turn-on control module 206 is electrically connected to the input terminal of the driver 207, and the output terminal of the driver 207 is electrically connected to the second terminal of the capacitor Cdrv. When it is necessary to turn on the first transistor 201 and the second transistor 202, the turn-on control module 206 generates the turn-on signal ENA, and then the driver 207 charges the capacitor Cdrv according to the turn-on signal ENA, so that the first transistor 201 and the second transistor 202 are briefly turned on. The effective pulse duration and duty cycle of the turn-on signal ENA cause a change in the DC potential of the gate, but this is limited to not affecting the turn-on of the first transistor 201 and the second transistor 202.

[0036] As mentioned above, the acquisition switches or equalization switches used in the prior art are prone to false switching when there are large fluctuations in the battery voltage or the voltage on the flying capacitor bus due to limitations in their circuit structure, which can lead to short circuits. In view of this, the equalization switch circuit 200 of this application further includes a protection unit 210.

[0037] Under normal conditions, the voltage fluctuation on the battery is minimal. The voltage on the flying capacitor bus is clamped to the current or previously sampled voltage, which may be higher or lower than the battery voltage. The connection between the battery and the flying capacitor bus is disconnected by the first transistor 201 and the second transistor 202, which are reverse-biased. The DC voltage on capacitor Cdrv follows the lower of the voltages at the first connection terminal VBN and the second connection terminal VBP. Voltage fluctuations on the battery or flying capacitor bus are transmitted to the protection unit 210 through capacitor Cdrv. If the voltage fluctuation exceeds a preset range, the protection unit 210 triggers the discharge of capacitor Cdrv, forcing the first transistor 201 and the second transistor 202 to turn off. That is, the protection unit 210 is used to compare the voltage at node C with a set threshold when the first transistor 201 and the second transistor 202 are turned off, and when the voltage at node C is less than the set threshold, the protection unit 210 is used to discharge the capacitor Cdrv to pull the voltage at the gate voltage (i.e., node B) of the first transistor 201 and the second transistor 202 down to the reference ground, ensuring that the first transistor 201 and the second transistor 202 are in the off state, thereby avoiding the first transistor 201 and the second transistor 202 from being mistakenly turned on.

[0038] Furthermore, the protection unit 210 includes a third transistor 203, a protection control module 204, and a comparator 205. The comparator 205 has a positive input terminal and a negative input terminal. The positive input terminal of the comparator 205 is used to receive a reference voltage Vth characterizing the set threshold. The negative input terminal of the comparator 205 is electrically connected to node C. The output terminal of the comparator 205 is electrically connected to one input terminal of the protection control module 204. The comparator 205 is used to compare the voltage at node C with the reference voltage Vth to generate a protection signal. The other input terminal of the protection control module 204 is electrically connected to the output terminal of the conduction control module 206. The output terminal of the protection control module 204 is electrically connected to the control terminal (e.g., gate) of the third transistor 203. The first terminal (e.g., drain) of the third transistor 203 is electrically connected to node B, and the second terminal (e.g., source) of the third transistor 203 is electrically connected to reference ground.

[0039] In one exemplary embodiment, when the equalization switch circuit 200 of this embodiment is in the off state, the conduction signal ENA is in the invalid state, the driver 207 is in the high impedance state, and the gates of the first transistor 201 and the second transistor 202 are pulled to the same potential as their sources by the resistor Rpd, that is, the potentials of node A and node B are equal. Simultaneously, the protection control module 204 is enabled by the invalid state conduction signal ENA, and monitors the voltage at the second terminal of capacitor Cdrv through comparator 205. When the voltage of the first connection terminal VBN or the second connection terminal VBP of the equalization switch circuit 200 suddenly drops (for example, a short circuit occurs in the power supply connected to it), it will cause the voltage at node A to drop. Then, through the action of Rpd and capacitor Cdrv, the voltage at node C drops by a corresponding amount. When the voltage at node C reaches a certain drop, for example, when the voltage at node C is less than the reference voltage Vth, comparator 205 provides an effective protection signal (e.g., high level) to the protection control module 204. The protection control module 204 turns on the third transistor 203 according to the effective protection signal to provide a discharge path from node B (or the gate of the first transistor 201 and the second transistor 202) to the reference ground, thereby preventing the first transistors 201 and 202 from being mis-turned on.

[0040] It should be noted that in the protection unit of this embodiment, when a voltage drop occurs while the first transistor 201 and the second transistor 202 are in the off state, the turn-on time of the third transistor 203 should be earlier than the time when the voltage at nodes A and B reaches the turn-on threshold of the first transistor 201 and the second transistor 202. In an exemplary embodiment, the above objective can be achieved by setting the voltage value of the reference voltage Vth.

[0041] Furthermore, the resistor Rpd of the equalization switch circuit 200 in this embodiment has a negative voltage protection function. When a negative voltage occurs at the first connection terminal VBN (i.e., the battery terminal), the current is limited by the resistor Rpd to provide clamping protection.

[0042] Figure 4This is a schematic diagram of the result of an equalization switching circuit for an equalization system according to a second embodiment of the present invention. The difference between the equalization switching circuit 300 of the second embodiment and the equalization switching circuit 200 of the first embodiment is that the equalization switching circuit 300 further includes a pre-charging unit 320. The input of the pre-charging unit 320 is used to receive a bias voltage Vb, and the output of the pre-charging unit 320 is electrically connected to the gates of the first transistor 301 and the second transistor 302. The pre-charging unit 320 is used to pre-charge the gates of the first transistor 301 and the second transistor 302 according to the bias voltage Vb, thereby pulling the gate potentials of the first transistor 301 and the second transistor 302 to a suitable operating point. When it is necessary to turn on the first transistor 301 and the second transistor 302, the driver 307 only needs to provide a small swing to fully turn on the first transistor 301 and the second transistor 302.

[0043] Furthermore, the pre-charge unit 320 includes a fourth transistor 321 and a resistor Rpu. The fourth transistor 321 is, for example, a P-type MOSFET R. The first terminal (e.g., the source) of the fourth transistor 321 is electrically connected to the bias voltage Vb and the first terminal of the resistor Rpu. The control terminal (e.g., the gate) of the fourth transistor 321 is electrically connected to the second terminal of the resistor Rpu and the first terminal of the capacitor Cdrv. The second terminal (e.g., the drain) of the fourth transistor 321 is electrically connected to the gates of the first transistor 301 and the second transistor 302.

[0044] Furthermore, in order to fully activate the first transistor 301 and the second transistor 302, the bias voltage Vb needs to be higher than the voltage at the first connection terminal VBN of the equalization switching circuit 300. Even further, the bias voltage Vb is at least equal to the sum of the voltage at the first connection terminal VBN and a set voltage, for example, equal to the voltage that can be supplied across a power source.

[0045] The bias voltage Vb can be generated in various ways. In one exemplary embodiment, the equalization system generally includes multiple equalization switch circuits 300, which are electrically connected to multiple power supplies. These power supplies are typically connected in series, meaning they are arranged sequentially, with the negative terminal of the preceding power supply connected to the positive terminal of the following power supply in any two adjacent power supplies. Typically, the negative terminal of the first power supply is connected to a reference ground, and the positive terminal of the last power supply provides the total DC voltage potential of the series power supply group (or series battery pack). Therefore, because the preceding power supply can provide a voltage one unit higher than the following power supply, the bias voltage Vb of the equalization switch circuit corresponding to the following power supply can be provided by the preceding power supply. Taking the number of power supplies as m, where m is an integer greater than 1, assuming... Figure 4 In this embodiment, the first connection terminal VBN of the equalization switch circuit 300 is electrically connected to the positive terminal of the i-th power supply (where 1 < i < m, and i is an integer), and the bias terminal 322 of the equalization switch circuit 300 is electrically connected to the positive terminal of the (i+1)-th power supply, thereby providing a bias voltage Vb that is one unit voltage higher than the first connection terminal VBN. In another embodiment, when i = m, the bias terminal 322 of the equalization switch circuit 300 can be connected to a charge pump to generate the bias voltage Vb.

[0046] Furthermore, the equalization switching circuit 300 in the second embodiment also includes a transient voltage suppressor (TVS) diode DT. The diode DT is connected between nodes A and B. When the TVS diode DT is subjected to a momentary high-energy impact, it can reduce its impedance suddenly at an extremely high speed (up to 1*10^-12 seconds) and absorb a large current, clamping the voltage between its two ends to a predetermined value, thereby ensuring that the subsequent circuit components are protected from damage by transient high-energy impacts.

[0047] Figure 5 This is a schematic diagram of the structure of an equalization system according to a third embodiment of the present invention. Figure 5 As shown, the equalization system 400 of this embodiment includes or is connected to a plurality of power sources 401. As previously described, each power source 401 can represent any suitable power source, such as a battery cell. Figure 5In one specific embodiment shown, each power source 401 is a single battery cell with a rated voltage. However, each power source 401 may also represent multiple battery cells, battery modules, multiple battery modules, or a collection of other battery cells. Furthermore, each power source 401 may use any other type of power source, such as a supercapacitor, fuel cell, or solar cell. It should also be noted that this embodiment does not limit the number of power sources connected in series; any number of power sources can be used here. For ease of explanation, power source 401 is... Figure 5 The order is represented as power supply 401a-power supply 401g.

[0048] As those skilled in the art will know, each power source 401 includes a positive terminal (“+”) and a negative terminal (“-”). Multiple power sources 401 are electrically connected together in series. Multiple power sources 401 are connected in series means that the power sources 401 are arranged sequentially, with the negative terminal of the preceding power source 401 electrically connected to the positive terminal of the following power source 401. That is, the positive terminal of power source 401a is electrically connected to the negative terminal of power source 401b, the positive terminal of power source 401b is electrically connected to the negative terminal of power source 401c, and so on. Typically, the negative terminal 415 of the first power source 401a is used for electrical connection to a reference ground, and the positive terminal 413 of the last power source 401g is used to provide the total DC voltage potential of the series power source group (or series battery pack).

[0049] The equalization system 400 includes an equalization switch array 410, a reversing switch array 420, a voltage acquisition switch array 430, a voltage sampling circuit 440, a controller 450, and an energy storage element 460.

[0050] The equalizer array 410 includes multiple equalizers 402. Each equalizer 402 includes a first connection terminal and a second connection terminal. When the equalizer 402 is activated, electrons can flow between the two terminals. Conversely, when the equalizer 402 is disabled, it generally prevents electrons from flowing between the two terminals.

[0051] Furthermore, the plurality of equalizing switches 402 in the equalizing switch array 410 can be implemented by the equalizing switch circuit 200 or 300 in the above embodiments. In the equalizing switch circuit 200, the first terminal (e.g., drain) of the first transistor 201 can serve as the first connection terminal VBN of the equalizing switch 402, the second terminal (e.g., source) of the first transistor 201 is connected to the second terminal (e.g., source) of the second transistor 202, and the first terminal (e.g., drain) of the second transistor 202 serves as the second connection terminal VBP of the equalizing switch 402.

[0052] Furthermore, the equalization switch circuit 200 in this embodiment also includes a protection unit 210. When the equalization switch 402 is disabled, the protection unit 210 compares the voltage at node C with a set threshold. When the voltage at node C is less than the set threshold, the protection unit 210 discharges the capacitor Cdrv to pull down the voltage at the gate voltage (i.e., node B) of the first transistor 201 and the second transistor 202 to the reference ground, ensuring that the first transistor 201 and the second transistor 202 are in the off state, thereby preventing the equalization switch 402 from being mis-turned on.

[0053] Furthermore, the number of equalizing switches 402 is greater than the number of power supplies 401 in the series power supply group. For example, the number of equalizing switches 402 is greater than the number of power supplies 401 by one. For instance, in the described embodiment, since there are 7 power supplies 401 connected in series, 8 equalizing switches 402 are used. For clarity, the 8 equalizing switches 402 are sequentially labeled 402a-402h. The first connection terminal of each equalizing switch 402 can be electrically connected to either the positive or negative terminal of the corresponding power supply 401. For example, the first connection terminal of equalizing switch 402a is electrically connected to the negative terminal of power supply 401a, the first connection terminal of equalizing switch 402b is electrically connected to the positive terminal of power supply 401a, and so on. Since the multiple power supplies 401 are connected in series, the first connection terminal of equalizing switch 402b is electrically connected to both the positive and negative terminals of power supply 401a and power supply 401b. The same reasoning applies to the other equalizing switches 402.

[0054] Refer again Figure 5 The equalization system 400 also includes a first power node 411 and a second power node 412 (the first power node 411 and the second power node 412 can also be referred to as flying capacitor bus nodes). The first power node 411 is formed by electrically connecting the second connection terminals of every other equalization switch 402, i.e., alternating equalization switches 402. The second power node 412 is formed by electrically connecting the second connection terminals of each equalization switch 402 that is not connected to the first power node 411. In a preferred embodiment, as... Figure 5 As shown, the first power node 411 is electrically connected to the second connection terminals of equalization switches 402b, 402d, 402f and 402h, and the second power node 412 is electrically connected to the second connection terminals of equalization switches 402a, 402c, 402e and 402g.

[0055] The multiple equalization switches 402 can be operated to selectively connect the positive terminal of a selected power supply 401 (e.g., power supply 401a-401g) to a first power supply node 411 and the negative terminal of the selected power supply 401 to a second power supply node 412, or connect the negative terminal of the selected power supply 401 to the first power supply node 411 and the positive terminal of the selected power supply 401 to the second power supply node 412.

[0056] The commutation switch array 420 has a first input terminal electrically connected to the first power node 411, a second input terminal electrically connected to the second power node 412, a first output terminal electrically connected to the first end of the energy storage element 460, and a second output terminal electrically connected to the second end of the energy storage element 460. The commutation switch array 420 can ensure that when the relative polarity of the first power node 411 and the second power node 412 is reversed due to the equalization switch array 410 being connected to an adjacent power source 401, the selected power source 401 is always electrically connected to the energy storage element 460 with the correct polarity.

[0057] Furthermore, the commutation switch array 420 includes switches 403-406. The first terminals of switches 403 and 404 are both electrically connected to the first power node 411, the second terminal of switch 403 is electrically connected to the first terminal of the energy storage element 460, and the second terminal of switch 404 is electrically connected to the second terminal of the energy storage element 460. In some embodiments, switches 403 and 404 may be implemented as transistors (e.g., metal-oxide-semiconductor (MOS) transistors), relays, other electrically controllable switches, or combinations thereof. Switch 403 is configured to selectively connect the first power node 411 to the first terminal of the energy storage element 460, and switch 404 is configured to selectively connect the first power node 411 to the second terminal of the energy storage element 460.

[0058] The first terminals of switches 405 and 406 are both electrically connected to the second power node 412. The second terminal of switch 405 is electrically connected to the first terminal of energy storage element 460, and the second terminal of switch 406 is electrically connected to the second terminal of energy storage element 460. In some embodiments, switches 405 and 406 may be implemented as transistors (e.g., metal-oxide-semiconductor (MOS) transistors), relays, other electrically controllable switches, or combinations thereof. Switch 405 is configured to selectively connect the second power node 412 to the first terminal of energy storage element 460, and switch 406 is configured to selectively connect the second power node 412 to the second terminal of energy storage element 460.

[0059] The energy storage element 460 is used to store or release energy. For example, the energy storage element 460 includes at least one flycapacitor Cfly. Figure 5The following explanation uses the energy storage element 460, which includes a flying capacitor Cfly, as an example.

[0060] The voltage acquisition switch array 430 has a first input terminal electrically connected to a first terminal of the flying capacitor Cfly, a second input terminal electrically connected to a second terminal of the flying capacitor Cfly, and a first output terminal and a second output terminal electrically connected to the voltage sampling circuit 440. The voltage acquisition switch array 430 is configured to provide the voltage on the flying capacitor Cfly to the voltage sampling circuit 440.

[0061] Furthermore, the voltage acquisition switch array 430 includes switches 407 and 408. The first terminal of switch 407 is electrically connected to the first terminal of the flying capacitor Cfly, and the second terminal of switch 407 is electrically connected to the voltage sampling circuit 440. The first terminal of switch 408 is electrically connected to the second terminal of the flying capacitor Cfly, and the second terminal of switch 408 is electrically connected to the voltage sampling circuit 440.

[0062] The voltage sampling circuit 440 is configured to acquire the voltage on the flying capacitor Cfly at preset time intervals to complete the voltage sampling of the power supply 401 that charges the flying capacitor Cfly, and provide all the acquired voltage data to the controller 450. For example, the voltage sampling circuit 440 can be implemented using an analog-to-digital converter (ADC), which is configured to convert the voltage signal on the flying capacitor Cfly into a corresponding digital signal. Therefore, the digital data carried by the digital signal corresponds proportionally to the voltage of the flying capacitor Cfly and the voltage of the power supply 401 that charges the flying capacitor Cfly.

[0063] The controller 440 is used to control the operation of various components in the equalization system 400. For example, the controller 440 may be a general-purpose central processing unit (CPU), a general-purpose processor, a digital signal processing unit (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The aforementioned processor can also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc. The controller 440 may be independent of the equalization system 400 or integrated within other units; no specific limitation is made herein.

[0064] In operation, the controller 440 controls the equalization switch array 410 to electrically connect each power source 401 in the series power supply group to the first power node 411 and the second power node 412 one at a time, and controls the switching of the commutation switch array 420 to connect the selected power source 401 to the first and second terminals of the flying capacitor Cfly with the correct polarity, so as to charge the flying capacitor Cfly to a voltage potential consistent with the potential difference across the selected power source 401. In this embodiment, the multiple equalization switches 402 in the equalization switch array 410 can be implemented by the equalization switch circuit 200 described above. For example, the controller 440 controls the conduction process of the corresponding equalization switch circuit 200 by applying a control signal to the conduction control module 206 in the corresponding equalization switch circuit 200.

[0065] For example, controller 440 can control equalization switch array 410 to electrically connect the positive and negative terminals of power supply 401a to the first power node 411 and the second power node 412, and control commutation switch array 420 to connect the first power node 411 to the first terminal of flying capacitor Cfly and the second power node 412 to the second terminal of flying capacitor Cfly, so as to charge flying capacitor Cfly to a voltage potential consistent with the potential difference across power supply 401a. Then, controller 440 controls equalization switch array 410 and commutation switch array 420 to disconnect, and then controls voltage acquisition switch array 430 to turn on, converting the voltage signal on flying capacitor Cfly into a corresponding digital signal via analog-to-digital converter (ADC) to complete voltage sampling of power supply 401a. This process is repeated until sampling of each power supply 401 in the series power supply group is completed, obtaining the voltage value of each power supply 401.

[0066] The controller 440 is also used to receive voltage values ​​from multiple power supplies 401a-401g acquired by the analog-to-digital converter (ADC). Then, by comparing the voltage values ​​of the multiple power supplies 401a-401g, the strong power supply with the largest voltage value and the weak power supply with the smallest voltage value can be found from these multiple power supplies 401.

[0067] In some embodiments, the controller 440 can sort the voltage values ​​of the plurality of power supplies 401a-401g in ascending order or descending order to obtain the weak and strong power supplies. The above is merely an example of the method for obtaining weak and strong power supplies; other methods will not be described in detail here.

[0068] After obtaining the strong and weak power supplies in the series power supply group, the controller 440 further includes a voltage equalization step for the strong and weak power supplies. This includes electrically connecting the strong power supply to the flying capacitor Cfly via an equalization switch array and a commutation switch array, thereby charging the flying capacitor Cfly. Then, the current path between the strong power supply and the flying capacitor is disconnected, and the weak power supply is electrically connected to the flying capacitor Cfly, thereby charging the weak power supply. The voltage sampling and voltage equalization steps are then repeated until the voltage values ​​of all power supplies 401a-401g in the series power supply group are the same.

[0069] In summary, the equalization switch circuit for an equalization system provided in this embodiment of the invention includes a first transistor and a second transistor configured in reverse order, and a first resistor and a capacitor for controlling the conduction of the first transistor and the second transistor. The first resistor is electrically connected between the source and gate of the first transistor and the second transistor, and the first end of the capacitor is connected to the gate of the first transistor and the second transistor. A narrow pulse conduction signal is applied to the second end of the capacitor to charge it, thereby controlling the conduction of the equalization switch. This equalization switch circuit uses a narrow pulse combined with capacitor driving to control the conduction of the first transistor and the second transistor, allowing the equalization switch to be turned on for only half a resonant cycle each time, reducing the power consumption of the circuit.

[0070] Furthermore, the equalization switch circuit of this embodiment of the invention also includes a protection unit. The protection unit is used to monitor the voltage at the second terminal of the capacitor when the equalization switch is disabled, and pulls the gates of the first transistor and the second transistor to ground when the voltage at the second terminal of the capacitor is less than a set threshold. This allows the equalization switch to be forcibly turned off when the voltage fluctuation at the power supply terminal or the flying capacitor bus exceeds a preset range, thus avoiding false turn-on of the equalization switch and protecting multiple power supplies in the equalization system from damage due to short circuits, thereby improving the safety and stability of the equalization system.

[0071] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0072] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A balancing switch circuit for a balancing system, said balancing system being used to balance the voltages across multiple power supplies, wherein, The equalization switching circuit includes: The first transistor, the first terminal of the first transistor serving as the first connection terminal of the equalization switching circuit; The second transistor has a first terminal serving as the second connection terminal of the equalization switching circuit. The second terminals of both the first transistor and the second transistor are electrically connected to the first node. The control terminals of both the first transistor and the second transistor are electrically connected to the second node. The first transistor and the second transistor are selected from MOSFET or IGBT. A first resistor is electrically connected between the first node and the second node; A capacitor, wherein a first terminal of the capacitor is electrically connected to a second node, and a second terminal of the capacitor is electrically connected to a third node; and The protection unit is used to monitor the voltage at the third node, and when the equalization switch circuit is in the off state, if the voltage at the third node is detected to be less than a set threshold, the voltage at the second node is pulled down to the reference ground to avoid mis-conduction of the first transistor and the second transistor.

2. The equalization switching circuit according to claim 1, wherein, The second terminal of the capacitor is also used to receive a conduction signal, which is used to charge the capacitor in order to control the conduction of the first transistor and the second transistor. The conduction signal is a pulse signal, and the first transistor and the second transistor are turned on during the effective pulse of the conduction signal.

3. The equalization switching circuit according to claim 2 further includes: A conduction control module is used to generate the conduction signal; as well as A driver is electrically connected between the output of the conduction control module and the second terminal of the capacitor.

4. The equalization switching circuit according to claim 3, wherein, The protection unit includes: A comparator is used to compare the voltage at the third node with a reference voltage, the reference voltage being used to characterize the set threshold, and the comparator is used to generate an effective protection signal when the voltage at the third node is less than the reference voltage; A third transistor, selected from a MOSFET, has a first terminal electrically connected to the second node and a second terminal electrically connected to the reference ground; and A protection control module, electrically connected to the control terminal of the third transistor, is used to turn on the third transistor according to the valid protection signal. The protection control module is also used to receive the conduction signal and enable or disable it according to the conduction signal.

5. The equalization switching circuit according to claim 4, wherein, When the first transistor and the second transistor are turned off, the voltage value of the reference voltage is set such that the turn-on time of the third transistor is earlier than the time when the voltage between the first node and the second node is equal to the turn-on threshold of the first transistor and the second transistor.

6. The equalization switching circuit according to claim 1, further comprising: A pre-charge unit is used to pre-charge the control terminals of the first transistor and the second transistor according to the bias voltage.

7. The equalization switching circuit according to claim 6, wherein, The pre-charging unit includes: A fourth transistor, selected from MOSFETs, has a first terminal connected to the bias voltage and a second terminal connected to the control terminals of the first and second transistors; and The second resistor has its first end connected to the bias voltage and its second end connected to the control terminal of the fourth transistor and the first end of the capacitor.

8. The equalization switching circuit according to claim 6, wherein, The bias voltage is set to be equal to the sum of the voltage at the first connection and the set voltage, wherein the set voltage is equal to the voltage across the power supply.

9. The equalization switching circuit according to claim 1, further comprising: A transient voltage suppressor diode is connected between the first node and the second node.

10. A voltage equalization system used to equalize the voltages across multiple power sources, comprising: Energy storage elements are configured to store or release energy; First power node; Second power node; The equalization switch array includes a plurality of equalization switch circuits as described in any one of claims 1-9, wherein the first connection terminal of each equalization switch circuit is electrically connected to the positive or negative terminal of the corresponding power supply, and the second connection terminal of each equalization switch circuit is electrically connected to the first power supply node or the second power supply node. A reversing switch array, connected between the first power node and the second power node and the energy storage element, is configured to switch such that the selected power source is electrically connected to the energy storage element according to a preset polarity. A voltage sampling circuit is configured to obtain the voltage values ​​of the plurality of power sources by acquiring the voltage values ​​on the energy storage element; as well as A controller is used to control the switching of the equalization switch array and the commutation switch array according to the voltage values ​​of the plurality of power supplies, so as to equalize the voltage values ​​of the plurality of power supplies.

11. The equalization system according to claim 10, wherein, The controller is configured to: The system selects a high-voltage power source with the largest voltage value and a low-voltage power source with the smallest voltage value from the plurality of power sources. It then electrically connects the high-voltage power source to the energy storage element, enabling the high-voltage power source to charge the energy storage element and enabling control of the energy storage element to charge the low-voltage power source. The energy storage element includes at least one flying capacitor.

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