Pixel circuit for high dynamic range image sensor

Abstract

The present application relates to a pixel circuit for a high dynamic range image sensor. The pixel circuit includes a first photodiode and a second photodiode. The first and second photodiodes generate charge in response to incident light. A first transfer transistor is coupled to the first photodiode. A first floating diffusion node is coupled to the first transfer transistor. A second transfer transistor is coupled to the second photodiode. A second floating diffusion node is coupled to the second transfer transistor. A dual floating diffusion transistor is coupled between the first and second floating diffusion nodes. An overflow transistor is coupled to the second photodiode. A capacitor is coupled between a voltage source and the overflow transistor. A capacitor readout transistor is coupled between the capacitor and the second floating diffusion node. An anti-blooming transistor is coupled between the first photodiode and a power supply line.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to high dynamic range (HDR) complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, mobile phones, video cameras, as well as in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing. The technology used to manufacture image sensors continues to advance rapidly. For example, the demand for higher resolution and lower power consumption has driven the further miniaturization and integration of these devices.

[0003] A typical complementary metal-oxide semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and, upon absorbing the image light, photogenerate image charge. The image charge photogenerated by the pixels can be measured as an analog output image signal on a column bit line that varies with the incident image light. In other words, the amount of photogenerated image charge is proportional to the intensity of the image light. This charge is read out as an analog signal from the column bit line and converted into a digital value to produce a digital image representing the external scene (i.e., image data).

[0004] Standard image sensors have a limited dynamic range of approximately 60 to 70 dB. However, the real-world dynamic range of brightness is much greater. For example, natural scenes often span a range of 90 dB and greater. To capture details in both bright highlights and dim shadows, high dynamic range (HDR) technology has been used in image sensors to increase the captured dynamic range. Summary of the Invention

[0005] One aspect of the present disclosure provides a pixel circuit comprising: a first photodiode and a second photodiode, wherein the first and second photodiodes generate photocharge in response to incident light; a first transfer transistor coupled to the first photodiode; a first floating diffusion node coupled to the first transfer transistor; a second transfer transistor coupled to the second photodiode; a second floating diffusion node coupled to the second transfer transistor; a double floating diffusion transistor coupled between the first and second floating diffusion nodes; an overflow transistor coupled to the second photodiode; a capacitor coupled between a voltage source and the overflow transistor; a capacitor readout transistor coupled between the capacitor and the second floating diffusion node; and an anti-blooming transistor coupled between the first photodiode and a power line.

[0006] Another aspect of the present disclosure provides an imaging system comprising: a pixel array including a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits includes: a first photodiode and a second photodiode, wherein the first and second photodiodes photogenerate charge in response to incident light; a first transfer transistor coupled to the first photodiode; a first floating diffusion node coupled to the first transfer transistor; a second transfer transistor coupled to the second photodiode; a second floating diffusion node coupled to the second transfer transistor; a double floating diffusion transistor coupled between the first and second floating diffusion nodes; an overflow transistor coupled to the second photodiode; a capacitor coupled between a voltage source and the overflow transistor; a capacitor readout transistor coupled between the overflow transistor and the second floating diffusion node; and an anti-blooming transistor coupled between the first photodiode and a power line; a control circuit system coupled to the pixel array to control operation of the pixel array, wherein the control circuit system is configured to selectively turn on the anti-blooming transistor to disable the first photodiode; and readout circuitry coupled to the pixel array to read out image data from the plurality of pixel circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0008] Figure 1 One example of an imaging system including a pixel array of high dynamic range pixel circuits according to the teachings of the present invention is described.

[0009] Figure 2A A schematic diagram illustrating one example of a high dynamic range pixel circuit according to the teachings of the present disclosure.

[0010] Figure 2B A schematic diagram illustrating another example of a high dynamic range pixel circuit according to the teachings of the present disclosure.

[0011] Figure 2C A schematic diagram illustrating yet another example of a high dynamic range pixel circuit according to the teachings of the present disclosure.

[0012] Figure 3 Shown is a table illustrating examples of four different readout signal gain settings from an example pixel circuit according to the teachings of the present disclosure.

[0013] Figure 4 Timing diagrams illustrating examples of readout of signals and reset signals at four different gain settings from an example pixel circuit are shown in accordance with the teachings of the present disclosure.

[0014] Figure 5 A schematic diagram illustrating yet another example of a high dynamic range pixel circuit according to the teachings of the present disclosure.

[0015] Corresponding reference characters indicate corresponding components throughout the several views. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. Additionally, common but well-understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted to facilitate an unobstructed view of these various embodiments of the present invention. DETAILED DESCRIPTION

[0016] Examples are described herein that relate to imaging systems having pixel arrays that include high dynamic range pixel circuitry. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, one skilled in the relevant art will recognize that the techniques described herein can be practiced without one or more of these specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0017] Reference throughout this specification to "one example" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0018] For ease of description, spatially relative terms such as "below," "beneath," "above," "below," "up," "top," "bottom," "left," "right," "center," "middle," and the like may be used herein to describe the relationship of one element or feature relative to another element or feature, as illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or flipped, an element described as being "below," "beneath," or "beneath" another element or feature would be oriented "above" the other element or feature. Thus, the exemplary terms "below" or "beneath" may encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, it should be understood that when an element is referred to as being "between" two other elements, it may be the only element between the two other elements or one or more intervening elements may also be present.

[0019] Throughout this specification, several specialized terms are used. These terms have their ordinary meanings in the art, unless specifically defined herein or the context of their use clearly indicates otherwise. It should be noted that element names and symbols (e.g., Si versus silicon) are used interchangeably throughout this disclosure; however, both have the same meaning.

[0020] As will be discussed, various examples of imaging systems include a pixel array having an example high dynamic range pixel circuit capable of providing multiple readout signals with different gain settings. In various examples, the pixel circuit includes multiple photodiodes that may have different corresponding light sensitivities. For example, in one example, the pixel circuit includes a first photodiode and a second photodiode. In the example, the first photodiode has a larger sensing area and therefore has a higher light sensitivity, while the second photodiode has a smaller sensing area and therefore has a lower light sensitivity than the first photodiode.

[0021] In various examples, charge photogenerated by a first photodiode in response to incident light can be transferred to a first floating diffusion node via a first transfer transistor, while charge photogenerated by a second photodiode in response to incident light can be transferred to a second floating diffusion node via a second transfer transistor. In response to bright light conditions during an integration period, excess charge photogenerated in the first photodiode can be configured to overflow to a second floating diffusion node via a dual floating diffusion transistor, while excess charge photogenerated in the second photodiode can be configured to overflow to a third floating diffusion node and a capacitor coupled to the third floating diffusion node via an overflow transistor. In various examples, the dual floating diffusion transistor is coupled between the first and second floating diffusion nodes, and a capacitor readout transistor is coupled between the second and third floating diffusion nodes.

[0022] In operation, charge in the first floating diffusion node of the first photodiode can be read out from the pixel circuit via a readout signal having a first conversion gain, or a high conversion gain (HCG). Charge in the first and second floating diffusion nodes of the first photodiode can be read out from the pixel circuit via a readout signal having a second conversion gain, or an intermediate conversion gain (MCG). Charge in the first and second floating diffusion nodes of the second photodiode can be read out from the pixel circuit via a readout signal having a third conversion gain, or another intermediate conversion gain (MCG). Charge in the first, second, third floating diffusion nodes, and capacitor of the second photodiode can be read out from the pixel circuit via a readout signal having a fourth conversion gain, or a low conversion gain (LCG). In various examples, it should also be understood that during a readout cycle of the second photodiode, an anti-blooming transistor coupled to the first photodiode can be configured to turn on to disable the first photodiode or deplete any charge from the first photodiode, thereby preventing charge from the first photodiode from affecting the readout of the second photodiode.

[0023] To illustrate, Figure 1 One example of an imaging system 100 having a pixel array including high dynamic range pixel circuitry in accordance with the teachings of the present invention is shown. In particular, Figure 1 1 illustrates an imaging system 100 including a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and function logic 108. In one example, pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 through Ry) and columns (e.g., C1 through Cx) to acquire image data of a person, place, object, etc., which can then be used to reproduce an image of the person, place, object, etc.

[0024] As will be discussed in various examples, each pixel circuit 104 includes a first photodiode with higher light sensitivity and a second photodiode with lower light sensitivity. The first photodiode can be configured for dark light detection, while the second photodiode can be configured for bright light detection. The full well capacity (or charge accumulation capacity) of the first and second photodiodes can be configured to be different, for example, the first photodiode can be configured to have a full well capacity that is greater than the full well capacity of the second photodiode. Preferably, the second photodiode senses more light than the first photodiode, so in some embodiments, the full well capacity of the second photodiode can be configured to be greater than the full well capacity of the first photodiode. Each pixel circuit 104 further includes first, second, and third floating diffusion nodes coupled to the first and second photodiodes, a capacitor coupled to the third floating diffusion node, a dual floating diffusion transistor coupled between the first and second floating diffusion nodes, a capacitor readout transistor coupled between the second and third floating diffusion nodes, an overflow transistor coupled between the second photodiode and the third floating diffusion node, and an anti-blooming transistor coupled to the first photodiode. In operation, the charge photogenerated by the first and second photodiodes can be read out from the pixel circuit 104 via multiple readout signals with different conversion gains to provide a high dynamic range according to the teachings of the present invention. In various examples, the readout circuit 106 can be configured to read out signals from the pixel circuit 104 of the pixel array 102 via the column bit lines 112. In various examples, the readout circuit 106 can include a current source, routing circuitry, and a comparator that can be included in an analog-to-digital converter or other.

[0025] In an example, the digital image data values ​​produced by the analog-to-digital converter in readout circuitry 106 may then be received by function logic 108. Function logic 108 may simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or other).

[0026] In one example, control circuit 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuit 110 can generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a lighting effect such as a flash.

[0027] In one example, imaging system 100 is implemented on a single semiconductor wafer. In another example, imaging system 100 is on stacked semiconductor wafers. For example, pixel array 102 is implemented on a pixel wafer or sensor wafer, and readout circuitry 106, control circuitry 110, and function logic 108 are implemented on an application-specific integrated circuit (ASIC) wafer, wherein the pixel wafer and ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through-substrate vias (TSVs). As another example, pixel array 102 and control circuitry 110 are implemented on a pixel wafer, and capacitor array, readout circuitry 106, and function logic 108 are implemented on an ASIC wafer, wherein the pixel wafer and ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through-substrate vias (TSVs). In another example, portions of each pixel 104 (including, for example, first and second photodiodes, a transfer transistor, an overflow transistor, and an anti-blooming transistor) are included in a first chip, while the capacitor array, capacitor readout transistors are included in a second chip, and the control circuitry and ASIC circuitry are included in a third chip stacked with the first and second chips, and so on.

[0028] In one example, the imaging system 100 may be included in a digital camera, a cell phone, a laptop computer, an endoscope, a webcam, an automotive imaging device, or the like. Additionally, the imaging system 100 may be coupled to other hardware, such as a processor (general purpose or otherwise), memory elements, outputs (USB ports, wireless transmitters, HDMI ports, etc.), lighting / flashlights, electrical inputs (keyboard, touch display, trackpad, mouse, microphone, etc.), and / or a display. The other hardware may transmit instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data supplied by the imaging system 100.

[0029] Figure 2A Schematic diagram illustrating one example of a high dynamic range pixel circuit 204A according to the teachings of the present disclosure. It should be understood that Figure 2A The pixel circuit 204A may be Figure 1 An example of one of the pixel circuits 104 included in the pixel array 102 is shown in FIG. 1 , and similarly named and numbered elements described above are similarly coupled and operate hereinafter.

[0030] As shown in the depicted example, pixel circuit 204A includes a first photodiode 214 and a second photodiode 228 configured to photogenerate charge (e.g., electrons or holes) in response to incident light. In one example, first photodiode 214 has a larger sensing area and, therefore, can be referred to as a large photodiode (LPD) with higher light sensitivity. In an example, second photodiode 228 has a smaller sensing area and, therefore, can be referred to as a small photodiode (SPD) with lower light sensitivity than first photodiode LPD 214. Second photodiode 228 can be configured to sense bright or intense light. First photodiode 214 and second photodiode 228 can be configured with different full well capacities, such as different implant configurations (e.g., doses or implant energies that result in depletion regions with different volumes). As shown in the example, a first transfer transistor 216 is coupled to first photodiode LPD 214, and a first floating diffusion node FD1 218 is coupled to first transfer transistor 216. In one example, the first transfer transistor 216 is controlled in response to a first transfer control signal LTX to control the transfer of charge from the first photodiode LPD 214 to the first floating diffusion node FD1 218. The second transfer transistor 230 is coupled to the second photodiode SPD 228, and the second floating diffusion node FD2 226 is coupled to the second transfer transistor 230. In one example, the second transfer transistor 230 is controlled in response to a second transfer control signal STX to control the transfer of charge from the second photodiode SPD 228 to the second floating diffusion node FD2 228. The second floating diffusion node FD2 228 can be further coupled to a junction capacitor, which is combined with a metal capacitor or a metal oxide semiconductor capacitor (MOSCAP) for charge storage.

[0031] Continuing with the depicted example, dual floating diffusion transistor 224 is coupled between first floating diffusion node FD1 218 and second floating diffusion node FD2 226. In one example, dual floating diffusion transistor 224 is controlled in response to dual floating diffusion signal DFD to control the transfer of charge between first floating diffusion node FD1 218 and second floating diffusion node FD2 226. In one example, overflow transistor 234 is coupled to second photodiode SPD 228, and third floating diffusion node FD3 236 is coupled to overflow transistor 234. In one example, overflow transistor 234 is controlled in response to overflow control signal OF. As shown in the depicted example, capacitor CAP 240 is coupled between voltage source VRFD 244 and third floating diffusion node FD3 236, which is coupled to overflow transistor 234. In one example, an upper capacitor electrode of capacitor CAP 240 is coupled to voltage source VRFD 244 and a lower capacitor electrode of capacitor CAP 240 is coupled to third floating diffusion node FD3 236 and overflow transistor 234 .

[0032] A capacitor readout transistor 238 is coupled between a third floating diffusion node FD3 236 (which is coupled to capacitor CAP 240) and a second floating diffusion node FD2 226. An antiblooming transistor 242 is coupled between the first photodiode LPD 214 and the power supply line PixVDD. The gate of the source follower transistor 220 is coupled to the first floating diffusion node FD1 218. A row select transistor 222 is coupled to the source follower transistor 220. As shown in the depicted example, the source follower transistor 220 and the row select transistor 222 are coupled between the power supply line PixVDD and the bit line 212.

[0033] exist Figure 2A 2, 226. In the example depicted in FIG, reset transistor 232 is coupled between voltage source VRFD 244 and second floating diffusion node FD2 226. In the depicted example, row select transistor 222 is configured to be controlled in response to row select signal RS, and reset transistor 232 is configured to be controlled in response to reset signal RST. A signal can be read out of pixel circuit 204A through bit line 212 and row select transistor 222 in response to charge at the gate of source follower transistor 220. In operation, charge photogenerated by first photodiode LPD 214 and second photodiode SPD 228 can be read out of pixel circuit 204A through bit line 212 via multiple readout signals having different conversion gains to provide a high dynamic range in accordance with the teachings of the present invention.

[0034] In the depicted example, charge is photogenerated in response to incident light in first photodiode LPD 214 and second photodiode SPD 228. In the example, first photodiode LPD 214 is configured for dim light (e.g., low light) sensing, and second photodiode SPD 228 is configured for bright light (e.g., bright light) sensing. During integration, excess charge photogenerated from first photodiode LPD 214 is configured to drain from first floating diffusion node FD1 218 and through dual floating diffusion transistor 224 to second floating diffusion node FD2 226, and may also drain through reset transistor 232 to voltage supply VRFD 244. Excess charge photogenerated from second photodiode SPD 228 is configured to overflow through overflow transistor 234 to third floating diffusion node FD3 236 to capacitor CAP 240, even when overflow transistor 234 is off. In one example, overflow transistor 234 may be configured to be more leaky than second transfer transistor 230 during integration. In various examples, the gate bias voltage supplied to the gate of overflow transistor 234 can be greater than the gate bias voltage supplied to second transfer transistor 230, and / or overflow transistor 234 can be configured with additional channel implants to provide a leakage path for excess charge photogenerated during integration between second photodiode SPD 228 and capacitor CAP 240. In various examples, capacitor CAP 240 is a lateral overflow integration capacitor (LOFIC), which can be implemented using a metal-oxide-semiconductor capacitor (MOSCAP), a metal-insulator-metal (MIM) capacitor, a high-k MIM capacitor, or the like. In one example, the capacitance of capacitor CAP 240 is configured to be greater than the capacitance associated with second floating diffusion node FD2 226 and the capacitance associated with first floating diffusion node FD1 218.

[0035] Continuing with the depicted example, the antiblooming transistor 242 is configured to be turned on to disable the first photodiode LPD 214 or to deplete the photogenerated charge of the first photodiode LPD 214 during readout of the second photodiode SPD 228. Thus, the charge photogenerated from the first photodiode LPD 214 is prevented from interfering with the readout of the photogenerated charge from the second photodiode SPD 228, thereby affecting the sensitivity of the second photodiode SPD 228. In various examples, it should be understood that even though the readout time of the second photodiode SPD 228 may be several microseconds, the first photodiode LPD 214 may still saturate and overflow to the first floating diffusion node FD1 218, which would negatively impact the readout of the second photodiode SPD 228 if the antiblooming transistor 242 were not present.

[0036] As will be discussed, in the depicted example, the capacitor readout transistor 238 is configured to selectively couple the capacitor CAP 240 and the third floating diffusion node FD3 236 to the second floating diffusion node FD2 226 to modulate the effective capacitance associated with the second photodiode SPD 228 to provide an intermediate conversion gain (MCG) readout signal of the charge from the second photodiode SPD 228. It should therefore be appreciated that when the capacitor readout transistor 238 is turned on, excess charge photogenerated from the second photodiode SPD 228 and stored in the capacitor CAP 240 and the third floating diffusion node FD3 236 may be read out through the second floating diffusion node FD2 226 to the first floating diffusion node FD1 218.

[0037] In operation, reset transistor 232 is configured to selectively reset pixel circuit 204A. For example, when turned on, charge in first photodiode LPD 214, second photodiode SPD 228, first floating diffusion node FD1 218, second floating diffusion node FD2 226, third floating diffusion node FD3 236, and / or capacitor CAP 240 can discharge through reset capacitor 232 to voltage source VRFD 244, thereby resetting first photodiode LPD 214, second photodiode SPD 228, first floating diffusion node FD1 218, second floating diffusion node FD2 226, and third floating diffusion node FD3 236.

[0038] In one example, it will be appreciated that Figure 2A The circuit elements of the pixel circuit 204A described in FIG. 1 may all be included in a single chip or semiconductor die. It should be understood that in other examples, one or more elements of the pixel circuit 204A may be included in two or more stacked chips coupled to each other. For illustration, Figure 2B FIG2 is a schematic diagram illustrating another example of a high dynamic range pixel circuit 204B according to the teachings of the present disclosure. It should be understood that Figure 2B The pixel circuit 204B may be Figure 1 1 and 2. FIG. 1 is another example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1 , and similarly named and numbered elements described above are similarly coupled and operate hereinafter. It should also be understood that Figure 2B The pixel circuit 204B depicted in FIG is substantially similar to the pixel circuit 204B discussed in detail above. Figure 2A Thus, it should be understood that Figure 2B The operation of the pixel circuit 204B is also similar to Figure 2A The operation of the pixel circuit 204A. As will be shown, Figure 2B The pixel circuit 204B and Figure 2A One of the differences between the pixel circuit 204A is Figure 2B The circuit elements of the example pixel circuit 204B illustrated in FIG. 1 are included in two chips, rather than in FIG. Figure 2A The example pixel circuit 204A is included in a single chip as depicted in FIG.

[0039] like Figure 2B , pixel circuit 204B includes circuit elements included in a first die 246 (e.g., a sensor die) and a second die 248 (e.g., an application specific integrated circuit (ASIC) die or a logic die). In one example, first die 246 and second die 248 are coupled together or stacked together in a stacked chip scheme to provide a complementary metal oxide semiconductor (CMOS) image sensor (CIS) according to the teachings of the present invention.

[0040] As shown in the depicted example, overflow transistor 234 is included in a first die 246, while at least a portion of third floating diffusion node FD3 236 and capacitor CAP 240 are included in a second die 248. In the example, overflow transistor 234 is coupled to third floating diffusion node FD3 236 and capacitor CAP 240 through a first hybrid junction 250 between the first die 246 and the second die 248.

[0041] exist Figure 2B , the first die 246 further includes a first photodiode LPD 214 and a second photodiode SPD 228, a first transfer transistor 216, a second transfer transistor 230, a first floating diffusion node FD1 218, and an antiblooming transistor 242. In the depicted example, the first die 246 further includes a capacitor readout transistor 238, which is also coupled to a third floating diffusion node FD3 236 and a capacitor CAP 240 via a first hybrid junction 250 between the first die 246 and the second die 248. As shown in the depicted example, the first die 246 also includes a reset transistor 232, a second floating diffusion node FD2 226, a dual floating diffusion transistor 224, a source follower transistor 220, and a row select transistor 222. In the depicted example, the reset transistor is coupled to a voltage source VRFD 244 via a hybrid junction 259 between the first die 246 and the second die 248. The second die 248 may further include one or more additional readout circuit components, such as current sources, routing circuitry, and comparators, which may be included in the analog-to-digital converter, control circuitry, and signal processing circuitry.

[0042] In each instance, it should be understood that Figure 2B The operation of the pixel circuit 204B depicted in FIG. 1 is similar to that of FIG. Figure 2AThe operation of the example pixel circuit 204A depicted in FIG is only in accordance with the teachings of the present invention, where the circuit elements of the example pixel circuit 204B are included in two chips (e.g., the first chip 246 and the second chip 248), while the circuit elements of the example pixel circuit 204A are included in a single chip.

[0043] Figure 2C FIG. 2 is a schematic diagram illustrating yet another example of a high dynamic range pixel circuit 204C according to the teachings of the present disclosure. It should be understood that Figure 2C The pixel circuit 204C may be Figure 1 1 and similarly named and numbered elements described above are similarly coupled and operate hereinafter. It should also be understood that Figure 2C The pixel circuit 204C depicted in FIG. 1 is substantially similar to the pixel circuit 204C discussed in detail above. Figure 2A The pixel circuit 204A and / or Figure 2B Thus, it should be understood that Figure 2C The operation of the pixel circuit 204C is also similar to Figure 2A The pixel circuit 204A and / or Figure 2B The operation of the pixel circuit 204B will be shown. Figure 2C The pixel circuit 204C and Figure 2B One of the differences between the pixel circuit 204B is Figure 2C The distribution of circuit elements of the example pixel circuit 204C illustrated in FIG. Figure 2B Distribution of circuit elements of the pixel circuit 204B.

[0044] To illustrate, Figure 2C , pixel circuit 204C includes circuit elements included in a first die 246 (e.g., a sensor die) and a second die 248 (e.g., a logic die). In one example, first die 246 and second die 248 are coupled together or stacked together in a stacked chip arrangement to provide a complementary metal oxide semiconductor (CMOS) image sensor (CIS) according to the teachings of the present invention. In one example, the second die may further include column circuitry, row circuitry, control circuitry, ASIC processing circuitry, and the like.

[0045] continue Figure 2C , the overflow transistor 234 is included in the first die 246, while the third floating diffusion node FD3 236 and the capacitor CAP 240 are included in the second die 248. In the example, the overflow transistor 234 is coupled to the third floating diffusion node FD3 236 and the capacitor CAP 240 through a first hybrid junction 250 between the first die 246 and the second die 248.

[0046] exist Figure 2C In the example depicted in FIG, the first die 246 further includes a first photodiode LPD 214 and a second photodiode SPD 228, a first transfer transistor 216, a second transfer transistor 230, a first floating diffusion node FD1 218, and an anti-blooming transistor 242. In the depicted example, the second die 248 further includes a capacitor readout transistor 238, a reset transistor 232, a second floating diffusion node FD2 226, a double floating diffusion transistor 224, a source follower transistor 220, and a row select transistor 222. Figure 2C , the first floating diffusion node FD1 218 can be coupled to the gate of the source follower transistor 220 and the double floating diffusion transistor 224 via a second hybrid junction 256 between the first die 252 and the second die 254. Figure 2C The example depicted in shows that the second transfer transistor 230 may be coupled to the second floating diffusion node FD2 236 through a third hybrid junction 258 between the first wafer 252 and the second wafer 254 .

[0047] It should be understood that in another example, a third stacked wafer may be implemented wherein Figure 2C The two dies depicted in FIG24 can be two of at least three dies in a stacked chip solution according to the teachings of the present invention. In this example, a third die can be coupled to and stacked with first die 246 and second die 248, where the third die can be a logic die that can include, for example, column circuitry, row circuitry, control circuitry, memory circuitry, ASIC processing circuitry, etc.

[0048] In each instance, it should be understood that Figure 2C The operation of the pixel circuit 204C depicted in FIG. 2 is similar to that of FIG. Figure 2A The example pixel circuit 204A and / or Figure 2B The operation of the example pixel circuit 204B is described in detail, except that the distribution of circuit elements of the example pixel circuit 204C in the two chips (e.g., the first chip 246 and the second chip 248) is different from the distribution of circuit elements in the example pixel circuit 204C described above in accordance with the teachings of the present invention. Figure 2A The example pixel circuit 204A and / or Figure 2B The example pixel circuit 204B shown in FIG. 10A discusses in detail the distribution of circuit elements in one or more chips.

[0049] Figure 3 A table illustrating examples of four different readout signal gain settings from an example pixel circuit according to the teachings of the present disclosure is shown. It should be understood that according to the teachings of the present invention, Figure 3The four different readout signal gain settings depicted in the example shown in FIG can be applied to any of the example pixel circuits described in this disclosure, including, for example, the above Figure 2A 、 Figure 2B and / or Figure 2C Pixel circuits 204A, 204B and / or 204C are described in detail in FIG.

[0050] like Figure 3 2 shows that, in accordance with the teachings of the present invention, in a first readout gain setting example, charge stored at a larger photodiode (e.g., first photodiode LPD 214) can be read out from a first floating diffusion node (e.g., first floating diffusion node FD1 218) to provide a high conversion gain (HCG) readout associated with a larger photodiode (e.g., first photodiode LPD 214 for dark light detection). In various examples, the charge stored at first floating diffusion node FD1 218 is read out through bit line 212 via source follower transistor 220 and through row select transistor 222.

[0051] According to the teachings of the present invention, Figure 3 The example depicted in FIG2 shows that, in a second readout gain setting example, charge stored at a larger photodiode (e.g., first photodiode LPD 214) can be read out from a first floating diffusion node (e.g., first floating diffusion node FD1 218) and a second floating diffusion node (e.g., second floating diffusion node FD2 226) to provide an intermediate conversion gain (MCG) readout associated with a large photodiode (e.g., first photodiode LPD 214 for dark-light detection) having a medium conversion gain that is less than the high conversion gain associated with a high conversion gain (HCG) readout. In each example, the charge stored at first floating diffusion node FD1 218 and second floating diffusion node FD2 226 is read out through bit line 212 via dual floating diffusion transistor 224, source follower transistor 220, and through row select transistor 222.

[0052] According to the teachings of the present invention, Figure 3The example depicted in FIG further shows that, in a third readout gain setting example, charge stored at a small photodiode (e.g., second photodiode SPD 228) can be read out from a first floating diffusion node (e.g., first floating diffusion node FD1 218) and a second floating diffusion node (e.g., second floating diffusion node FD2 226) to provide another intermediate conversion gain (MCG) readout associated with the small photodiode (e.g., second photodiode SPD 228 for bright light detection). The conversion gain associated with the intermediate conversion gain (MCG) readout of the small photodiode (e.g., second photodiode SPD 228) can be less than the high conversion gain associated with the high conversion gain (HCG) readout of the larger photodiode (e.g., first photodiode LPD 214). In each example, the charge stored at first floating diffusion node FD1 218 and second floating diffusion node FD2 226 is read out through bit line 212 via dual floating diffusion transistor 224, source follower transistor 220, and through row select transistor 222. In various examples, in accordance with the teachings of the present invention, the anti-blooming transistor 242 can be turned on during readout of the second photodiode SPD 228 to disable the first photodiode LPD 214 or deplete the charge of the first photodiode LPD 214, thereby preventing any charge photogenerated from the first photodiode LPD 214 in response to incident light from affecting the readout operation of the second photodiode SPD 228.

[0053] According to the teachings of the present invention, Figure 3The example depicted in FIG2 also shows that, in a fourth readout gain setting example, charge stored at a small photodiode (e.g., second photodiode SPD 228) and a capacitor (e.g., capacitor CAP 240) can be read out from a first floating diffusion node (e.g., first floating diffusion node FD1 218), a second floating diffusion node (e.g., second floating diffusion node FD2 236), and a third floating diffusion node (e.g., third floating diffusion node FD3 236) to provide a low conversion gain (LCG) readout associated with the small photodiode (e.g., second photodiode SPD 228 for bright light detection). The conversion gain associated with the low conversion gain (LCG) readout of the small photodiode (e.g., second photodiode SPD 228) is less than the conversion gain associated with the medium conversion gain (MCG) readout of the small photodiode (e.g., second photodiode SPD 228). In various examples, the charge stored at the first floating diffusion node FD1 218, the second floating diffusion node FD2 226, and the third floating diffusion node FD3 236 is read out through the bit line 212 via the dual floating diffusion transistor 224, the capacitor readout transistor 238, the source follower transistor 220, and through the row select transistor 222. In various examples, in accordance with the teachings of the present invention, the anti-blooming transistor 242 can be turned on during readout of the second photodiode SPD 228 to disable the first photodiode LPD 214 or deplete the charge of the first photodiode LPD 214 (e.g., charge photogenerated by the first photodiode LPD 214 during readout of the second photodiode SPD 228), thereby preventing the charge from the first photodiode LPD 214 from affecting the readout of the second photodiode SPD 228.

[0054] Figure 4 A timing diagram illustrating an example of readout of signals and reset signals at four different conversion gain settings from an example pixel circuit according to the teachings of the present disclosure is shown. It should be understood that according to the teachings of the present invention, Figure 3 The signals depicted in the example timing diagram shown in FIG. 1 can be applied to any of the example pixel circuits described in this disclosure, including, for example, the example pixel circuits described above. Figure 2A 、 Figure 2B and / or Figure 2C Pixel circuits 204A, 204B and / or 204C are described in detail in FIG.

[0055] As shown, Figure 4 The example depicted in illustrates row select signal RS 422, reset signal RST 432, double floating diffusion signal DFD 424, capacitor readout signal CRD 438, large transfer control signal LTX 416, small transfer control signal STX 430, antiblooming signal AB 442, voltage supply signal VRFD 444, and overflow signal OF 434. Figure 4 The example depicted in shows that an idle period 460 is followed by a precharge period 462, which is followed by an integration period 464, which is followed by a readout period 466.

[0056] Figure 4 The timing diagram example shown in shows that during the idle period 460, the row select signal RS 422, the capacitor read signal CRD 438, the large transfer control signal LTX 416, the small transfer control signal STX 430, the anti-blooming signal AB 442, the voltage source signal VRFD 444 and the overflow signal OF 434 are at low values ​​and the reset signal RST 432 and the double floating diffusion signal DFD424 are at high values.

[0057] Then, during the precharge cycle 462, the row select signal RS 422, the capacitor readout signal CRD 438, the small transfer control signal STX 430, the antiblooming signal AB 442, and the voltage supply signal VRFD 444 transition to high levels, thereby allowing the associated pixel circuit to be reset. Then, the capacitor readout signal CRD 438 and the small transfer control signal STX 430 transition to low levels and the large transfer control signal LTX 416 pulses, and then the antiblooming signal AB 442 transitions to low levels, and then the voltage supply signal VRFD 444 transitions to low levels, and then the row select signal RS 422 transitions to low levels to prepare the pixel circuit for integration.

[0058] Then, during an integration period 464, row select signal RS 422, capacitor readout signal CRD 438, large transfer control signal LTX 416, small transfer control signal STX 430, antiblooming signal AB 442, voltage source signal VRFD 444, and overflow signal OF 434 are at low levels, and reset signal RST 432 and double floating diffusion signal DFD 424 are at high levels. The low level of overflow signal OF 434 can be configured to be the same as or different from the low level of small transfer control signal STX 430. In one example, the low level of overflow signal OF 434 can be greater than the low level of small transfer control signal STX 430. Thus, when a first or large photodiode (e.g., first photodiode LPD 214) is saturated, excess charge photogenerated by the corresponding first or large photodiode (e.g., first photodiode LPD 214) that overflows to the first floating diffusion node (e.g., first floating diffusion node FD1 218) will be drained from the first floating diffusion node FD1 218 and reach the voltage supply VRFD 244 through the dual floating diffusion transistor 224, the second floating diffusion node FD2 226, and the reset transistor 232. Simultaneously, when a second or small photodiode (e.g., second photodiode SPD 228) is saturated, excess charge photogenerated by the corresponding second or small photodiode (e.g., second photodiode SPD228) will overflow to the capacitor CAP 240 through the third floating diffusion node FD3 236 for storage.

[0059] Then, during the readout cycle 466, the row select signal RS 422 transitions high, and then the voltage source signal VRFD 444 transitions high, and then the reset signal RST 432 transitions low. Then, the intermediate conversion gain reset signal value of LPD (MCG RST for LPD) can be read out from the pixel circuit.

[0060] Next, the dual floating diffusion signal DFD 424 transitions to a low value, and then the high conversion gain reset signal value (HCGRST) can be read out from the pixel circuit.

[0061] Next, the large transfer control signal LTX 416 is pulsed, and then the high conversion gain signal value (HCG SIG) associated with the first or large photodiode (eg, first photodiode LPD 214) can be read out from the pixel circuit.

[0062] Then, the double floating diffusion signal DFD 424 transitions to a high value and the large transfer control signal LTX 416 pulses, and then the intermediate conversion gain signal value of LPD (MCG SIG of LPD) associated with the first or large photodiode (e.g., first photodiode LPD 214) can be read out from the pixel circuit.

[0063] Then, the antiblooming signal AB transitions to a high level and the reset signal pulsates. Then, the small photodiode reset signal (SPD RST) is read out.

[0064] Then, the small transfer control signal STX 430 is pulsed and a small photodiode signal value (SPD SIG) corresponding to the intermediate conversion gain signal value of the SPD can be read out. This signal can include the charge transferred to the first and second floating diffusion nodes, such as Figure 3 The third readout gain setting is depicted in FIG.

[0065] Then, the capacitor readout signal CRD 438 and the small transfer control signal STX 430 transition to a high value and then the capacitor signal value (CAP SIG) value corresponding to the low conversion gain signal value of the SPD can be read out. This signal can include the photogenerated charge accumulated and stored in the small photodiode (SPD) and the excess photogenerated charge overflowed and stored in the associated capacitor, such as Figure 3 The fourth readout gain setting is depicted in FIG.

[0066] Next, the reset signal RST 432 is pulsed, and the capacitor read signal CRD 438 and the small transfer control signal STX 430 transition to a low value. Then, after the reset signal RST 432 pulses, the capacitor read signal CRD 438 and the small transfer control signal STX 430 transition back to a high value, and the capacitor reset signal value (CAP RST) is read out. Next, the capacitor read signal CRD 438, the small transfer control signal STX 430, the anti-blooming signal AB 442, and then the voltage supply signal VRFD 444 and then the row select signal transition to a low value to complete the read cycle 466. It should be understood that in the illustrated example, the anti-blooming signal AB442 remains high (e.g., turning on the associated anti-blooming transistor 242) during the entire readout operation of the second or small photodiode (e.g., the second photodiode SPD 228) during a readout cycle that includes a capacitor signal value (CAP SIG) and a capacitor reset signal value (CAP RST) associated with the second or small photodiode (e.g., the second photodiode SPD 228) to avoid charge from the first or large photodiode (e.g., the first photodiode LPD 214) interfering with the photodiode (or image) signal associated with the second or small photodiode (e.g., the second photodiode SPD 228).

[0067] It should be appreciated that, in various examples, a correlated double sampling (CDS) value of an intermediate conversion gain (LPD-MCG) signal value of the LPD can be determined in response to a difference between an intermediate conversion gain signal value of the LPD (MCG SIG of LPD) and an intermediate conversion gain reset signal value of the LPD (MCG RST of LPD). A CDS value of a high conversion gain (HCG) signal value associated with a first or large photodiode can be determined in response to a difference between the high conversion gain signal value (HCG SIG) and the high conversion gain reset signal value (HCG RST). A CDS value of a small photodiode (SPD) signal value having an intermediate conversion gain associated with a second or small photodiode (e.g., second photodiode SPD 228) can be determined in response to a difference between the small photodiode signal value (SPD SIG) and the small photodiode reset signal value (SPD RST). A low conversion gain (SPDLCG) signal value of the capacitor (CAP) signal value may be determined in response to a difference between the capacitor signal value (CAP SIG) and a capacitor reset signal value (CAP RST) read out after the capacitor signal value (CAP SIG). Subsequently, an image signal associated with the example pixel circuit may be generated based on a high conversion gain signal value (HCGSIG) associated with a first or large photodiode (e.g., first photodiode LPD 214), an intermediate conversion gain signal value (LPD MCG SIG) associated with the first or large photodiode (e.g., first photodiode LPD 214), an intermediate conversion gain small photodiode (SPD) signal value associated with a second or small photodiode (e.g., second photodiode SPD 228), and a low conversion gain (SPD LCG) signal associated with the second or small photodiode (e.g., second photodiode SPD 228), thereby achieving a high dynamic range of up to 140 dB by extending the dynamic range associated with bright light imaging.

[0068] Figure 5 Schematic diagram illustrating yet another example of a high dynamic range pixel circuit 504 according to the teachings of the present disclosure. It should be understood that Figure 5 The pixel circuit 504 may be Figure 1 1 and similarly named and numbered elements described above are similarly coupled and operate hereinafter. It should also be understood that Figure 5 The pixel circuit 504 depicted in FIG is similar to the pixel circuit 504 discussed in detail above. Figure 2A The pixel circuit 204A depicted in FIG. 2 shares many similarities. Thus, it should be appreciated that Figure 5 The operation of the pixel circuit 504 is also similar to Figure 2A The operation of the pixel circuit 204A. As will be shown, Figure 5 The pixel circuit 504 and Figure 2A One of the differences between the pixel circuit 204A and the CMOS pixel circuit 204B is that the reset transistor 532 is coupled between the power supply line PixVDD and the first floating diffusion node FD1 518 .

[0069] Specifically, if Figure 5 As shown in the example depicted in FIG, pixel circuit 504 includes a first photodiode 514 and a second photodiode 528 configured to photogenerate charge in response to incident light. In one example, first photodiode 514 has a larger sensing area and, therefore, can be referred to as a large photodiode (LPD) having higher light sensitivity and configured for sensing dim light. In an example, second photodiode 528 has a smaller sensing area and, therefore, can be referred to as a small photodiode (SPD) having lower light sensitivity than first photodiode 514 and configured for sensing bright or intense light. As shown in the example, a first transfer transistor 516 is coupled to first photodiode 514, and a first floating diffusion node FD1 518 is coupled to first transfer transistor 516. In one example, first transfer transistor 516 is controlled in response to a first transfer control signal LTX. A second transfer transistor 530 is coupled to second photodiode 528, and a second floating diffusion node FD2 526 is coupled to second transfer transistor 530. In one example, second transfer transistor 530 is controlled in response to a second transfer control signal STX.

[0070] Continuing with the depicted example, dual floating diffusion transistor 524 is coupled between first floating diffusion node FD1 518 and second floating diffusion node FD2 526. In one example, overflow transistor 534 is coupled to second photodiode 528, and third floating diffusion node FD3 536 is coupled to overflow transistor 534. In one example, overflow transistor 534 is controlled in response to overflow control signal OF. As shown in the depicted example, capacitor CAP 540 is coupled between voltage source VRFD 544 and third floating diffusion node FD3 536, which is coupled to overflow transistor 534. Additionally, capacitor readout transistor 538 is coupled between third floating diffusion node FD3 536 (which is coupled to capacitor CAP 540) and second floating diffusion node FD2 526. Antiblooming transistor 542 is coupled between first photodiode 514 and power supply line PixVDD. The gate of source follower transistor 520 is coupled to first floating diffusion node FD1 518 and row select transistor 522 is coupled to source follower transistor 520. Source follower transistor 520 and row select transistor 522 are coupled between power line PixVDD and bit line 512 as shown in the depicted example.

[0071] As mentioned, Figure 5An example pixel circuit 504 with Figure 2A One of the differences between the example pixel circuit 204A is that Figure 5 In the example pixel circuit 504 depicted in FIG, the reset transistor 532 is coupled between the power supply line PixVDD and the first floating diffusion node FD1 518. Therefore, it should be understood that in Figure 5 , the antiblooming transistor 542 is coupled between the drain of the reset transistor 532 and the first photodiode LPD 514. Thus, in the depicted example, the common drain of the reset transistor 532 and the antiblooming transistor 542 can be shared to provide layout flexibility and pixel scaling in accordance with the teachings of the present invention.

[0072] In the depicted example, the row select transistor 522 is configured to be controlled in response to a row select signal RS, and the reset transistor 532 is configured to be controlled in response to a reset signal RST. A signal can be read out of the pixel circuit 504 through the bit line 512 and the row select transistor 522 in response to the charge at the gate of the source follower transistor 520. In operation, the charge photogenerated by the first photodiode 514 and the second photodiode 528 can be read out of the pixel circuit 504 through the bit line 512 via multiple readout signals with different gains to provide a high dynamic range in accordance with the teachings of the present invention, as also described in detail above.

[0073] The above description of the illustrated examples of the present invention (including what is described in the Abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the present invention have been described herein for illustration, those skilled in the relevant art will recognize that various modifications are possible within the scope of the present invention.

[0074] These modifications can be made to the invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the appended claims, which are to be interpreted in accordance with recognized principles of claim interpretation.

Claims

1. A pixel circuit, comprising: a first photodiode and a second photodiode, wherein the first and second photodiodes photogenerate charge in response to incident light; a first transfer transistor coupled to the first photodiode; a first floating diffusion node coupled to the first transfer transistor; a second transfer transistor coupled to the second photodiode; a second floating diffusion node coupled to the second transfer transistor; a dual floating diffusion transistor coupled between the first and second floating diffusion nodes; an overflow transistor coupled to the second photodiode; a capacitor coupled between a voltage source and the overflow transistor; a capacitor readout transistor coupled between the capacitor and the second floating diffusion node; and an anti-blooming transistor coupled between the first photodiode and a power supply line, The anti-blooming transistor is configured to (a) be turned on to disable the first photodiode during readout of the second photodiode, and (b) be turned off for readout of the first photodiode so that charge stored in the first photodiode can be read out during readout of the first photodiode.

2. The pixel circuit according to claim 1 , further comprising: a source follower transistor having a gate coupled to the first floating diffusion node; and A row select transistor is coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between the power line and a bit line. 3 . The pixel circuit of claim 2 , further comprising a reset transistor coupled between the power line and the first floating diffusion node. 4 . The pixel circuit of claim 2 , further comprising a reset transistor coupled between the voltage source and the second floating diffusion node. 5 . The pixel circuit according to claim 4 , wherein the pixel circuit is included in a stacked complementary metal oxide semiconductor (CIS) image sensor (CIS) system including at least a first chip and a second chip stacked with the first chip. 6 . The pixel circuit of claim 5 , wherein the overflow transistor is included in the first die, wherein the capacitor is included in the second die, wherein the overflow transistor is coupled to the capacitor through a first hybrid junction between the first die and the second die.

7. The pixel circuit of claim 6, wherein the first die further comprises the first and second photodiodes, the first and second transfer transistors, the first floating diffusion node, and the anti-blooming transistor.

8. The pixel circuit according to claim 7, wherein the first die further includes the capacitor readout transistor, wherein the capacitor readout transistor is coupled to the capacitor through the first hybrid junction between the first die and the second die, The first chip further includes the reset transistor, the second floating diffusion node, the double floating diffusion transistor, the source follower transistor and the row select transistor.

9. The pixel circuit according to claim 7, wherein the second chip further comprises the capacitor readout transistor, the reset transistor, the second floating diffusion node, the double floating diffusion transistor, the source follower transistor, and the row select transistor, wherein the first floating diffusion node is coupled to the gate of the source follower transistor and the double floating diffusion transistor through a second hybrid bond between the first wafer and the second wafer, The second transfer transistor is coupled to the second floating diffusion node via a third hybrid junction between the first wafer and the second wafer. 10 . The pixel circuit of claim 1 , wherein the first photodiode has a first light sensitivity and the second photodiode has a second light sensitivity, wherein the first light sensitivity is greater than the second light sensitivity.

11. A pixel circuit according to claim 1, wherein a first conversion gain signal is configured to be read out from the pixel circuit in response to the charge photogenerated by the first photodiode and transferred to the first floating diffusion node, wherein the dual floating diffusion transistor is configured to be turned off when the first conversion gain signal is read out from the pixel circuit.

12. A pixel circuit according to claim 10, wherein a second conversion gain signal is configured to be read out from the pixel circuit in response to the charge photogenerated by the first photodiode and transferred to the first floating diffusion node and the second floating diffusion node, wherein the dual floating diffusion transistor is configured to be turned on and the capacitor readout transistor is configured to be turned off when the second conversion gain signal is read out from the pixel circuit.

13. A pixel circuit according to claim 10, wherein a third conversion gain signal is configured to be read out from the pixel circuit in response to the charge photogenerated by the second photodiode and transferred to the second floating diffusion node and the first floating diffusion node, wherein the dual floating diffusion transistor and the anti-blooming transistor are configured to be turned on and the capacitor readout transistor is configured to be turned off when the third conversion gain signal is read out from the pixel circuit.

14. The pixel circuit of claim 1, wherein excess charge photogenerated by the second photodiode in response to bright incident light is configured to overflow from the second photodiode to the capacitor through the overflow transistor.

15. A pixel circuit according to claim 14, wherein a fourth conversion gain signal is configured to be read out from the pixel circuit in response to the charge photogenerated by the second photodiode that is transferred to the second floating diffusion node and the first floating diffusion node and in response to the excess charge photogenerated by the second photodiode that has overflowed to the capacitor in response to the bright incident light, wherein the dual floating diffusion transistor, the capacitor readout transistor and the anti-blooming transistor are configured to be turned on when the fourth conversion gain signal is read out from the pixel circuit.

16. An imaging system comprising: A pixel array comprising a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits comprises: a first photodiode and a second photodiode, wherein the first and second photodiodes photogenerate charge in response to incident light; a first transfer transistor coupled to the first photodiode; a first floating diffusion node coupled to the first transfer transistor; a second transfer transistor coupled to the second photodiode; a second floating diffusion node coupled to the second transfer transistor; a dual floating diffusion transistor coupled between the first and second floating diffusion nodes; an overflow transistor coupled to the second photodiode; a capacitor coupled between a voltage source and the overflow transistor; a capacitor readout transistor coupled between the overflow transistor and the second floating diffusion node; and an anti-blooming transistor coupled between the first photodiode and a power line; a control circuitry coupled to the pixel array to control operation of the pixel array, wherein the control circuitry is configured to (a) selectively turn on the anti-blooming transistor to disable the first photodiode during readout of the second photodiode, and (b) selectively turn off the anti-blooming transistor for readout of the first photodiode so that charge stored in the first photodiode can be read out during readout of the first photodiode; and Readout circuitry is coupled to the pixel array to read out image data from the plurality of pixel circuits.

17. The imaging system of claim 16, further comprising functional logic coupled to the readout circuitry to store the image data from each of the plurality of pixel circuits.

18. The imaging system of claim 16, wherein each of the plurality of pixel circuits further comprises: a source follower transistor having a gate coupled to the first floating diffusion node; and A row select transistor is coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between the power line and a bit line.

19. The imaging system of claim 18, wherein each of the plurality of pixel circuits further comprises a reset transistor coupled between the power line and the first floating diffusion node.

20. The imaging system of claim 18, wherein each of the plurality of pixel circuits further comprises a reset transistor coupled between the voltage source and the second floating diffusion node.

21. The imaging system of claim 20, further comprising at least a first wafer and a second wafer stacked with the first wafer.

22. The imaging system of claim 21 , further comprising: a first wafer; and a second chip stacked with the first chip, wherein the overflow transistor of each of the multiple pixel circuits is included in the first chip, wherein the capacitor of each of the multiple pixel circuits is included in the second chip, and wherein the overflow transistor of each of the multiple pixel circuits is coupled to the capacitor of each of the multiple pixel circuits through a corresponding first hybrid junction between the first chip and the second chip.

23. The imaging system of claim 22, wherein the first and second photodiodes, the first and second transfer transistors, the first floating diffusion node, and the antiblooming transistor of the each of the plurality of pixel circuits are included in the first wafer.

24. The imaging system according to claim 23, wherein the capacitor readout transistor of the each of the plurality of pixel circuits is included in the first die, wherein the capacitor readout transistor of the each of the plurality of pixel circuits is coupled to the capacitor of the each of the plurality of pixel circuits through the respective first hybrid junction between the first die and the second die, The reset transistor, the second floating diffusion node, the double floating diffusion transistor, the source follower transistor, and the row select transistor of each of the plurality of pixel circuits are further included in the first chip.

25. The imaging system according to claim 23, wherein the capacitor readout transistor, the reset transistor, the second floating diffusion node, the double floating diffusion transistor, the source follower transistor, and the row select transistor of each of the plurality of pixel circuits are included in the second die, wherein the first floating diffusion node of the each of the plurality of pixel circuits is coupled to the gate of the source follower transistor and the double floating diffusion transistor of the each of the plurality of pixel circuits through a respective second hybrid junction between the first die and the second die, wherein the second transfer transistor of the each of the plurality of pixel circuits is coupled to the second floating diffusion node of the each of the plurality of pixel circuits through a corresponding third hybrid junction between the first die and the second die.

26. The imaging system of claim 16, wherein the first photodiode of each of the plurality of pixel circuits has a first light sensitivity and the second photodiode of each of the plurality of pixel circuits has a second light sensitivity, wherein the first light sensitivity is greater than the second light sensitivity.

27. An imaging system according to claim 16, wherein a first conversion gain signal is configured to be read out from each of the multiple pixel circuits in response to the charge photogenerated by the first photodiode and transferred to the first floating diffusion node of each of the multiple pixel circuits, and wherein the dual floating diffusion transistor of each of the multiple pixel circuits is configured to be turned off when the first conversion gain signal is read out from each of the multiple pixel circuits.

28. An imaging system according to claim 26, wherein a second conversion gain signal is configured to be read out from each of the multiple pixel circuits in response to the charge photogenerated by the first photodiode and transferred to the first floating diffusion node and the second floating diffusion node of each of the multiple pixel circuits, wherein the dual floating diffusion transistor of each of the multiple pixel circuits is configured to be turned on and the capacitor readout transistor of each of the multiple pixel circuits is configured to be turned off when the second conversion gain signal is read out from each of the multiple pixel circuits.

29. The imaging system of claim 26 , wherein a third conversion gain signal is configured to be read out from the pixel circuit in response to the charge photogenerated by the second photodiode and transferred to the second floating diffusion node and the first floating diffusion node, wherein the dual floating diffusion transistor and the anti-blooming transistor are configured to be turned on and the capacitor readout transistor is configured to be turned off when the third conversion gain signal is read out from the pixel circuit.

30. The imaging system of claim 16 , wherein excess charge photogenerated by the second photodiode of each of the plurality of pixel circuits in response to bright incident light is configured to overflow from the second photodiode of each of the plurality of pixel circuits to the capacitor of each of the plurality of pixel circuits through the overflow transistor of each of the plurality of pixel circuits.

31. An imaging system according to claim 30, wherein a fourth conversion gain signal is configured to be read out from each of the multiple pixel circuits in response to the charge photogenerated by the second photodiode of each of the multiple pixel circuits and transferred to the second floating diffusion node and the first floating diffusion node of each of the multiple pixel circuits and in response to the excess charge photogenerated by the second photodiode of each of the multiple pixel circuits and overflowing to the capacitor of each of the multiple pixel circuits in response to the bright incident light, wherein the dual floating diffusion transistor, the capacitor readout transistor and the anti-blooming transistor of each of the multiple pixel circuits are configured to be turned on to disable the first photodiode when the fourth conversion gain signal is read out from each of the multiple pixel circuits.

32. An imaging system according to claim 31, wherein a third conversion gain signal is configured to be read out from the pixel circuit in response to the charge photogenerated by the second photodiode and transferred to the second floating diffusion node and the first floating diffusion node, wherein the dual floating diffusion transistor and the anti-blooming transistor are configured to be turned on and the capacitor readout transistor is configured to be turned off when the third conversion gain signal is read out from the pixel circuit, and wherein the image data of each of the plurality of pixel circuits is generated based on the third and fourth conversion gain signals.

Images