Embedded circuit board and preparation method thereof

Abstract

The present application provides an embedded circuit board and a preparation method thereof, the preparation method comprising: forming a first circuit layer on at least one side of a conductive adhesive layer; pressing an insulating layer onto the first circuit layer so that the first circuit layer is embedded in the insulating layer; forming a second circuit layer on a side of the insulating layer away from the first circuit layer; separating the first circuit layer from the conductive adhesive layer to obtain the embedded circuit board. The preparation method of the present application does not require etching of the copper foil layer after the board is separated, so that the surfaces of the first circuit layer and the insulating layer can be flush (without height difference), which can avoid hitting the insulating layer during wiring, thereby improving wiring accuracy and improving the problem of poor wiring.

Description

Technical Field

[0001] The present application relates to a method for preparing an embedded circuit board and an embedded circuit board prepared by the preparation method. Background Art

[0002] Embedded circuit boards have an embedded circuit structure, where the surface traces are buried in the dielectric layer. Figures 1A to 1D Conventional embedded trace substrate (ETS) is usually made by laminating and embedding the carrier board on both sides. Figure 1A , a copper foil layer 20' is formed on opposite sides of the carrier board 10'. Then, refer to Figure 1B , roughening the copper foil layer 20' to form a rough surface 201' (copper teeth), then forming an anti-corrosion film (not shown) on the rough surface 201', and then performing exposure, development, etching, and removing the anti-corrosion film to form an inner layer circuit 30'. Next, please refer to Figure 1C , press the insulating resin layer 40' (dielectric layer) onto the inner circuit 30' so that the inner circuit 30' is buried in the insulating resin layer 40', and then manufacture the outer circuit 50' on the insulating resin layer 40', wherein the copper foil layer 20', the inner circuit 30', the insulating resin layer 40' and the outer circuit 50' constitute the substrate 60', and peel off the two substrates 60' on both sides of the carrier board 10' (also called split board). Finally, please refer to Figure 1D , the copper foil layer 20' and the copper teeth on the substrate 60' are etched away to obtain the embedded circuit board 100'. In order to remove the rough surface 201' (copper teeth), the amount of etching on the copper foil layer 20' will be increased, resulting in a height difference H between the insulating resin layer 40' and the inner layer circuit 30'.

[0003] However, in the subsequent bonding (also known as wire bonding) operation of the client, the height difference H makes it easy for the wire to hit the insulating resin layer 40 ′ (dielectric layer) during bonding, which affects the wire drop rate of the client. Summary of the invention

[0004] In view of this, the present application proposes a method for preparing an embedded circuit board, which can eliminate the height difference between the circuit layer and the insulation layer, thereby improving the wire bonding accuracy and improving the problem of poor wire bonding.

[0005] An embodiment of the present application provides a method for preparing an embedded circuit board, comprising the following steps:

[0006] forming a first circuit layer on at least one side of the conductive adhesive layer;

[0007] Laminating the insulating layer on the first circuit layer so that the first circuit layer is buried in the insulating layer;

[0008] forming a second circuit layer on a side of the insulating layer away from the first circuit layer;

[0009] The first circuit layer is separated from the conductive adhesive layer to obtain the embedded circuit board.

[0010] In one embodiment, the step of "forming a first circuit layer on at least one side of the conductive adhesive layer" includes: forming a first anti-etching film on at least one side of the conductive adhesive layer; patterning the first anti-etching film to form a first mask layer, the first mask layer including a plurality of first gaps; forming a plurality of first routing lines in the plurality of first gaps respectively, removing the first mask layer, and the plurality of first routing lines forming the first circuit layer.

[0011] In one embodiment, before the step of “patterning the first anti-etching film to form a first mask layer”, the step of “forming a first circuit layer on at least one side of the conductive adhesive layer” further includes: exposing the first anti-etching film.

[0012] In one embodiment, the step of "forming a second circuit layer on a side of the insulating layer away from the first circuit layer" includes: forming a seed layer on a side of the insulating layer away from the first circuit layer; forming a blind hole on the seed layer and the insulating layer, the blind hole penetrating the seed layer and the insulating layer and exposing a portion of the first circuit layer; forming a second anti-etching film on a side of the seed layer away from the insulating layer; patterning the second anti-etching film to form a second mask layer, the second mask layer including a plurality of second gaps; forming a plurality of second routings in the plurality of second gaps, respectively, and forming a conductive structure in the blind hole; removing the second mask layer and the seed layer, the plurality of second routings forming the second circuit layer, and the conductive structure electrically connecting the first circuit layer and the second circuit layer.

[0013] In one embodiment, before the step of “patterning the second anti-etching film to form a second mask layer”, the step of “forming a second circuit layer on a side of the insulating layer away from the first circuit layer” further includes: exposing the second anti-etching film.

[0014] In one embodiment, after the step of "separating the first circuit layer from the conductive adhesive layer", the preparation method further comprises the step of performing an appearance inspection on the embedded circuit board using automatic optical inspection.

[0015] In one embodiment, after the step of "performing an appearance inspection on the embedded circuit board using automatic optical inspection", the preparation method further comprises: forming protective layers on the outer sides of the first circuit layer and the second circuit layer respectively.

[0016] In one embodiment, the insulating layer is a prepreg or a resin layer, and the material of the resin layer includes polypropylene.

[0017] Another aspect of the present application provides an embedded circuit board, the embedded circuit board comprising a first circuit layer, an insulating layer, and a second circuit layer. The first circuit layer is embedded in the insulating layer, and the surface of the insulating layer close to the first circuit layer is flush with the surface of the first circuit layer exposed outside the insulating layer. The second circuit layer is arranged on a side of the insulating layer away from the first circuit layer.

[0018] In one embodiment, a protective layer is provided on a side of the first circuit layer facing away from the insulating layer, and a protective layer is provided on a side of the second circuit layer facing away from the insulating layer.

[0019] The embedded circuit board and its preparation method of the present application use a conductive adhesive layer to replace the copper foil layer in the traditional preparation method as the conductor layer, and then form the first circuit layer and the second circuit layer through processes such as copper electroplating, which can increase the line width and have good conduction performance. Since there is no need to etch the copper foil layer after the board is divided, the surface of the first circuit layer and the insulating layer can be made flush (without height difference), which can avoid hitting the insulating layer during wiring, thereby improving the wiring accuracy and improving the problem of poor wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figures 1A to 1D The present invention is a schematic cross-sectional diagram of the process of preparing an embedded circuit board according to the prior art.

[0021] FIG. 2A to FIG. 2C A cross-sectional schematic diagram of forming a first circuit layer on at least one side of a conductive adhesive layer provided in one embodiment of the present application.

[0022] Figure 3 For the general Figure 2C The cross-sectional diagram of the first circuit layer and the insulating layer after being pressed together is shown.

[0023] FIG. 4A to FIG. 4E For Figure 3 The cross-sectional view of the second wiring layer formed on one side of the insulating layer is shown.

[0024] Figure 5 For the general Figure 4E A schematic cross-sectional view of the device after the first circuit layer and the conductive adhesive layer are separated.

[0025] Figure 6 For Figure 5 The schematic cross-sectional view of the embedded circuit board shown is a schematic diagram of a protective layer disposed on the outer side of the embedded circuit board.

[0026] Main component symbols

[0027] Embedded circuit board 100, 100'

[0028] Loading plate 10'

[0029] Copper foil layer 20'

[0030] Rough surface 201'

[0031] Inner line 30'

[0032] Insulating resin layer 40'

[0033] Outer line 50'

[0034] Baseboard 60'

[0035] Height difference H

[0036] Conductive adhesive layer 10

[0037] First resist film 101

[0038] First mask layer 102

[0039] First gap 103

[0040] First line 104

[0041] First circuit layer 20

[0042] Insulation layer 30

[0043] The second circuit layer 40

[0044] Seed layer 401

[0045] Blind hole 402

[0046] Second resist film 403

[0047] Second mask layer 404

[0048] Second gap 405

[0049] Second routing 406

[0050] Conductive structure 407

[0051] Protective layer 50

[0052] The following specific implementation manner will further illustrate the embodiments of the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the technical field of the present application. The terms used herein are only for the purpose of describing specific implementation methods and are not intended to limit the present application embodiments.

[0054] It will be understood that when a layer is referred to as being “on” another layer, it can be directly on the other layer or intervening layers may be present therebetween. On the contrary, when a layer is referred to as being “directly on” another layer, there are no intervening layers.

[0055] In addition, the descriptions of "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0056] Here, the embodiments of the present application are described with reference to the cross-sectional views, which are schematic diagrams of the idealized embodiments (and intermediate configurations) of the present application. Thus, it is foreseeable that the shapes of the diagrams are different due to manufacturing processes and / or tolerances. Therefore, the embodiments of the present application should not be interpreted as being limited to the specific shapes of the regions illustrated here, but should include deviations in shapes such as those produced due to manufacturing. The regions shown in the figures are themselves only schematic, and their shapes are not intended to illustrate the actual shapes of the devices, and are not intended to limit the scope of the present application.

[0057] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0058] See also Figures 2A to 6 In one embodiment of the present application, a method for preparing an embedded circuit board 100 is provided, which comprises the following steps:

[0059] Step S10, see FIG. 2A to FIG. 2C , which shows the step of forming the first circuit layer 20 on at least one side of the conductive adhesive layer 10 in one embodiment of the present application. In this embodiment, a first circuit layer 20 is formed on two opposite sides of the conductive adhesive layer 10, that is, two first circuit layers 20 are formed.

[0060] like Figure 2A As shown, a first anti-etching film 101 is formed on at least one side of the conductive adhesive layer 10. In this embodiment, two layers of the first anti-etching film 101 are pressed onto opposite sides of the conductive adhesive layer 10, respectively.

[0061] See also Figure 2B, patterning the first resist film 101 to form a first mask layer 102, wherein the first mask layer 102 includes a plurality of first gaps 103. In this embodiment, a laser beam is used to pattern the first resist film 101. The laser beam can directly ablate the first resist film 101 to remove a portion of the first resist film 101, thereby forming a first mask layer 102 having a plurality of first gaps 103. The plurality of first gaps 103 can expose a portion of the surface of the conductive adhesive layer 10.

[0062] Furthermore, in some embodiments, before the step of patterning the first resist film 101 to form the first mask layer 102, the first resist film 101 may be exposed. Exposure may change the physical and chemical properties of the first resist film 101 to increase the bonding force of the first resist film 101 on the conductive adhesive layer 10. It is understood that the method for preparing the embedded circuit board 100 of the present embodiment may also omit the step of exposing the first resist film 101, that is, after forming the first resist film 101, the first resist film 101 may be directly patterned without exposing the first resist film 101. That is, the above-mentioned step of exposing the first resist film 101 is a selective step, not a necessary step.

[0063] See also Figure 2C , a plurality of first wirings 104 are respectively formed in the plurality of first gaps 103, and the first mask layer 102 is removed, so that the plurality of first wirings 104 form a first circuit layer 20. In this embodiment, the plurality of first wirings 104 are formed by electroplating (for example, but not limited to copper plating) to form the first circuit layer 20.

[0064] Step S20, see Figure 3 , which shows a cross-sectional schematic diagram of an embodiment of the present application after laminating the insulating layer 30 and the first circuit layer 20. After laminating, the first circuit layer 20 is buried in the insulating layer 30, that is, the insulating layer 30 completely covers the first circuit layer 20.

[0065] Furthermore, in some embodiments, the insulating layer 30 may be, but not limited to, a prepreg or a resin layer. The material of the resin layer may be, but not limited to, polypropylene (PP). In this embodiment, the material of the insulating layer is polypropylene.

[0066] Step S30, see FIG. 4A to FIG. 4E , which shows a cross-sectional schematic diagram of forming a second circuit layer 40 on a side of the insulating layer 30 away from the first circuit layer 20 according to an embodiment of the present application.

[0067] like Figure 4AAs shown, a seed layer 401 is formed on the side of the insulating layer 30 away from the first circuit layer 20. In this embodiment, the seed layer is formed by chemical copper plating. Of course, the seed layer made of copper or other metal materials can also be formed by other known processes such as sputtering and electroplating. In addition, the chemical copper plating process generally includes the steps of: fluffing, degumming, neutralization, acid immersion, cleaning, micro-etching, pre-preg, activation, reduction, chemical copper plating, water washing, etc.

[0068] See also Figure 4B , a blind hole 402 may be formed on the seed layer 401 and the insulating layer 30 by, but not limited to, mechanical drilling or laser drilling. The blind hole 402 penetrates the seed layer 401 and the insulating layer 30, and exposes a portion of the first circuit layer 20. The number of the blind holes 402 may be adjusted according to actual needs, and the present application does not impose any limitation thereto.

[0069] See also Figure 4C A second anti-etching film 403 is formed on a side of the seed layer 401 away from the insulating layer 30 .

[0070] See also Figure 4D , patterning the second resist film 403 to form a second mask layer 404, the second mask layer 404 including a plurality of second gaps 405. In this embodiment, a laser beam is used to pattern the second resist film 403. The laser beam can directly ablate the second resist film 403 to remove a portion of the second resist film 403, thereby forming a second mask layer 404 having a plurality of second gaps 405. The plurality of second gaps 405 can expose a portion of the surface of the seed layer 401. The blind hole 402 is exposed outside the second mask layer 404.

[0071] Furthermore, in some embodiments, before the step of patterning the second resist film 403 to form the second mask layer 404, the second resist film 403 may be exposed. Exposure may change the physical and chemical properties of the second resist film 403 to increase the bonding force of the second resist film 403 attached to the seed layer 401. It is understood that the step of exposing the second resist film 403 may be omitted in this embodiment, that is, after forming the second resist film 403, the second resist film 403 may be directly patterned without exposing the second resist film 403. That is, the above-mentioned step of exposing the second resist film 403 is a selective step, not a necessary step.

[0072] See also Figure 4E, a plurality of second traces 406 are respectively formed in the plurality of second gaps 405, and a conductive structure 407 is formed in the blind hole 402. The second mask layer 404 and the seed layer 401 are removed, and the plurality of second traces 406 form the second circuit layer 40, and the conductive structure 407 electrically connects the first circuit layer 20 and the second circuit layer 40. In this embodiment, the plurality of second traces 406 and the conductive structure 407 are formed by electroplating (for example, but not limited to copper plating), thereby forming the second circuit layer 40. The conductive structure 407 is a conductive hole. In other embodiments, the conductive structure 407 may be a conductive column.

[0073] Furthermore, in some embodiments, the seed layer 401 may be removed by flash etching. The flash etching method mainly controls parameters such as etching time to quickly remove the seed layer 401 to reduce excessive corrosion of the second circuit layer 40. The specific process is a conventional technical means in the art and will not be described in detail here.

[0074] Step S40, see Figure 5 , the first circuit layer 20 is separated from the conductive adhesive layer 10, and the first circuit layer 20, the insulating layer 30 and the second circuit layer 40 form an embedded circuit board 100. The first circuit layer 20 is embedded in the insulating layer 30, and the surface of the insulating layer 30 close to the first circuit layer 20 is flush with the surface of the first circuit layer 20 exposed outside the insulating layer 30 (there is no height difference between the two), and the second circuit layer 40 is arranged on the side of the insulating layer 30 away from the first circuit layer 20.

[0075] Further, in some embodiments, after obtaining Figure 5 After the embedded circuit board 100 is shown, an automatic optical inspection (Automatic Optical Inspection, AOI) can be used to perform appearance inspection on the embedded circuit board to replace manual visual inspection, thereby improving efficiency and accuracy.

[0076] See also Figure 6 In some embodiments, for the embedded circuit board 100 that has passed the appearance inspection, a protective layer 50 may be provided on the outer side of the first circuit layer 20 and the second circuit layer 40 (i.e., the side away from the insulating layer 30). The protective layer 50 is used to protect the first circuit layer 20 and the second circuit layer 40 from being invaded by external water vapor or scratched by foreign objects. In this embodiment, the protective layer 50 is a solder mask. In other embodiments, the protective layer 50 may also be a cover-lay (CVL).

[0077] The embedded circuit board 100 and its preparation method of the present application use a conductive adhesive layer 10 to replace the copper foil layer 20' in the traditional preparation method as a conductor layer, and then form a first circuit layer 20 and a second circuit layer 40 through processes such as copper electroplating, which can increase the line width and have good conduction performance. Since there is no need to etch the copper foil layer 20' after the board is separated, the surface of the first circuit layer 20 and the insulating layer 30 can be made flush (without height difference), which can avoid hitting the insulating layer during wire bonding, thereby improving the wire bonding accuracy and improving the problem of poor wire bonding.

[0078] The above descriptions are some specific implementations of the present application, but they are not limited to these implementations in actual application. For ordinary technicians in this field, other variations and changes made according to the technical concept of the present application should all fall within the protection scope of the present application.

Claims

1. A method for preparing an embedded circuit board, characterized in that: The steps include: forming a first anti-etching film on at least one side of the conductive adhesive layer; patterning the first resist film to form a first mask layer, wherein the first mask layer includes a plurality of first gaps; Forming a plurality of first wirings in the plurality of first gaps respectively by electroplating, removing the first mask layer, and forming a first circuit layer by the plurality of first wirings; Laminating the insulating layer on the first circuit layer so that the first circuit layer is buried in the insulating layer; forming a second circuit layer on a side of the insulating layer away from the first circuit layer; The first circuit layer is separated from the conductive adhesive layer to obtain the embedded circuit board; wherein the surface of the insulating layer away from the second circuit layer is flush with the surface of the first circuit layer away from the second circuit layer.

2. The method for preparing an embedded circuit board according to claim 1, characterized in that: Before the step of “patterning the first anti-etching film to form a first mask layer”, the step of “forming a first circuit layer on at least one side of the conductive adhesive layer” further includes: exposing the first anti-etching film.

3. The method for preparing an embedded circuit board according to claim 1, characterized in that: The step of “forming a second circuit layer on a side of the insulating layer away from the first circuit layer” comprises: forming a seed layer on a side of the insulating layer away from the first wiring layer; forming a blind hole on the seed layer and the insulating layer, wherein the blind hole penetrates the seed layer and the insulating layer and exposes a portion of the first circuit layer; forming a second anti-etching film on a side of the seed layer away from the insulating layer; patterning the second resist film to form a second mask layer, wherein the second mask layer includes a plurality of second gaps; forming a plurality of second wirings in each of the plurality of second gaps, and forming a conductive structure in the blind hole; The second mask layer and the seed layer are removed, a plurality of the second wirings form the second circuit layer, and the conductive structure electrically connects the first circuit layer and the second circuit layer.

4. The method for preparing an embedded circuit board according to claim 3, characterized in that: Before the step of “patterning the second anti-etching film to form a second mask layer”, the step of “forming a second circuit layer on a side of the insulating layer away from the first circuit layer” further includes: exposing the second anti-etching film.

5. The method for preparing an embedded circuit board according to claim 1, characterized in that: After the step of "separating the first circuit layer from the conductive adhesive layer", the preparation method further includes the step of performing appearance inspection on the embedded circuit board using automatic optical inspection.

6. The method for preparing an embedded circuit board according to claim 5, characterized in that: After the step of "performing an appearance inspection on the embedded circuit board using automatic optical inspection", the preparation method further includes: forming protective layers on the outer sides of the first circuit layer and the second circuit layer respectively.

7. The method for preparing an embedded circuit board according to claim 1, characterized in that: The insulating layer is a prepreg or a resin layer, and the material of the resin layer includes polypropylene.

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