Methods, electronic devices, and storage media for saving and reading waveform data

Abstract

The embodiment of the present application provides a method, electronic device and storage medium for saving and reading waveform data. The saving method includes: obtaining a description of a logic system design; determining the necessary signals and secondary signals of the logic system design according to the logic system design, wherein there is a mapping relationship between the secondary signals and the necessary signals; simulating the logic system design to save the waveform data of the necessary signals as a first database; saving the mapping relationship between the secondary signals and the necessary signals as a second database; and mapping the first database and the second database to the waveform database of the logic system design.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer software technology, and in particular to a method for storing and reading waveform data, an electronic device, and a storage medium. Background Art

[0002] With the development of electronic technology, logic system design (e.g., chip design) has been widely used. The debugging of logic system design usually involves the debugging of simulation waveforms. For example, for a logic system design, a simulation waveform diagram of multiple signals within a certain period of time can be obtained through a simulation tool. The simulation waveform is stored as a waveform database, and the waveform database can be read by a debugging tool to reproduce the simulation waveform, and the debugging work of the logic system design is carried out accordingly.

[0003] As the complexity of chip design increases, the size of waveform data is also increasing. During debugging, waveform data needs to be frequently read and displayed based on the waveform data. Excessively large waveform data makes it difficult and time-consuming to save and read waveform data. Summary of the invention

[0004] The first aspect of the present application provides a method for saving waveform data. The method includes: obtaining a description of a logic system design; determining the necessary signals and secondary signals of the logic system design according to the logic system design, wherein there is a mapping relationship between the secondary signals and the necessary signals; simulating the logic system design to save the waveform data of the necessary signals as a first database; saving the mapping relationship between the secondary signals and the necessary signals as a second database; and mapping the first database and the second database to the waveform database of the logic system design.

[0005] The second aspect of the present application provides a method for reading waveform data from a waveform database, wherein the waveform database includes a first database storing waveform data of necessary signals of a logic system design and a second database storing mapping relationships between secondary signals of the logic system design and the necessary signals. The method includes: receiving a request to read waveform data of a first signal of the logic system design in a given time period, the first signal being the secondary signal; in response to the first signal being the secondary signal, obtaining a first mapping relationship and a first necessary signal corresponding to the secondary signal from the second database; reading waveform data of the first necessary signal in the given time period from the first database; and determining waveform data of the first signal in the given time period based on the first mapping relationship and the waveform data of the first necessary signal in the given time period.

[0006] The third aspect of the present application provides an electronic device, which includes a memory for storing a group of instructions and at least one processor configured to execute the group of instructions so that the electronic device executes the method described in the first aspect or the second aspect.

[0007] A fourth aspect of the present application provides a non-transitory computer-readable storage medium, which stores a set of instructions for a computer, and the set of instructions is used to cause the computer to perform the method described in the first aspect or the second aspect when executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A schematic diagram of a host according to an embodiment of the present application is shown.

[0010] Figure 2 A schematic diagram of a simulation tool and a debugging tool according to an embodiment of the present application is shown.

[0011] Figure 3 An exemplary design to be tested according to an embodiment of the present application is shown.

[0012] Figure 4 A schematic diagram of saving waveform data according to an embodiment of the present application is shown.

[0013] Figure 5 A schematic diagram of reading waveform data from a waveform database according to an embodiment of the present application is shown.

[0014] Figure 6 A flow chart of a method for storing waveform data according to an embodiment of the present application is shown.

[0015] Figure 7 A flow chart of a method for reading waveform data from a waveform database according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0017] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0018] Simulation testing is to apply various stimuli to the logic system design on the host running the simulation test system to detect whether the logic system design can achieve the predetermined functions.

[0019] Figure 1 FIG. 1 is a schematic diagram of a host 100 according to an embodiment of the present application. The host 100 may be an electronic device running a simulation system. Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other in communication within the host through the bus 110.

[0020] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0021] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). In some embodiments, the simulation test system for simulation test design may be a computer program stored in the memory 104. Figure 1As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method of starting software according to functions of the present application) and data to be processed (e.g., the memory may store temporary codes generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0022] The network interface 106 can be configured to provide communication with other external devices to the host 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC) etc.), a cellular network, the Internet or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0023] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0024] The bus 110 may be configured to transmit information between various components of the host 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (e.g., a USB port, a PCI-E bus), etc.

[0025] It should be noted that, although the above host architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the host architecture may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above host architecture may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0026] Figure 2The schematic diagram of the simulation tool 202 and the debugging tool 200 according to the embodiment of the present application is shown. The simulation tool 202 and the debugging tool 200 may be computer programs running on the host 100.

[0027] In the field of chip design, a design can usually be simulated using a simulation tool, such as the GalaxSim simulation tool produced by Xinhuazhang Technology Co., Ltd. Figure 2 The exemplary simulation tool 202 shown may include a compiler 120 and a simulator 220. The compiler 120 may compile a design (e.g., a logic system design 210) into a target code 204, and the simulator 220 may perform simulation according to the target code 204 and output a simulation result 206. For example, the simulation tool 202 may output the simulation result (e.g., a simulation waveform) via Figure 1 The peripheral interface 108 is output to an output device (for example, displayed on a display). The logic system design 210 may include a design to be tested 210a and a verification environment 210b. The verification environment 210b may also be called a testbench. For example, the verification environment 210b may be a UVM environment.

[0028] The simulation result 206 (usually waveform data) can also be stored in the form of a waveform database. The waveform database storing the waveform data can also be called a waveform file.

[0029] The debugging tool 200 can also read the simulation result 206. The debugging tool 200 can be, for example, the Fusion Debug debugging tool produced by Xinhuazhang Technology Co., Ltd. For example, the debugging tool 200 can read the simulation result 206 stored in a waveform file, and generate a corresponding simulation waveform for debugging. The debugging tool 200 can also read the description of the logic system design 210 (usually SystemVerilog and Verilog code) and display it to the user. The debugging tool 200 can also generate various graphical interfaces (for example: debugging window) to facilitate the user's debugging work. The user can issue a debugging command to the debugging tool 200 (for example, run the logic system design 210 to a certain moment), and the debugging tool 200 applies the debugging command to the simulation tool 202 to execute accordingly. The debugging tool 200 can also read a log file. The log file may include various information of the simulation process, including information of simulation errors, line numbers of errors, time when simulation errors occur, etc.

[0030] It is understandable that, in addition to being connected to the simulation tool 202 , the debugging tool 200 may also be connected to a hardware emulator.

[0031] Before the logic system design is put into actual operation, the compiled logic system design needs to be run and debugged using the aforementioned debugging tool 200. The debugging tool 200 can receive user instructions from the user and make corresponding debugging actions. In some embodiments, the user can issue user instructions by clicking the mouse in the graphical interface; in some embodiments, the user can enter a command line in the command line interface to issue a user instruction. If an abnormality is found in the logic system design during the debugging process, it is necessary to further diagnose the abnormality found, find out the cause and the specific source location of the abnormality, and make corrections to ensure the robustness of the logic system design.

[0032] As mentioned above, simulation of large-scale chip design generates large-scale waveform data, and the reading and writing of large-scale waveform data is usually time-consuming. Usually, the waveform data generated by simulation is stored on the hard disk. When the waveform needs to be viewed, the host reads it into the memory and renders the waveform according to the waveform data. Users often choose to render waveforms of signals in different time periods, so users have the need to quickly read and generate waveform graphs. This is in conflict with the slow reading of large-scale waveform data.

[0033] Therefore, how to efficiently read and write waveform data is a technical problem that needs to be solved urgently.

[0034] The inventor of the present application proposes a method for storing and reading waveforms, an electronic device, and a storage medium to compress the size of waveform data, thereby fundamentally improving the reading and writing speed of waveform data.

[0035] A logic system design usually includes a design to be tested and a testbench for providing stimulus to the design to be tested and evaluating the design to be tested. The design to be tested usually includes multiple modules and multiple signals corresponding to the multiple modules. A module can be a gate circuit or a functional module composed of multiple gate circuits.

[0036] Figure 3 An exemplary design under test 300 according to an embodiment of the present application is shown.

[0037] like Figure 3 As shown, the design under test 300 includes multiple modules 302-308. The design under test 300 includes multiple signals a, b, c, d, e, f, g, and h. Among them, signals a and b are input signals of module 302 (for example, an AND gate); signals c and d are input signals of module 304 (for example, an OR gate); signals e and f are inputs of module 306 (for example, an AND gate), and are also outputs of modules 302 and 304 respectively; signal g is the output of module 306 and is also the input of module 308 (for example, a NOT gate); signal h is the output of module 308.

[0038] It can be seen that the values ​​of signals e, f, g, and h can be calculated based on the values ​​of signals a and b and the circuit structure. For example, e = a&b, g = (a&b) and (c or d), or h = NOT ((a&b) and (c or d)). In other words, there is a mapping relationship between signals e, g, and h and signals a and b. In this example, it is a&b or other more complex mapping relationships (for example, (a&b) and (c or d), or NOT ((a&b) and (c or d))).

[0039] Therefore, signals that can be calculated depending on the values ​​of other signals and the circuit structure can be called secondary signals, while signals that stimulate the operation of the entire circuit can be called essential signals. Usually, essential signals can be the output of a flip-flop or the output of a memory in a logic system design. The circuit structure of a logic system design can usually be obtained from the netlist of the logic system design.

[0040] Therefore, if the waveform data (e.g., changes in signal values) of the primary signal (e.g., signals a and b) during the entire simulation can be saved, and then combined with the mapping relationship between the primary signal and the secondary signal (e.g., the operator &), the waveform data of the secondary signal (e.g., signal e) can be restored.

[0041] Figure 4 A schematic diagram of saving waveform data according to an embodiment of the present application is shown.

[0042] like Figure 4 As shown, the simulation tool 202 can read the description of the logic system design 210 (e.g., the netlist of the logic system design 210) and simulate the design to be tested 210a, thereby generating a simulation result 206. The simulation result 206 can include a database 402 storing waveform data of the main signal and a database 404 storing the mapping relationship between the secondary signal and the necessary signal. It can be understood that the mapping relationship in the database 404 also includes all the secondary signals.

[0043] The mapping relationship can be obtained from the netlist of the logic system design. In other words, the mapping relationship can actually be obtained in the compilation stage of the logic system design 210, and there is no need to run a simulation.

[0044] Database 402 and database 404 can be mapped to waveform database 410 of logic system design 210. Waveform database 410 is a virtual database and does not actually exist. In some embodiments, virtual file technology can be used to implement the above mapping. By using virtual file technology, the database that the user can see and operate is waveform database 410, but the user's operation on waveform database 410 will be decomposed and applied to database 402 and / or 404 accordingly, and the results fed back from database 402 and / or 404 can be provided to the user via the interface of waveform database 410.

[0045] Thus, during the simulation process, the simulation tool 202 can only save the values ​​of the main signals during the simulation (e.g., value changes), which reduces the burden on the simulation tool 202 during the simulation, reduces the amount of data generated, and improves the simulation speed and reduces the size of the waveform database.

[0046] Figure 5 A schematic diagram 500 of reading waveform data from a waveform database according to an embodiment of the present application is shown.

[0047] The debugging tool 200 may receive a signal (eg, Figure 3 e) a request 502 for waveform data of a secondary signal over a given time period.

[0048] By using virtual file technology, waveform database 410 can determine that request 502 should be distributed to database 404. Database 404 returns the query that primary signals associated with signal e are a and b, and reads mapping relationship 504 between primary signals a and b and secondary signal e (eg, e=a&b). Figure 5 The mapping relationship 504 is shown in the form of a circuit diagram. It can be understood that, in fact, the mapping relationship is usually stored in the form of an expression.

[0049] The waveform database 410 may further query the waveform data 506 (eg, value changes (vc)) of the main signals a and b within a given time period according to the main signals a and b determined above. Figure 5 The waveform data 506 is shown in the form of a waveform. It can be understood that, in fact, the waveform data is usually stored in a digital form.

[0050] According to the waveform data 506 of the main signals a and b and the mapping relationship 504 between the secondary signal e and the main signals a and b, the debugging tool 200 can determine the waveform data of the signal e in a given time period.

[0051] In some embodiments, when the signal to be read by the request 502 is the main signal, the waveform database 410 can directly apply the request to the waveform database 402 to read the waveform data 508 of the main signal within a given time period. It can be understood that the waveform data 508 is obtained by calculation, which usually consumes certain computing resources and time.

[0052] The calculation method is usually to calculate the value of signal e at each moment based on the values ​​of signals a and b.

[0053] In this way, users do not have to read huge amounts of data to display waveforms. Instead, they can read only the necessary associated signals and then obtain the desired waveforms through calculations, thereby reducing the amount of data required to read for rendering waveforms and improving the running speed of debugging tools.

[0054] Figure 6 FIG. 6 is a flowchart of a method 600 for storing waveform data according to an embodiment of the present application. The method 600 may be Figure 1 The method 600 is executed by the host 100, more specifically, by the simulation tool 202 running on the host 100. The method 600 may include the following steps.

[0055] In step 602, a logical system design (e.g., Figure 4 In some embodiments, the description of the logic system design may be a netlist. The netlist may be used to describe the circuit structure of the logic system design (especially the design to be tested).

[0056] In step 604, necessary signals (e.g., Figure 3 signals a, b, c, d) and secondary signals (e.g. Figure 3 There is a mapping relationship between the secondary signal and the necessary signal. The mapping relationship usually corresponds to the circuit structure of the logic system design. Figure 3 In the description of , this application gives several examples of mapping relationships, which will not be repeated here.

[0057] In some embodiments, the necessary signal includes an output of a flip-flop in the logic system design or an output of a memory in the logic system design, and the value of the secondary signal is computable based on the value of the necessary signal and the netlist.

[0058] In some embodiments, the mapping relationship is determined according to the netlist.

[0059] In step 606, the logic system is simulated to store the waveform data of the necessary signal into a first database (eg, Figure 4The waveform data is usually a value change of a signal.

[0060] In step 608, the mapping relationship between the secondary signal and the necessary signal is saved as a second database (eg, Figure 4 database 404).

[0061] In step 610, the first database and the second database are mapped to the waveform database of the logic system design (eg, Figure 4 database 410).

[0062] Thus, during the simulation process, the simulation tool 202 can only save the values ​​of the main signals during the simulation (e.g., value changes), which reduces the burden on the simulation tool 202 during the simulation, reduces the amount of data generated, and improves the simulation speed and reduces the size of the waveform database.

[0063] Figure 7 A flowchart of a method 700 for reading waveform data from a waveform database according to an embodiment of the present application is shown. The waveform database (e.g., Figure 5 The waveform database 410) includes a first database (e.g., Figure 5 The mapping relationship between the secondary signal of the logic system design and the necessary signal is stored in the second database (for example, Figure 5 The method 700 may be performed by Figure 1 The method 700 is executed by the host 100, more specifically, by the debugging tool 200 running on the host 100. The method 700 may include the following steps.

[0064] At step 702, a first signal (eg, Figure 5 e) a request for waveform data of a signal in a given time period (e.g., Figure 5 Request 502 in ). The first signal is the secondary signal.

[0065] In step 704, in response to the first signal being the secondary signal, a first mapping relationship (eg, Figure 5 504) and the first necessary signal (eg, Figure 5 Signals a and b in ).

[0066] In step 706, the waveform data of the first necessary signal in the given time period is read from the first database (for example, Figure 5 Waveform data 506 in ).

[0067] In step 708, the waveform data of the first signal in the given time period is determined according to the first mapping relationship and the waveform data of the first necessary signal in the given time period (for example, Figure 5 Waveform data 508).

[0068] In some embodiments, the mapping relationship is determined according to a netlist of the logic system design.

[0069] In some embodiments, the necessary signal includes an output of a flip-flop in the logic system design or an output of a memory in the logic system design, and the value of the secondary signal is computable based on the value of the necessary signal and the netlist.

[0070] In this way, users do not have to read huge amounts of data to display waveforms. Instead, they can read only the necessary associated signals and then obtain the desired waveforms through calculations, thereby reducing the amount of data required to read for rendering waveforms and improving the running speed of debugging tools.

[0071] The present application also provides an electronic device. The electronic device may be Figure 1 The electronic device may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device performs methods 600 and 700.

[0072] The embodiment of the present application further provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores a set of computer instructions, and the set of instructions is used to enable the computer to perform methods 600 and 700 when executed.

[0073] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0074] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0075] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0076] This application is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A method for storing waveform data, comprising: Obtain a description of the logical system design; Determining necessary signals and minor signals of the logic system design according to the logic system design, wherein a mapping relationship exists between the minor signals and the necessary signals; Simulating the logic system design to store the waveform data of the necessary signal as a first database; storing the mapping relationship between the secondary signal and the necessary signal as a second database; and Mapping the first database and the second database into a waveform database designed for the logic system; The necessary signal includes an output of a trigger in the logic system design or an output of a memory in the logic system design, and the value of the secondary signal is computable based on the value of the necessary signal and a netlist.

2. The method of claim 1, wherein: The description of the logical system design is a netlist.

3. The method of claim 2, further comprising: The mapping relationship is determined according to the netlist.

4. A method for reading waveform data from a waveform database, wherein: The waveform database includes a first database storing waveform data of necessary signals of the logic system design and a second database storing mapping relationships between secondary signals of the logic system design and the necessary signals, and the method includes: receiving a request for reading waveform data of a first signal of the logic system design in a given time period, the first signal being the secondary signal; In response to the first signal being the secondary signal, acquiring a first mapping relationship and a first necessary signal corresponding to the secondary signal from the second database; Reading the waveform data of the first necessary signal within the given time period from the first database; and Determine the waveform data of the first signal in the given time period according to the first mapping relationship and the waveform data of the first necessary signal in the given time period; The necessary signal includes an output of a trigger in the logic system design or an output of a memory in the logic system design, and the value of the secondary signal is computable based on the value of the necessary signal and a netlist.

5. The method of claim 4, wherein: The mapping relationship is determined according to a netlist of the logic system design.

6. An electronic device, comprising: a memory for storing a set of computer instructions; as well as A processor, configured to execute the computer instructions so that the electronic device executes the method as claimed in any one of claims 1 to 5. 7 . A non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the method according to claim 1 .

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