Array substrate and display panel

Abstract

The present application discloses an array substrate and a display panel. The array substrate includes a base substrate, a first electrode layer, an insulating layer, and a second electrode layer, which are sequentially arranged. The base substrate includes a display area and a non-display area. The first electrode layer includes a first common electrode located in the display area. The second electrode layer includes a plurality of pixel electrodes and a common electrode wiring located in the display area. The plurality of pixel electrodes are spaced apart. The common electrode wiring is arranged between at least two adjacent pixel electrodes. The extension direction of the common electrode wiring is consistent with the extension direction of the edge of the adjacent pixel electrode. The present application arranges a common electrode wiring between at least two adjacent pixel electrodes. When a signal is input, the common electrode wiring reacts with the adjacent pixel electrode to enhance the electric field strength at the edge of the corresponding pixel first electrode, thereby improving the dark lines at the edge of the pixel electrode and improving the transmittance of the array substrate.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] With the gradual development of display technology, the mainstream display technologies include liquid crystal displays, organic semiconductor displays, and quantum dot displays. At the same time, as consumer demand increases, high refresh rates and high image quality are becoming increasingly essential for high-end electronic display products. Liquid crystal display panels, with their advantages of low power consumption and high image quality, are also gaining popularity. However, in existing LCD display panels, the electric field gradually weakens at the edges of the pixel electrodes in the array substrate, causing dark lines to form at the edges. This reduces the overall transmittance of the array substrate, further affecting the display quality of the display panel. Summary of the Invention

[0003] The embodiments of the present application provide an array substrate and a display panel, which can solve the problem of reduced transmittance caused by dark lines at the edges of pixel electrodes of the existing array substrate due to weakening of the electric field.

[0004] An embodiment of the present application provides an array substrate, comprising:

[0005] A base substrate, comprising a display area and a non-display area;

[0006] A first electrode layer is provided on the base substrate, wherein the first electrode layer includes a first common electrode located in the display area;

[0007] an insulating layer, disposed on a side of the first electrode layer facing away from the base substrate;

[0008] A second electrode layer is arranged on a side of the insulating layer away from the first electrode layer, and the second electrode layer includes a plurality of pixel electrodes and a common electrode wiring located in the display area. The plurality of pixel electrodes are arranged at intervals, and the common electrode wiring is arranged between at least two adjacent pixel electrodes, and the extension direction of the common electrode wiring is consistent with the extension direction of the edge of the adjacent pixel electrode.

[0009] Optionally, in some embodiments of the present application, the common electrode wiring is provided between any two adjacent pixel electrodes.

[0010] Optionally, in some embodiments of the present application, the second electrode layer includes a plurality of pixel electrode groups arranged in parallel along a first direction, each of the pixel electrode groups includes a plurality of pixel electrodes arranged in parallel along a second direction, and the second direction forms an angle with the first direction; at least one common electrode line is arranged between two adjacent pixel electrode groups, and the extension direction of the common electrode line is consistent with the extension direction of the edge of the adjacent pixel electrode group.

[0011] Optionally, in some embodiments of the present application, the spacing between the common electrode wiring and the edges of two adjacent pixel electrode groups is equal.

[0012] Optionally, in some embodiments of the present application, the pixel electrode includes a plurality of branch electrodes spaced apart along the first direction, and the extension direction of the branch electrodes is consistent with the extension direction of the common electrode wiring; there is a first spacing between the edge of the pixel electrode group and the adjacent common electrode wiring, and there is a second spacing between two adjacent branch electrodes of the pixel electrode, and the first spacing is equal to the second spacing.

[0013] Optionally, in some embodiments of the present application, the width of the common electrode trace in the multiple first directions is greater than or equal to 4 microns and less than or equal to 5 microns.

[0014] Optionally, in some embodiments of the present application, the array substrate includes a first signal line arranged in the display area, a first opening is opened on the insulating layer at a position corresponding to the first signal line, and the common electrode line is electrically connected to the first signal line through the first opening.

[0015] Optionally, in some embodiments of the present application, the array substrate includes a second signal line arranged in the non-display area, the second signal line is arranged on the same layer as the first signal line, the first electrode layer includes a second common electrode located in the non-display area, the second common electrode is electrically connected to the first common electrode, and the second electrode layer includes a connecting electrode located in the non-display area; a second opening is provided on the insulating layer at a position corresponding to the second signal line, the connecting electrode is electrically connected to the second signal line through the second opening, and a third opening is provided on the insulating layer at a position corresponding to the second common electrode, the connecting electrode is electrically connected to the second common electrode through the third opening.

[0016] Optionally, in some embodiments of the present application, the array substrate further includes a data line arranged in the display area, and the orthographic projection of the common electrode line on the base substrate at least partially overlaps with the orthographic projection of the data line on the base substrate.

[0017] Correspondingly, an embodiment of the present application further provides a display panel, which includes any of the array substrates described above.

[0018] In an embodiment of the present application, an array substrate includes a base substrate, a first electrode layer, an insulating layer, and a second electrode layer, which are sequentially arranged. The base substrate includes a display area and a non-display area. The first electrode layer includes a first common electrode located in the display area. The second electrode layer includes a plurality of pixel electrodes and a common electrode wiring located in the display area. The plurality of pixel electrodes are spaced apart. The common electrode wiring is disposed between at least two adjacent pixel electrodes, and the extension direction of the common electrode wiring is consistent with the extension direction of the edges of the adjacent pixel electrodes. In the present application, by disposing a common electrode wiring between at least two adjacent pixel electrodes, when a signal is input, the common electrode wiring reacts with the adjacent pixel electrodes to enhance the electric field strength at the edges of the corresponding pixel electrodes, thereby improving the dark lines at the edges of the pixel electrodes and improving the transmittance of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 This is a schematic structural diagram of a display area corresponding to an array substrate provided in an embodiment of the present application;

[0021] Figure 2 This is a schematic structural diagram of another array substrate corresponding to a display area provided in an embodiment of the present application;

[0022] Figure 3 This is a schematic structural diagram of a non-display area of ​​an array substrate provided in an embodiment of the present application;

[0023] Figure 4 This is a schematic diagram of the distribution of pixel electrodes of an array substrate provided in an embodiment of the present application;

[0024] Figure 5 This embodiment of the present application provides a Figure 4 Schematic diagram of the enlarged structure of area A in the middle;

[0025] Figure 6 This is a schematic structural diagram of a row of pixel electrodes in an array substrate provided by an embodiment of the present application;

[0026] Figure 7 1 is a comparative schematic diagram of the electric field distribution at the edge of a pixel electrode in an array substrate provided by an embodiment of the present application;

[0027] Figure 8 Schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0028] Description of reference numerals:

[0029]

[0030] DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0032] The embodiments of the present application provide an array substrate and a display panel, which are described in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.

[0033] First, the embodiment of the present application provides an array substrate, such as Figures 1 to 3 As shown, the array substrate 100 includes a base substrate 110, which serves as a supporting structure for the array substrate 100 and is used to support other functional structural layers of the array substrate 100 to ensure the structural stability of the array substrate 100. The base substrate 110 includes a display area S1 and a non-display area S2. The non-display area S2 serves as a signal input area for inputting control signals to the display area S1 to control the image displayed in the display area S1.

[0034] like Figure 1 As shown, the array substrate 100 includes a first electrode layer 140, which is arranged on the base substrate 110. The first electrode layer 140 includes a first common electrode 141 located in the display area S1. The first common electrode 141 is used to couple with the pixel electrode 161 to form an electric field and control the deflection of the liquid crystal to realize the control function of the array substrate 100.

[0035] The array substrate 100 includes an insulating layer 150 , which is arranged on the side of the first electrode layer 140 away from the base substrate 110 . The insulating layer 150 is used to separate the first electrode layer 140 from subsequent functional layers to avoid interference between them, thereby affecting the normal use of the array substrate 100 .

[0036] The array substrate 100 includes a second electrode layer 160, which is disposed on a side of the insulating layer 150 facing away from the first electrode layer 140. The second electrode layer 160 includes a plurality of pixel electrodes 161 located in the display area S1 and a common electrode trace 162. The plurality of pixel electrodes 161 are spaced apart, and the common electrode trace 162 is disposed between at least two adjacent pixel electrodes 161. When a signal is input, the electric field at the edge of the pixel electrodes 161 gradually weakens, resulting in a dark pattern. The formation of the dark pattern directly affects the overall transmittance of the array substrate 100, thereby affecting display quality. By disposing the common electrode trace 162 between two adjacent pixel electrodes 161, when a signal is input, the common electrode trace 162 reacts with the adjacent pixel electrode 161, enhancing the electric field strength at the edge of the corresponding pixel electrode 161. This improves the dark pattern at the edge of the pixel electrode 161 and improves the transmittance of the array substrate 100.

[0037] It should be noted that in the embodiment of the present application, the common electrode wiring 162 and the pixel electrode 161 are arranged in the same film layer, and the common electrode wiring 162 and the first common electrode 141 are arranged in different film layers, but the signals input to the first common electrode 141 and the common electrode wiring 162 are the same, that is, during the use of the array substrate 100, the input signal on the first common electrode 141 is used to control the display mode, and the signal on the common electrode wiring 162 is used to enhance the edge electric field of the adjacent pixel electrode 161 that is originally gradually weakened, so that the same signal can realize two functions, thereby simplifying the signal input method on the array substrate 100.

[0038] Among them, the extension direction of the common electrode wiring 162 is consistent with the extension direction of the edge of the adjacent pixel electrode 161, that is, when a signal is input, the electric field response of the common electrode wiring 162 and the edge of the adjacent pixel electrode 161 can remain consistent in the extension direction, thereby improving the uniformity of the electric field strength change at the edge of the pixel electrode 161, so as to further improve the transmittance of the array substrate 100.

[0039] It should be noted that if Figure 6As shown, the pixel electrode 161 has a first bending region, and the common electrode trace 162 between two adjacent pixel electrodes 161 has a second bending region at a position corresponding to the first bending region, and the structural shape of the second bending region is consistent with the structural shape of the first bending region, that is, the extension direction of the common electrode trace 162 is consistent with the extension direction of the edge of the adjacent pixel electrode 161. It can be understood that the consistent extension direction described in the embodiment of the present application refers to the consistent extension direction of the edge contours of the common electrode trace 162 and the adjacent pixel electrode 161, so that the spacing between the common electrode trace 162 and the adjacent pixel electrode 161 in the extension direction is equal everywhere, so that when a signal is input, the electric field reaction of the common electrode trace 162 and the edge of the adjacent pixel electrode 161 can be consistent in the extension direction, thereby improving the uniformity of the electric field intensity change at the edge of the pixel electrode 161, effectively reducing the dark line area and improving the distribution uniformity of the dark line area, thereby improving the overall transmittance of the array substrate 100.

[0040] In the embodiment of the present application, the array substrate 100 includes a base substrate 110, a first electrode layer 140, an insulating layer 150, and a second electrode layer 160, which are sequentially arranged. The base substrate 110 includes a display area S1 and a non-display area S2. The first electrode layer 140 includes a first common electrode 141 located in the display area S1. The second electrode layer 160 includes a plurality of pixel electrodes 161 and a common electrode trace 162 located in the display area S1. The plurality of pixel electrodes 161 are spaced apart, and the common electrode trace 162 is disposed between at least two adjacent pixel electrodes 161. The common electrode trace 162 extends in the same direction as the edges of the adjacent pixel electrodes 161. In the present application, by disposing the common electrode trace 162 between at least two adjacent pixel electrodes 161, when a signal is input, the common electrode trace 162 reacts with the adjacent pixel electrode 161 to enhance the electric field strength at the edge of the corresponding pixel electrode 161, thereby improving the dark lines at the edge of the pixel electrode 161 and improving the transmittance of the array substrate 100.

[0041] In some embodiments, a common electrode line 162 is arranged between any two adjacent pixel electrodes 161, that is, when multiple pixel electrodes 161 are distributed in an array, the common electrode lines 162 are also distributed in an array into a mesh structure, so that a common electrode line 162 is arranged between every two pixel electrodes 161, so that when a signal is input, the electric field strength of at least two side edges of each pixel electrode 161 can be enhanced, thereby improving the overall dark pattern situation, so as to further improve the transmittance of the array substrate 100.

[0042] Optional, such as Figure 4As shown, the second electrode layer 160 includes a plurality of pixel electrode groups 164 arranged in parallel along a first direction X. Each pixel electrode group 164 includes a plurality of pixel electrodes 161 arranged in parallel along a second direction Y, where the second direction forms an angle with the first direction. In other words, taking the first direction X as the row direction and the second direction Y as the column direction as an example, the plurality of pixel electrodes 161 are arranged in an array, and the plurality of pixel electrodes 161 in each column constitute a pixel electrode group 164, and the plurality of pixel electrode groups 164 are arranged in a row.

[0043] At least one common electrode trace 162 is disposed between two adjacent pixel electrode groups 164, and the extension direction of the common electrode trace 162 is consistent with the extension direction of the edges of the adjacent pixel electrode groups 164. In other words, the common electrode trace 162 is disposed between two adjacent columns of pixel electrodes 161, and the extension direction of the common electrode trace 162 is consistent with the extension direction of the edges of the adjacent columns of pixel electrodes 161. This allows one common electrode trace 162 to simultaneously improve the uniformity of the electric field intensity variation at the edges of an entire adjacent column of pixel electrodes 161, effectively reducing dark streaks at the edges of the entire column of pixel electrodes 161, thereby improving the overall transmittance of the array substrate 100.

[0044] In some embodiments, common electrode traces 162 are provided on two opposite sides of any pixel electrode group 164 in the first direction X. That is, the plurality of pixel electrode groups 164 are treated as a whole, and common electrode traces 162 are provided on two opposite sides of the whole in the first direction X, so as to improve the dark lines at the edge areas of the display area S1 of the array substrate 100 in the first direction X, thereby improving the transmittance of the array substrate 100 and enhancing the display quality.

[0045] It should be noted that the relative placement of the common electrode traces 162 and the pixel electrodes 161 can be adjusted according to actual circumstances and is not particularly limited herein. The common electrode traces 162 can be placed only in areas where dark lines are more obvious, and can be omitted in areas without obvious dark lines. This reduces the number of common electrode traces 162, which can both reduce process complexity and save costs.

[0046] Optionally, the spacing between the common electrode line 162 and the edges of two adjacent pixel electrode groups 164 is equal, that is, the common electrode line 162 is located in the middle area of ​​the gap between the two adjacent pixel electrode groups 164, so that when a signal is input, the electric field reaction between the common electrode line 162 and the two adjacent pixel electrode groups 164 is consistent, thereby improving the uniformity of the electric field strength change at the edge of the pixel electrode group 164, so as to further improve the uniformity of the transmittance of the array substrate 100, and thereby improve the display quality.

[0047] like Figure 6As shown, in some embodiments, the pixel electrode 161 includes a plurality of branch electrodes 1611 spaced apart along a first direction X. The extension direction of the branch electrodes 1611 is consistent with the extension direction of the common electrode trace 162. That is, the distribution direction of the plurality of branch electrodes 1611 of each pixel electrode 161 is consistent with the distribution direction of the plurality of pixel electrode groups 164, and the extension direction of the branch electrodes 1611 is consistent with the extension direction of the edges of the pixel electrode groups 164. The plurality of branch electrodes 1611 are electrically connected to each other, thereby forming a pixel electrode 161.

[0048] Among them, there is a first spacing between the edge of the pixel electrode group 164 and the adjacent common electrode line 162, and there is a second spacing between two adjacent branch electrodes 1611 of the pixel electrode 161, and the first spacing is equal to the second spacing. That is, in the first direction X, the spacing of all gaps is equal. On the one hand, since the common electrode line 162 and the pixel electrode 161 are located in the same film layer and formed using the same mask, setting the spacing of all gaps to be equal helps to simplify the mask design of the second electrode layer 160 and improve production efficiency. On the other hand, if the branch electrodes 1611 and the common electrode line 162 are both regarded as a signal line and the first spacing is set to be equal to the second spacing, the spacing between any two signal lines is equal. When a signal is input, the electric field reaction between any two signal lines is consistent, resulting in a consistent electric field strength distribution. While effectively reducing the dark line area, it can also improve the distribution uniformity of the dark line area, thereby improving the uniformity of the transmittance and enhancing the display quality.

[0049] In other embodiments, Figure 2 As shown, two common electrode traces 162 are arranged between two adjacent pixel electrode groups 164 along the first direction X. When a signal is input, an electric field reaction occurs between the two adjacent pixel electrode groups 164 and their respective adjacent common electrode traces 162, thereby enhancing the originally gradually weakening electric field between the two adjacent pixel electrode groups 164 while avoiding mutual interference, thereby reducing the dark pattern area around the pixel electrode group 164, effectively weakening the transmittance reduction caused by the dark pattern area, and improving display quality.

[0050] In some other embodiments, there is a third spacing between the two common electrode lines 162 between two adjacent pixel electrode groups 164, and the third spacing is equal to the first spacing. That is, the first spacing, the second spacing, and the third spacing are all equal, that is, in the first direction X, the spacings of all gaps are equal.

[0051] On the one hand, since the common electrode line 162 and the pixel electrode 161 are located in the same film layer and are formed using the same mask, setting the spacing of all gaps to be equal helps to simplify the mask design of the second electrode layer 160 and improve production efficiency; on the other hand, if the branch electrode 1611 and the common electrode line 162 are both regarded as a signal line, and the first spacing, the second spacing and the third spacing are set to be equal, the spacing between any two signal lines is equal. When the signal is input, the electric field reaction between any two signal lines is consistent, so that the electric field strength distribution is consistent, which can effectively reduce the dark line area while improving the distribution uniformity of the dark line area, thereby improving the uniformity of the transmittance and enhancing the display quality.

[0052] Optionally, when manufacturing the common electrode trace 162, the width of the common electrode trace 162 in the first direction X can be set to be greater than or equal to 4 microns and less than or equal to 5 microns. If the width of the common electrode trace 162 in the first direction X is too small, the precision requirements of the common electrode trace 162 manufacturing process will be increased, increasing the manufacturing difficulty and cost; if the width of the common electrode trace 162 in the first direction X is too large, the spacing between the common electrode trace 162 and the adjacent pixel electrode group 164 will be too small, thereby increasing the risk of contact between the common electrode trace 162 and the adjacent pixel electrode group 164, and being detrimental to the electric field reaction between the common electrode trace 162 and the adjacent pixel electrode group 164.

[0053] During the actual manufacturing process, the width of the common electrode trace 162 in the first direction X can be set to 4 microns, 4.2 microns, 4.5 microns, 4.8 microns or 5 microns, etc. The specific value of the width can be adjusted accordingly according to design requirements. It is only necessary to ensure that the setting of the common electrode trace 162 can effectively improve the dark lines at the edges of the adjacent pixel electrode group 164 and improve the transmittance of the array substrate 100. There is no special restriction here.

[0054] It should be noted that in the process of manufacturing the common electrode wiring 162, the number and width of the common electrode wiring 162 between two adjacent pixel electrode groups 164 can be designed and adjusted according to the spacing between two adjacent pixel electrode groups 164, the spacing between two adjacent branch electrodes 1611 in a pixel electrode 161, and the manufacturing accuracy of the common electrode wiring 162, so as to ensure that the setting of the common electrode wiring 162 can effectively improve the dark lines at the edges of adjacent pixel electrode groups 164 and improve the transmittance of the array substrate 100.

[0055] Optional, such as Figure 1 and Figure 5As shown, the array substrate 100 includes a first signal line 121 disposed within the display area S1. A first opening 151 is provided on the insulating layer 150 at a position corresponding to the first signal line 121. The common electrode trace 162 is electrically connected to the first signal line 121 through the first opening 151. The array substrate 100 also includes a source and a drain disposed within the display area S1, and the pixel electrode 161 is electrically connected to the drain. That is, during use of the array substrate 100, a signal is input to the common electrode trace 162 via the first signal line 121 within the display area S1. By controlling the conduction of the signal between the source and the drain, a signal is input to the pixel electrode 161, generating an electric field reaction between the common electrode trace 162 and adjacent pixel electrodes 161. This effectively reduces dark lines at the edges of adjacent pixel electrodes 161 and improves the transmittance of the array substrate 100.

[0056] like Figure 3 As shown, the array substrate 100 includes a second signal line 122 disposed in the non-display area S2, the second signal line 122 being disposed on the same layer as the first signal line 121. The first electrode layer 140 includes a second common electrode 142 located in the non-display area S2, the second common electrode 142 being electrically connected to the first common electrode 141. The second electrode layer 160 includes a connecting electrode 163 located in the non-display area S2. That is, when manufacturing the array substrate 100, the first signal line 121 and the second signal line 122 are simultaneously formed using a single photomask process, the electrically connected first common electrode 141 and the second common electrode 142 are simultaneously formed using a single photomask process, and the pixel electrode 161, the common electrode trace 162, and the connecting electrode 163 are simultaneously formed using a single photomask process.

[0057] A second opening 152 is defined on the insulating layer 150 at a position corresponding to the second signal line 122, and the connecting electrode 163 is electrically connected to the second signal line 122 via the second opening 152. A third opening 153 is defined on the insulating layer 150 at a position corresponding to the second common electrode 142, and the connecting electrode 163 is electrically connected to the second common electrode 142 via the third opening 153. In other words, the first common electrode 141 is electrically connected to the second signal line 122 via the second common electrode 142 and the connecting electrode 163. When the array substrate 100 is in use, an input signal is transmitted via the second signal line 122 in the non-display area S2 to the connecting electrode 163, which is then transmitted to the second common electrode 142. The signal is then transmitted by the second common electrode 142 to the first common electrode in the display area S1, thereby controlling the display mode of the display area S1.

[0058] It is understood that the base substrate 110 includes a substrate layer, a signal layer (including a first signal line 121 and a second signal line 122), a gate insulating layer 133, a data line 123, a passivation layer 131, and a planarization layer 132, which are arranged in sequence. Correspondingly, the first opening 151 and the second opening 152 sequentially penetrate the insulating layer, the planarization layer 132, the passivation layer 131, and the gate insulating layer 133, and the third opening 153 penetrates the insulating layer.

[0059] It should be noted that when the array substrate 100 is in use, the input signals on the first common electrode 141 and the common electrode trace 162 in the display area S1 are both transmitted from the signal line (not shown) in the non-display area S2. Specifically, the input signal on the common electrode trace 162 is directly transmitted from the signal line in the non-display area S2 to the first signal line 121, and then from the first signal line 121 to the common electrode trace 162. The input signal on the first common electrode 141 is first transmitted from the signal line in the non-display area S2 to the second signal line 122, and then from the second signal line 122 to the connecting electrode 163, and then from the connecting electrode 163 to the second common electrode 142, and then from the second common electrode 142 to the first common electrode 141.

[0060] Specifically, Figure 7 A comparative schematic diagram of the edge electric field distribution of a pixel electrode 161 in an array substrate 100 provided in an embodiment of the present application, wherein the solid line a represents the distribution of the edge electric field of the pixel electrode 161 when no common electrode wiring 162 is provided between two adjacent pixel electrodes 161, and the dotted line b represents the distribution of the edge electric field of the pixel electrode 161 when a common electrode wiring 162 is provided between two adjacent pixel electrodes 161.

[0061] For FFS (Fringe Field Switching) liquid crystal display technology, an electric field is formed by coupling the pixel electrode 161 and the first common electrode 141, so that the aligned liquid crystal molecules are deflected in a direction parallel to the plane of the array substrate 100 under the action of the electric field, thereby improving the light transmittance of the liquid crystal layer 300, that is, the transmittance.

[0062] like Figure 7As shown, when no common electrode trace 162 is provided between two adjacent pixel electrodes 161, the electric field strength between the two adjacent pixel electrodes 161 is in a gradually weakening state, which limits the deflection of the aligned liquid crystal molecules. At this time, more dark lines will appear at the edges of the pixel electrodes 161, resulting in a decrease in the transmittance of the array substrate 100. When a common electrode trace 162 is provided between two adjacent pixel electrodes 161, during the input signal process, an electric field reaction occurs between the common electrode trace 162 and the adjacent pixel electrodes 161, thereby strengthening the originally weakening electric field strength, helping to deflect the aligned liquid crystal molecules under the action of the electric field, and thus helping to improve the light transmission efficiency of the liquid crystal layer 300.

[0063] Among them, Figure 7 As shown, the array substrate 100 further includes a data line 123 arranged in the display area S1, and the orthographic projection of the common electrode line 162 on the base substrate 110 at least partially overlaps with the orthographic projection of the data line 123 on the base substrate 110, that is, in the thickness direction of the array substrate 100, the common electrode line 162 and the data line 123 are stacked, and the common electrode line 162 is located between two adjacent pixel electrodes 161, so that the common electrode line 162 can shield the capacitive coupling between the data line 123 and the pixel electrode 161, thereby improving the overall display effect of the array substrate 100.

[0064] Secondly, an embodiment of the present application provides a display panel, which includes an array substrate. The specific structure of the array substrate refers to the above embodiment. Since this display panel adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here one by one.

[0065] like Figure 8 As shown, the display panel 10 includes an array substrate 100, a color filter substrate 200, and a liquid crystal layer 300. The color filter substrate 200 is located on the side of the array substrate 100 where the second electrode layer 160 faces away from the base substrate 110 of the array substrate 100, and the color filter substrate 200 is disposed opposite the array substrate 100. During assembly of the display panel 100, the array substrate 100 and the color filter substrate 200 are fastened together to form a receiving cavity, and the liquid crystal layer 300 is filled in the receiving cavity between the color filter substrate 200 and the array substrate 100. During operation of the display panel 100, the drive signal on the array substrate 100 is modulated to cause the liquid crystal molecules in the liquid crystal layer 300 to rotate, thereby changing the angle of the emitted light and forming different display images.

[0066] For FFS (Fringe Field Switching) liquid crystal display technology, an electric field is formed by coupling the pixel electrode 161 and the first common electrode 141, so that the aligned liquid crystal molecules are deflected in a direction parallel to the plane of the array substrate 100 under the action of the electric field, thereby improving the light transmittance efficiency of the liquid crystal layer 300.

[0067] Specifically, the array substrate 100 includes a base substrate 110, a first electrode layer 140, an insulating layer 150, and a second electrode layer 160, which are sequentially arranged. The base substrate 110 includes a display area S1 and a non-display area S2. The first electrode layer 140 includes a first common electrode 141 located in the display area S1. The second electrode layer 160 includes a plurality of pixel electrodes 161 and a common electrode trace 162 located in the display area S1. The plurality of pixel electrodes 161 are arranged at intervals, and the common electrode trace 162 is arranged between at least two adjacent pixel electrodes 161. The common electrode trace 162 extends in the same direction as the edge of the adjacent pixel electrode 161. In the present application, by arranging the common electrode trace 162 between at least two adjacent pixel electrodes 161, when a signal is input, the common electrode trace 162 reacts with the adjacent pixel electrode 161 to enhance the electric field strength at the edge of the corresponding pixel electrode 161, thereby improving the dark lines at the edge of the pixel electrode 161, increasing the transmittance of the array substrate 100, and further improving the display quality of the display panel 10.

[0068] It should be noted that the application scope of the display panel 10 in the embodiment of the present application is very wide, including various display and lighting display devices such as televisions, computers, mobile phones, foldable and rollable display screens, as well as wearable devices such as smart bracelets and smart watches, all of which are within the scope of the application field of the display panel 10 in the embodiment of the present application.

[0069] Finally, an embodiment of the present application also provides a display device, which includes a display panel. The specific structure of the display panel refers to the above embodiment. Since this display device adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here one by one.

[0070] The display device includes a display panel 10, a control circuit, and a housing. The housing is connected to the display panel 10 to support and fix the display panel 10. The control circuit is disposed in the housing and electrically connected to the display panel 10 to control the display panel 10 to display images.

[0071] The display panel 10 can be fixed to the housing to form an integral unit with the housing. The display panel 10 and the housing form a sealed space for accommodating the control circuit. The control circuit can be the mainboard of the display device. At the same time, the control circuit can also integrate one or more functional components such as a battery, an antenna structure, a microphone, a speaker, a headphone jack, a universal serial bus interface, a camera, a distance sensor, an ambient light sensor, and a processor, so that the display device can be adapted to various application fields.

[0072] It should be noted that the display device is not limited to the above content. It can also include other devices, such as a camera, an antenna structure, a fingerprint unlocking module, etc., to expand its scope of use, which is not limited here.

[0073] The above is a detailed introduction to an array substrate and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: A base substrate, comprising a display area and a non-display area; A first electrode layer is provided on the base substrate, wherein the first electrode layer includes a first common electrode located in the display area; an insulating layer, disposed on a side of the first electrode layer facing away from the base substrate; a second electrode layer, disposed on a side of the insulating layer facing away from the first electrode layer, the second electrode layer comprising a plurality of pixel electrodes and a common electrode wiring located in the display area, the plurality of pixel electrodes being spaced apart, the common electrode wiring being disposed between at least two adjacent pixel electrodes and insulated from the pixel electrodes, and the common electrode wiring extending in a direction consistent with an extending direction of an edge of an adjacent pixel electrode; The second electrode layer includes a plurality of pixel electrode groups arranged in parallel along a first direction, each pixel electrode group includes a plurality of pixel electrodes arranged in parallel along a second direction, and the second direction forms an angle with the first direction; two common electrode traces are provided between two adjacent pixel electrode groups, and the extension direction of the common electrode traces is consistent with the extension direction of the edges of the adjacent pixel electrode groups; The pixel electrode includes a plurality of branch electrodes spaced apart along the first direction, and the extending direction of the branch electrodes is consistent with the extending direction of the common electrode wiring; There is a first spacing between the edge of the pixel electrode group and the adjacent common electrode line, there is a second spacing between two adjacent branch electrodes of the pixel electrode, and the first spacing is equal to the second spacing; there is a third spacing between the two common electrode lines between two adjacent pixel electrode groups, and the third spacing is equal to the first spacing and the second spacing.

2. The array substrate according to claim 1, wherein: The common electrode wiring is arranged between any two adjacent pixel electrodes.

3. The array substrate according to claim 1, wherein: The spacing between the common electrode wiring and the edges of two adjacent pixel electrode groups is equal.

4. The array substrate according to claim 1, wherein: The width of the common electrode wiring in the first direction is greater than or equal to 4 micrometers and less than or equal to 5 micrometers.

5. The array substrate according to claim 1, wherein: The array substrate includes a first signal line arranged in the display area. A first opening is opened on the insulating layer at a position corresponding to the first signal line. The common electrode wiring is electrically connected to the first signal line through the first opening.

6. The array substrate according to claim 5, wherein: The array substrate includes a second signal line arranged in the non-display area, the second signal line is arranged in the same layer as the first signal line, the first electrode layer includes a second common electrode located in the non-display area, the second common electrode is electrically connected to the first common electrode, and the second electrode layer includes a connecting electrode located in the non-display area; a second opening is opened on the insulating layer at a position corresponding to the second signal line, the connecting electrode is electrically connected to the second signal line through the second opening, and a third opening is opened on the insulating layer at a position corresponding to the second common electrode, the connecting electrode is electrically connected to the second common electrode through the third opening.

7. The array substrate according to claim 1, wherein: The array substrate further includes a data line disposed in the display area, and an orthographic projection of the common electrode line on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate.

8. A display panel, characterized in that: The display panel includes the array substrate according to any one of claims 1 to 7.

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