Array substrate and manufacturing method thereof, and display panel

Abstract

This application discloses an array substrate, a method for manufacturing the same, and a display panel. The second source electrode of the array substrate is connected to the first source electrode via a first source portion, and the second drain electrode is connected to the first drain electrode via a first drain portion. This allows the second source electrode and the second drain electrode to overlap the first active layer and the second active layer, thereby achieving a dual-active-layer shared gate electrode structure that significantly improves the current characteristics of TFT devices. This dual-active-layer shared gate electrode structure achieves high integration of TFT devices and enables narrow-frame displays on display panels.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] With the advent of the 5G era, the demand for various display devices continues to grow. Among them, new display technologies represented by mini-LED screens and micro-LED screens (hereinafter collectively referred to as MLED screens) have entered a stage of accelerated development. Compared with traditional LCD and OLED screens, MLED screens are regarded as the most promising new display technology due to their high contrast, low power consumption, high visual angle, wide color gamut and other advantages. Oxide semiconductor thin-film transistors have become the best choice for MLED display devices due to their unique advantages such as higher mobility, large-area uniformity and low process temperature. MLED display devices are current-driven devices, which have higher requirements on the mobility and reliability of thin-film transistors (hereinafter collectively referred to as TFTs), and the driving circuits are usually more complex. Therefore, in order to achieve high-performance MLED display devices, a high-performance TFT array substrate is crucial. Summary of the Invention

[0003] An object of the present invention is to provide an array substrate and a method for manufacturing the same, so as to solve the current technical problems of low mobility and poor reliability of thin film transistors.

[0004] To achieve the above object, the present invention provides an array substrate, comprising:

[0005] a first metal layer;

[0006] a first active layer disposed on the first metal layer, the first active layer including a first source portion, a first drain portion, and a first channel portion, wherein the first metal layer disposed corresponding to the first source portion is a first source electrode, and the first source portion is connected to the first source electrode; the first metal layer disposed corresponding to the first drain portion is a first drain electrode, and the first drain portion is connected to the first drain electrode; and the first metal layer disposed corresponding to the first channel portion is a light shielding portion;

[0007] a second metal layer disposed on the first active layer, the second metal layer including a gate electrode, the gate electrode being disposed corresponding to the first channel portion;

[0008] a second active layer disposed on the second metal layer; and

[0009] A third metal layer is disposed on the second active layer, and the third metal layer includes a second source electrode and a second drain electrode that are spaced apart from each other, wherein the second source electrode is connected to the first source portion; and the second drain electrode is connected to the first drain portion.

[0010] Furthermore, the second active layer includes a second source portion, a second drain portion and a second channel portion;

[0011] The second source electrode is correspondingly arranged on the second source portion, the second drain electrode is correspondingly arranged on the second drain portion, and the second channel portion is correspondingly arranged to the gate electrode.

[0012] Furthermore, the first source electrode and the light shielding portion are integrally formed, and the first drain electrode is spaced apart from the first source electrode and the light shielding portion; or,

[0013] The first drain electrode and the light shielding portion are integrally formed, and the first source electrode is spaced apart from the first drain electrode and the light shielding portion.

[0014] Furthermore, the array substrate further includes: an anode, which is arranged on the first active layer and connected to the first drain portion.

[0015] Furthermore, the array substrate further includes: a conductive portion, and the anode is connected to the first drain portion through the conductive portion.

[0016] Furthermore, the array substrate further includes:

[0017] a base substrate, the first metal layer being disposed on the base substrate;

[0018] a buffer layer disposed on the first metal layer, the buffer layer having a first opening for exposing the first source electrode and the first drain electrode, such that the first source portion is connected to the first source electrode through the first opening, and the first drain portion is connected to the first drain electrode through the first opening;

[0019] a gate insulating layer, correspondingly disposed between the first channel portion and the gate electrode;

[0020] a first passivation layer covering the gate electrode and extending onto the base substrate; wherein the second active layer is disposed on the first passivation layer, and the first passivation layer has a second opening for exposing the first source electrode portion and the first drain electrode portion, so that the second active layer is connected to the first source electrode portion and the first drain electrode portion;

[0021] a second passivation layer covering the third metal layer and extending onto the base substrate; and

[0022] The planar layer is disposed on the second passivation layer and extends onto the base substrate.

[0023] Furthermore, the array substrate further includes:

[0024] a third opening, which penetrates the planar layer, the second passivation layer, and the first passivation layer and is used to expose the first drain portion;

[0025] a conductive portion disposed on the planar layer and connected to the first drain portion through the third opening;

[0026] The anode is disposed on the conductive portion.

[0027] To achieve the above object, the present invention further provides a method for preparing an array substrate, comprising the following steps:

[0028] forming a first metal layer;

[0029] performing patterning on the first metal layer to form a first source electrode, a first drain electrode, and a light shielding portion;

[0030] forming a first active layer on the first metal layer, the first active layer including a first source portion, a first drain portion, and a first channel portion, wherein the first source portion is disposed corresponding to the first source electrode and connected to the first source electrode; the first drain portion is disposed corresponding to the first drain electrode and connected to the first drain electrode; and the first channel portion is disposed corresponding to the light shielding portion;

[0031] forming a second metal layer on the first active layer;

[0032] performing patterning on the second metal layer to form a gate electrode, wherein the gate electrode is disposed corresponding to the first channel portion;

[0033] forming a second active layer on the second metal layer;

[0034] forming a third metal layer on the second active layer;

[0035] The third metal layer is patterned to form a second source electrode and a second drain electrode that are spaced apart from each other, wherein the second source electrode is connected to the first source portion; and the second drain electrode is connected to the first drain portion.

[0036] Furthermore, after the step of forming a first active layer on the first metal layer, the method further includes:

[0037] An anode is formed on the first active layer, and the anode is connected to the first drain portion.

[0038] To achieve the above object, the present invention further provides a display panel, comprising the array substrate described in any one of the above embodiments.

[0039] The technical effect of the present invention is to provide an array substrate, a method for manufacturing the same, and a display panel, wherein a second source electrode is connected to the first source electrode via a first source portion, and a second drain electrode is connected to the first drain electrode via a first drain portion, so that the second source electrode and the second drain electrode overlap the first active layer and the second active layer, thereby realizing a structure in which two active layers share a gate electrode, which can significantly improve the current characteristics of a TFT device. The present application adopts a dual-active-layer shared gate electrode structure, achieving a high degree of integration of TFT devices and enabling narrow-frame display of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0041] Figure 1 This is a structural diagram of the array substrate provided in Example 1 of the present application.

[0042] Figure 2 This is a flow chart of the array substrate preparation method provided in Example 1 of the present application.

[0043] Figure 3 This is a schematic diagram of the structure of the patterned first metal layer provided in Example 1 of the present application.

[0044] Figure 4 This is a schematic diagram of the structure after the first active layer is formed provided in Example 1 of the present application.

[0045] Figure 5 This is a schematic diagram of the structure of the patterned third metal layer provided in Example 1 of the present application.

[0046] Figure 6 This is a structural diagram of the array substrate provided in Example 1 of the present application.

[0047] The components of the accompanying drawings are identified as follows:

[0048] 1. Base substrate; 2. First metal layer; 21. First source electrode; 22. First drain electrode; 23. Light shielding portion; 3. Buffer layer; 4. First active layer; 41. First source portion; 42. First drain portion; 43. First channel portion; 5. Gate insulating layer; 6. Second metal layer; 61. Gate electrode; 7. First passivation layer; 8. Second active layer; 81. Second source portion; 82. Second drain portion; 83. Second channel portion; 9. Third metal layer; 10. Second passivation layer; 11. Conductive portion; 12. Anode; 13. Planarization layer; 101. First opening; 102. Second opening; 103. Through hole; 104. Third opening. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0050] In the description of the present application, it should be understood that the terms "upper", "lower", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0051] Example 1

[0052] like Figure 1 As shown, this embodiment provides an array substrate, including a first metal layer 2 , a first active layer 4 , a second metal layer 6 , a second active layer 8 and a third metal layer 9 .

[0053] The first active layer 4 is disposed on the first metal layer 2. Specifically, the first active layer 4 includes a first source portion 41, a first drain portion 42, and a first channel portion 43. The first metal layer 2 corresponding to the first source portion 41 is the first source electrode 21, and the first source portion 41 is connected to the first source electrode 21; the first metal layer 2 corresponding to the first drain portion 42 is the first drain electrode 22, and the first drain portion 42 is connected to the first drain electrode 22; and the first metal layer 2 corresponding to the first channel portion 43 is the light shielding portion 23.

[0054] In this embodiment, the first source electrode 21 is provided on the same layer as the first drain electrode 22 and the light shielding portion 23. Specifically, the first source electrode 21 and the light shielding portion 23 are integrally formed, and the first drain electrode 22 is spaced apart from the first source electrode 21 and the light shielding portion 23. Simply put, the first metal layer 2 has two metal segments. The left metal segment can be a structure in which the first source electrode 21 and the light shielding portion 23 are integrally formed, while the right metal segment can be a structure in which the first drain electrode 22 is formed. Of course, the positions of the left and right metal segments can also be swapped.

[0055] It should be noted that in other embodiments, the first drain electrode 22 and the light shielding portion 23 may be integrally formed, and the first source electrode 21 may be spaced apart from the first drain electrode 22 and the light shielding portion 23. Simply put, the first metal layer 2 has two metal segments. The left metal segment may be the structure of the first source electrode 21, and the right metal segment may be the structure of the first drain electrode 22 and the light shielding portion 23 integrally formed. Similarly, the positions of the left and right metal segments may also be swapped, which will not be detailed here.

[0056] In this embodiment, the material used for the first active layer 4 can be semiconductor metal oxides such as IGZO, IGZTO, and IGTO.

[0057] The second metal layer 6 is disposed on the first active layer 4 . The second metal layer 6 includes a gate electrode 61 . The gate electrode 61 is disposed corresponding to the first channel portion 43 .

[0058] The second active layer 8 is disposed on the second metal layer 6. The second active layer 8 includes a second source portion 81, a second drain portion 82, and a second channel portion 83. The second source electrode 91 is correspondingly disposed on the second source portion 81, the second drain electrode 92 is correspondingly disposed on the second drain portion 82, and the second channel portion 83 is correspondingly disposed with the gate electrode 61.

[0059] In this embodiment, the material used for the second active layer 8 can be semiconductor metal oxides such as IGZO, IGZTO, and IGTO.

[0060] The third metal layer 9 is disposed on the second active layer 8 and includes a second source electrode 91 and a second drain electrode 92 spaced apart from each other, wherein the second source electrode 91 is connected to the first source portion 41, and the second drain electrode 92 is connected to the first drain portion 42. Specifically, the second source electrode 91 is connected to the first source electrode 21 via the first source portion 41, and the second drain electrode 92 is connected to the first drain electrode 22 via the first drain portion 42, so that the second source electrode 91 and the second drain electrode 92 overlap the first active layer 4 and the second active layer 8, thereby realizing a structure in which two active layers share a gate electrode 61, which can significantly improve the current characteristics of the TFT device. This embodiment adopts a dual active layer shared gate electrode structure to achieve a high degree of integration of the TFT device and enable a narrow-frame display of the display panel.

[0061] In this embodiment, the materials used for the first metal layer 2, the second metal layer 6, and the third metal layer 9 can be any one of the following materials: Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, and Mo / Cu / ITO.

[0062] Furthermore, the array substrate further includes a base substrate 1 , a buffer layer 3 , a gate insulating layer 5 , a first passivation layer 7 , a second passivation layer 10 , a conductive portion 11 and an anode 12 .

[0063] Specifically, the first metal layer 2 is provided on the base substrate 1. The base substrate 1 can be a flexible or rigid glass substrate, which is not limited here.

[0064] The buffer layer 3 is disposed on the first metal layer 2. The buffer layer 3 has a first opening 101 for exposing the first source electrode 21 and the first drain electrode 22, so that the first source portion 41 is connected to the first source electrode 21 through the first opening 101, and the first drain portion 42 is connected to the first drain electrode 22 through the first opening 101. Specifically, in this embodiment, the buffer layer 3 has two first openings 101. The first opening 101 on the left is used to achieve a conductive connection between the first source portion 41 and the first source electrode 21, and the first opening 101 on the right is used to achieve a conductive connection between the first drain portion 42 and the first drain electrode 22.

[0065] In this embodiment, the buffer layer 3 is made of SiOx or a SiNx / SiOx stack.

[0066] The gate insulating layer 5 is correspondingly disposed between the first channel portion 43 and the gate electrode 61 .

[0067] The first passivation layer 7 covers the gate electrode 61 and extends to the upper surface of the base substrate 1. The second active layer 8 is disposed on the first passivation layer 7. The first passivation layer 7 is provided with a second opening 102 for exposing the first source portion 41 and the first drain portion 42. Specifically, in this embodiment, the first passivation layer 7 is provided with two second openings 102. The second opening 102 on the left is used to achieve a conductive connection between the second source electrode 91 and the first source portion 41, and the second opening 102 on the right is used to achieve a conductive connection between the second drain electrode 92 and the first drain portion 42.

[0068] In this embodiment, the material used for the first passivation layer 7 includes but is not limited to SiOx.

[0069] The second passivation layer 10 covers the third metal layer 9 and extends to the upper surface of the base substrate 1. Specifically, the second passivation layer 10 covers the second source electrode 91, the second drain electrode 92, the second channel portion 83, the first passivation layer 7, and extends to the upper surface of the base substrate 1.

[0070] In this embodiment, the material used for the second passivation protection layer may be SiOx or a SiNx / SiOx stacked layer, but is not limited to others.

[0071] In this embodiment, the first passivation layer 7 serves as a gate insulating layer between the gate electrode 61 and the second active layer 8 , and also forms a double protection layer structure with the second passivation layer 10 , which can effectively improve the reliability of the TFT device.

[0072] In this embodiment, the array substrate further includes a through hole 103 , which passes through the second passivation layer 10 and the first passivation layer 7 and exposes the first drain electrode portion 42 .

[0073] The conductive portion 11 is disposed on the second passivation layer 10, and the conductive portion 11 is attached to the sidewall of the through hole 103 and connected to the first drain portion 42. The conductive portion 11 can be a metal electrode of the LED.

[0074] The anode 12 is disposed on the conductive portion 11, and the anode 12 is connected to the first drain portion 42 through the conductive portion 11. The anode 12 may be made of ITO.

[0075] This embodiment also provides a display panel, comprising the array substrate described above. This display panel utilizes a dual-active-layer shared gate electrode structure, achieving a high degree of integration of TFT devices and enabling a narrow-frame display. The display panel may be a mini-LED display panel, a micro-LED display panel, an OLED display panel, or the like, without particular limitation. In other words, the array substrate provided in this embodiment is applicable to most types of display panels.

[0076] like Figure 2As shown, this embodiment also provides a method for preparing an array substrate, comprising the following steps:

[0077] S11, forming a first metal layer 2 on a base substrate 1, referring to Figure 3 .

[0078] S12, patterning the first metal layer 2 to form a first source electrode 21, a first drain electrode 22 and a light shielding portion 23, referring to Figure 3 .

[0079] In this embodiment, the first source electrode 21 is provided on the same layer as the first drain electrode 22 and the light shielding portion 23. Specifically, the first source electrode 21 and the light shielding portion 23 are integrally formed, and the first drain electrode 22 is spaced apart from the first source electrode 21 and the light shielding portion 23. Simply put, the first metal layer 2 has two metal segments. The left metal segment can be a structure in which the first source electrode 21 and the light shielding portion 23 are integrally formed, while the right metal segment can be a structure in which the first drain electrode 22 is formed. Of course, the positions of the left and right metal segments can also be swapped.

[0080] It should be noted that in other embodiments, the first drain electrode 22 and the light shielding portion 23 may be integrally formed, and the first source electrode 21 may be spaced apart from the first drain electrode 22 and the light shielding portion 23. Simply put, the first metal layer 2 has two metal segments. The left metal segment may be the structure of the first source electrode 21, and the right metal segment may be the structure of the first drain electrode 22 and the light shielding portion 23 integrally formed. Similarly, the positions of the left and right metal segments may also be swapped, which will not be detailed here.

[0081] In this embodiment, the material used for the first active layer 4 can be semiconductor metal oxides such as IGZO, IGZTO, and IGTO.

[0082] S13, forming a buffer layer 3 on the first metal layer 2 and extending to the base substrate 1, referring to Figure 4 .

[0083] S14, the buffer layer 3 is subjected to a hole-digging process to form a first opening 101, wherein the first opening 101 is used to expose the first source electrode 21 and the first drain electrode 22, referring to Figure 5 .

[0084] In this embodiment, the buffer layer 3 is made of SiOx or a SiNx / SiOx stack.

[0085] S15, forming a first active layer 4 on the first metal layer 2, the first active layer 4 including a first source portion 41, a first drain portion 42 and a first channel portion 43, wherein the first source portion 41 is arranged corresponding to the first source electrode 21, and the first source portion 41 is connected to the first source electrode 21; the first drain portion 42 is arranged corresponding to the first drain electrode 22, and the first drain portion 42 is connected to the first drain electrode 22; the first channel portion 43 is arranged corresponding to the light shielding portion 23, refer to Figure 5 .

[0086] In this embodiment, the material used for the first active layer 4 can be semiconductor metal oxides such as IGZO, IGZTO, and IGTO.

[0087] S16, forming a gate insulating layer 5 on the first active layer 4, referring to Figure 5 .

[0088] S17, forming a second metal layer 6 on the gate insulating layer 5, referring to Figure 5 .

[0089] S18, patterning the second metal layer 6 to form a gate electrode 61, the gate electrode 61 is arranged corresponding to the first channel portion 43, refer to Figure 5 .

[0090] When the second metal layer 6 is patterned to form the gate electrode 61 (ie, the top gate), the gate insulating layer 5 is patterned using a top gate self-alignment process.

[0091] S19, forming a first passivation layer 7 on the second metal layer 6 and extending to the base substrate 1, referring to Figure 5 .

[0092] S110, digging the first passivation layer 7 to form a second opening 102, the second opening 102 is used to expose the first source portion 41 and the first drain portion 42, refer to Figure 5 .

[0093] Specifically, in this embodiment, the first passivation layer 7 has two second openings 102. The left second opening 102 is used to achieve a conductive connection between the second source electrode 91 and the first source portion 41, and the right second opening 102 is used to achieve a conductive connection between the second drain electrode 92 and the first drain portion 42. The material used for the first passivation layer 7 includes, but is not limited to, SiOx.

[0094] S111, forming a second active layer 8 on the second metal layer 6. The second active layer 8 includes a second source portion 81, a second drain portion 82 and a second channel portion 83. The second source electrode 91 is correspondingly arranged on the second source portion 81, the second drain electrode 92 is correspondingly arranged on the second drain portion 82, and the second channel portion 83 is correspondingly arranged with the gate electrode 61. Figure 5 .

[0095] In this embodiment, the material used for the second active layer 8 can be semiconductor metal oxides such as IGZO, IGZTO, and IGTO.

[0096] S112, forming a third metal layer 9 on the second active layer 8, referring to Figure 5 .

[0097] S113, patterning the third metal layer 9 to form a second source electrode 91 and a second drain electrode 92 spaced apart, wherein the second source electrode 91 is connected to the first source portion 41; the second drain electrode 92 is connected to the first drain portion 42, referring to Figure 5 .

[0098] Specifically, the second source electrode 91 is connected to the first source electrode 21 via the first source portion 41, and the second drain electrode 92 is connected to the first drain electrode 22 via the first drain portion 42. This allows the second source electrode 91 and the second drain electrode 92 to overlap the first active layer 4 and the second active layer 8, thereby achieving a dual-active layer shared gate electrode 61 structure, which can significantly improve the current characteristics of the TFT device. This embodiment adopts a dual-active layer shared gate electrode structure, achieving a high degree of integration of the TFT device and enabling a narrow-frame display panel.

[0099] In this embodiment, the materials used for the first metal layer 2, the second metal layer 6, and the third metal layer 9 can be any one of the following materials: Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, and Mo / Cu / ITO.

[0100] S114, forming a second passivation layer 10 on the third metal layer 9, referring to Figure 1 .

[0101] Specifically, the second passivation layer 10 covers the third metal layer 9 and extends to the upper surface of the base substrate 1. Specifically, the second passivation layer 10 covers the second source electrode 91, the second drain electrode 92, the second channel portion 83, the first passivation layer 7, and extends to the upper surface of the base substrate 1.

[0102] In this embodiment, the material used for the second passivation protection layer may be SiOx or a SiNx / SiOx stacked layer, but is not limited to others.

[0103] S115, the second passivation layer 10 is subjected to a hole-digging process to form a through hole 103, the through hole 103 penetrates the second passivation layer 10 and the first passivation layer 7, and exposes the first drain portion 42, referring to Figure 1 .

[0104] S116, forming a conductive portion 11 disposed on the second passivation layer 10, wherein the conductive portion 11 is attached to the sidewall of the through hole 103 and connected to the first drain portion 42. The conductive portion 11 can be a metal electrode of the LED, refer to Figure 1 .

[0105] S117, forming an anode 12 on the conductive portion 11, wherein the anode 12 is connected to the first drain portion 42 through the conductive portion 11, referring to Figure 1 The material used for the anode 12 may be ITO.

[0106] Example 2

[0107] This embodiment provides an array substrate and a manufacturing method thereof, and a display panel, which include most of the technical solutions of the embodiment 1, except that the conductive portion 11 and the anode 12 are arranged at different positions.

[0108] like Figure 6 As shown, the array substrate provided in this embodiment further includes a planar layer 13 and a third opening 104 .

[0109] The planarization layer 13 is disposed on the second passivation layer 10 and extends onto the base substrate 1 .

[0110] The third opening 104 penetrates the planar layer 13 , the second passivation layer 10 , and the first passivation layer 7 and is used to expose the first drain portion 42 ;

[0111] In this embodiment, the conductive portion 11 is disposed on the planar layer 13 and connected to the first drain portion 42 through the third opening 104. The anode 12 is disposed on the conductive portion 11.

[0112] The array substrate manufacturing method provided in this embodiment includes the following steps after forming a second passivation layer 10 on the third metal layer 9:

[0113] A planar layer 13 is formed on the second passivation layer 10 and extends onto the base substrate 1;

[0114] The planar layer 13 is subjected to a hole-digging process to form a third opening 104 . The third opening 104 sequentially penetrates the planar layer 13 , the second passivation layer 10 , and the first passivation layer 7 , and exposes the first drain electrode portion 42 .

[0115] A conductive portion 11 is formed on the planar layer 13 . The conductive portion 11 is attached to the sidewall of the third opening 104 and connected to the first drain portion 42 .

[0116] An anode 12 is formed on the conductive portion 11 , wherein the anode 12 is connected to the first drain portion 42 through the conductive portion 11 .

[0117] In the array substrate, manufacturing method thereof, and display panel provided in the embodiments of the present application, the second source electrode 91 is connected to the first source electrode 21 via the first source electrode portion 41, and the second drain electrode 92 is connected to the first drain electrode 22 via the first drain electrode portion 42. This allows the second source electrode 91 and the second drain electrode 92 to overlap the first active layer 4 and the second active layer 8, thereby achieving a structure in which two active layers share a gate electrode 61, significantly improving the current characteristics of the TFT device. This application utilizes a dual-active-layer shared gate electrode structure to achieve a high degree of integration of TFT devices, enabling narrow-frame display of the display panel.

[0118] The above is a detailed introduction to an array substrate, a preparation method thereof, and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: a first metal layer; a first active layer disposed on the first metal layer, the first active layer including a first source portion, a first drain portion, and a first channel portion, wherein the first metal layer disposed corresponding to the first source portion is a first source electrode, and the first source portion is connected to the first source electrode; the first metal layer disposed corresponding to the first drain portion is a first drain electrode, and the first drain portion is connected to the first drain electrode; and the first metal layer disposed corresponding to the first channel portion is a light shielding portion; a second metal layer disposed on the first active layer, the second metal layer including a gate electrode, the gate electrode being disposed corresponding to the first channel portion; a second active layer disposed on the second metal layer; and A third metal layer is disposed on the second active layer, and the third metal layer includes a second source electrode and a second drain electrode that are spaced apart from each other, wherein the second source electrode is connected to the first source portion; and the second drain electrode is connected to the first drain portion.

2. The array substrate according to claim 1, wherein: The second active layer includes a second source portion, a second drain portion and a second channel portion; The second source electrode is correspondingly arranged on the second source portion, the second drain electrode is correspondingly arranged on the second drain portion, and the second channel portion is correspondingly arranged to the gate electrode.

3. The array substrate according to claim 1, wherein: The first source electrode and the light shielding portion are integrally formed, and the first drain electrode is spaced apart from the first source electrode and the light shielding portion; or, The first drain electrode and the light shielding portion are integrally formed, and the first source electrode is spaced apart from the first drain electrode and the light shielding portion.

4. The array substrate according to claim 1, wherein: Also includes: An anode is disposed on the first active layer and connected to the first drain portion.

5. The array substrate according to claim 4, wherein: Also includes: A conductive portion, through which the anode is connected to the first drain portion.

6. The array substrate according to claim 1, wherein: Also includes: a base substrate, the first metal layer being disposed on the base substrate; a buffer layer disposed on the first metal layer, the buffer layer having a first opening for exposing the first source electrode and the first drain electrode, such that the first source portion is connected to the first source electrode through the first opening, and the first drain portion is connected to the first drain electrode through the first opening; a gate insulating layer, correspondingly disposed between the first channel portion and the gate electrode; a first passivation layer covering the gate electrode and extending onto the base substrate; wherein the second active layer is disposed on the first passivation layer, and the first passivation layer has a second opening for exposing the first source electrode portion and the first drain electrode portion, so that the second active layer is connected to the first source electrode portion and the first drain electrode portion; a second passivation layer covering the third metal layer and extending onto the base substrate; and The planar layer is disposed on the second passivation layer and extends onto the base substrate.

7. The array substrate according to claim 6, wherein: Also includes: a third opening, which penetrates the planar layer, the second passivation layer, and the first passivation layer and is used to expose the first drain portion; a conductive portion disposed on the planar layer and connected to the first drain portion through the third opening; The anode is disposed on the conductive portion.

8. A method for preparing an array substrate, characterized in that: The steps include: forming a first metal layer; performing patterning on the first metal layer to form a first source electrode, a first drain electrode, and a light shielding portion; forming a first active layer on the first metal layer, the first active layer including a first source portion, a first drain portion, and a first channel portion, wherein the first source portion is disposed corresponding to the first source electrode and connected to the first source electrode; the first drain portion is disposed corresponding to the first drain electrode and connected to the first drain electrode; and the first channel portion is disposed corresponding to the light shielding portion; forming a second metal layer on the first active layer; performing patterning on the second metal layer to form a gate electrode, wherein the gate electrode is disposed corresponding to the first channel portion; forming a second active layer on the second metal layer; forming a third metal layer on the second active layer; The third metal layer is patterned to form a second source electrode and a second drain electrode that are spaced apart from each other, wherein the second source electrode is connected to the first source portion; and the second drain electrode is connected to the first drain portion.

9. The method for preparing an array substrate according to claim 8, wherein: After the step of forming a first active layer on the first metal layer, the method further includes: An anode is formed on the first active layer, and the anode is connected to the first drain portion.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 7.

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