A gate driver control method and circuit

Abstract

The present invention discloses a gate driver control method and circuit. The method includes: when it is detected that the MOS transistor is driven to turn on by the gate driver, starting the temperature detection circuit and the current detection circuit; outputting the voltage across a third resistor through the temperature detection circuit, and determining the temperature of the gate driver based on the voltage across the third resistor, wherein the third resistor is a resistor connected in series between the TMPO pin of the gate driver and a ground terminal; adjusting the real-time voltages of the ISP pin and the ISN pin of the gate driver based on the current detection circuit so that the real-time voltage of the ISP pin is consistent with the real-time voltage of the ISN pin; and after it is detected that the MOS transistor is turned off, turning off the temperature detection circuit and the current detection circuit, monitoring the state of the gate driver in real time by performing temperature detection and current detection on the gate driver, thereby improving the safety of the gate driver.

Description

Technical Field

[0001] The present application relates to the field of gate driver technology, and more specifically, to a gate driver control method and circuit. Background Art

[0002] With the increasing number of automotive electronic devices, such as automatic transmissions, electric rearview mirror folding, central control automatic door locks and other advanced functions, the driving method of electronic control modules has evolved from the traditional on-board relay driving solution to more and more semiconductor driver chips (pre-drivers, MOSFET) solutions. The main function of the gate driver is to convert the controller signal into a high-voltage, high-current pulse to control the gate of the MOSFET or IGBT. The gate control signal needs to meet specific voltage and current requirements to ensure that they can work stably in the on or off state.

[0003] As cars become increasingly intelligent, the use of high-voltage, high-current automotive electronic driver chips will also pose certain safety hazards (for example, high voltage and high current can damage automotive parts and cause high-temperature spontaneous combustion). Existing gate driver chips cannot meet the needs of automotive electronics due to their complex structure and pins, as well as large standby current and operating current.

[0004] Therefore, it is a technical problem that needs to be solved urgently by those skilled in the art to propose a gate driver control method and circuit for performing temperature detection and current detection on the gate driver to improve the safety of the gate driver. Summary of the Invention

[0005] The invention discloses a gate driver control method, which is used to solve the technical problem that gate drivers in the prior art are prone to safety problems.

[0006] The method is applied to a gate driver control circuit including a gate driver circuit, a temperature detection circuit, and a current detection circuit. The gate driver circuit includes a gate driver and a MOS transistor to be driven. The method includes:

[0007] When it is detected that the MOS transistor to be driven is driven to turn on by the gate driver, starting the temperature detection circuit and the current detection circuit;

[0008] outputting a voltage across a third resistor through the temperature detection circuit, and determining the temperature of the gate driver based on the voltage across the third resistor, wherein the third resistor is a resistor connected in series between a TMPO pin of the gate driver and a ground terminal;

[0009] Adjusting the real-time voltages of the ISP pin and the ISN pin of the gate driver based on the current detection circuit so that the real-time voltage of the ISP pin is consistent with the real-time voltage of the ISN pin;

[0010] After detecting that the MOS transistor to be driven is turned off, the temperature detection circuit and the current detection circuit are turned off.

[0011] In some embodiments of the present application, when it is detected that the MOS transistor to be driven is driven to turn on by the gate driver, the temperature detection circuit and the current detection circuit are started, specifically:

[0012] When the signal of the IN pin of the gate driver is high, the MOS transistor to be driven is driven to turn on, and the temperature detection circuit and the current detection circuit are started;

[0013] When the signal of the IN pin of the gate driver is low, the MOS transistor to be driven is driven to be turned off, and the temperature detection circuit and the current detection circuit are turned off.

[0014] In some embodiments of the present application, the temperature detection circuit includes a first comparison module and a first feedback module. The temperature detection circuit outputs a voltage across a third resistor, and the temperature of the gate driver is determined based on the voltage across the third resistor. Specifically,

[0015] Collecting the voltage across the first resistor and comparing it with a reference voltage VT set inside the gate driver to obtain a first comparison result;

[0016] After the first feedback module receives the first comparison result, negative feedback regulation is performed through the P-type MOS transistor in the first feedback module to make the voltage of the first resistor consistent with the reference voltage VT set inside the gate driver, and the voltage across the third resistor at this time is output, and the temperature of the gate driver is determined based on the voltage across the third resistor;

[0017] The first resistor is disposed between the TMP pin of the gate driver and the temperature detection circuit, and the first resistor is a thermistor.

[0018] In some embodiments of the present application, the current detection circuit includes a second comparison module, a logic judgment output module, a delay module, and a second feedback module. The real-time voltages of the ISP pin and the ISN pin of the gate driver are adjusted based on the current detection circuit to make the real-time voltage of the ISP pin consistent with the real-time voltage of the ISN pin. Specifically,

[0019] comparing voltages across a second resistor by the second comparison module and outputting a second comparison result, wherein the second resistor is arranged between a resistor connected to the ISN pin of the gate driver and a resistor connected to the ISP pin;

[0020] determining, by the logic judgment output module, a current direction across the second resistor based on the second comparison result, and latching the obtained current direction result;

[0021] The second feedback module is activated after a preset delay time by the delay module;

[0022] Feedback regulation is performed through the second feedback module to make the real-time voltage of the ISP pin consistent with the real-time voltage of the ISN pin.

[0023] In some embodiments of the present application, after it is detected that the MOS transistor to be driven is turned off, the current direction result latched in the logic judgment output module is cleared.

[0024] In some embodiments of the present application, the second comparison module compares the voltages across the second resistor and outputs a second comparison result, specifically:

[0025] When the potential of the first terminal of the second resistor is greater than the potential of the second terminal of the second resistor, the second comparison result is a high level;

[0026] When the potential of the first terminal of the second resistor is less than the potential of the second terminal of the second resistor, the second comparison result is a low level;

[0027] The first end potential is the potential of one end of the second resistor close to the ISP pin of the gate driver connected to the resistor, and the second end potential is the potential of one end of the second resistor close to the ISN pin of the gate driver connected to the resistor.

[0028] In some embodiments of the present application, the logic judgment output module determines the current direction across the second resistor based on the second comparison result, and latches the obtained current direction result, specifically:

[0029] When the second comparison result is a high level, the current direction is from the first end of the second resistor to the second end of the second resistor;

[0030] When the second comparison result is a low level, the current direction is from the second end of the second resistor to the first end of the second resistor;

[0031] The first end of the second resistor is an end of the second resistor close to the ISP pin of the gate driver, and the second end of the second resistor is an end of the second resistor close to the ISN pin of the gate driver.

[0032] In some embodiments of the present application, the gate driver circuit also includes an external resistor and a first capacitor, the first end of the external resistor is connected to the RS terminal of the gate driver, the other end of the external resistor is connected to the ground terminal, one end of the first capacitor is connected to the OUT terminal of the gate driver, and the other end of the first capacitor is connected to the DC power supply of the gate driver. The external resistor is an adjustable resistor, and the charging speed of the first capacitor is adjusted by adjusting the resistance value of the external resistor.

[0033] Accordingly, the present invention further proposes a gate driver control circuit, the circuit comprising:

[0034] A gate driver circuit, comprising a gate driver and a MOS transistor to be driven, and configured to drive the MOS transistor to be driven through the gate driver;

[0035] a temperature detection circuit, configured to output a voltage across a third resistor through the temperature detection circuit and determine the temperature of the gate driver based on the voltage across the third resistor, wherein the third resistor is a resistor connected in series between the TMPO pin of the gate driver and the ground terminal;

[0036] a current detection circuit, configured to adjust the real-time voltages of the ISP pin and the ISN pin of the gate driver based on the current detection circuit so that the real-time voltage of the ISP pin is consistent with the real-time voltage of the ISN pin;

[0037] The temperature detection circuit and the current detection circuit are respectively connected to the gate driver circuit.

[0038] By applying the above technical solution, a gate driver control method and circuit are proposed. The method includes: when it is detected that the MOS transistor to be driven is driven to turn on by the gate driver, starting the temperature detection circuit and the current detection circuit; outputting the voltage across a third resistor through the temperature detection circuit, and determining the temperature of the gate driver based on the voltage across the third resistor, wherein the third resistor is a resistor connected in series between the TMPO pin of the gate driver and the ground terminal; adjusting the real-time voltages of the ISP pin and the ISN pin of the gate driver based on the current detection circuit so that the real-time voltage of the ISP pin is consistent with the real-time voltage of the ISN pin; after detecting that the MOS transistor to be driven is turned off, turning off the temperature detection circuit and the current detection circuit, and monitoring the state of the gate driver in real time by performing temperature detection and current detection on the gate driver, thereby improving the safety of the gate driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic flow chart of a gate driver control method according to an embodiment of the present invention is shown;

[0041] Figure 2 A schematic diagram of the structure of a temperature detection circuit proposed in an embodiment of the present application is shown;

[0042] Figure 3 A schematic diagram of the circuit structure of a temperature detection circuit proposed in an embodiment of the present invention is shown;

[0043] Figure 4 A schematic structural diagram of a current detection circuit proposed in an embodiment of the present invention is shown;

[0044] Figure 5 A schematic diagram of the circuit structure of a current detection circuit proposed in an embodiment of the present invention is shown;

[0045] Figure 6 FIG. 2 shows a schematic diagram of a circuit structure of a gate driver circuit according to an embodiment of the present invention;

[0046] Figure 7 shows a voltage variation waveform diagram of each pin of the gate driver in an embodiment of the present invention;

[0047] Figure 8 A schematic structural diagram of a gate driver control circuit proposed in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0049] The embodiment of the present application discloses a gate driver control method, which is applied to a gate driver control circuit including a gate driver circuit, a temperature detection circuit and a current detection circuit. The gate driver circuit includes a gate driver and a MOS transistor to be driven, such as Figure 1 As shown, the method includes:

[0050] Step S101 : when it is detected that the MOS transistor to be driven is driven to be turned on by the gate driver, the temperature detection circuit and the current detection circuit are started.

[0051] In this embodiment, after the MOS transistor to be driven is turned on, the voltage and temperature of each pin of the gate driver will be in a changing state. When the voltage and temperature exceed the safe value, there will be a safety risk. Therefore, a temperature detection circuit and a current detection circuit are provided in this solution. The above circuits are both connected to the gate driver circuit. By real-time monitoring and adjustment of the temperature and current of the gate driver circuit, the safety of the gate driver, the MOS transistor to be driven, and other auxiliary components of the gate driver circuit is ensured.

[0052] In order to determine whether it is necessary to turn on the temperature detection circuit and the current detection circuit, in some embodiments of the present application, when it is detected that the MOS transistor to be driven is driven to turn on by the gate driver, the temperature detection circuit and the current detection circuit are started, specifically:

[0053] When the signal of the IN pin of the gate driver is high, the MOS transistor to be driven is driven to turn on, and the temperature detection circuit and the current detection circuit are started;

[0054] When the signal of the IN pin of the gate driver is low, the MOS transistor to be driven is driven to be turned off, and the temperature detection circuit and the current detection circuit are turned off.

[0055] In this embodiment, the attached Figure 6 The gate driver circuit in the embodiment is used as an example to illustrate the principle of determining whether the temperature detection circuit and the current detection circuit need to be turned on.

[0056] The gate driver includes 14 pins, the 0th pin is the GND pin, the first pin is the VCC pin, which is connected to the external boost circuit DC power supply V1, the second pin is the SW pin, which is connected to the external boost circuit inductor L1, the third pin is the rs pin, which is connected to the external boost circuit detection resistor Rrs, the fourth pin is the IN pin, which is connected to the external DC power supply V2 as the enable input (0V or 5V, when the IN voltage is high (5V), the N1 tube is turned on, and when the IN is low (0V), the N1 is turned off), and the fifth pin DG1 is the current detection direction output. When DG1 is high, the current The current flows from A to B, DG1 is low, and the current flows from B to A. The sixth pin is the OUT pin, and the external capacitor C1 charges it; the seventh pin is the TMP pin, and the external resistor R1 is connected; the eighth pin is the ISP pin, and the external resistor R5 is connected; the ninth pin is the ISN pin, and the external resistor R6 is connected; the tenth pin is the gate pin, and the gate of the external resistor MOS tube N1 is connected; the eleventh pin is the source pin, and the source of the external MOS tube N1 is connected; the twelfth pin is the CSO pin, and the external resistor R4 is connected; the thirteenth pin is the TMPO pin, and the external resistor R3 is connected.

[0057] V1 is the boost circuit input voltage, L1 is the boost circuit energy storage inductor, C1 is the boost circuit load capacitor, and Rrs is the boost circuit sense resistor. R1 is the thermistor used for temperature detection, R2 is the current sense resistor, R5 and R6 are the current sense input resistors, R3 and R4 are the temperature sense output resistors, and R7 is the load. V1, L1, Rrs, C1, along with the diodes and switches inside the gate driver chip, form the boost circuit. The MOSFET to be driven is the MOSFET outside the chip that needs to be driven.

[0058] in, Figure 6 Gate driver pins and functions: vcc is the power supply pin, sw is the drain of the boost converter switch tube, rs is the boost circuit current detection pin, IN is the enable input pin, DG1 is the current direction output pin, out is the boost circuit output pin, TMP is the temperature detection input pin, ISP and ISN are the current detection input pins, gate is the gate drive pin, source is the source of the MOS tube to be driven, CSO is the current detection output pin, and TMPO is the temperature detection output pin.

[0059] After the power supply V1 is powered on, the boost circuit starts working to charge the capacitor of the out pin. When the out pin voltage is higher than the power supply voltage of 12.5V, the boost circuit stops working. When the IN signal is high, the gate pin voltage Vgate = Vout. At this time, the MOS transistor to be driven is turned on, and current detection and temperature detection are enabled. When IN is low, the gate pin voltage Vgate = Vsource. At this time, the MOS transistor to be driven is turned off.

[0060] In addition, if Figure 6 In the circuit shown, a boost circuit is integrated on the periphery of the gate driver, which includes an external resistor Rrs. The resistance value of the external resistor Rrs is adjusted by Rrs to adjust the charging speed of the first capacitor C1. The specific principle is: during the power-on process, the boost circuit also charges the out pin. If the start signal arrives at this time (that is, IN is high), the MOS tube to be driven needs to wait until the out pin voltage is higher than the power supply voltage 12.5V (that is, Vout-VCC>12.5V) before it can be turned on (there are two conditions for the first turn-on of the MOS tube to be driven: 1. IN is high; 2. Vout-VCC>12.5V). In this case, the delay of the MOS tube to be driven is determined by the charging time of the out pin. For different application environments, there will be different requirements for the drive start delay. Therefore, this application can adjust the turn-on delay of the MOS tube to be driven according to actual application requirements.

[0061] Out is both the output of the boost circuit and provides gate bias for the MOSFET to be driven. Therefore, the gate drive logic within the chip is also powered by the Out pin, making Out both an output and an input pin. Providing gate voltage to the MOSFET to be driven using the boosted Out pin voltage effectively ensures that the MOSFET to be driven operates in its deep linear region under normal circumstances.

[0062] Step S102 : Outputting a voltage across a third resistor through the temperature detection circuit and determining the temperature of the gate driver based on the voltage across the third resistor, where the third resistor is a resistor connected in series between the TMPO pin of the gate driver and the ground terminal.

[0063] In this embodiment, the temperature detection circuit outputs a voltage across the third resistor. Since the third resistor is a resistor connected in series between the TMPO pin of the gate driver and the ground terminal, the voltage across the third resistor is the voltage of the TMPO pin of the gate driver, and whether the temperature exceeds the predetermined range is indirectly determined by the voltage.

[0064] In order to determine the temperature of the gate driver, in some embodiments of the present application, the temperature detection circuit includes a filtering module, a first comparison module, and a first feedback module. The temperature detection circuit outputs a voltage across a third resistor, and the temperature of the gate driver is determined based on the voltage across the third resistor. Specifically,

[0065] The voltage across the first resistor is collected and compared with a reference voltage VT set inside the gate driver to obtain a first comparison result. VT is a reference voltage relative to VCC. The filtering module is used to filter the reference voltage inside the gate driver.

[0066] After the first feedback module receives the first comparison result, negative feedback regulation is performed through a P-type MOS transistor in the first feedback module to make the processed voltage of the first resistor consistent with the voltage of the TMP pin of the gate driver, and the voltage across the third resistor at this time is output, and the temperature of the gate driver is determined based on the voltage across the third resistor;

[0067] The first resistor is disposed between the TMP pin of the gate driver and the temperature detection circuit, and the first resistor is a thermistor.

[0068] In this embodiment, Figure 2 and Figure 3 Take the example to explain the principle of the temperature acquisition circuit in this solution.

[0069] The temperature detection circuit includes resistors R11 and R22, P-type MOS tubes P1 to P4, N-type MOS tubes N1 to N5, the sources of P1 and P2 are connected to VCC, the gates of P1 and P2 are connected, the drain of P1 is connected to the drain of N1, the drain of P2 is connected to the drain of N2, the gate of N1 is connected to one end of the resistor R, the other end of the resistor R is connected to Vtmp, the gate of N2 is connected to the TMP pin, the sources of N1 and N2 are connected and then connected to the drain of N4, the gates of N3 and N4 are connected, and the sources of N3 and N4 are connected. They are all connected to the VSC1 terminal, the drain of N3 is connected to the current source, and the capacitor C1 is connected between the VT (a reference voltage relative to VCC) terminal and VSC1. The drain of N1 is also connected to the gate of P3, and the source of P3 is connected to VCC. The drain of N3 is also connected to the gate of N5, the drain of P3 is connected to the drain of N5, the source of N5 is connected to the VSC1 terminal, the drain of P3 is connected to the gate of P4, the source of P4 is connected to the TMP pin, and the drain of P4 is connected to the TMP0 pin; the function of R1 and C1 is filtering.

[0070] In this solution, temperature detection is achieved by utilizing the characteristic of thermistor R1 (the thermistor's resistance increases with increasing temperature) by detecting the voltage across the TMP pin R1. A comparison module compares the voltages at points M and N. The negative feedback regulation of P4 adjusts the voltage at point N in the comparison module, i.e., the TMP pin voltage. When the voltages at points M and N are equal, the comparison module is stable. The voltage across R3 is V3 = R3*VT / R1, where V3 is the voltage across the third resistor, R3 is the resistance of the third resistor, VT is the reference voltage relative to VCC designed within the gate driver chip, and R1 is the resistance of the first resistor. Since R1 is a thermistor, its resistance changes with temperature. This change in R1's resistance causes a change in V3, so changes in V3 reflect temperature changes. In the formula, VT is the reference voltage relative to VCC designed within the chip. Feedback regulation ensures that the voltage at the TMP pin is equal to VT. When the chip is operating normally, the voltage VCC-VT is constant (chip design), i.e., the voltage across the thermistor is a fixed value.

[0071] Step S103 : adjusting the real-time voltages of the ISP pin and the ISN pin of the gate driver based on the current detection circuit so that the real-time voltage of the ISP pin is consistent with the real-time voltage of the ISN pin.

[0072] In this embodiment, the real-time voltages of the ISP pin and the ISN pin of the gate driver are adjusted to be equal to each other, thereby ensuring the current safety of the gate driver circuit.

[0073] In order to ensure the current safety of the gate driver circuit, in some embodiments of the present application, the current detection circuit includes a second comparison module, a logic judgment output module, a delay module and a second feedback module. The real-time voltages of the ISP pin and the ISN pin of the gate driver are adjusted based on the current detection circuit to make the real-time voltage of the ISP pin consistent with the real-time voltage of the ISN pin. Specifically,

[0074] comparing voltages across a second resistor by the second comparison module and outputting a second comparison result, wherein the second resistor is arranged between a resistor connected to the ISN pin of the gate driver and a resistor connected to the ISP pin;

[0075] determining, by the logic judgment output module, a current direction across the second resistor based on the second comparison result, and latching the obtained current direction result;

[0076] The second feedback module is activated after a preset delay time by the delay module;

[0077] Feedback regulation is performed through the second feedback module to make the real-time voltage of the ISP pin consistent with the real-time voltage of the ISN pin.

[0078] In this embodiment, Figure 4 As shown, the current detection circuit includes a second comparison module, a logic judgment output module, a delay module and a second feedback module. The second comparison module is used to determine the current direction by detecting the voltage across the resistor R2 when the MOS transistor to be driven is turned on, and send the determination result to the logic judgment output module. The logic judgment output module latches the determination result and outputs it through the DG1 pin. The latched result is cleared after the MOS transistor to be driven is turned off. The delay module starts to delay for a preset time. After the delay ends, the second feedback module is turned on. Through the adjustment of the second feedback module, the voltages of the ISP and ISN pins are made equal.

[0079] In order to further explain the principle of the current detection circuit, we will now explain it in conjunction with a specific circuit diagram, such as Figure 5 Shown is a circuit schematic diagram of a current detection circuit provided by this application.

[0080] The second comparison module includes NMOS transistors MN1 to MN9 and PMOS transistors MP1 to MN3, wherein MN4, MN8, and MN9 are depletion-type NMOS transistors. The gate of MN1 is connected to the ISN pin, the gate of MN2 is connected to the ISP pin, the drains of MN1 and MN2 are connected to the VCC terminal, the sources of MP1, MP2, and MP3 are connected to the VCC terminal, MN3, MN4, MN5, MN8, and MN9 are connected to the VDD terminal, the source of MN1 is connected to the drain of MN4, and the source of MN1 is also connected to the M The gate of N6 is connected, the source of MN2 is connected to the drain of MN5, the source of MN2 is also connected to the gate of MN6, the drain of MN3 is short-circuited with the gate and then connected to the current source, the gates of MN4, MN5, MN8, and MN9 are connected to the current source, the gate and drain of MP1 are short-circuited and connected to the drain of MN6, the drain of MP2 is connected to the drain of MN7, MP1 is connected to the gate of MP2, the sources of MN6 and MN7 are connected to the drain of MN8, the gate of MP3 is connected to the drain of MP2, and the drain of MP3 is connected to the drain of MN9.

[0081] When the MOS transistor to be driven is turned on, the second comparison module determines the current flow direction by detecting the voltage across R2 (i.e., the voltage at points a and b determines the current flow direction. At this time, no current flows through R5 and R6, and Va = VISP; Vb = VISN). When the current flows from point a to point b, the positive input voltage value of the second comparison module is greater than the negative input value, and the second comparison module output DG1 is high. When the current flows from point b to point a, the positive input voltage value is less than the negative input value, and the second comparison module output DG1 is low.

[0082] The logic judgment output module includes a Schmitt trigger, a NOT gate, a NOR gate, and a P-type MOS transistor MP4. The Schmitt trigger U1 is connected to the drain of MP3, and the output end is connected to the input end of the first NOT gate U2. The output end of the first NOT gate U2 serves as one input end of the NOR gate U3. The output end of the NOR gate U4 serves as another input end of U3. The other input end of the NOR gate U4 is the incL signal. The output end of U4 is connected to the input end of U5. The output end of U5 is connected to the gate of MP4. The source of MP4 is connected to VCC, and the other end is connected to the resistor.

[0083] After the second comparison module determines the current direction, it latches the result and outputs it through the DG1 pin (the current direction result latched by the logic judgment module is cleared after the MN1 tube is turned off).

[0084] The delay module includes a P-type MOS transistor MP5 and an N-type MOS transistor MP10, an OR gate, and a NOR gate. The gate of MP5 is connected to the incL signal, the source is connected to the current source, the drain is connected to the source of MN10, the gate of MN10 is connected to the gate of MP5, the drain of MN10 is connected to the Vbb terminal, the input of the NOT gate U6 is connected to the drain of MP5, the output of U6 serves as an input of U7, the gate of MP4 serves as another input of U7, the output of U7 serves as an input of U8, the output of U6 serves as another input of U8, the output of U8 serves as the input of U10, and the output of U7 serves as the input of U9.

[0085] After the logic judgment output module outputs the result, the delay module starts timing for 5us, and the second feedback module is turned on when the timing ends.

[0086] The second feedback module includes P-type MOS tubes MP6 to MP16, N-type MOS tubes MN11 to MN15, resistors, and capacitors. The sources of MP6, MP7, and MP13 are all connected to the VCC terminal, the sources of MN13, MN14, and MN15 are all connected to the VDD terminal, the gate and drain of MP6 are short-circuited, the gate of MP6 is connected to the gate of MP7, the drain of MP6 is connected to the drain of MP8, the drain of MP7 is connected to the drain of MP10, the source of MP8 is connected to the drain of MN12, the source of MP10 is connected to the drain of MN11, the source of MP9 is connected to the drain of MP8, the gate of MP8 and the gate of MP8 are connected to the output terminal of U10, the source of MP11 is connected to the drain of MP10, the gates of MP9 and MP11 are both connected to the output terminal of U9, the gate of MN11 is connected to the ISN pin, and the gate of MN12 is connected to the ISN pin. Connect to the ISP pin, the sources of MN11 and MN12 are connected and then connected to the drain of MN14, the gate and drain of MN13 are short-circuited and then connected to the current source, the gate of MN13 is connected to the gate of MN14, the gate of MN14 is connected to the gate of MN15, the drain of MP7 is connected to the gate of MP12, and a resistor and a capacitor are connected between the gate and drain of MP12 in sequence, the drain of MP12 is connected to the drain of MN15, and the drain of MP12 is also connected to the gates of MP13 and MP15, the gate of MP16 is connected to the output of U10, the gate of MP14 is connected to the output of U9, the drain of MP13 is connected to the source of MP14, the drain of MP15 is connected to the source of MP16, the source of MP13 is connected to the ISP pin, the source of MP15 is connected to the ISN pin, and the drains of MP14 and MP16 are connected and then connected to the CSO pin.

[0087] After the timing is over, the second feedback module is turned on, and through feedback adjustment, VISP is finally made equal to VISN.

[0088] In order to ensure stable operation of the current detection circuit, in some embodiments of the present application, after detecting that the MOS transistor to be driven is turned off, the current direction result latched in the logic judgment output module is cleared.

[0089] In order to output the second comparison result, in some embodiments of the present application, the second comparison module compares the voltages across the second resistor and outputs the second comparison result, specifically:

[0090] When the potential of the first terminal of the second resistor is greater than the potential of the second terminal of the second resistor, the second comparison result is a high level;

[0091] When the potential of the first terminal of the second resistor is less than the potential of the second terminal of the second resistor, the second comparison result is a low level;

[0092] The first end potential is the potential of one end of the second resistor close to the ISP pin of the gate driver connected to the resistor, and the second end potential is the potential of one end of the second resistor close to the ISN pin of the gate driver connected to the resistor.

[0093] In order to determine the direction of the current across the second resistor, in some embodiments of the present application, the logic judgment output module determines the direction of the current across the second resistor based on the second comparison result, and latches the obtained current direction result, specifically as follows:

[0094] When the second comparison result is a high level, the current direction is from the first end of the second resistor to the second end of the second resistor;

[0095] When the second comparison result is a low level, the current direction is from the second end of the second resistor to the first end of the second resistor;

[0096] The first end of the second resistor is an end of the second resistor close to the ISP pin of the gate driver, and the second end of the second resistor is an end of the second resistor close to the ISN pin of the gate driver.

[0097] In order to further improve the safety of the gate driver, in some embodiments of the present application, the gate driver circuit also includes an external resistor and a first capacitor, the first end of the external resistor is connected to the RS terminal of the gate driver, the other end of the external resistor is connected to the ground terminal, one end of the first capacitor is connected to the OUT terminal of the gate driver, and the other end of the first capacitor is connected to the DC power supply of the gate driver. The external resistor is an adjustable resistor, and the charging speed of the first capacitor is adjusted by adjusting the resistance value of the external resistor.

[0098] Step S104 , after detecting that the MOS transistor to be driven is turned off, turning off the temperature detection circuit and the current detection circuit.

[0099] like Figure 7As shown in the figure, the actual effect of this solution is demonstrated. In the figure, the horizontal direction represents time and the vertical direction represents voltage. VCC is the gate driver power supply voltage, out is the output voltage, rs is the boost circuit current detection pin voltage, IN is the enable input pin voltage, and gate is the gate drive pin voltage. At T1, after the power supply V1 is powered on, the boost circuit starts to charge the out pin, the out pin voltage increases, and the rs pin voltage increases. At T2, when the out pin voltage is higher than the power supply voltage of 12.5V (Vout-VCC>12.5V), the boost circuit stops working and there is no output voltage at the rs end. At T3, the IN pin signal is high, the MOS tube to be driven is turned on, and the gate pin voltage Vgate=Vout. After the MOS tube to be driven is turned on, current detection and temperature detection are turned on, which can realize real-time temperature detection and bidirectional current detection. At T4, when IN is low, the N1 tube is turned off, VGS=0, the gate pin voltage Vgate=Vsource, and the current detection and temperature detection are turned off.

[0100] By applying the above technical solution, a gate driver control method and circuit are proposed. The method includes: when it is detected that the MOS transistor to be driven is driven to turn on by the gate driver, starting the temperature detection circuit and the current detection circuit; outputting the voltage across a third resistor through the temperature detection circuit, and determining the temperature of the gate driver based on the voltage across the third resistor, wherein the third resistor is a resistor connected in series between the TMPO pin of the gate driver and the ground terminal; adjusting the real-time voltages of the ISP pin and the ISN pin of the gate driver based on the current detection circuit so that the real-time voltage of the ISP pin is consistent with the real-time voltage of the ISN pin; after detecting that the MOS transistor to be driven is turned off, turning off the temperature detection circuit and the current detection circuit, and monitoring the state of the gate driver in real time by performing temperature detection and current detection on the gate driver, thereby improving the safety of the gate driver.

[0101] The embodiment of the present application also provides a gate driver control circuit, such as Figure 8 As shown, the circuit includes:

[0102] A gate driver circuit, comprising a gate driver and a MOS transistor to be driven, and configured to drive the MOS transistor to be driven through the gate driver;

[0103] a temperature detection circuit, configured to output a voltage across a third resistor through the temperature detection circuit and determine the temperature of the gate driver based on the voltage across the third resistor, wherein the third resistor is a resistor connected in series between the TMPO pin of the gate driver and the ground terminal;

[0104] a current detection circuit, configured to adjust the real-time voltages of the ISP pin and the ISN pin of the gate driver based on the current detection circuit so that the real-time voltage of the ISP pin is consistent with the real-time voltage of the ISN pin;

[0105] The temperature detection circuit and the current detection circuit are respectively connected to the gate driver circuit.

[0106] In summary, this application has the following beneficial effects:

[0107] 1. The solution of this application integrates a boost circuit in the gate driver. During the power-on process, the out pin of the gate driver is charged through the boost circuit. The turn-on delay of the MOS tube to be driven is determined by the charging time of the out pin. During the charging process, the charging speed of the C1 capacitor can be adjusted by adjusting the resistance value of the external resistor Rrs. The turn-on delay of the MOS tube to be driven can be adjusted according to actual application requirements.

[0108] 2. The solution of this application integrates a current detection circuit in the gate driver, and realizes bidirectional current detection through the detection resistor R2 and the fifth pin DG1. When DG1 is high, the current flows from A to B, and when DG1 is low, the current flows from B to A. When the VCC power supply is connected reversely, the output current of the gate driver chip can still be detected in real time.

[0109] 3. The solution of this application integrates a temperature detection circuit in the gate driver, utilizes the temperature-dependent characteristics of thermistor, adjusts the comparison input voltage through negative feedback in the temperature detection circuit, and realizes real-time temperature detection by detecting the voltage across R3.

[0110] 4. It integrates boost circuit, current and temperature detection functions, realizes externally adjustable temperature detection and current detection, and improves the flexibility of system design.

[0111] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0112] In the present invention, unless otherwise expressly specified or limited, the terms "enter," "connect," and "connection" should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0113] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. Throughout this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0114] Although embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are illustrative and are not to be construed as limiting the present invention. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A gate driver control method, characterized in that: Applied to a gate driver control circuit including a gate driver circuit, a temperature detection circuit, and a current detection circuit, the gate driver circuit including a gate driver and a MOS transistor to be driven, the method comprising: When it is detected that the MOS transistor to be driven is driven to turn on by the gate driver, starting the temperature detection circuit and the current detection circuit; outputting a voltage across a third resistor through the temperature detection circuit, and determining the temperature of the gate driver based on the voltage across the third resistor, wherein the third resistor is a resistor connected in series between a TMPO pin of the gate driver and a ground terminal; Adjusting the real-time voltages of the ISP pin and the ISN pin of the gate driver based on the current detection circuit so that the real-time voltage of the ISP pin is consistent with the real-time voltage of the ISN pin; After detecting that the MOS transistor to be driven is turned off, turning off the temperature detection circuit and the current detection circuit; The current detection circuit includes a second comparison module, a logic judgment output module, a delay module and a second feedback module. The real-time voltages of the ISP pin and the ISN pin of the gate driver are adjusted based on the current detection circuit to make the real-time voltage of the ISP pin consistent with the real-time voltage of the ISN pin. Specifically: comparing voltages across a second resistor by the second comparison module and outputting a second comparison result, wherein the second resistor is arranged between a resistor connected to the ISN pin of the gate driver and a resistor connected to the ISP pin; determining, by the logic judgment output module, a current direction across the second resistor based on the second comparison result, and latching the obtained current direction result; The second feedback module is activated after a preset delay time by the delay module; Feedback regulation is performed through the second feedback module to make the real-time voltage of the ISP pin consistent with the real-time voltage of the ISN pin.

2. The method according to claim 1, wherein When it is detected that the MOS transistor to be driven is turned on by the gate driver, the temperature detection circuit and the current detection circuit are started, specifically: When the signal of the IN pin of the gate driver is high, the MOS transistor to be driven is driven to turn on, and the temperature detection circuit and the current detection circuit are started; When the signal of the IN pin of the gate driver is low, the MOS transistor to be driven is driven to be turned off, and the temperature detection circuit and the current detection circuit are turned off.

3. The method according to claim 1, wherein The temperature detection circuit includes a first comparison module and a first feedback module. The temperature detection circuit outputs a voltage across a third resistor, and determines the temperature of the gate driver based on the voltage across the third resistor. Specifically, Collecting the voltage across the first resistor and comparing it with a reference voltage VT set inside the gate driver to obtain a first comparison result; After the first feedback module receives the first comparison result, negative feedback regulation is performed through the P-type MOS transistor in the first feedback module to make the voltage of the first resistor consistent with the reference voltage VT set inside the gate driver, and the voltage across the third resistor at this time is output, and the temperature of the gate driver is determined based on the voltage across the third resistor; The first resistor is disposed between the TMP pin of the gate driver and the temperature detection circuit, and the first resistor is a thermistor.

4. The method according to claim 1, wherein After detecting that the MOS transistor to be driven is turned off, the current direction result latched in the logic judgment output module is cleared.

5. The method according to claim 4, wherein The second comparison module compares the voltages across the second resistor and outputs a second comparison result, specifically: When the potential of the first terminal of the second resistor is greater than the potential of the second terminal of the second resistor, the second comparison result is a high level; When the potential of the first terminal of the second resistor is less than the potential of the second terminal of the second resistor, the second comparison result is a low level; The first end potential is the potential of one end of the second resistor close to the ISP pin of the gate driver connected to the resistor, and the second end potential is the potential of one end of the second resistor close to the ISN pin of the gate driver connected to the resistor.

6. The method according to claim 5, wherein The logic judgment output module determines the current direction of the second resistor based on the second comparison result, and latches the obtained current direction result, specifically: When the second comparison result is a high level, the current direction is from the first end of the second resistor to the second end of the second resistor; When the second comparison result is a low level, the current direction is from the second end of the second resistor to the first end of the second resistor; The first end of the second resistor is an end of the second resistor close to the ISP pin of the gate driver, and the second end of the second resistor is an end of the second resistor close to the ISN pin of the gate driver.

7. The method according to claim 1, wherein The gate driver circuit also includes an external resistor and a first capacitor, wherein a first end of the external resistor is connected to the RS terminal of the gate driver, and the other end of the external resistor is connected to the ground terminal, one end of the first capacitor is connected to the OUT terminal of the gate driver, and the other end of the first capacitor is connected to the DC power supply of the gate driver. The external resistor is an adjustable resistor, and the charging speed of the first capacitor is adjusted by adjusting the resistance value of the external resistor.

8. A gate driver control circuit, characterized in that: The circuit uses the method according to any one of claims 1 to 7, and the circuit comprises: A gate driver circuit, comprising a gate driver and a MOS transistor to be driven, and configured to drive the MOS transistor to be driven through the gate driver; a temperature detection circuit, configured to output a voltage across a third resistor via the temperature detection circuit, and determine the temperature of the gate driver based on the voltage across the third resistor, wherein the third resistor is a resistor connected in series between a TMPO pin of the gate driver and a ground terminal; a current detection circuit, configured to adjust the real-time voltages of the ISP pin and the ISN pin of the gate driver based on the current detection circuit so that the real-time voltage of the ISP pin is consistent with the real-time voltage of the ISN pin; The temperature detection circuit and the current detection circuit are respectively connected to the gate driver circuit.

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