A method for improving the scrapping of mobile phone HDI board caused by the open circuit gap caused by the PP filling depression

Abstract

The present invention discloses a method for improving the open circuit gap caused by the depression of the PP glue filling in the buried holes of the mobile phone HDI board, which is scrapped. The method comprises the following steps: drilling holes on the inner daughter board, and metalizing the holes by copper plating and full-board electroplating in sequence, and producing the inner layer circuit on the inner daughter board; pressing the outer copper foil and the inner daughter board together through a prepreg to form the inner board; drilling a first-order blind hole connected to the adjacent inner layer circuit on both surfaces of the inner board with a controlled depth; first metalizing the first-order blind hole by copper plating, and then performing hole-filling electroplating on the inner board to fill the first-order blind hole, and plating the copper layer on the board surface to a thickness 5μm greater than the designed thickness during the hole-filling electroplating; then removing the 5μm thickened copper layer on the board surface by grinding the board to make the board surface smooth; and producing the sub-outer layer circuit on the inner daughter board. When making the hole-filling electroplating to fill the first-order blind hole, the method of the present invention makes the board surface thicker by 5μm on the basis of the design to fill the pit on the board surface, thereby improving the problem of open circuit gap caused by corrosion in the pit.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board production, and in particular to a method for improving the scrapping of mobile phone HDI boards caused by open circuit gaps and depressions caused by PP glue filling in buried holes. Background Art

[0002] During the production of printed circuit boards, laser blind holes and mechanically drilled through holes are designed in the inner layer of the 2-stage 8-layer mobile phone HDI board. When the inner daughter board (the inner daughter board is a four-layer board) and the copper foil are pressed together to form the inner board (the inner board is a six-layer board), the through holes are filled with PP epoxy resin flow glue. After pressing and filling, the through holes form buried holes. Because there are many through holes drilled in the inner daughter board (144,000 holes per board, and the main drill tip is 0.2mm), when the inner daughter board is pressed together with the copper foil, Taiguang PP glue with a thickness of 52μm and an epoxy resin content of 75% is used to fill the holes. The epoxy glue is fluid, which easily causes the thickness of the dielectric layer on the buried hole to be 3-6μ smaller than the thickness of the dielectric layer in other areas. m, which results in a 3-5μm pit on the surface of the inner layer board corresponding to the buried hole. A first-order blind hole connecting the adjacent inner layer circuit will be drilled on the inner layer board. After the first-order blind hole is filled with hole-filling electroplating, the surface at the hole mouth will also be 3-5μm lower than other board positions. The sub-outer layer circuit made on the inner layer board is a fine circuit (minimum line width / spacing: 50 / 50μm), which requires high resolution (minimum L / S: 25 / 25μm) 25μm thick dry film production. The circuit is wired on the buried hole. The 25μm thick dry film cannot cover the 3-5μm pit, resulting in the pit being corroded by acid etching solution, which in turn causes quality problems such as open circuit gaps. Summary of the Invention

[0003] In response to the above-mentioned existing technical defects, the present invention provides a method for improving the problem of open gaps caused by the depression of PP filling glue in the buried holes of mobile phone HDI boards. When filling the first-order blind holes with electroplating, the board surface is thickened by 5μm based on the design to fill the pits on the board surface, thereby improving the problem of open gaps caused by corrosion in the pits.

[0004] In order to solve the above technical problems, the present invention provides a method for improving the scrapping of open circuit gaps caused by the depression of PP glue filling in buried holes of mobile phone HD I boards, comprising the following steps:

[0005] S1. Drill holes on the inner daughter board, and metalize the holes by copper deposition and full-board electroplating in sequence, and then make the inner layer circuit on the inner daughter board;

[0006] S2, press the outer copper foil and the inner sub-board together through the prepreg to form the inner board;

[0007] S3, using laser to drill a controlled depth on both surfaces of the inner layer board to connect with the adjacent inner layer circuits;

[0008] S4. First, the first-order blind holes are metalized by copper plating, and then the inner layer board is electroplated to fill the first-order blind holes. During the electroplating, the thickness of the copper layer on the board surface is plated to 5μm greater than the designed thickness.

[0009] S5, then remove the 5μm thickened copper layer on the board surface by grinding the board to make the board surface smooth;

[0010] S6. Then, a sub-outer layer circuit is produced on the inner daughter board.

[0011] Furthermore, in step S4, segmented electroplating is adopted for hole filling electroplating, and the segmented electroplating includes seven stages, as follows: the first stage electroplating time is 6 minutes, the current density is 1.44ASD; the second stage electroplating time is 6 minutes, the current density is 1.44ASD; the third stage electroplating time is 8 minutes, the current density is 2.16ASD; the fourth stage electroplating time is 8 minutes, the current density is 2.16ASD; the fifth stage electroplating time is 8 minutes, the current density is 2.16ASD; the sixth stage electroplating time is 7 minutes, the current density is 1.8ASD; the seventh stage electroplating time is 7 minutes, the current density is 1.8ASD.

[0012] Furthermore, the jet frequency during the electroplating in the first to third stages is 120 Hz, the jet frequency during the electroplating in the fourth and fifth stages is 100 Hz, and the jet frequency during the electroplating in the sixth and seventh stages is 80 Hz.

[0013] Furthermore, in step S5, non-woven fabric is used to brush the inner layer plate during plate grinding.

[0014] Furthermore, in step S6, a dry film is first applied to the surface of the inner layer board, and then a sub-outer layer circuit pattern is formed by exposure and development in sequence, exposing the copper surface at the non-circuit pattern portion, and etching is performed to obtain the sub-outer layer circuit, and then the dry film is removed.

[0015] Furthermore, in step S6, a sub-outer layer circuit is produced on the inner layer board by applying a wet film.

[0016] Furthermore, in step S6, a layer of 16-18 μm thick ink is first coated on the surface of the inner layer board, and then the ink is pre-cured by baking, and then the sub-outer layer circuit pattern is formed by exposure and development in sequence, exposing the copper surface of the non-circuit pattern part, and the sub-outer layer circuit is obtained after etching, and then the ink is removed.

[0017] Furthermore, a segmented baking plate is used for pre-curing the ink; the conditions for the segmented baking plate are baking at 80°C for 1 minute, baking at 90°C for 1.5 minutes, baking at 100°C for 2 minutes, baking at 105°C for 2 minutes, baking at 90°C for 2 minutes, and baking at 70°C for 1.5 minutes.

[0018] Furthermore, after step S6, the following steps are also included:

[0019] S7, pressing the outer copper foil and the inner layer board together through the prepreg to form a production board;

[0020] S8. Drilling a second-order blind hole on both surfaces of the production board with a controlled depth by laser, the second-order blind hole being connected to the adjacent sub-outer layer circuit;

[0021] S9, first metallizing the second-order blind vias by copper deposition, and then performing hole-filling electroplating on the production board to fill the second-order blind vias;

[0022] S10, and then use negative and positive film processes to produce outer layer circuits on the production board.

[0023] Furthermore, the inner layer board is a multilayer board in which a core board and an outer layer of copper foil are pressed together by a prepreg, and an inner layer circuit is made on the core board before pressing.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] In the present invention, when filling the first-order blind vias by hole-filling electroplating, the board surface is thickened by 5 μm on the basis of the design to fill the pits on the board surface, thereby improving the open gap problem caused by corrosion at the pits, that is, the board surface is thickened as a whole, and even the board surface corresponding to the buried vias and blind vias is thickened by 5 μm. The pits in the board surface are filled with the thickened copper layer, and then the 5 μm thickened copper layer in the board surface is removed by grinding the board, that is, the thickened portion of the board surface copper layer outside the buried vias and blind vias is removed, so that the entire board surface is flat and free of pits, solving the open gap problem caused by corrosion during subsequent circuit etching due to the presence of pits on the board surface; of course, when the depth of the pits is less than 5 μm, the excess board surface copper layer corresponding to the buried vias and blind vias will also be ground away during grinding. It is only necessary to ensure that the overall board surface copper layer is flat and meets the thickness required by the design. DETAILED DESCRIPTION

[0026] In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further introduced and illustrated in conjunction with specific embodiments below.

[0027] Example 1

[0028] This embodiment shows a method for manufacturing an eight-layer mobile phone HDI board, which can improve the problem of open circuit gaps and scrap caused by PP glue filling depression in buried vias of mobile phone HDI boards. The method includes the following processing steps in sequence:

[0029] (1) Cutting: Cut the core board according to the panel size of 520mm×620mm. The thickness of the core board is 0.5mm, and the thickness of the copper layer on both surfaces of the core board is 0.5oz.

[0030] (2) Inner layer circuit production (negative film process): Inner layer pattern transfer, use a vertical coating machine to coat the photosensitive film, the film thickness of the photosensitive film is controlled at 8μm, and a fully automatic exposure machine is used to complete the exposure of the inner layer circuit with a 5-6 grid exposure ruler (21 grid exposure ruler), and the inner layer circuit pattern is formed after development; inner layer etching, the exposed and developed core board is etched to etch the inner layer circuit, and the inner layer line width is measured to be 3mil; inner layer AOI, and then check the inner layer circuit for defects such as open and short circuits, circuit gaps, and circuit pinholes. Defective products will be scrapped, and products without defects will be sent to the next process.

[0031] (3) Lamination: The browning speed is based on the bottom copper thickness. The core board, prepreg, and outer copper foil are laminated in sequence as required. Then, appropriate lamination conditions are selected according to the Tg of the sheet material to press the laminated board to form the inner layer sub-board.

[0032] (4) Drilling: Based on the existing drilling technology, drilling is performed on the inner sub-board according to the design requirements.

[0033] (5) Copper plating: A thin layer of copper is deposited on the board surface and the hole wall using the chemical copper plating method. The backlight test is level 10, and the thickness of the copper plating in the hole is 0.5μm.

[0034] (6) Full-board electroplating: Full-board electroplating is performed at a current density of 18ASF for 120 minutes to thicken the copper layer on the hole and the board surface.

[0035] (7) Inner layer circuit production (negative film process): Inner layer pattern transfer, use a vertical coating machine to coat the photosensitive film, the film thickness of the photosensitive film is controlled at 8μm, and a fully automatic exposure machine is used to complete the exposure of the inner layer circuit with a 5-6 grid exposure ruler (21 grid exposure ruler), and the inner layer circuit pattern is formed after development; inner layer etching, the inner layer sub-board after exposure and development is etched out of the inner layer circuit, and the inner layer line width is measured to be 3mil; inner layer AO I, and then check the inner layer circuit for defects such as open and short circuits, circuit gaps, and circuit pinholes. Defective products will be scrapped, and products without defects will be sent to the next process.

[0036] (8) Lamination: The browning speed is based on the bottom copper thickness. The inner layer sub-board, prepreg, and outer copper foil are stacked in sequence as required. Then, appropriate lamination conditions are selected according to the Tg of the sheet material to press the laminated board to form the inner layer board. During the lamination, the through holes on the inner layer sub-board are filled with flow glue. After lamination, the through holes on the inner layer sub-board are formed into buried holes.

[0037] (9) Drilling blind holes: Use laser to control the depth of the two surfaces of the inner layer board to drill a first-order blind hole that connects to the adjacent inner layer circuit.

[0038] (10) Copper plating: A thin layer of copper is deposited on the board surface and the hole wall using the chemical copper plating method. The backlight test is level 10, and the thickness of the copper plating in the hole is 0.5μm.

[0039] (11) Full board electroplating: The inner layer board is subjected to hole filling electroplating to fill the first-order blind holes, and the thickness of the copper layer on the board surface is plated to 5μm thicker than the design thickness during the hole filling electroplating process. That is, during the hole filling electroplating process, the thickness of the copper layer on the board surface is thickened by 5μm on the basis of the design to fill the pits at the corresponding buried holes and blind holes.

[0040] In the above, in order to simultaneously achieve the purpose of filling the blind hole and thickening the copper layer on the board surface, the segmented electroplating method is adopted during the hole filling electroplating, and the segmented electroplating includes seven stages, as follows: the first stage electroplating time is 6 minutes, the current density is 1.44ASD; the second stage electroplating time is 6 minutes, the current density is 1.44ASD; the third stage electroplating time is 8 minutes, the current density is 2.16ASD; the fourth stage electroplating time is 8 minutes, the current density is 2.16ASD; the fifth stage electroplating time is 8 minutes, the current density is 2.16ASD; the sixth stage electroplating time is 7 minutes, the current density is 1.8ASD; the seventh stage electroplating time is 7 minutes, the current density is 1.8ASD.

[0041] Preferably, the jet frequency during the first to third stages of electroplating is 120 Hz, the jet frequency during the fourth and fifth stages of electroplating is 100 Hz, and the jet frequency during the sixth and seventh stages of electroplating is 80 Hz.

[0042] (12) Grinding the board: Use non-woven cloth to brush the inner layer of the board to remove the 5μm thickened copper layer on the board surface to make the board surface smooth.

[0043] In the above, the grinding brush configuration from front to back is: 2 pairs of 600# high-cut non-woven fabrics + 2 pairs of 800# high-cut non-woven fabrics + 2 pairs of 1200# ordinary non-woven fabrics, the plate conveying speed is 2.5m / min, the current pressure is 2A, the plate is ground twice, and the plate is turned over for the second grinding, that is, after the first grinding, the inner layer plate needs to be turned over before the second grinding.

[0044] (13) Making the sub-outer circuit (negative film process): First, apply a layer of 16-18μm thick ink on the surface of the inner layer board, then pre-cure the ink by baking, and then use the DI exposure machine to expose and develop to form the sub-outer circuit pattern, exposing the copper surface of the non-circuit pattern part, and then etching to obtain the sub-outer circuit, and then remove the ink.

[0045] In the above, ink viscosity: use No. 3 flow cup to test for 90 seconds; use 500# coating roller to apply ink on the board surface, and the scraper pressure when applying ink is 1.0kg / cm 2 , the coating speed is 9m / min.

[0046] In the above, a segmented baking plate is used for pre-curing the ink; the conditions for the segmented baking plate are baking at 80°C for 1 minute, baking at 90°C for 1.5 minutes, baking at 100°C for 2 minutes, baking at 105°C for 2 minutes, baking at 90°C for 2 minutes, and baking at 70°C for 1.5 minutes.

[0047] In the above description, the exposure energy during exposure is based on a 19-step exposure scale (a total exposure scale of 41 levels).

[0048] In the above, vacuum spray etching is used during etching, and the pressure of the upper spray is 2.2kg / cm 2 The pressure of the downward spray is 1.8kg / cm 2 , the conveying speed of the board is 5m / min.

[0049] In the above, the board surface is pre-treated before applying the ink, that is, the board surface is micro-etched with an ultra-roughening solution to roughen the board surface and improve the bonding strength between the board surface and the ink in the later stage. The micro-etching amount is controlled at 0.8-1.2μm. After micro-etching, the inner layer board is dried at 85℃.

[0050] (14) Lamination: The browning speed is based on the bottom copper thickness. The inner layer board, prepreg sheet and outer copper foil are laminated in sequence as required. Then, appropriate lamination conditions are selected according to the Tg of the board material to press the laminated board to form a production board.

[0051] (15) Drilling blind holes: Use laser to control the depth of drilling on both surfaces of the production board to form second-order blind holes that connect to the adjacent sub-outer layer circuits.

[0052] (16) Copper plating: A thin layer of copper is deposited on the board surface and hole wall by using the chemical copper plating method. The backlight test is level 10, and the thickness of the copper plating in the hole is 0.5μm.

[0053] (17) Full board electroplating: The production board is fully electroplated according to the design requirements to increase the thickness of the hole copper and the board surface copper layer.

[0054] (18) Production of outer layer circuits (positive film process): Transfer of outer layer pattern, using fully automatic exposure machine and positive film circuit film, with 5-7 grid exposure scale (21 grid exposure scale) to complete the exposure of outer layer circuit, after development, the outer layer circuit pattern is formed on the production board; electroplating of outer layer pattern, and then copper plating and tin plating on the production board respectively, setting the electroplating parameters according to the required copper thickness, copper plating is 1.8ASD current density electroplating for 60 minutes on the whole board, tin plating is 1.2ASD current density electroplating for 10 minutes, tin thickness 3-5μm; then stripping, etching and tin stripping are carried out in sequence to etch the outer layer circuit on the production board; outer layer AOI, using automatic optical inspection system, by comparing with CAM data, detect whether the outer layer circuit has defects such as open circuit, gap, incomplete etching, short circuit, etc.

[0055] (19) Solder mask and silk screen characters: After silk screen printing solder mask ink on the surface of the multilayer board, it is sequentially processed through pre-curing, exposure, development and heat curing to solidify the solder mask ink into a solder mask layer; specifically, the solder mask ink and the characters on the TOP surface are added with "UL mark", so that a layer is coated on the circuits and substrates that do not need to be soldered to prevent bridging between circuits during soldering, provide a permanent electrical environment and chemical corrosion resistance, and at the same time beautify the appearance.

[0056] (20) Surface treatment (nickel-gold deposition): The copper surface of the pad at the solder mask window position is chemically deposited with a nickel layer and a gold layer of a certain required thickness. The nickel layer thickness is 3-5μm; the gold layer thickness is 0.05-0.1μm.

[0057] (21) Electrical test: Test the electrical conductivity of the finished board. The test method used for this board is: flying probe test.

[0058] (22) Molding: According to the existing technology and the design requirements, the shape of the gong is made with an external tolerance of + / -0.05mm to produce an eight-layer mobile phone HDI board.

[0059] (23) FQC: Inspect the appearance of the HDI board according to the customer's acceptance standards and our inspection standards. If there are any defects, repair them in time to ensure that we provide customers with excellent quality control.

[0060] (24) FQA: Re-test the appearance, hole copper thickness, dielectric layer thickness, green oil thickness, inner layer copper thickness of the HDI board to see if they meet customer requirements.

[0061] (25) Packaging: The HDI board is sealed and packed according to the packaging method and packaging quantity required by the customer, and desiccant and humidity card are placed before shipment.

[0062] Example 2

[0063] The present embodiment shows a method for manufacturing an eight-layer mobile phone HDI board, which can improve the problem of open circuit gaps and scrap caused by the PP filler concavity of the buried holes of the mobile phone HDI board. The processing steps are basically the same as those in Example 1, except for the step (13) of manufacturing the sub-outer layer circuit, which is as follows:

[0064] (13) Making the sub-outer layer circuit (negative film process): First, a 25 μm thick dry film is applied to the inner layer board surface, and then the sub-outer layer circuit pattern is formed by exposure and development in sequence, exposing the copper surface of the non-circuit pattern part, and then etching to obtain the sub-outer layer circuit, and then the dry film is removed.

[0065] The technical solutions provided by the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the embodiments of the present invention. The description of the above embodiments is only applicable to help understand the principles of the embodiments of the present invention. At the same time, for those skilled in the art, according to the embodiments of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A method for improving the scrapping of open circuit gaps caused by the depression of PP glue filling in buried holes of mobile phone HDI boards, characterized in that: The following steps are involved: S1. Drill holes on the inner daughter board, and metalize the holes by copper deposition and full-board electroplating in sequence, and then make the inner layer circuit on the inner daughter board; S2, press the outer copper foil and the inner sub-board together through the prepreg to form the inner board; S3, using laser to drill a controlled depth on both surfaces of the inner layer board to connect with the adjacent inner layer circuits; S4. First, the first-order blind holes are metalized by copper plating, and then the inner layer board is filled with hole plating to fill the first-order blind holes. During the hole filling electroplating, the thickness of the copper layer on the board surface is plated to 5μm greater than the designed thickness. The hole filling electroplating adopts a segmented electroplating method, which includes seven stages, as follows: the first stage electroplating time is 6 minutes, the current density is 1.44ASD; the second stage electroplating time is 6 minutes, the current density is 1.44ASD; the third stage electroplating time is 8 minutes, the current density is 2.16ASD; The fourth stage electroplating time is 8 minutes, the current density is 2.16ASD; the fifth stage electroplating time is 8 minutes, the current density is 2.16ASD; the sixth stage electroplating time is 7 minutes, the current density is 1.8ASD; the seventh stage electroplating time is 7 minutes, the current density is 1.8ASD; the jet frequency during the first to third stages electroplating is 120HZ, the jet frequency during the fourth and fifth stages electroplating is 100HZ, and the jet frequency during the sixth and seventh stages electroplating is 80HZ; S5, then remove the 5μm thickened copper layer on the board surface by grinding the board to make the board surface smooth; S6, then make the sub-outer layer circuit on the inner daughter board; S7, pressing the outer copper foil and the inner layer board together through the prepreg to form a production board; S8. Drilling a second-order blind hole on both surfaces of the production board with a controlled depth by laser, the second-order blind hole being connected to the adjacent sub-outer layer circuit; S9, first metallizing the second-order blind vias by copper deposition, and then performing hole-filling electroplating on the production board to fill the second-order blind vias; S10, and then use the positive film process to produce the outer layer circuit on the production board.

2. The method for improving the scrapping of open circuit gaps caused by PP glue filling depression in buried vias of mobile phone HDI boards according to claim 1 is characterized in that: In step S5, the inner layer plate is brushed with non-woven fabric during plate grinding.

3. The method for improving the scrapping of open circuit gaps caused by PP glue filling depression in buried vias of mobile phone HDI boards according to claim 1, characterized in that: In step S6, a dry film is first applied to the inner layer board surface, and then a sub-outer layer circuit pattern is formed by sequentially exposing and developing, exposing the copper surface of the non-circuit pattern portion, and etching is performed to obtain the sub-outer layer circuit, and then the dry film is removed.

4. The method for improving the scrapping of open circuit gaps caused by PP glue filling depression in buried vias of mobile phone HDI boards according to claim 1, characterized in that: In step S6, a sub-outer layer circuit is produced on the inner layer board by applying a wet film.

5. The method for improving the scrapping of open circuit gaps caused by PP glue filling depression in buried vias of mobile phone HDI boards according to claim 4 is characterized in that: In step S6, a layer of 16-18 μm thick ink is first coated on the surface of the inner layer board, and then the ink is pre-cured by baking. Then, the sub-outer layer circuit pattern is formed by exposure and development in sequence, exposing the copper surface of the non-circuit pattern part. After etching, the sub-outer layer circuit is obtained, and then the ink is removed.

6. The method for improving the scrapping of open circuit gaps caused by PP glue filling depression in buried vias of mobile phone HDI boards according to claim 5, characterized in that: A segmented baking plate is used for pre-curing the ink; the segmented baking plate conditions are baking at 80°C for 1 minute, baking at 90°C for 1.5 minutes, baking at 100°C for 2 minutes, baking at 105°C for 2 minutes, baking at 90°C for 2 minutes, and baking at 70°C for 1.5 minutes.

7. The method for improving the scrapping of open circuit gaps caused by PP glue filling depression in buried vias of mobile phone HDI boards according to claim 1, characterized in that: The inner layer sub-board is a multi-layer board in which a core board and an outer layer of copper foil are pressed together by a prepreg, and the inner layer circuit is made on the core board before pressing.