Voltage holding device and electronic device using the same

Abstract

The application provides a voltage holding device and an electronic device using the same. The voltage holding device uses a hysteresis voltage of a hysteresis comparator to update the charge of a capacitor efficiently and pursue lower power consumption. On the other hand, because the advanced voltage holding circuit pursues lower power consumption, the refresh time must be designed to be longer, which results in the inability to perform a large amount of yield tests. However, the technical solution provided by the application can cooperate with related application circuits to greatly shorten the test time, increase the testability and reliability of the voltage holding device.

Description

Technical Field

[0001] This invention relates to a voltage holding device and electronic devices using the same, and more particularly to a voltage holding device and electronic devices using the same that enable rapid testing and have high voltage accuracy. Background Technology

[0002] Traditional voltage hold-up circuits use a clock signal to update the charge and maintain voltage accuracy. With increasingly stringent requirements for voltage accuracy, environmental influences on the charge force users to select the shortest possible refresh time, which prevents more efficient reduction of power consumption. Furthermore, advanced voltage hold-up circuits, aiming for lower power consumption, have longer refresh times, hindering extensive yield testing and reducing the testability and reliability of the circuit.

[0003] Please refer to Figure 1 , Figure 1 This is a circuit diagram of a conventional voltage holding circuit. The voltage holding circuit 100 includes two PMOS transistors MP1 and MP2, two capacitors C1 and C2, and two diodes D1 and D2. By controlling PMOS transistors MP1 and MP2 with the control signal CS1, MP1 and MP2 can be turned on or off, thereby charging capacitor C1 with the input voltage Vin and charging capacitor C2 with the voltage Vh, or discharging capacitors C1 and C2. The voltage holding circuit 100 outputs a voltage Nout held by capacitor C2. Furthermore, when PMOS transistors MP1 and MP2 are on, the voltage Nout held by capacitor C2 is equal to the voltage Vin; when PMOS transistors MP1 and MP2 are off, the voltage Nout held by capacitor C2 deviates from the predetermined voltage value due to the leakage current of PMOS transistors MP1 and MP2. When the leakage current is very small, although the voltage Nout held by capacitor C2 will not deviate from the predetermined voltage value quickly, in order to ensure the requirement of high voltage accuracy, the voltage holding circuit 100 must use a shorter refresh time, which results in power consumption not being reduced more efficiently.

[0004] Please refer to Figure 2 , Figure 2This is a circuit diagram of a conventional voltage holding device. The voltage holding device 300 includes a voltage generation circuit 310, a reference current generation circuit 320, capacitors C1 and C2, switches S1 and S2, a hysteresis comparator 330, and control logic 340. In this embodiment, the hysteresis comparator 330 compares voltages V1 and V2 and determines whether the voltage difference reaches the hysteresis voltage V_hys of the hysteresis comparator 330 to generate a comparison result signal. The control logic 340 controls the voltage Vin generated by the voltage generation circuit 310 and controls the switching on and off of switches S1 and S2 based on the comparison result signal. The voltage generation circuit 310 generates the voltage Vin based on the reference current IEF provided by the reference current generation circuit 320 and the comparison result signal.

[0005] Please refer to the following at the same time Figure 2 and Figure 3 , Figure 3 yes Figure 2 The waveform diagram shows a portion of the signal from the voltage holding device. During the holding period t_hold, switches S1 and S2 are closed. The voltage Vin generated by the voltage generation circuit 310 is greater than the reference voltage V_ref. Therefore, the leakage current of switches S1 and S2 can charge capacitors C1 and C2, causing the voltages V1 and V2 on capacitors C1 and C2 to rise from the reference voltage V_ref. Because the capacitances of capacitors C1 and C2 are different, their charging speeds are different. Correspondingly, the voltage difference between capacitors C1 and C2 increases over time. After the voltage difference between V1 and V2 reaches the hysteresis voltage V_hys of the hysteresis comparator 330, the comparison result signal changes state, causing the control logic 340 to turn on switches S1 and S2, and the voltage holding device 300 enters the sampling period t_sample. During the sampling period t_sample, the voltage value of the voltage Vin generated by the voltage generation circuit 310 is equal to the voltage value of the reference voltage V_ref. The voltages V1 and V2 will start to drop to the voltage value of the reference voltage V_ref. Then, after the voltages V1 and V2 drop to the voltage value of the reference voltage V_ref, the comparison result signal changes state, causing the control logic 340 to close the switches S1 and S2, and the voltage holding device 300 re-enters the holding period t_hold.

[0006] During the hold period t_hold, the leakage current charges capacitors C1 and C2, causing voltages V1 and V2 to rise. The voltage difference between V1 and V2 must reach the hysteresis voltage V_hys before the comparison result signal of the hysteresis comparator 330 changes state. Therefore, the voltage holding device 300 needs to spend a relatively long time holding, which reduces the refresh rate. Furthermore, voltage V1 must rise to a certain value before the voltage difference between V1 and V2 reaches the hysteresis voltage V_hys. Therefore, the voltage generation circuit 310 must output a higher voltage Vin to charge capacitors C1 and C2. Figure 2 and Figure 3 If the reference voltage V_ref is 1.2 volts, then the supply voltage of the low-dropout regulator (LDO) must be 1.5 times 1.2 volts, or 1.8 volts. If the capacitance of capacitor C2 is designed to be 10 times that of capacitor C1, the hysteresis voltage V_hys is 50 millivolts, and the leakage current through switch S1 is 0.12 times the leakage current through switch S2, the maximum voltage V2 is 1.45 volts. This means the LDO must output a supply voltage of 2.175 volts, which exceeds 110% of 1.8 volts (1.98 volts). Therefore, the voltage holding device 300 would cause the LDO operating at low voltages to burn out. Summary of the Invention

[0007] This invention provides a voltage holding device, comprising a first voltage holding circuit, a second voltage holding circuit, a first input voltage selection device, a second input voltage selection device, and a voltage difference detector. The first voltage holding circuit has a first capacitor, a first input terminal, and a first output terminal for generating a first voltage. The first capacitor is electrically connected between a low voltage source and the first output terminal, and the on / off state of the first input terminal and the first output terminal is determined by a switch control signal. The second voltage holding circuit has a second capacitor, a second input terminal, and a second output terminal for generating a second voltage. The second capacitor is electrically connected between a low voltage source and the second output terminal, and the on / off state of the second input terminal and the second output terminal is determined by a switch control signal. The first input voltage selection device is electrically connected to the first input terminal and selectively provides one of a reference voltage, a test reference voltage, and a system high voltage to the first input terminal as a first input voltage. The second input voltage selection device is electrically connected to the second input terminal and selectively provides one of a system low voltage and a reference voltage to the first input terminal as a second input voltage. The voltage difference detector is electrically connected to the first voltage holding circuit and the second voltage holding circuit. It is used to detect the voltage difference between the first voltage and the second voltage and generate a switch control signal based on the voltage difference.

[0008] This invention also provides an electronic device using the voltage holding device described above, the electronic device including the aforementioned voltage holding device and a system circuit electrically connected to the voltage holding device.

[0009] In summary, compared with prior art, the voltage holding device provided by the present invention has lower power consumption and can increase the testability and reliability of the voltage holding device. It can even allow the use of low-dropout regulators that operate at low voltage without burning out the low-dropout regulators.

[0010] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0011] The accompanying drawings are provided to enable those skilled in the art to further understand the invention and are incorporated in and constitute a part of the specification of the invention. The drawings illustrate exemplary embodiments of the invention and are used together with the specification to explain the principles of the invention.

[0012] Figure 1 This is a circuit diagram of a traditional voltage holding circuit.

[0013] Figure 2 This is a circuit diagram of a traditional voltage holding device.

[0014] Figure 3 yes Figure 2 The waveform diagram of some signals of the voltage holding device.

[0015] Figure 4 This is a circuit diagram of a voltage holding device according to an embodiment of the present invention.

[0016] Figure 5 This is a waveform diagram of some signals of the voltage holding device in operation mode according to an embodiment of the present invention.

[0017] Figure 6 This is a waveform diagram of some signals of the voltage holding device in test mode according to an embodiment of the present invention.

[0018] Figure 7 This is another waveform diagram of some signals of the voltage holding device in operation mode according to an embodiment of the present invention.

[0019] 100, 410, 420: Voltage holding circuit

[0020] 300, 400: Voltage holding devices

[0021] 310: Voltage generation circuit

[0022] 320: Reference current generation circuit

[0023] 330, 431: Hysteresis comparators

[0024] 340: Control Logic

[0025] 430: Voltage Difference Detector

[0026] 440, 450: Input voltage selection device

[0027] AVDD: System High Voltage

[0028] AVSS: System Low Voltage

[0029] C1, C2: Capacitors

[0030] CS1: Control signal

[0031] D1, D2: Diodes

[0032] IREF: Reference Current

[0033] MP1, MP2: PMOS transistors

[0034] Nout, V1, V2, Vh, Vin: Voltage

[0035] V_hys: Hysteresis voltage

[0036] V_ref: Reference voltage

[0037] V_test: Test reference voltage

[0038] S1, S2: Switches

[0039] SE1, SE2, SE3: Selectors

[0040] SW: Switch control signal

[0041] t0, t1, t3: Time points

[0042] t_hold: Hold period

[0043] t_sample: sampling period Detailed Implementation

[0044] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same element symbols are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the invention, and the following examples are not intended to limit the scope of the invention.

[0045] To address the problems of prior art, the technical solution proposed in this invention utilizes whether a voltage difference reaches the hysteresis voltage of a hysteresis comparator to efficiently update the capacitor's charge and achieve lower power consumption. On the other hand, advanced voltage holding circuits, in pursuit of lower power consumption, must have longer refresh times, making extensive yield testing impossible. However, the technical solution proposed in this invention, when used with relevant application circuits, can significantly shorten testing time, increasing the testability and reliability of voltage holding devices.

[0046] Furthermore, the technical solution proposed in this invention uses two voltage holding circuits. These two voltage holding circuits use two currents with the same direction to charge and discharge two capacitors respectively. A voltage difference detector, such as a hysteresis comparator, detects the voltage difference between the two capacitors. The hysteresis voltage can be set to the required voltage holding accuracy. Then, a switching control signal generated by the voltage difference detector is used to switch the two voltage holding circuits on and off to update the charge of the two capacitors. Therefore, when the current charges the capacitors, and the capacitors are affected by process, voltage, and temperature (PVT), the refresh time will also be adjusted accordingly. That is, the technical solution proposed in this invention can maintain high voltage accuracy by relying on accurate hysteresis voltage. Moreover, during testing, two sets of voltage holding circuits and two large currents with the same direction are used to directly measure whether the hysteresis voltage designed by the voltage difference detector meets expectations. That is, the voltage change is directly judged to quickly detect whether the voltage accuracy is suitable for use.

[0047] First, please refer to Figure 4 , Figure 4 This is a circuit diagram of a voltage holding device according to an embodiment of the present invention. The voltage holding device 400 includes voltage holding circuits 410 and 420, a voltage difference detector 430, and input voltage selection devices 440 and 450. The voltage holding device 400 can operate in either an operating mode or a test mode. In operating mode, the voltage holding device 400 performs general operation, sampling and holding, so that the steady-state reference voltage V_ref at the output terminals of voltage holding circuits 410 and 420 is sampled. The voltage holding device 400 maintains high voltage accuracy by controlling voltage holding circuits 410 and 420 through the voltage difference detector 430. In test mode, the voltage holding device 400 performs detection operation, quickly detecting whether the voltage accuracy is suitable for use.

[0048] The voltage holding circuit 410 has a capacitor C1, an input terminal, and an output terminal for generating a voltage V1. The capacitor C1 is electrically connected between a low voltage (e.g., ground voltage) and the output terminal of the voltage holding circuit 410, and the on / off state of the input and output terminals of the voltage holding circuit 410 is determined by a switch control signal SW. For example, this can be implemented by controlling a PMOS transistor MP1 located between the input and output terminals of the voltage holding circuit 410 using the switch control signal SW. The PMOS transistor MP1 has a drain as the input terminal of the voltage holding circuit 410, a gate that receives the switch control signal SW, and a source as the output terminal of the voltage holding circuit 410. The PMOS transistor MP1 can be implemented using other types of transistors or switching switches, and the present invention is not limited thereto.

[0049] The voltage holding circuit 420 has a capacitor C2, an input terminal, and an output terminal for generating a voltage V2. The capacitor C2 is electrically connected between the low voltage and the output terminal of the voltage holding circuit 420. The on / off state of the input and output terminals of the voltage holding circuit 420 is determined by a switch control signal SW, for example, by controlling a PMOS transistor MP2 located between the input and output terminals of the voltage holding circuit 420 using the switch control signal SW. The PMOS transistor MP2 has a drain serving as the input terminal of the voltage holding circuit 420, a gate receiving the switch control signal SW, and a source serving as the output terminal of the voltage holding circuit 420. The PMOS transistor MP2 can be implemented using other types of transistors or switching switches, and the present invention is not limited thereto.

[0050] Voltage difference detector 430 is electrically connected to voltage holding circuits 410 and 420. Voltage difference detector 430 detects the voltage difference between voltages V1 and V2 and generates a switching control signal SW based on the voltage difference. Voltage difference detector 430 can be a hysteresis comparator 431 and has a hysteresis voltage V_hys. When the voltage difference rises from zero to the hysteresis voltage V_hys, the switching control signal SW output by voltage difference detector 430 changes from a logic high level to a logic low level. The period from the voltage difference rising from zero to the hysteresis voltage V_hys is the holding period t_hold. When the voltage difference drops from the hysteresis voltage V_hys to zero, the switching control signal SW output by voltage difference detector 430 changes from a logic low level to a logic high level. The period from the voltage difference dropping from the hysteresis voltage V_hys to zero is the sampling period t_sample. Of course, the present invention is not limited to the implementation of the voltage difference detector 430 with the hysteresis comparator 431 as the implementation method, and other types of voltage difference detection devices may also be used to implement the function of the voltage difference detector 430.

[0051] The input voltage selection device 440 is electrically connected to the input terminal of the voltage holding circuit 410, and is used to selectively provide one of the reference voltage V_ref, the test reference voltage V_test, and the system high voltage AVDD to the input terminal of the voltage holding circuit 410 as the input voltage. The input voltage selection device 440 includes selectors SE1 and SE2. The output terminal of selector SE1 is electrically connected to the input terminal of the voltage holding circuit 410. The two input terminals of selector SE1 are respectively electrically connected to the system high voltage AVDD and the output terminal of selector SE2. The two input terminals of selector SE2 are respectively electrically connected to the reference voltage V_ref and the test reference voltage V_test. In other implementations, the combination of selectors SE1 and SE2 can be replaced by a selector with three input terminals and one output terminal. In summary, the implementation of the input voltage selection device 440 is not intended to limit the invention.

[0052] The input voltage selection device 450 is electrically connected to the input of the voltage holding circuit 420, and is used to selectively provide either the system low voltage AVSS or the reference voltage V_ref to the input of the voltage holding circuit 420 as the input voltage. The input voltage selection device 450 includes a selector SE3, the output of which is electrically connected to the input of the voltage holding circuit 420, and the two inputs of the selector SE3 are electrically connected to the system low voltage AVSS and the reference voltage V_ref, respectively.

[0053] Please refer to the following at the same time Figure 4 and Figure 5 , Figure 5 This is a waveform diagram of some signals of the voltage holding device in operation mode according to an embodiment of the present invention. In operation mode, the voltage V1 of the voltage holding device 400 rises from the reference voltage V_ref between time points t0 and t1, and the voltage V2 of the voltage holding device 400 falls from the reference voltage V_ref between time points t0 and t1. The period between time points t0 and t1 is the holding period t_hold. The switch control signal SW is at a logic high level to turn off PMOS transistors MP1 and MP2. The drain of PMOS transistor MP1 is connected to the system high voltage AVDD through selector SE1, and the drain of PMOS transistor MP2 is connected to the system low voltage AVSS through selector SE3. This allows the leakage current of PMOS transistor MP1 to charge capacitor C1 through the system high voltage AVDD, and the leakage current of PMOS transistor MP2 to discharge capacitor C2 through the system low voltage AVSS. As a result, between time points t0 and t1, voltage V1 rises and voltage V2 falls. At time t1, the voltage difference between voltages V1 and V2 reaches the hysteresis voltage V_hys, causing the switching control signal SW to change from logic high to logic low, thus turning on PMOS transistors MP1 and MP2. This occurs for a short period after time t1 (details are as follows). Figure 7 (As shown) represents the sampling period t_sample. During the sampling period t_sample, voltage V1 drops to the reference voltage V_ref, and voltage V2 rises to the reference voltage V_ref, making the sampled voltages V1 and V2 equal to the reference voltage V_ref. When voltages V1 and V2 are equal to the reference voltage V_ref, the switch control signal SW goes to a logic high level, the sampling period t_sample ends, and the period t_hold begins again.

[0054] Please continue to refer to Figure 4 In test mode, the switch control signal SW is forcibly set to a logic low level, thus the input and output terminals of voltage holding circuit 410 are turned on (i.e., PMOS transistor MP1 is turned on), and the input and output terminals of voltage holding circuit 420 are turned on (i.e., PMOS transistor MP2 is turned on). Input voltage selection device 440 selects the system high voltage AVDD as the input voltage of voltage holding circuit 410, and input voltage selection device 450 selects the system low voltage AVSS as the input voltage of voltage holding circuit 420, thereby performing a first test. The first test includes testing whether selector SE1 of input voltage selection device 440 is functioning correctly, testing whether selector SE3 of input voltage selection device 450 is functioning correctly, and testing whether voltage difference detector 430 is functioning correctly. If operating normally, voltage V1 will rise, and voltage V2 will fall, causing the voltage difference to reach the hysteresis voltage V_hys, and the switch control signal SW will become a logic high level. In addition, the first test also included simultaneous testing of whether the PMOS transistors MP1 and MP2 and capacitors C1 and C2 were functioning properly.

[0055] After performing the first test described above, the switch control signal SW is still forcibly kept at a logic low level. However, the input voltage selection device 440 selects the reference voltage V_ref as the input voltage of the voltage holding circuit 410, and the input voltage selection device 450 selects the reference voltage V_ref as the input voltage of the voltage holding circuit 420, thereby performing a second test. The second test includes testing whether the selector SE1 of the input voltage selection device 440 is normal, testing whether SE2 and the selector SE3 of the input voltage selection device 450 are normal, and testing whether the voltage difference detector 430 is normal. If it is operating normally, voltages V1 and V2 will be maintained at the reference voltage V_ref, and the switch control signal SW will be maintained at a logic low level. In addition, the second test also includes simultaneously testing whether the PMOS transistors MP1 and MP2 and capacitors C1 and C2 are normal.

[0056] Please refer to the following: Figure 4 and Figure 6 , Figure 6This is a waveform diagram of a portion of the signals from the voltage holding device in test mode according to an embodiment of the present invention. (Similar to...) Figure 6 As shown, in test mode, after performing the first and second tests, at time point t3, the switch control signal SW is forced to a logic high level, the test reference voltage V_test becomes a logic high level, and the input voltage selection device 440 selects the test reference voltage V_test to input into the voltage holding circuit 410, and the input voltage selection device 450 selects the reference voltage V_ref to input into the voltage holding circuit 420, thereby performing the third test. The third test includes checking whether the selectors SE1 and SE2 of the input voltage selection device 440 are normal, whether the selector SE3 of the input voltage selection device 450 is normal, whether the voltage difference detector 430 is normal, and whether the hysteresis voltage V_hys of the voltage difference detector 430 deviates from a predetermined value. Furthermore, the third test also includes simultaneously testing whether the PMOS transistors MP1 and MP2 and capacitors C1 and C2 are normal.

[0057] The first, second, and third tests described above can quickly determine whether the selectors SE1, SE2, and SE3, capacitors C1 and C2, and the voltage difference detector 430 in the operating path are functioning normally and as expected. Unlike previous tests, which required a considerable amount of time, the architecture of the voltage holding device 400 of this invention simplifies the testing process and reduces the time required, thus improving the testability and reliability of the voltage holding device 400.

[0058] Please refer to the following at the same time Figure 4 and Figure 7 , Figure 7 This is another waveform diagram of some signals of the voltage holding device in operation mode according to an embodiment of the present invention. Figure 7 The waveform is actually Figure 5 An enlarged schematic diagram of the waveform. In operation mode, when the voltage difference drops from the hysteresis voltage to zero, it enters the holding period t_hold. The voltage difference detector 430 generates a switch control signal SW to turn off PMOS transistors MP1 and MP2. The input voltage selection device 440 selects the system high voltage AVDD as the input voltage of the voltage holding circuit 410, and the input voltage selection device 450 selects the system low voltage AVSS as the input voltage of the voltage holding circuit 420. This allows the capacitor C1 to be charged and the capacitor C2 to be discharged through two leakage currents (the leakage current of PMOS transistor MP1 in the voltage holding circuit 410 and the leakage current of PMOS transistor MP2 in the voltage holding circuit 420), so that voltage V1 rises from the reference voltage V_ref and voltage V2 falls from the reference voltage V_ref, and the voltage difference rises from zero to the hysteresis voltage V_hys.

[0059] When the voltage difference rises from zero to the hysteresis voltage V_hys, the sampling period t_sample begins. Voltage difference detector 430 generates a switch control signal SW, turning on PMOS transistors MP1 and MP2. Input voltage selection device 440 selects the reference voltage V_ref as the input voltage of voltage holding circuit 410, and input voltage selection device 450 selects the reference voltage V_ref as the input voltage of voltage holding circuit 420. This causes voltage V1 to drop to the reference voltage V_ref and voltage V2 to rise to the reference voltage V_ref, and the voltage difference to drop from the hysteresis voltage V_hys to zero. Then, after the sampling period t_sample ends, the holding period t_hold begins, and so on.

[0060] Furthermore, in this embodiment of the invention, if the reference voltage V_ref is 1.2 volts, then the supply voltage of the low-dropout regulator (LDO) must be 1.5 times 1.2 volts, that is, 1.8 volts. If the capacitance of capacitor C2 is designed to be 10 times that of capacitor C1, the hysteresis voltage V_hys is 50 millivolts, and the leakage current through PMOS transistor MP1 is 0.12 times the leakage current through PMOS transistor MP2, the maximum voltage value of voltage V2 is 1.223 volts. This means that the low-dropout regulator must output a supply voltage of 1.835 volts, which does not exceed 110% of 1.8 volts (1.98 volts). Therefore, the voltage holding device 400 will not cause the low-dropout regulator operating at low voltages to burn out.

[0061] Incidentally, embodiments of the present invention also provide an electronic device using the aforementioned voltage holding device, which includes the aforementioned voltage holding device and a system circuit electrically connected to the voltage holding device. The system circuit may be any form of functional chip or circuit depending on the type of electronic device, and the present invention is not limited thereto.

[0062] In summary, the voltage holding device provided in this embodiment of the invention has the following advantages: (1) the voltage change (i.e., the aforementioned voltage difference) is less than the hysteresis voltage of the voltage difference detector, so that the voltage holding device can maintain a high voltage accuracy regardless of changes in external factors (e.g., process, voltage and temperature); (2) during testing, it is possible to quickly test whether all components on the operation path are working properly; (3) during testing, it is only necessary to ensure that the hysteresis voltage of the voltage difference detector meets the requirements to determine that the voltage change is less than the hysteresis voltage of the voltage difference detector, and thus to know that the voltage holding device can achieve the required voltage accuracy. It is not necessary to go through operation conversion to know whether the voltage holding device can achieve the required accuracy, thus reducing testing time and cost.

[0063] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereto will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A voltage holding device, characterized in that, include: A first voltage holding circuit has a first capacitor, a first input terminal and a first output terminal for generating a first voltage, wherein the first capacitor is electrically connected between the low voltage and the first output terminal, and the on and off states of the first input terminal and the first output terminal are determined by a switch control signal. The second voltage holding circuit has a second capacitor, a second input terminal and a second output terminal for generating a second voltage, wherein the second capacitor is electrically connected between the low voltage and the second output terminal, and the on and off of the second input terminal and the second output terminal are determined by the switch control signal. A first input voltage selection device is electrically connected to the first input terminal and is used to selectively provide one of a reference voltage, a test reference voltage, and a system high voltage to the first input terminal as the first input voltage. A second input voltage selection device, electrically connected to the second input terminal, is used to selectively provide one of the system low voltage and the reference voltage to the first input terminal as the second input voltage; as well as A voltage difference detector is electrically connected to the first voltage holding circuit and the second voltage holding circuit, and is used to detect the voltage difference between the first voltage and the second voltage, and generate the switching control signal based on the voltage difference.

2. The voltage holding device as described in claim 1, characterized in that, In the operation mode: When the voltage difference rises from zero to the hysteresis voltage of the voltage difference detector, the voltage difference detector generates the switching control signal to turn on the first input terminal and the first output terminal of the first voltage holding circuit, and to turn on the second input terminal and the second output terminal of the second voltage holding circuit. The first input terminal voltage selection device selects the reference voltage as the first input voltage, and the second input terminal voltage selection device selects the reference voltage as the second input voltage, so that the first voltage drops to the reference voltage and the second voltage rises to the reference voltage, and the voltage difference drops from the hysteresis voltage to zero. as well as When the voltage difference drops from the hysteresis voltage to zero, the voltage difference detector generates a switch control signal to disconnect the first input terminal and the first output terminal of the first voltage holding circuit, and to disconnect the second input terminal and the second output terminal of the second voltage holding circuit. The first input voltage selection device selects the system high voltage as the first input voltage, and the second input voltage selection device selects the system low voltage as the second input voltage. The leakage current of the first voltage holding circuit and the second voltage holding circuit respectively charge the first capacitor and discharge the second capacitor, so that the first voltage rises from the reference voltage and the second voltage falls from the reference voltage, and the voltage difference rises from zero to the hysteresis voltage.

3. The voltage holding device as described in claim 1, characterized in that, In test mode: The first input terminal of the first voltage holding circuit is turned on and the first output terminal is turned on, the second input terminal of the second voltage holding circuit is turned on and the second output terminal is turned on, the first input terminal voltage selection device selects the system high voltage as the first input voltage, and the second input terminal voltage selection device selects the system low voltage as the second input voltage, so as to perform a first test on the first input terminal voltage selection device, the second input terminal voltage selection device and the voltage difference detector; After performing the first test, the first input voltage selection device selects the reference voltage as the first input voltage, and the second input voltage selection device selects the reference voltage as the second input voltage, so as to perform a second test on the first input voltage selection device, the second input voltage selection device and the voltage difference detector; as well as After performing the second test, the first input voltage selection device selects the test reference voltage as the first input voltage, and the second input voltage selection device selects the reference voltage as the second input voltage, so as to perform a third test on the first input voltage selection device, the second input voltage selection device and the voltage difference detector.

4. The voltage holding device as described in claim 1, characterized in that, The first input voltage selection device includes: A first selector and a second selector, wherein an output terminal of the first selector is electrically connected to the first input terminal, two input terminals of the first selector are respectively electrically connected to the system high voltage and an output terminal of the second selector, and two input terminals of the second selector are respectively electrically connected to the reference voltage and the test reference voltage.

5. The voltage holding device as described in claim 1, characterized in that, The second input voltage selection device includes: A third selector, wherein one output terminal of the third selector is electrically connected to the second input terminal, and the two input terminals of the third selector are respectively electrically connected to the system low voltage and the reference voltage.

6. The voltage holding device as claimed in claim 1, characterized in that, The first voltage holding circuit includes: A first PMOS transistor has a drain serving as the first input terminal, a gate receiving the switching control signal, and a source serving as the first output terminal; and The first capacitor.

7. The voltage holding device as claimed in claim 1, characterized in that, The second voltage holding circuit includes: The second PMOS transistor has a drain as the second input terminal, a gate for receiving the switching control signal, and a source as the second output terminal; and The second capacitor.

8. The voltage holding device as claimed in claim 1, characterized in that, The voltage difference detector is a hysteresis comparator.

9. The voltage holding device as claimed in claim 1, characterized in that, The period during which the voltage difference drops from the hysteresis voltage of the voltage difference detector to zero is a sampling period, and the period during which the voltage difference rises from zero to the hysteresis voltage is a holding period, wherein during the holding period, the first voltage rises from the reference voltage and the second voltage drops from the reference voltage, and during the sampling period, the first voltage drops to the reference voltage and the second voltage rises to the reference voltage.

10. An electronic device, characterized in that, The electronic device includes: The voltage holding device as described in claims 1 to 9; The system circuit is electrically connected to the voltage holding device.

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