Output circuit, display driver, and display device

Abstract

The present application provides an output circuit, a display driver and a display device. The present application has: a positive voltage signal supply circuit that supplies a positive voltage signal having a voltage higher than a reference power supply voltage to a first node or blocks the supply; a negative voltage signal supply circuit that supplies a negative voltage signal having a voltage lower than the reference power supply voltage to a second node or blocks the supply; a first switch including a P-channel transistor having a source and a back gate connected to the first node and a drain connected to a first output terminal, which connects the first output terminal to the first node in an on state; a second switch including an N-channel transistor having a source and a back gate connected to the second node and a drain connected to the first output terminal, which connects the first output terminal to the second node in an on state; and a third switch and a fourth switch, which apply the reference power supply voltage to the first node and the second node, respectively, in an on state.

Description

[0001] This application is a divisional application of the invention patent application filed on January 15, 2021, with application number 202110059525.2 and title "Output Circuit, Display Driver and Display Device". Technical Field

[0002] This invention relates to an output circuit that outputs positive and negative voltages, a display driver that drives a display screen, and a display device. Background Technology

[0003] Currently, liquid crystal display devices, which are large-screen display devices, are generally known to use liquid crystal panels driven by an active matrix method as display devices.

[0004] In a liquid crystal display (LCD), multiple data lines extending vertically along the two-dimensional image and multiple gate lines extending horizontally along the two-dimensional image are arranged in an intersecting configuration. Furthermore, at each intersection of these multiple data lines and multiple gate lines, a pixel portion connecting the data lines and the gate lines is formed.

[0005] The liquid crystal display device includes the liquid crystal screen and a data driver, which supplies grayscale data signals having analog voltage values ​​corresponding to the brightness levels of each pixel to the data lines in data pulses per unit of a horizontal scan period.

[0006] To prevent degradation of the LCD screen, the data driver performs polarity reversal driving, which alternately supplies positive and negative grayscale data signals to the LCD screen every specified frame interval.

[0007] As an output circuit for performing this polarity reversal drive, an output circuit is proposed that includes a group of switches that receives a positive polarity driving voltage and a negative polarity driving voltage corresponding to the grayscale data signal, alternately selects one of the two, and outputs it to the liquid crystal screen (see, for example, Patent Document 1). Figures 8-10 (SW1 to SW12). In the output circuit described in Patent Document 1, by using switches SW1 to SW12, a positive drive voltage (5V) is output from the output pad OUT1 (as described in the document). Figure 8 The state of OUT1 outputting a negative polarity drive voltage (-5V) is switched to the state described in the literature. Figure 10 (state).

[0008] Furthermore, during this polarity switching, the output circuit described in Patent Document 1 is as described in the document. Figure 9In this case, the one end of each switch is set to 0V, and then the state shown in the document is switched. Figure 10 Accordingly, each switch can be configured using a low voltage element having a range of 1 / 2 of the liquid crystal drive voltage.

[0009] [Related Art Document]

[0010] [Patent Document]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-102211 SUMMARY

[0012] [Problems to be Solved by the Invention]

[0013] Further, in manufacturing the switches SW1 to SW12 described in the patent document 1, it is conceivable to configure these switches using a Metal Oxide Semiconductor (MOS) transistor.

[0014] However, the output circuit described in the patent document 1 has the following problem, that is, in the case where the MOS transistor is used to configure the switches SW1 to SW8 through which the current corresponding to the drive voltage flows, the following problem occurs, and thus it is not possible to simply achieve the like.

[0015] For example, the switch SW5 of the patent document 1 is configured using an N-channel MOS transistor (hereinafter, simply referred to as NMOS transistor), and the range of the voltage value of the drive voltage of the positive polarity is set to GND to VDD, and the range of the voltage value of the drive voltage of the negative polarity is set to -VDD to GND. Figure 8

[0016] At this time, in the case where the switch SW5 is used to output the drive voltage of the positive polarity, the gate of the switch SW5 is applied with VDD, and thus is set to the on state. Accordingly, the switch SW5 outputs the drive voltage of the positive polarity received by the source thereof from the drain.

[0017] According to the configuration, in the case where the voltage value of the drive voltage of the positive polarity received by the source of the switch SW5 is a relatively low voltage of GND or in the vicinity of GND, the switch SW5 can output the drive voltage having the voltage value.

[0018] However, the NMOS transistor cannot output the drive voltage in the voltage range of VDD and (VDD - Vth) in the case where the voltage value of the drive voltage of the positive polarity received by the source thereof is in the voltage range.

[0019] ​That is, in a case where the NMOS transistor is used to configure the switch SW5, the following problem occurs, that is, the voltage range (high voltage side) of the drive voltage at the time of output becomes narrow with respect to the positive polarity drive voltage received by itself, and the like.

[0020] Further, in a case where the switch SW6 shown in Fig. 1 of Patent Document 1 is configured by using a PMOS transistor (hereinafter, referred to as PMOS transistor), the voltage range of the drive voltage of the positive polarity is assumed to be GND to VDD, and the voltage range of the drive voltage of the negative polarity is assumed to be -VDD to GND. Figure 8 Further, in a case where the switch SW6 shown in Fig. 1 of Patent Document 1 is configured by using a PMOS transistor (hereinafter, referred to as PMOS transistor), the voltage range of the drive voltage of the positive polarity is assumed to be GND to VDD, and the voltage range of the drive voltage of the negative polarity is assumed to be -VDD to GND.

[0021] Further, in a case where the switch SW6 shown in Fig. 1 of Patent Document 1 is configured by using a PMOS transistor (hereinafter, referred to as PMOS transistor), the voltage range of the drive voltage of the positive polarity is assumed to be GND to VDD, and the voltage range of the drive voltage of the negative polarity is assumed to be -VDD to GND. Figure 8

[0022] At this time, in a case where the switch SW6 is used to output the drive voltage of the negative polarity, the switch SW6 is set to the on state by applying -VDD to the gate of the switch SW6. Thus, the switch SW6 outputs the drive voltage of the negative polarity received by the source of the switch SW6 from the drain.

[0023] According to the configuration, in a case where the voltage value of the drive voltage of the negative polarity received by the source of the switch SW6 is a relatively high voltage of GND or in the vicinity of GND, the switch SW6 can output the drive voltage having the voltage value.

[0024] However, in a case where the voltage value of the drive voltage of the negative polarity received by the source of the switch SW6 is in the voltage range between -VDD and (-VDD + |Vtp|) due to the threshold voltage Vtp of the PMOS transistor, the switch SW6 cannot output the drive voltage in such a voltage range.

[0025] That is, in a case where the PMOS transistor is used to configure the switch SW6, the following problem occurs, that is, the voltage range (particularly, low voltage side) of the drive voltage at the time of output becomes narrow with respect to the negative polarity drive voltage received by itself, and the like.

[0026] Further, in a case where the switch SW6 shown in Fig. 1 of Patent Document 1 is configured by using a PMOS transistor (hereinafter, referred to as PMOS transistor), the voltage range of the drive voltage of the positive polarity is assumed to be GND to VDD, and the voltage range of the drive voltage of the negative polarity is assumed to be -VDD to GND. Figure 8 ​During the period in which the illustrated switch SW5 outputs the positive polarity drive voltage as described, it is necessary to pre-set SW6 to the off state by applying GND to the gate of SW6. At this time, both the gate and the source of SW6 become GND, and thus SW6 becomes a PN junction state in which current flows from the drain of SW6 to the back gate (GND) is applied. Therefore, problems such as the inability of SW6 to function in the off state occur.

[0027] Therefore, the purpose of the present application is to provide an output circuit that can switch between outputting a positive polarity voltage signal and a negative polarity voltage signal, can be implemented using a low voltage MOS transistor to achieve a small area and low cost, and can output a wide range of voltages.

[0028] [Technical means for solving the problem]

[0029] The output circuit of the present application includes: a positive voltage signal supply circuit that supplies a positive voltage signal having a higher voltage than a reference power supply voltage to a first node, or blocks supply of the positive voltage signal to the first node; a negative voltage signal supply circuit that supplies a negative voltage signal having a lower voltage than the reference power supply voltage to a second node, or blocks supply of the negative voltage signal to the second node; a first output terminal; a first switch that connects the first output terminal to the first node in the on state, and blocks connection of the first output terminal to the first node in the off state; a second switch that connects the first output terminal to the second node in the on state, and blocks connection of the first output terminal to the second node in the off state; a third switch that applies the reference power supply voltage to the first node in the on state, and stops applying the reference power supply voltage to the first node in the off state; and a fourth switch that applies the reference power supply voltage to the second node in the on state, and stops applying the reference power supply voltage to the second node in the off state, and the first switch is composed of a P-channel transistor having the source and back gate connected to the first node and the drain connected to the first output terminal, and the second switch is composed of an N-channel transistor having the source and back gate connected to the second node and the drain connected to the first output terminal.

[0030] Further, the output circuit of the present application includes: a positive voltage signal supply circuit that supplies a positive voltage signal having a higher voltage than a reference power supply voltage to a first node or blocks supply of the positive voltage signal to the first node; a negative voltage signal supply circuit that supplies a negative voltage signal having a lower voltage than the reference power supply voltage to a second node or blocks supply of the negative voltage signal to the second node; a first output terminal; a first switch that connects the first output terminal to the first node in an on state and blocks connection of the first output terminal to the first node in an off state; a second switch that connects the first output terminal to the second node in an on state and blocks connection of the first output terminal to the second node in an off state; a third switch that applies the reference power supply voltage to the first node in an on state and stops application of the reference power supply voltage to the first node in an off state; a fourth switch that applies the reference power supply voltage to the second node in an on state and stops application of the reference power supply voltage to the second node in an off state; a first voltage control circuit that performs on-off control of the first switch; and a second voltage control circuit that performs on-off control of the second switch, and the first switch is constituted by a P-channel transistor having a source connected to the first node and a drain connected to the first output terminal, the second switch is constituted by an N-channel transistor having a source connected to the second node and a drain connected to the first output terminal, the first voltage control circuit has a first control member that causes a gate voltage of the P-channel transistor to change in conjunction with a change in voltage supplied to the first node when the P-channel transistor is controlled to be in an on state, and the second voltage control circuit has a second control member that causes a gate voltage of the N-channel transistor to change in conjunction with a change in voltage supplied to the second node when the N-channel transistor is controlled to be in an on state.

[0031] Further, the data driver of the present application includes a plurality of output circuits each having a positive voltage signal supply circuit that supplies a positive voltage signal having a higher voltage than a reference power supply voltage to a first node or a third node, or blocks supply of the positive voltage signal to the first node or the third node; a negative voltage signal supply circuit that supplies a negative voltage signal having a lower voltage than the reference power supply voltage to a second node or a fourth node, or blocks supply of the negative voltage signal to the second node or the fourth node; a first output terminal and a second output terminal; a first switch that connects the first output terminal to the first node in an on state, and blocks connection of the first output terminal to the first node in an off state; a second switch that connects the first output terminal to the second node in an on state, and blocks connection of the first output terminal to the second node in an off state; a third switch that applies the reference power supply voltage to the first node in an on state, and stops application of the reference power supply voltage to the first node in an off state; a fourth switch that applies the reference power supply voltage to the second node in an on state, and stops application of the reference power supply voltage to the second node in an off state; a fifth switch that connects the second output terminal to the third node in an on state, and blocks connection of the second output terminal to the third node in an off state; a sixth switch that connects the second output terminal to the fourth node in an on state, and blocks connection of the second output terminal to the fourth node in an off state; a seventh switch that applies the reference power supply voltage to the third node in an on state, and stops application of the reference power supply voltage to the third node in an off state; and an eighth switch that applies the reference power supply voltage to the fourth node in an on state, and stops application of the reference power supply voltage to the fourth node in an off state, and the first switch is constituted by a P-channel transistor having a source and a back gate connected to the first node and a drain connected to the first output terminal, the second switch is constituted by an N-channel transistor having a source and a back gate connected to the second node and a drain connected to the first output terminal, the fifth switch is constituted by a P-channel transistor having a source and a back gate connected to the third node and a drain connected to the second output terminal, the sixth switch is constituted by an N-channel transistor having a source and a back gate connected to the fourth node and a drain connected to the second output terminal, and the data driver outputs a plurality of gray scale voltage signals having voltage values of positive polarity or negative polarity from the plurality of output circuits to drive a plurality of data lines of a liquid crystal display panel.

[0032] Further, the display device of the present application includes the data driver, and a liquid crystal display panel having a plurality of data lines that receive the plurality of gray scale voltage signals output from the data driver.

[0033] [Effects of the Invention]

[0034] In the output circuit of the present application, a P-channel transistor whose source and back gate are connected to a first node and whose drain is connected to an output terminal is used to form a first switch which receives a positive voltage signal via the first node and supplies it to the output terminal in an on state. Further, an N-channel transistor whose source and back gate are connected to a second node and whose drain is connected to the output terminal is used to form a second switch which receives a negative voltage signal via the second node and supplies it to the output terminal in an on state.

[0035] According to the above structure, the first switch and the second switch which output the positive voltage signal and the negative voltage signal, respectively, can be implemented using MOS transistors with low withstand voltage, so that area saving and low cost can be achieved. Further, according to the structure of the output circuit, signals with a wide voltage range can be output. Further, by applying the output circuit to the output section of a data driver of a liquid crystal display device, a gray scale voltage signal with a wide voltage range can be supplied to a data line of a liquid crystal display panel, so that area saving and low cost can be achieved without degrading image quality. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A circuit diagram showing the structure of the output circuit 100 as the first embodiment.

[0037] Figure 2 A time chart showing the internal operation of the output circuit.

[0038] Figure 3 An equivalent circuit diagram of the output circuit showing the operation mode of the output circuit in the period Tl.

[0039] Figure 4 An equivalent circuit diagram of the output circuit showing the operation mode of the output circuit in the period T2.

[0040] Figure 5 An equivalent circuit diagram of the output circuit showing the operation mode of the output circuit in the period T3.

[0041] Figure 6 An equivalent circuit diagram of the output circuit showing the operation mode of the output circuit in the period T4.

[0042] Figure 7 A circuit diagram showing the structure of the output circuit 200 as the second embodiment.

[0043] Figure 8A circuit diagram showing the structure of the output circuit 100A as the third embodiment.

[0044] Figure 9 A circuit diagram showing the structure of the output circuit 100-1 as the fourth embodiment.

[0045] Figure 10 A timing chart showing the internal operation of the output circuit of the fourth embodiment.

[0046] Figure 11 An equivalent circuit diagram of the output circuit showing the operation mode of the output circuit of the fourth embodiment in the period T1.

[0047] Figure 12 An equivalent circuit diagram of the output circuit showing the operation mode of the output circuit of the fourth embodiment in the period T2.

[0048] Figure 13 An equivalent circuit diagram of the output circuit showing the operation mode of the output circuit of the fourth embodiment in the period T3.

[0049] Figure 14 An equivalent circuit diagram of the output circuit showing the operation mode of the output circuit of the fourth embodiment in the period T4.

[0050] Figure 15 A circuit diagram showing the structure of the output circuit 100-2 as the fifth embodiment.

[0051] Figure 16 A circuit diagram showing the structure of the output circuit 100-3 as the sixth embodiment.

[0052] Figure 17 A circuit diagram showing the structure of the output circuit 100-4 as the seventh embodiment.

[0053] Figure 18 A circuit diagram showing the structure of the output circuit 200-1 as the eighth embodiment.

[0054] Figure 19 A circuit diagram showing the structure of the output circuit 300 as the ninth embodiment.

[0055] Figure 20 A circuit diagram showing the structure of the output circuit 300-1 as the tenth embodiment.

[0056] Figure 21 A block diagram showing the structure of a display device 400 having a data driver 80 including the output circuit of the present application.

[0057] Figure 22This is a block diagram illustrating the internal structure of the data driver 80.

[0058] [Explanation of Symbols]

[0059] 10A: Positive voltage signal supply circuit

[0060] 20A: Negative voltage signal supply circuit

[0061] 11, 21: Output selection switches

[0062] 13, 23: Switch

[0063] 35: Control Department

[0064] 80: Data Driver

[0065] 100: Output circuit

[0066] 400: Display device Detailed Implementation

[0067] [Example 1]

[0068] Figure 1 This is a circuit diagram illustrating the structure of an output circuit 100, which is the first embodiment of the output circuit of the present invention. Furthermore, the output circuit 100 is an output circuit capable of receiving a positive voltage signal Vpi having a positive polarity and a negative voltage signal Vni having a negative polarity, and selectively outputting one of a positive voltage signal Vp obtained by amplifying the positive voltage signal Vpi and a negative voltage signal Vn obtained by amplifying the negative voltage signal Vni.

[0069] like Figure 1 As shown, the output circuit 100 includes a positive voltage signal supply circuit 10A, a negative voltage signal supply circuit 20A, an output selection switch 11 and an output selection switch 21, a switch 13 and a switch 23, a control unit 35, and an output terminal DL1.

[0070] The positive voltage signal supply circuit 10A includes an amplifier circuit 10 and a switch 15. The amplifier circuit 10 is, for example, a voltage follower operational amplifier whose output terminal is connected to its inverting input terminal. Alternatively, the amplifier circuit 10 may be an amplifier circuit that amplifies the input voltage signal Vpi with a gain of less than 1 or a gain of more than 1.

[0071] The amplifier circuit 10 is supplied with power supply voltage VGND and power supply voltage VDDH. It receives a positive voltage signal Vpi with a positive polarity at its non-inverting input terminal and amplifies and outputs the positive voltage signal Vpi.

[0072] In addition, the positive voltage signal Vp is a signal of positive polarity whose voltage value varies within a range described below.

[0073] VGND < Vp < VDDH

[0074] VGND = reference power supply voltage (e.g., 0 V)

[0075] VDDH = positive power supply voltage (e.g., 5 V)

[0076] The amplification circuit 10 outputs the positive voltage signal Vp from its output terminal, and supplies it to the switch 15.

[0077] The switch 15 is constituted by, for example, a Complementary Metal Oxide Semiconductor (CMOS) switch, and is set to an on state or an off state in accordance with a control signal Sz11. The switch 15, in the case where it is set to the on state, supplies the positive voltage signal Vp output from the amplification circuit 10 to the output selection switch 11 via the node Ns11.

[0078] In addition, as the amplification circuit 10, an amplification circuit including the function of the switch 15 can also be used.

[0079] The switch 13 is an NMOS transistor that receives a control signal Sr11 at the gate. The drain of the switch 13 is connected to the node Ns11, and the source and the back gate are applied with the reference power supply voltage VGND. The switch 13, in the case where the control signal Sr11 received at its gate has the reference power supply voltage VGND, becomes the off state. On the other hand, in the case where the control signal Sr11 has the positive power supply voltage VDDH, the switch 13 becomes the on state, and applies the reference power supply voltage VGND to the node Ns11. In addition, with respect to the switch 13, hereinafter, it is also referred to as the NMOS transistor switch 13.

[0080] The output selection switch 11 is a PMOS transistor that receives a control signal St11 at the gate. The source and the back gate of the output selection switch 11 are connected to the node Ns11, and the drain is connected to the output terminal DL1. The output selection switch 11, in the case where the control signal St11 received at its gate has the reference power supply voltage VGND when the node Ns11 is the reference power supply voltage VGND, becomes the off state. On the other hand, in the case where the control signal St11 has a negative voltage VGn within a prescribed voltage difference with respect to the positive voltage signal Vp, the output selection switch 11 becomes the on state, and electrically connects the node Ns11 and the output terminal DL1. In addition, with respect to the output selection switch 11, hereinafter, it is also referred to as the PMOS transistor switch 11.

[0081] The negative voltage signal supply circuit 20A includes an amplification circuit 20 and a switch 25. The amplification circuit 20 is, for example, an operational amplifier of a voltage follower whose output terminal and inverting input terminal are connected to each other. Alternatively, the amplification circuit 20 can be an amplification circuit that amplifies an input voltage signal with a gain of less than 1 or a gain of 1 or more.

[0082] The amplification circuit 20 is supplied with a power supply voltage VGND and a power supply voltage VDDL, receives a negative voltage signal Vn having a voltage value of a negative polarity at its non-inverting input terminal, and amplifies and outputs the negative voltage signal Vn.

[0083] The negative voltage signal Vn is a signal of a negative polarity whose voltage value is in a range described below.

[0084] VGND > Vn > VDDL

[0085] VGND = reference power supply voltage (for example, 0 V)

[0086] VDDL = negative power supply voltage (for example, -5 V)

[0087] The amplification circuit 20 outputs the negative voltage signal Vn from its output terminal and supplies it to the switch 25.

[0088] The switch 25 is constituted by, for example, a CMOS switch and is set to an on state or an off state in accordance with a control signal Sz21. The switch 25 supplies the negative voltage signal Vn output from the amplification circuit 20 to the output selection switch 21 via a node Ns21 when it is set to the on state.

[0089] Alternatively, the amplification circuit 20 can be an amplification circuit that includes the function of the switch 25.

[0090] The switch 23 is a PMOS transistor that receives a control signal Sr21 at its gate. The drain of the switch 23 is connected to the node Ns21, and the source and back gate thereof are applied with the reference power supply voltage VGND. The switch 23 becomes in the off state when the control signal Sr21 received at its gate has the reference power supply voltage VGND. On the other hand, when the control signal Sr21 has the negative power supply voltage VDDL, the switch 23 becomes in the on state and applies the reference power supply voltage VGND to the node Ns21. Hereinafter, the switch 23 will also be referred to as a PMOS transistor switch 23.

[0091] The output selection switch 21 is an NMOS transistor that receives a control signal St21 at the gate. The source and back gate of the output selection switch 21 are connected to the node Ns21, and the drain is connected to the output terminal DL1. Also, the output selection switch 21 is also referred to as the NMOS transistor switch 21 hereinafter. When the node Ns21 is the reference power supply voltage VGND, the control signal St21 received at the gate of the output selection switch 21 has the reference power supply voltage VGND, and the output selection switch 21 becomes the off state. On the other hand, when the control signal St21 has a positive voltage VGp within a prescribed voltage difference with respect to the negative voltage signal Vn, the output selection switch 21 becomes the on state, and electrically connects the node Ns21 and the output terminal DL1.

[0092] The control section 35 generates the control signal Sr11, the control signal Sr21, the control signal St11, the control signal St21, the control signal Sz11, and the control signal Sz21 as control signals that select one of the positive voltage signal Vp and the negative voltage signal Vn. Also, in the case where the switches 15 and 25 are each composed of a CMOS switch, the control section 35 generates the complementary signals of Sz11 and Sz21. In the timing charts of the drawings that explain the embodiments of the present application, the control signals of the CMOS switches are control signals supplied to the gates of the NMOS transistors that compose the CMOS switches for convenience.

[0093] Figure 2 FIG. 6 is a timing chart that shows an example of the control signals Sr11, Sr21, St11, St21, Sz11, and Sz21 generated by the control section 35.

[0094] Also, Figure 2 In FIG. 6, an example of the control signals generated by the control section 35 is shown in the case where the output circuit 100 periodically and alternately switches the output of the positive voltage signal Vp and the negative voltage signal Vn, which is so-called polarity inversion driving. Also, Figure 2 In FIG. 6, the on-off control of each switch, and the changes in the voltage V11 of the node Ns11, the voltage V21 of the node Ns21, and the voltage of the output terminal DL1 are shown in each of the positive driving period of the positive voltage signal Vp and the negative driving period of the negative voltage signal Vn. Also, the positive voltage signal Vp and the negative voltage signal Vn can be a single or multiple step signals, or a variable signal such as a sine wave within a voltage range corresponding to each polarity.

[0095] As Figure 2As shown, the positive drive period is divided into at least two periods, period T1 and period T2, and the negative drive period is also divided into at least two periods, period T3 and period T4.

[0096] The following is a reference. Figure 2 as well as Figures 3-6 On the one hand, with Figure 2 The detailed operation of the output circuit 100 corresponding to the control signals Sr11, Sr21, St11, St21, Sz11, and Sz21 shown will be explained. Furthermore, Figures 3-6 This is an equivalent circuit diagram representing the state of the output circuit 100 in each of periods T1 to T4. At this time, just before entering period T1 (initial state), the circuit is in the state where the negative voltage signal Vn generated by the negative voltage signal supply circuit 20A is supplied to the output terminal DL1 via the output selection switch 21; this is the operating state during period T4 of the negative drive period. Furthermore, Figures 3-6 In the diagram, dotted lines represent the paths of the HiZ state where the signal supply is blocked.

[0097] Figure 2 In the first phase (T1), switches 15 and 25 are both turned off according to control signals Sz11 and Sz21, blocking the supply of voltage signals from the positive voltage signal supply circuit 10A and the negative voltage signal supply circuit 20A. Furthermore, a control signal Sr11 with a positive power supply voltage VDDH is supplied to the gate of switch 13, thus turning switch 13 on, and the voltage V11 at node Ns11 becomes the reference power supply voltage VGND. Moreover, a control signal Sr21 with a negative power supply voltage VDDL is supplied to the gate of switch 23, thus turning switch 23 on. Figure 2 As shown, the voltage V21 of node Ns21 is boosted from the negative voltage signal Vn during the previous negative drive to the reference power supply voltage VGND. Furthermore, a control signal St11 with the reference power supply voltage VGND is supplied to the gate of the output selection switch 11, thus... Figure 3 As shown, output selection switch 11 is in the off state. Furthermore, a control signal St21 with voltage VGp is ​​supplied to the gate of output selection switch 21, thus... Figure 3 As shown, output selection switch 21 is in the ON state.

[0098] Therefore, during period T1, such as Figure 3 As shown, the reference power supply voltage VGND, which is the voltage V21 of node Ns21, is applied to the output terminal DL1 via the output selection switch 21.

[0099] At this time, asFigure 2 As shown, the voltage of the output terminal DL1 of the negative voltage signal Vn is boosted via the output selection switch 21 to the reference power source voltage VGND.

[0100] In addition, during the entire period T1, each terminal (gate, drain, source, back gate) of the switch 13 is controlled between the reference power source voltage VGND and the positive power source voltage VDDH. Each terminal of the output selection switch 11 and the switch 23 is controlled between the reference power source voltage VGND and the negative power source voltage VDDL. The drain, source, back gate among each terminal of the output selection switch 21 is controlled between the reference power source voltage VGND and the negative power source voltage VDDL. At the gate of the output selection switch 21, the positive-side voltage VGp is applied, which is within a prescribed voltage difference (voltage resistance) from the reference power source voltage VGND supplied to the node Ns21, in which the output selection switch 21 becomes an on state. Therefore, the output selection switch 11, the output selection switch 21, and the switch 13, the switch 23 are controlled within any voltage resistance range of the voltage difference between the reference power source voltage VGND and the positive power source voltage VDDH, or the voltage difference between the reference power source voltage VGND and the negative power source voltage VDDL.

[0101] Next, during the period T2, the control signal Sr11 having the reference power source voltage VGND is supplied to the gate of the switch 13, and thus the switch 13 becomes an off state. Also, the control signal Sr21 having the negative power source voltage VDDL is continuously supplied to the gate of the switch 23, and thus the switch 23 maintains an on state, and the voltage V21 of the node Ns21 becomes the reference power source voltage VGND. Also, the switch 15 among the switch 15 and the switch 25 is switched to an on state according to the control signal Sz11 and the control signal Sz21. Thus, the positive voltage signal Vp generated by the positive voltage signal supply circuit 10A is supplied to the node Ns11. Also, the control signal St11 having the voltage VGn is supplied to the gate of the output selection switch 11, and thus the output selection switch 11 becomes an on state. Also, the control signal St21 having the reference power source voltage VGND is supplied to the gate of the output selection switch 21, and thus the output selection switch 21 is switched to an off state.

[0102] Thus, during the period T2, as shown in Figure 4 the positive voltage signal Vp generated by the positive voltage signal supply circuit 10A is applied to the output terminal DL1 via the node Ns11 and the output selection switch 11.

[0103] At this time, as shown in Figure 4 the output selection switch 21 is in an off state, and in a state in which the electrical connection with the output terminal DL1 is blocked. Thus, as shown in Figure 2As shown, the voltage V11 of the node Ns11 and the voltage of the output terminal DL1 are raised from the state of the reference power supply voltage VGND to the positive voltage signal Vp. On the other hand, the voltage V21 of the node Ns21 is maintained as the state of the reference power supply voltage VGND as shown. Figure 2 As shown, the voltage V11 of the node Ns11 and the voltage of the output terminal DL1 are raised from the state of the reference power supply voltage VGND to the positive voltage signal Vp. On the other hand, the voltage V21 of the node Ns21 is maintained as the state of the reference power supply voltage VGND as shown.

[0104] In addition, during the entire period T2, each terminal (gate, drain, source, back gate) of the switch 13 and the output selection switch 21 is controlled between the reference power supply voltage VGND and the positive power supply voltage VDDH. Each terminal of the switch 23 is controlled between the reference power supply voltage VGND and the negative power supply voltage VDDL. The drain, source, and back gate among the terminals of the output selection switch 11 are controlled between the reference power supply voltage VGND and the positive power supply voltage VDDH. At the gate of the output selection switch 11, the negative-side voltage VGn is applied, which is within a prescribed voltage difference (voltage resistance) of the output selection switch 11 becoming an on state with respect to the positive voltage signal Vp. Therefore, the output selection switch 11, the output selection switch 21, and the switch 13, the switch 23 are controlled within any voltage resistance range of the voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH, or the voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0105] Next, during the period T3, the switch 15 and the switch 25 both become an off state according to the control signal Sz11 and the control signal Sz21, and the supply of the voltage signal from the positive voltage signal supply circuit 10A and the negative voltage signal supply circuit 20A is blocked. Also, the gate of the switch 13 is supplied with the control signal Sr11 having the positive power supply voltage VDDH, and thus the switch 13 becomes an on state as shown. Figure 2 As shown, the voltage V11 of the node Ns11 is lowered from the positive voltage signal Vp to the reference power supply voltage VGND. Also, the gate of the switch 23 is continuously supplied with the control signal Sr21 having the negative power supply voltage VDDL, and thus the on state is maintained, and the voltage V21 of the node Ns21 is continuously maintained as the reference power supply voltage VGND. Also, the gate of the output selection switch 11 is continuously supplied with the control signal St11 having the voltage VGn, and thus the output selection switch 11 is maintained in an on state as shown. Figure 5 As shown, the output selection switch 11 is maintained in an on state. Also, the gate of the output selection switch 21 is continuously supplied with the control signal St21 having the reference power supply voltage VGND, and thus the output selection switch 21 is maintained in an off state as shown. Figure 5 As shown, the output selection switch 21 is maintained in an off state.

[0106] Therefore, during the period T3, the reference power supply voltage VGND as the voltage V11 of the node Ns11 is applied to the output terminal DL1 via the output selection switch 11 as shown. Figure 5 As shown, the voltage V11 of the node Ns11 and the voltage of the output terminal DL1 are raised from the state of the reference power supply voltage VGND to the positive voltage signal Vp. On the other hand, the voltage V21 of the node Ns21 is maintained as the state of the reference power supply voltage VGND as shown.

[0107] At this time, as Figure 2 As shown, the voltage at the output terminal DL1 of the positive voltage signal Vp is reduced to the reference power supply voltage VGND via the output selection switch 11.

[0108] Furthermore, throughout the entire period T3, although the state of switch 13 changes from open to closed, the control voltage range of each switch remains unchanged. Therefore, similar to period T2, output selection switches 11, 21, 13, and 23 are controlled within any withstand voltage range of the voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH, or the voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0109] Next, during period T4, a control signal Sr11 with a positive power supply voltage VDDH continues to be supplied to the gate of switch 13, thus switch 13 becomes on, and the voltage V11 at node Ns11 continues to be the reference power supply voltage VGND. Furthermore, a control signal Sr21 with the reference power supply voltage VGND is supplied to the gate of switch 23, thus switch 23 becomes off. Moreover, based on control signals Sz11 and Sz21, only switch 25 of switches 15 and 25 switches to the on state. As a result, the negative voltage signal Vn generated by the negative voltage signal supply circuit 20A is supplied to node Ns21. Furthermore, a control signal St11 with the reference power supply voltage VGND is supplied to the gate of output selection switch 11, thus output selection switch 11 becomes off. Furthermore, a control signal St21 with voltage VGp is ​​supplied to the gate of output selection switch 21, thus output selection switch 21 switches to the on state.

[0110] Therefore, during period T4, such as Figure 6 As shown, the negative voltage signal Vn generated by the negative voltage signal supply circuit 20A is applied to the output terminal DL1 via node Ns21 and output selection switch 21.

[0111] At this time, as Figure 6 As shown, the output selection switch 11 is in the off state, thus blocking the electrical connection with the output terminal DL1. Therefore, as Figure 2 As shown, the voltage V21 at node Ns21 and the voltage at output terminal DL1 decrease from the reference power supply voltage VGND to the negative voltage signal Vn. On the other hand, the voltage V11 at node Ns11... Figure 2 As shown, the reference power supply voltage VGND is maintained.

[0112] Furthermore, throughout period T4, the terminals (gate, drain, source, and back gate) of switch 23 and output selection switch 11 are controlled between the reference power supply voltage VGND and the negative power supply voltage VDDL. The terminals of switch 13 are controlled between the reference power supply voltage VGND and the positive power supply voltage VDDH. The drain, source, and back gate of the terminals of output selection switch 21 are controlled between the reference power supply voltage VGND and the negative power supply voltage VDDL. A positive voltage VGp is ​​applied to the gate of output selection switch 21. This positive voltage VGp, relative to the negative voltage signal Vn, is within a specified voltage difference (withstand voltage) for output selection switch 21 to be in the ON state. Therefore, output selection switches 11, 21, 13, and 23 are controlled within either the voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH, or the voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0113] The following is about Figures 2-6 The characteristics of the drive control shown are explained.

[0114] In the Figures 2-6 In the drive control shown, a switching period (T1) is set when switching from the supply period of the negative voltage signal Vn (T4) to the supply period of the positive voltage signal Vp (T2). During the switching period (T1), nodes Ns11 and Ns21 are driven to the reference power supply voltage VGND, and the output selection switch 21 is set to the ON state. After the output terminal DL1, which will become the negative voltage signal Vn, is driven to the reference power supply voltage VGND from node Ns21, the switch is made to the supply period of the positive voltage signal Vp (T2). Furthermore, the gate voltage that controls the output selection switch 11 to the ON state is set to voltage VGn, and the gate voltage that controls the output selection switch 21 to the ON state is set to voltage VGp. Therefore, the output selection switch 11, output selection switch 21, and switches 13 and 23 are controlled within any voltage range of the voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH, or the voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0115] Similarly, at the time of switching from the period (T2) of supply of the positive voltage signal Vp to the period (T4) of supply of the negative voltage signal Vn, a switching period (T3) is provided. In the switching period (T3), the node Nsll and the node Ns21 are driven to the reference power supply voltage VGND, and the output selection switch 11 is set to the on state. After the output terminal DLl which is to become the positive voltage signal Vp is driven to the reference power supply voltage VGND from the node Nsll, the period (T4) of supply of the negative voltage signal Vn is switched. Further, the gate voltages which cause the output selection switch 11 and the output selection switch 21 to be controlled to the on state are set to the voltage VGn and the voltage VGp, respectively. Thus, the output selection switch 11, the output selection switch 21, and the switches 13 and 23 are controlled to be within any of the voltage withstand ranges of the voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH or the voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0116] Further, by causing the positive voltage signal supply circuit 10A to operate with the voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH and causing the negative voltage signal supply circuit 20 to operate with the voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL, the output circuit 100 can be controlled to be within any of the voltage withstand ranges of the voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH or the voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL. Therefore, the output circuit 100 can be constituted by low voltage elements whose voltage difference is, for example, about one-half, with respect to the output voltage range (VDDL < DLl voltage < VDDH) of the output terminal DLl. The low voltage elements (transistors) can be reduced in size in accordance with a scaling principle, for example, and thus the output circuit 100 constituted by the low voltage elements can be greatly reduced in circuit area.

[0117] Here, as a comparison, for example, consider the case where, in the switching period (Tl), the switches 13 and 23 are both set to the on state, the node Nsll and the node Ns21 are both short-circuited to the reference power supply voltage VGND, and the output selection switch 11 and the output selection switch 21 are also both set to the on state.

[0118] At this time, the output terminal DLl is the negative voltage signal Vn during the previous negative drive period, and thus the voltage of the node Nsll immediately after the start of the switching period (Tl) temporarily becomes a voltage at which the reference power supply voltage VGND and the negative voltage signal Vn (for example, near VDDL) are divided by the respective on resistances of the output selection switch 11 and the switch 13, that is, a voltage lower than the reference power supply voltage VGND, and gradually returns to the reference power supply voltage VGND. Thus, at this time, the voltage difference between the gate supplied with the positive power supply voltage VDDH and the source that is the node Nsll exceeds the power supply-to-power supply voltage difference (voltage resistance) between the reference power supply voltage VGND and the positive power supply voltage VDDH for the switch 13.

[0119] Further, a case is assumed in which, during the switching period (Tl), the switch 13 and the switch 23 are both set to the on state, the node Nsll and the node Ns21 are both short-circuited to the reference power supply voltage VGND, and the output selection switch 11 and the output selection switch 21 are both set to the off state.

[0120] At this time, the output terminal DLl is the negative voltage signal Vn during the previous negative drive period, and thus the output terminal DLl also holds the negative voltage signal Vn during the switching period (Tl). Immediately after the start of the positive voltage signal supply period (T2), if the output selection switch 11 is on, the voltage of the node Nsll temporarily becomes a voltage at which the positive voltage signal Vp (for example, near VGND) output from the positive voltage signal supply circuit 10A and the negative voltage signal Vn (for example, near VDDL) of the output terminal DLl are divided by the output resistance of the positive voltage signal supply circuit 10A and the on resistance of the output selection switch 11, that is, a voltage lower than the reference power supply voltage VGND. Thus, it is possible that the output element of the positive voltage signal supply circuit 10A exceeds the power supply-to-power supply voltage difference (voltage resistance) between the reference power supply voltage VGND and the positive power supply voltage VDDH.

[0121] Next, a case is considered in which, during the switching period (T3), the switch 13 and the switch 23 are both set to the on state, the node Nsll and the node Ns21 are both short-circuited to the reference power supply voltage VGND, and the output selection switch 11 and the output selection switch 21 are both set to the on state.

[0122] At this time, the output terminal DLl is the positive voltage signal Vp during the previous positive drive period (T2), and thus the voltage of the node Ns21 immediately after the start of the switching period (T3) temporarily becomes a voltage at which the reference power supply voltage VGND and the positive voltage signal Vp (for example, near VDDH) are divided by the on resistances of the output selection switch 21 and the switch 23, that is, a voltage higher than the reference power supply voltage VGND, and gradually returns to the reference power supply voltage VGND. Thus, at this time, the voltage difference between the gate supplied with the negative power supply voltage VDDL and the source of the node Ns21 exceeds the power supply-to-power supply voltage difference (voltage resistance) between the reference power supply voltage VGND and the negative power supply voltage VDDL for the switch 23.

[0123] Further, the case is considered in which, during the switching period (T3), the switch 13 and the switch 23 are both set to the on state, the node Nsll and the node Ns21 are both short-circuited to the reference power supply voltage VGND, and the output selection switch 11 and the output selection switch 21 are both set to the off state.

[0124] At this time, the output terminal DLl is the positive voltage signal Vp during the previous positive drive period (T2), and thus the output terminal DLl also maintains the positive voltage signal Vp during the switching period (T3). Immediately after the start of the negative voltage signal supply period (T4), if the output selection switch 21 is off, the voltage of the node Ns21 temporarily becomes a voltage at which the negative voltage signal Vn (for example, near VGND) output from the negative voltage signal supply circuit 20A and the positive voltage signal Vp (for example, near VDDH) of the output terminal DLl are divided by the output resistance of the negative voltage signal supply circuit 20A and the on resistance of the output selection switch 21, that is, a voltage higher than the reference power supply voltage VGND. Thus, it is possible that the output element of the negative voltage signal supply circuit 20A exceeds the power supply-to-power supply voltage difference (voltage resistance) between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0125] In contrast to this, Figures 2-6 In the drive control shown, the output circuit 100 can be controlled within either of the voltage resistance ranges of the power supply-to-power supply voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH or the power supply-to-power supply voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL. Thus, the output circuit 100 can be configured from low voltage resistance elements whose voltage difference is, for example, about one-half with respect to the output voltage range (VDDL < DLl voltage < VDDH) of the output terminal DLl, and an area-saving output circuit can be realized.

[0126] As described above, Figure 1In the output circuit 100 shown, an output selection switch 11 that supplies the positive voltage signal Vp to the output terminal DL1 is configured using a PMOS transistor in which the source and the back gate are connected to each other. Also, an output selection switch 12 that supplies the negative voltage signal Vn to the output terminal DL1 is configured using an NMOS transistor in which the source and the back gate are connected to each other.

[0127] Here, regarding the output selection switch 11 (PMOS transistor), in the case of outputting the positive voltage signal Vp, the on state is set by supplying a negative voltage VGn that is within the withstand voltage with respect to the positive voltage signal Vp to the gate. Also, during a period in which the positive voltage signal Vp is not output, the output selection switch 11 is reliably set to the off state by supplying the reference power supply voltage VGND to the gate, and the reference power supply voltage VGND is applied to the source and the back gate of the output selection switch 11.

[0128] Also, regarding the output selection switch 21 (NMOS transistor), in the case of outputting the negative voltage signal Vn, the on state is set by supplying a positive voltage VGp that is within the withstand voltage with respect to the negative voltage signal Vn to the gate. Also, during a period in which the negative voltage signal Vn is not output, the output selection switch 21 is reliably set to the off state by supplying the reference power supply voltage VGND to the gate, and the reference power supply voltage VGND is applied to the source and the back gate of the output selection switch 21.

[0129] It is important that the output circuit 100 is configured by using the positive voltage signal supply circuit, the negative voltage signal supply circuit, and the first to fourth switches as follows, so that each of the switching elements can be configured using a MOS transistor, particularly a MOS transistor with low withstand voltage, and a voltage signal with a wide range of output voltage can be output. That is, the positive voltage signal supply circuit 10A supplies a positive voltage signal Vp with a voltage higher than a reference power supply voltage VGND to the first node Nsll, or blocks the supply of the positive voltage signal to the first node. The negative voltage signal supply circuit 20A supplies a negative voltage signal Vn with a voltage lower than the reference power supply voltage VGND to the second node Ns21, or blocks the supply of the negative voltage signal to the second node. The first switch 11 connects the first output terminal DLl to the first node in the on state, and blocks the connection of the first output terminal to the first node in the off state. The second switch 21 connects the first output terminal DLl to the second node in the on state, and blocks the connection of the first output terminal to the second node in the off state. The third switch 13 applies the reference power supply voltage to the first node in the on state, and stops the application of the reference power supply voltage to the first node in the off state. The fourth switch 23 applies the reference power supply voltage to the second node in the on state, and stops the application of the reference power supply voltage to the second node in the off state.

[0130] In addition, the first switch is configured by a P-channel transistor whose source and back gate are connected to the first node and whose drain is connected to the first output terminal. The second switch is configured by an N-channel transistor whose source and back gate are connected to the second node and whose drain is connected to the first output terminal.

[0131] Therefore, according to the output circuit 100, as an output circuit which switches a positive voltage signal and a negative voltage signal and outputs from an output terminal, a MOS transistor with low withstand voltage can be used to achieve area saving and low cost.

[0132] [Embodiment 2]

[0133] Figure 7 A circuit diagram showing the configuration of an output circuit 200 as a second embodiment of the output circuit of the present application.

[0134] The output circuit 100 alternately outputs a positive voltage signal or a negative voltage signal with respect to a load of one system, and in contrast, the output circuit 200 performs the following polarity inversion drive, that is, outputs a positive voltage signal to one of two loads of two systems, outputs a negative voltage signal to the other, and alternately switches the polarity of both.

[0135] In addition, Figure 7 In the output circuit 200 shown, the positive voltage signal supply circuit 10B is used instead of the positive voltage signal supply circuit 10AFigure 1 The positive voltage signal supply circuit 10A shown is replaced with the negative voltage signal supply circuit 20B, and the control section 35 is replaced with the control section 35A. Furthermore, Figure 7 In the output circuit 200 shown, the output terminal DL2, the switches 14 and 24, the output selection switch 12, and the output selection switch 22 are newly provided, and the other structures are the same as those of the output circuit 200 shown in Figure 1

[0136] Figure 7 In the output circuit 200 shown, the output terminal DL2, the switches 14 and 24, the output selection switch 12, and the output selection switch 22 are newly provided, and the other structures are the same as those of the output circuit 200 shown in

[0137] The output selection switch 12 is constituted by a PMOS transistor whose source and back gate are connected to the node Ns 12 and whose drain is connected to the output terminal DL2. The output selection switch 22 is constituted by an NMOS transistor whose source and back gate are connected to the node Ns 22 and whose drain is connected to the output terminal DL2.

[0138] The switch 14 is constituted by an NMOS transistor connected to the node Ns 12 and the reference power supply voltage VGND. The switch 24 is constituted by a PMOS transistor connected to the node Ns 22 and the reference power supply voltage VGND.

[0139] Figure 7 The positive voltage signal supply circuit 10B shown is constituted by the positive voltage signal supply circuit 10A shown in Fig. 1, to which the switch 16 is added. Figure 1 The positive voltage signal supply circuit 10A shown is replaced with the negative voltage signal supply circuit 20B, and the control section 35 is replaced with the control section 35A. Furthermore,

[0140] The negative voltage signal supply circuit 20B is constituted by the negative voltage signal supply circuit 20A shown in Fig. 1, to which the switch 26 is added. Figure 1 The negative voltage signal supply circuit 20A shown is replaced with the negative voltage signal supply circuit 20B, and the control section 35 is replaced with the control section 35A. Furthermore,

[0141] ​Output selection switches 12 and 22 are controlled to be on and off by control signals St12 and St22 received at their respective gates. Similarly, switches 14 and 24 are controlled to be on and off by control signals Sr12 and Sr22 received at their respective gates. Switches 16 and 26 are controlled to be on and off by control signals Sz12 and Sz22. Figure 7 In this context, the voltages of nodes Ns12 and Ns22 are set as voltage V12 and voltage V22, respectively.

[0142] Figure 7 In the output circuit 200 shown, when a positive voltage signal Vp is output to the output terminal DL1, the output selection switches 11, 21, 13, 15, 23, and 25 that control the output to the output terminal DL1 each perform their respective operations. Figure 2 During the positive drive period (T1, T2), the same on / off control is applied. At this time, the output selection switches 12, 22, 14, 16, 24, and 26 controlling the output to output terminal DL2 each perform the same control as the negative drive period (T3, T4) of output selection switches 11, 21, 13, 15, 23, and 25, outputting a negative voltage signal Vn to output terminal DL2. Furthermore, when outputting the negative voltage signal Vn to output terminal DL1, the output selection switches 11, 21, 13, 15, 23, and 25 controlling the output to output terminal DL1 each perform the same control as the negative drive period (T3, T4), outputting a negative voltage signal Vn to output terminal DL2. Figure 2 During the negative drive period (T3, T4), the same on / off control is applied. At this time, the output selection switches 12, 22, 14, 16, 24, and 26 that control the output to the output terminal DL2 perform the same control as the output selection switches 11, 21, 13, 15, 23, and 25 during the positive drive period (T1, T2), and output a positive voltage signal Vp to the output terminal DL2.

[0143] Control Unit 35A and Figure 1 Similarly, the control unit 35 shown is used to... Figure 2The timing shown generates the control signals Srll, Sr21, Stll, St21, Szll, and Sz21 described above. Further, the control section 35A generates the control signals Sr12, Sr22, St12, St22, Sz12, and Sz22 of the signal patterns described above. In addition, in the case where the switches 15, 16, 25, and 26 are each constituted by a CMOS switch, the respective complementary signals of Szll, Sz12, Sz21, and Sz22 are also generated by the control section 35A.

[0144] Here, the circuit (12, 14, 16, 22, 24, 26) connected to the output terminal DL2 is of the same structure as the circuit (11, 13, 15, 21, 23, 25) connected to the output terminal DLl.

[0145] That is, Figure 7 In the output circuit 200 shown, as with the output circuit 100, the driving control shown is performed. Figures 2-6 However, in the driving control shown with respect to the output terminal DL2, the supply period of the positive voltage signal Vp and the supply period of the negative voltage signal Vn are exchanged. That is, while the positive voltage signal Vp is supplied to the output terminal DLl, the negative voltage signal Vn is supplied to the output terminal DL2, and while the negative voltage signal Vn is supplied to the output terminal DLl, the positive voltage signal Vp is supplied to the output terminal DL2. Figures 2-6

[0146] Further, Figure 7 In the output circuit 200 shown, as with the output circuit 100, each of the switching elements can be constituted by a low-voltage-withstand MOS transistor. Also, the output selection switches 12 and 22 are controlled in the same manner as the output selection switches 11 and 21, whereby a signal of a wide voltage range can be output. Therefore, area saving and low cost of the output circuit can be achieved.

[0147] [Embodiment 3]

[0148] Figure 8 A circuit diagram showing the structure of an output circuit 100A as a third embodiment of the output circuit of the present application. Figure 8 Here, the voltage control circuit 30 is employed as the circuit that generates the control signal Stll in the control section 35, and the voltage control circuit 40 is employed as the circuit that generates the control signal St21, and the other structures are the same as in Figure 1 [Embodiment 4]

[0149] ​The voltage control circuit 30 includes a switch 31 and a switch 32. The switch 31 applies the reference power supply voltage VGND to the node Ngll in the on state, and controls the output selection switch 11 to be off. The switch 32 applies the negative-side voltage VGn within the withstand voltage with respect to the positive electrode voltage signal Vp output from the positive electrode voltage signal supply circuit 10A to the node Ngll in the on state, and controls the output selection switch 11 to be on. The switch 31 and the switch 32 are set to the on state and the off state, respectively, complementarily.

[0150] Here, the voltage (VGND or VGn) of the node Ngll applied from one of the switch 31 and the switch 32 is supplied to the gate of the output selection switch 11 as the control signal Stll. In addition, the voltage VGn has a plurality of voltage values corresponding to the positive electrode voltage signal Vp. For example, the voltage VGn can also be a voltage lower than the voltage obtained by subtracting the absolute value of the threshold voltage of the output selection switch (PMOS transistor) 11 from the reference power supply voltage VGND, and be a voltage value VGnl of (VDDL + VGND) / 2 or more, which is an intermediate voltage between the negative electrode power supply voltage (VDDL) and the reference power supply voltage VGND, and a voltage value VGn2 of the reference power supply voltage VGND or less.

[0151] The voltage control circuit 40 includes a switch 41 and a switch 42. The switch 41 applies the reference power supply voltage VGND to the node Ng21 in the on state, and controls the output selection switch 21 to be off. The switch 42 applies the positive-side voltage VGp within the withstand voltage with respect to the negative electrode voltage signal Vn output from the negative electrode voltage signal supply circuit 20A to the node Ng21 in the on state, and controls the output selection switch 21 to be on. The switch 41 and the switch 42 are set to the on state and the off state, respectively, complementarily.

[0152] Here, the voltage (VGND or VGp) of the node Ng21 applied from one of the switch 41 and the switch 42 is supplied to the gate of the output selection switch 12 as the control signal St21. In addition, the voltage VGp has a plurality of voltage values corresponding to the negative electrode voltage signal Vn. For example, the voltage VGp can be a voltage higher than the voltage obtained by adding the threshold voltage of the output selection switch (NMOS transistor) 21 to the reference power supply voltage VGND, and be a voltage value VGpl of (VDDH + VGND) / 2 or less, which is an intermediate voltage between the positive electrode power supply voltage VDD and the reference power supply voltage VGND, and a voltage value VGp2 of the reference power supply voltage VGND or less.

[0153] Hereinafter, the actual operation of the voltage control circuit 30 and the voltage control circuit 40 will be described.

[0154] First, the operation in the case where the positive voltage signal Vp1 supplied from the positive voltage signal supply circuit 10A to the node Nsll is output to the output terminal DLl via the output selection switch (PMOS transistor switch) 11 will be described. At this time, the switch 32 is set to be on, and a voltage VGn is supplied to the gate of the output selection switch 11.

[0155] Also at this time, in the case where the positive voltage signal Vp is a voltage signal of around the middle voltage between the positive power supply voltage VDDH and the reference power supply voltage, the voltage VGn supplied to the gate of the PMOS transistor switch 11 is set to VGn2 (for example, the reference power supply voltage VGND).

[0156] On the other hand, in the case where the positive voltage signal Vp is a voltage signal of less than around the middle voltage between the positive power supply voltage VDDH and the reference power supply voltage VGND, the voltage VGn supplied to the gate of the PMOS transistor switch 11 is set to VGn1 (for example, a voltage of (VDDL + VGND) / 2 or more and less than VGND).

[0157] Thus, the output selection switch (PMOS transistor switch) 11 can pass a wide range of positive voltage signals of between VGND and VDD, and the gate-source voltage of the output selection switch 11 is controlled to be within the withstand voltage.

[0158] Here, the selection of the voltage value (VGn1, VGn2) of the voltage VGn corresponding to the positive voltage signal Vp can be controlled, for example, by a prescribed bit Dmp on the upper side in a k (k is an integer of 2 or more) bit digital signal corresponding to the voltage level of the positive voltage signal Vp.

[0159] In addition, in the case where the positive voltage signal Vp is output to the output terminal DLl, the output selection switch (NMOS transistor switch) 21 is set to be in the off state. At this time, the node Ns21 is supplied with the reference power supply voltage VGND via the switch 23, and the switch 41 of the voltage control circuit 40 is in the on state, and the reference power supply voltage VGND is also supplied to the gate of the NMOS transistor switch 21. Therefore, the gate and the source of the NMOS transistor switch 21 both become the reference power supply voltage VGND, and the NMOS transistor switch 21 is in the off state.

[0160] Next, the operation in the case where the negative voltage signal Vn supplied from the negative voltage signal supply circuit 20A to the node Ns21 is output to the output terminal DLl via the output selection switch (NMOS transistor switch) 21 will be described. At this time, the switch 42 is set to be on, and a voltage VGp is supplied to the gate of the output selection switch 21.

[0161] Furthermore, at this time, when the negative voltage signal Vn is a voltage signal that is close to the midpoint between the negative power supply voltage VDDL and the reference power supply voltage VGND, the voltage VGp supplied to the gate of the NMOS transistor switch 21 is set to VGp2 (e.g., the reference power supply voltage VGND).

[0162] On the other hand, when the negative voltage signal Vn is a voltage signal near or above the midpoint between the negative power supply voltage VDDL and the reference power supply voltage VGND, the voltage VGp supplied to the gate of the NMOS transistor switch 21 is set to VGp1 (for example, a voltage less than (VDDH+VGND) / 2 and greater than VGND).

[0163] Therefore, the output selection switch (NMOS transistor switch) 21 can allow a wide range of negative voltage signals between VGND and VDDL to pass through, and the gate-source voltage of the output selection switch 21 is controlled within the withstand voltage range.

[0164] Here, the selection of the voltage values ​​(VGp1, VGp2) of the voltage VGp corresponding to the negative voltage signal Vn can be controlled, for example, by a specified bit Dmn on the upper side of a k-bit digital signal (k being an integer greater than 2) corresponding to the voltage level of the negative voltage signal Vn.

[0165] Furthermore, when a negative voltage signal Vn is output to the output terminal DL1, the output selection switch (PMOS transistor) 11 is set to the off state. At this time, node Ns11 is supplied with the reference power supply voltage VGND through switch 13, and switch 31 of voltage control circuit 30 is turned on, also supplying the reference power supply voltage VGND to the gate of PMOS transistor 11. Therefore, both the gate and source of PMOS transistor 11 become the reference power supply voltage VGND, and PMOS transistor 11 is turned off.

[0166] According to the aforementioned structure, voltage control circuit 30 operates within a voltage range between the negative-side voltage VGn and the reference power supply voltage VGND, while voltage control circuit 40 operates within a voltage range between the reference power supply voltage VGND and the positive-side voltage VGp. Therefore, both voltage control circuit 30 and voltage control circuit 40 can be constructed using low-voltage components.

[0167] Furthermore, by placing the voltage control circuit 30 in Figure 7 The output circuit 200 shown has output selection switches 11 and 12, each with its gate. A voltage control circuit 40 is located at the gate of each output selection switch 21 and 22, thereby enabling... Figure 7 The structure shown can also output voltage signals with a wide voltage range.

[0168] expressFigure 8 The control section 35 of the output circuit 100A, and the control signals Srll, the control signals Sr21, the control signals Stll, the control signals St21, the control signals Szll, and the control signals Sz21 generated by the voltage control circuit 30 and the voltage control circuit 40 included in the control section 35 have the same time chart as that of the output circuit 100B. Figure 2 Hereinafter, the operation of the voltage control circuit 30 and the voltage control circuit 40 will be described. Figure 2

[0169] In the period Tl, the voltage control circuit 30 supplies the control signal Stll having the reference power supply voltage VGND to the gate of the output selection switch (PMOS transistor) 11. Further, in the period Tl, the voltage control circuit 40 continues to supply the control signal St21 having the voltage VGp supplied in the negative electrode drive period before the period Tl to the gate of the output selection switch (NMOS transistor) 21. Thus, the output selection switch 11 and the output selection switch 21 are set to the off and on states, respectively. Figure 2 In the period T2, the voltage control circuit 30 supplies the control signal Stll having the voltage value of the voltage VGn selected based on the prescribed bit Dmp on the upper side in the k-bit digital signal corresponding to the voltage level of the positive electrode voltage signal Vp to the gate of the output selection switch (PMOS transistor) 11. Further, in the period T2, the voltage control circuit 40 supplies the control signal St21 having the reference power supply voltage VGND to the gate of the output selection switch (NMOS transistor) 21. Thus, the output selection switch 11 and the output selection switch 21 are set to the on and off states, respectively.

[0170] In the period T3, the voltage control circuit 30 continues to supply the control signal Stll having the voltage VGn supplied in the period T2 to the gate of the output selection switch (PMOS transistor) 11. Further, in the period T3, the voltage control circuit 40 supplies the control signal St21 having the reference power supply voltage VGND to the gate of the output selection switch (NMOS transistor) 21. Thus, the output selection switch 11 and the output selection switch 21 are set to the on and off states, respectively.

[0171]

[0172] ​Next, during period T4, the voltage control circuit 30 supplies a control signal St11, having a reference power supply voltage VGND, to the gate of the output selection switch (PMOS transistor) 11. Furthermore, during the same period T4, the voltage control circuit 40 supplies a control signal St21, having a voltage value VGp selected based on a predetermined bit Dmn on the upper side of a k-bit digital signal corresponding to the voltage level of the negative voltage signal Vn. This sets the on / off state of the output selection switch 21.

[0173] In addition, regarding the waveforms of other control signals besides those mentioned above, and the voltages V11 at node Ns11, V21 at node Ns21, and the voltage at output terminal DL1, and... Figure 2 As shown, the description is omitted.

[0174] [Example 4]

[0175] Figure 9 This is a circuit diagram illustrating the structure of output circuit 100-1, which is the fourth embodiment of the output circuit of the present invention. Furthermore, output circuit 100-1 is related to... Figure 1 , Figure 7 and Figure 8 Similarly, the output circuits 100, 200, and 100A shown can switch between outputting a positive voltage signal Vp and a negative voltage signal Vn. Output circuit 100-1 is an output circuit that can realize each switch including an output selection switch not only using transistor circuits formed on a semiconductor substrate, but also using thin-film transistor circuits without a back gate, such as those formed on an insulating substrate like glass or plastic.

[0176] like Figure 9 As shown, the output circuit 100-1 includes a positive voltage signal supply circuit 10A, a negative voltage signal supply circuit 20A, an output selection switch 11a, an output selection switch 21a, a switch 13a, a switch 23a, a capacitor element C11, a capacitor element C21, a control unit 35, and an output terminal DL1.

[0177] The positive voltage signal supply circuit 10A includes an amplifier circuit 10 and a switch 15. The amplifier circuit 10 is, for example, an operational amplifier with a voltage follower whose output terminal is connected to its inverting input terminal. Alternatively, the amplifier circuit 10 may be an amplifier circuit that amplifies the input voltage signal Vpi with a gain of less than 1 or a gain of more than 1.

[0178] The amplification circuit 10 is supplied with a power supply voltage VGND and a power supply voltage VDDH, receives a positive voltage signal Vp having a voltage value of a positive polarity at a non-inverted input terminal thereof, and amplifies and outputs the positive voltage signal Vp.

[0179] In addition, the positive voltage signal Vp is a signal of a positive polarity whose voltage value varies within a range described below.

[0180] VGND < Vp < VDDH

[0181] VGND = reference power supply voltage (e.g., 0 V)

[0182] VDDH = positive power supply voltage (e.g., 5 V)

[0183] The amplification circuit 10 outputs the positive voltage signal Vp from an output terminal thereof and supplies it to the switch 15.

[0184] The switch 15 is set to an on state or an off state in accordance with a control signal Sz11. The switch 15, when set to the on state, supplies the positive voltage signal Vp output from the amplification circuit 10 to the output selection switch 11a via a node Ns11.

[0185] In addition, as the amplification circuit 10, an amplification circuit including the function of the switch 15 can also be used.

[0186] The switch 13a is, for example, a thin film transistor or an NMOS transistor that receives a control signal Sr11 at a gate electrode. A drain electrode of the switch 13a is connected to the node Ns11, and a source electrode is applied with the reference power supply voltage VGND. The switch 13a becomes an off state when the control signal Sr11 received at the gate electrode thereof has the reference power supply voltage VGND. On the other hand, when the control signal Sr11 has the positive power supply voltage VDDH, the switch 13a becomes an on state, and applies the reference power supply voltage VGND to the node Ns11.

[0187] The output selection switch 11a is, for example, a thin film transistor or a PMOS transistor that receives a control signal St11 at a gate electrode. A source electrode of the output selection switch 11a is connected to the node Ns11, and a drain electrode is connected to an output terminal DL1. The output selection switch 11a becomes an off state when the control signal St11 received at the gate electrode thereof has the reference power supply voltage VGND when the node Ns11 is the reference power supply voltage VGND. On the other hand, when the control signal St11 has a negative voltage VGn that is a prescribed voltage difference on the negative side with respect to the positive voltage signal Vp, the output selection switch 11a becomes an on state, and electrically connects the node Ns11 and the output terminal DL1.

[0188] One end of a capacitor element Cll is commonly connected to the source of the output selection switch 11a and to the node Nsll. The other end of the capacitor element Cll is connected to the gate of the output selection switch 11a. The capacitor element Cll holds the gate-source voltage of the output selection switch 11a using the charge accumulated in its own capacitor when the gate (node Ngll) of the output selection switch 11a is in a high impedance (HiZ) state.

[0189] The negative voltage signal supply circuit 20A includes an amplification circuit 20 and a switch 25. The amplification circuit 20 is, for example, an operational amplifier of a voltage follower in which the output terminal and the inverting input terminal are connected to each other. Alternatively, the amplification circuit 20 can be an amplification circuit that amplifies the input voltage signal Vni with a gain of less than 1 or a gain of 1 or more.

[0190] The amplification circuit 20 is supplied with a power supply voltage VGND and a power supply voltage VDDL, receives the negative voltage signal Vni having a voltage value of a negative polarity at the non-inverting input terminal, and amplifies and outputs the negative voltage signal Vn.

[0191] The negative voltage signal Vn is a signal of a negative polarity whose voltage value is in the following range.

[0192] VGND > Vn > VDDL

[0193] VGND = reference power supply voltage (for example, 0 V)

[0194] VDDL = negative power supply voltage (for example, -5 V)

[0195] The amplification circuit 20 outputs the negative voltage signal Vn from the output terminal and supplies it to the switch 25.

[0196] The switch 25 is set to an on state or an off state in accordance with a control signal Sz21. When the switch 25 is set to the on state, the negative voltage signal Vn output from the amplification circuit 20 is supplied to the output selection switch 21a via the node Ns21. Alternatively, the amplification circuit 20 can be an amplification circuit that includes the function of the switch 25.

[0197] The switch 23a includes, for example, a thin film transistor or a PMOS transistor that receives a control signal Sr21 at a gate. A drain of the switch 23a is connected to the node Ns21, and a source is applied with a reference power supply voltage VGND. The switch 23a becomes in an off state when the control signal Sr21 received at the gate thereof has the reference power supply voltage VGND. On the other hand, the switch 23a becomes in an on state when the control signal Sr21 has a negative power supply voltage VDDL, and applies the reference power supply voltage VGND to the node Ns21.

[0198] The output selection switch 21a includes, for example, a thin film transistor or an NMOS transistor that receives a control signal St21 at a gate. A source of the output selection switch 21a is connected to the node Ns21, and a drain is connected to the output terminal DL1. The output selection switch 21a becomes in an off state when the control signal St21 received at the gate thereof has the reference power supply voltage VGND, in a case where the node Ns21 is the reference power supply voltage VGND. On the other hand, the output selection switch 21a becomes in an on state when the control signal St21 has a positive voltage VGp with respect to the negative voltage signal Vn by a prescribed voltage difference, and electrically connects the node Ns21 and the output terminal DL1.

[0199] One end of a capacitor element C21 is commonly connected to the source of the output selection switch 21a and the node Ns21. The other end of the capacitor element C21 is connected to the gate of the output selection switch 21a. The capacitor element C21 holds the gate-source voltage of the output selection switch 21a using the charge accumulated in the capacitor thereof when the gate (the node Ng21) of the output selection switch 21a is in a high impedance state (hereinafter, referred to as HiZ).

[0200] The control section 35 generates the control signal Sr11, the control signal Sr21, the control signal St11, the control signal St21, the control signal Sz11, and the control signal Sz21 as control signals that select one of the positive voltage signal Vp and the negative voltage signal Vn. Among them, the control signal St11 is generated by a voltage control circuit 130 included in the control section 35, and the control signal St21 is generated by a voltage control circuit 140 included in the control section 35.

[0201] The voltage control circuit 130 includes switches 131 and 132. When switch 131 is in the ON state, it applies the reference power supply voltage VGND to node Ng11, controlling the output selection switch 11a to the OFF state. When switch 132 is in the ON state, it applies the negative power supply voltage VDDL to node Ng11, accumulating a charge in capacitor C11 corresponding to the gate-source voltage of output selection switch 11a. Both switches 131 and 132 are set to the OFF state when outputting the positive voltage signal Vp to output terminal DL1. At this time, the gate (node ​​Ng11) of output selection switch 11a is set to the HiZ state, but the charge accumulated in capacitor C11 is used to maintain the gate-source voltage of output selection switch 11a, keeping output selection switch 11a in the ON state.

[0202] The voltage control circuit 140 includes switches 141 and 142. When switch 141 is in the ON state, it applies the reference power supply voltage VGND to node Ng21, controlling the output selection switch 21a to the OFF state. When switch 142 is in the ON state, it applies the positive power supply voltage VDDH to node Ng21, accumulating a charge in capacitor C21 corresponding to the gate-source voltage of output selection switch 21a. Both switches 141 and 142 are set to the OFF state when outputting the negative voltage signal Vn to output terminal DL1. At this time, the gate (node ​​Ng11) of output selection switch 21a is set to the HiZ state, but the charge accumulated in capacitor C21 is used to maintain the gate-source voltage of output selection switch 21a, keeping output selection switch 21a in the ON state.

[0203] Figure 10 To indicate Figure 9 A timing diagram of an example of the control signals Sr11, Sr21, St11, St21, Sz11, and Sz21 generated by the control unit 35 and the voltage control circuit 130 and voltage control circuit 140 included in the control unit 35.

[0204] in addition, Figure 10 This example illustrates a control signal generated by the control unit 35 when the output circuit 100-1 periodically alternates between outputting positive voltage signals Vp and negative voltage signals Vn, performing a so-called polarity reversal drive. Furthermore, Figure 10In the diagram, during the positive drive period of the output positive voltage signal Vp and the negative drive period of the output negative voltage signal Vn, the on / off control of each switch and the changes in the voltages V11 at node Ns11, V21 at node Ns21, and the voltage at output terminal DL1 are also shown. Furthermore, the positive voltage signal Vp and the negative voltage signal Vn can be single or multiple step signals, or variable signals such as sine waves, within the voltage range corresponding to their respective polarities.

[0205] like Figure 10 As shown, the positive drive period is divided into at least two periods, T1 and T2, and the negative drive period is also divided into at least two periods, T3 and T4. Furthermore, period T1 is divided into periods T1A and T1B only for control signal St11, and period T3 is divided into periods T3A and T3B only for control signal St21.

[0206] The following is a reference. Figure 10 as well as Figures 11-14 On the one hand, with Figure 10 The detailed operation of the output circuit 100-1 corresponding to the control signals Sr11, Sr21, St11, St21, Sz11, and Sz21 shown is explained. Furthermore, Figures 11-14 This is an equivalent circuit diagram representing the state of the output circuit 100 during each of periods T1 to T4. At this time, just before entering period T1 (initial state), the circuit is in the following state: the negative voltage signal Vn generated by the negative voltage signal supply circuit 20A is supplied to the output terminal DL1 via the output selection switch 21a; this is the operating state during period T4 of the negative drive period. Furthermore, Figures 11-14 In the diagram, dotted lines represent the paths of the HiZ state where the signal supply is blocked.

[0207] Figure 10 In the process, firstly, during period T1, switches 15 and 25 are both turned off according to control signals Sz11 and Sz21, blocking the supply of voltage signals from the positive voltage signal supply circuit 10A and the negative voltage signal supply circuit 20A. Furthermore, during period T1, a control signal Sr11 with a positive power supply voltage VDDH is supplied to the gate of switch 13a, turning switch 13a on, and driving the voltage V11 at node Ns11 to the reference power supply voltage VGND. Moreover, a control signal Sr21 with a negative power supply voltage VDDL is supplied to the gate of switch 23a, turning switch 23a on. Figure 10 As shown, the voltage V21 of node Ns21 is increased from the negative voltage signal Vn during the previous negative drive to the reference power supply voltage VGND.

[0208] Furthermore, during period T1, switches 141 and 142 of the voltage control circuit 140 are both in the off state, and the gate of the output selection switch 21a continues to maintain the voltage VGp from the previous negative drive period in the Hiz state. In addition, the voltage VGp at the gate of the output selection switch 21a is maintained at a voltage difference with the source voltage of the output selection switch 21a through capacitor element C21, and thus changes in conjunction with the voltage change of the voltage V21 at node Ns21. Therefore, as... Figure 11 As shown, the output selection switch 21a remains on, and the reference power supply voltage VGND driven at node Ns21 is applied to the output terminal DL1 via the output selection switch 21a. Therefore, as Figure 10 As shown, the voltage at the output terminal DL1 of the negative voltage signal Vn is boosted to the reference power supply voltage VGND via the output selection switch 21a.

[0209] Furthermore, the control signal St11 is controlled during periods T1A and T1B, which divide period T1 into two. During the first half of period T1, period T1A, switch 131 in voltage control circuit 130 and switch 132 is turned on, supplying the gate of output selection switch 11a with the control signal St11 having the reference power supply voltage VGND. Thus, as... Figure 11 As shown, the output selection switch 11a is in the off state.

[0210] Moreover, the control signal St11 controls, as Figure 10 As shown, after the voltage at the output terminal DL1 is sufficiently boosted to the reference power supply voltage VGND, the circuit switches from the first half (T1A) of period T1 to the second half (T1B). During period T1B, switch 132 in voltage control circuit 130 is turned on, supplying a control signal St11, which is the negative power supply voltage VDDL, to the gate of output selection switch 11a. Thus, as... Figure 11 As shown, the output selection switch 11a is switched to the ON state.

[0211] During this period T1B, the capacitor element C11 stores a charge equal to the voltage difference (VDDL - VGND) between the reference power supply voltage VGND supplied to node Ns11 and the negative power supply voltage VDDL supplied to the gate of output selection switch 11a. The voltage of the gate of output selection switch 11a relative to node Ns11 is maintained at the negative side voltage VGn by the gate-source voltage difference (VDDL - VGND) of output selection switch 11a.

[0212] Furthermore, throughout the entire period T1, the terminals (gate, drain, and source) of switch 13a are controlled between the reference power supply voltage VGND and the positive power supply voltage VDDH. The terminals of output selection switches 11a, 23a, and capacitor C11 are controlled between the reference power supply voltage VGND and the negative power supply voltage VDDL. The drain and source terminals of output selection switch 21a are controlled between the reference power supply voltage VGND and the negative power supply voltage VDDL. The voltage of the gate of output selection switch 21a relative to its source is maintained at the positive side voltage VGp within the withstand voltage range through capacitor C21 in the Hiz state. Therefore, output selection switches 11a, 21a, 13a, 23a, C11, and C21 are controlled within any withstand voltage range of the voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH, or the voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0213] Next, during period T2, a control signal Sr11 with the reference power supply voltage VGND is supplied to the gate of switch 13a, and switch 13a becomes open. Furthermore, during period T2, a control signal Sr21 with the negative power supply voltage VDDL continues to be supplied to the gate of switch 23a, and switch 23a remains on. Thus, Figure 12 The voltage V21 at node Ns21 shown maintains the reference power supply voltage VGND. Furthermore, during period T2, switch 141 in voltage control circuit 140 and switch 142 is turned on, supplying a control signal St21 with the reference power supply voltage VGND to the gate of output selection switch 21a. Thus, as... Figure 12 As shown, output selection switch 21a is in the off state. Furthermore, during period T2, switches 131 and 132 of the voltage control circuit 130 are both in the off state, the supply of control signal St11 is blocked, and the gate (node ​​Ng11) of output selection switch 11a is set to the Hiz state. However, the capacitor element c11 retains the charge of the voltage difference (VDDL - VGND) accumulated during period T1B, thus maintaining the gate-source voltage (VDDL - VGND) of output selection switch 11a, and output selection switch 11a remains in the on state throughout period T2. Moreover, during period T2, switch 15 is turned on according to control signal Sz11, as... Figure 12As shown, the positive voltage signal Vp is supplied from the positive voltage signal supply circuit 10A to the node Nsll. Also, during the period T2, the switch 25 is maintained in the off state by the control signal Sz21, so the supply of the voltage signal from the negative voltage signal supply circuit 20A continues to be blocked. Further, during the period T2, the gate voltage VGn of the output selection switch 11a varies in linkage with the voltage variation of the node Nsll in a state in which the voltage difference (VDDL - VGND) is maintained. Further, during the period T2, the voltage of the output terminal DLl, to which the positive voltage signal Vp is supplied via the output selection switch 11a, varies from the reference power supply voltage VGND to the positive voltage signal Vp as shown. Figure 10 In the signal waveform of the control signal Stll during which the supply of the control signal Stll is blocked, the gate voltage waveform of the output selection switch 11a is indicated by a dotted line signal in the signal waveform.

[0214] Therefore, during the period T2, as shown, the positive voltage signal Vp is supplied to the output terminal DLl via the output selection switch 11a, and the voltage of the output terminal DLl varies from the reference power supply voltage VGND to the positive voltage signal Vp as shown. Figure 12 At this time, with respect to any positive voltage signal Vp in the range from the reference power supply voltage VGND to the positive power supply voltage VDDH, the output selection switch 11a has a gate-source voltage difference (VDDL - VGND) in a state in which the low on-resistance is maintained, so a high current supply capability (high driving capability) can be exerted. Also, during the period T2, even if the voltage value of the positive voltage signal Vp varies, the output selection switch 11a can realize a high current supply capability (high driving capability) in a state in which the low on-resistance is maintained. Figure 10 Further, during the entire period T2, each terminal (gate, drain, source) of the switch 13a and the output selection switch 21a is controlled between the reference power supply voltage VGND and the positive power supply voltage VDDH. Each terminal of the switch 23a is controlled between the reference power supply voltage VGND and the negative power supply voltage VDDL. The drain and the source of each terminal of the output selection switch 11a are controlled between the reference power supply voltage VGND and the positive power supply voltage VDDH. The gate of the output selection switch 11a is controlled to a negative side voltage VGn within the withstand voltage by the capacitor element Cl l in the Hiz state with respect to the source. Therefore, the output selection switch 11a, the output selection switch 21a, and the switches 13a and 23a, and the capacitor elements Cl l and C21 are controlled within any withstand voltage range of the power supply-to-power supply voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH, or the power supply-to-power supply voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0215]

[0216] ​Next, during period T3, switches 15 and 25 are both turned off according to control signals Sz11 and Sz21, blocking the supply of voltage signals from the positive voltage signal supply circuit 10A and the negative voltage signal supply circuit 20A. Furthermore, during period T3, a control signal Sr21 with a negative power supply voltage VDDL is continuously supplied to the gate of switch 23a, keeping switch 23a in the on state, and the voltage V21 at node Ns21 is driven to the reference power supply voltage VGND. Moreover, a control signal Sr11 with a positive power supply voltage VDDH is supplied to the gate of switch 13a, turning switch 13a into the on state, as... Figure 10 As shown, the voltage V11 at node Ns11 decreases from the positive voltage signal Vp during period T2 to the reference power supply voltage VGND.

[0217] Furthermore, during period T3, switches 131 and 132 of the voltage control circuit 130 remain in the off state, and the gate of the output selection switch 11a continues to maintain the voltage VGn of period T2 in the HiZ state. In addition, the voltage VGn of the gate of the output selection switch 11a is maintained at a voltage difference with the voltage of the source of the output selection switch 11a through the capacitor element C11, and thus changes in conjunction with the voltage change of the voltage V11 at node Ns11. Therefore, as... Figure 13 As shown, the output selection switch 11a remains on, and the reference power supply voltage VGND driven at node Ns11 is applied to the output terminal DL1 via the output selection switch 11a. Therefore, as Figure 10 As shown, the voltage at the output terminal DL1 of the positive voltage signal Vp is reduced to the reference power supply voltage VGND via the output selection switch 11a.

[0218] Furthermore, the control signal St21 is controlled during periods T3A and T3B, which divide period T3 into two. During the first half of period T3A, switch 141 in voltage control circuit 140 and switch 142 are in the ON state, supplying the gate of output selection switch 21a with a control signal St21 having a reference power supply voltage VGND. Thus, as... Figure 13 As shown, the output selection switch 21a is in the off state.

[0219] Moreover, the control signal St21 controls, as Figure 10 As shown, after the voltage at the output terminal DL1 is sufficiently boosted to the reference power supply voltage VGND, the circuit switches from the first half (T1A) of period T1 to the second half (T1B). During period T3B, switch 142 in voltage control circuit 140 is turned on, supplying a control signal St21 with a positive power supply voltage VDDH to the gate of output selection switch 21a. Thus, as... Figure 13As shown, the output selection switch 21a is switched to the on state.

[0220] At this time, during the period T3B, the voltage difference (VDDH - VGND) of the voltage difference between the voltage of the reference power supply voltage VGND supplied to the node Ns21 and the voltage of the positive power supply voltage VDDH supplied to the gate of the output selection switch 21a is stored as the charge in the capacitor element C21. The voltage of the gate of the output selection switch 21a with respect to the node Ns21 is maintained at the positive side voltage VGp by the voltage difference (VDDH - VGND) between the gate-source voltage of the output selection switch 21a.

[0221] In addition, during the entire period T3, each terminal (gate, drain, source) of the switch 23a is controlled between the reference power supply voltage VGND and the negative power supply voltage VDDL. Each terminal of the output selection switch 21a, the switch 13a, and the capacitor element C21 is controlled between the reference power supply voltage VGND and the positive power supply voltage VDDH. The drain and the source among the terminals of the output selection switch 11a are controlled between the reference power supply voltage VGND and the positive power supply voltage VDDH. The voltage of the gate of the output selection switch 11a with respect to the source is maintained at the negative side voltage VGn within the withstand voltage by the capacitor element C11 in the Hiz state. Thus, the output selection switch 11a, the output selection switch 21a, and the switches 13a and 23a, and the capacitor elements C11 and C21 are controlled within any of the withstand voltage ranges of the power supply voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH or the power supply voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0222] Next, during the period T4, the control signal Sr21 having the reference power supply voltage VGND is supplied to the gate of the switch 23a, and the switch 23a becomes the off state. Also, during the period T4, the control signal Sr11 having the positive power supply voltage VDDH continues to be supplied to the gate of the switch 13a, and the switch 13a maintains the on state. Thus, as shown in FIG. 6, the voltage V11 with respect to the node Ns11 also maintains the reference power supply voltage VGND. Also, during the period T4, the switch 131 among the switches 131 and 132 of the voltage control circuit 130 becomes the on state, and the control signal St11 having the reference power supply voltage VGND is supplied to the gate of the output selection switch 11a and the capacitor element C11. Thus, as shown in FIG. 6, the voltage V11 with respect to the node Ns11 also maintains the reference power supply voltage VGND. Figure 10 Figure 14 ​As shown, the output selection switch 11a becomes the off state. Further, in the period T4, both the switch 141 and the switch 142 of the voltage control circuit 140 become the off state, the supply of the control signal St21 is blocked, and the gate (the node Ng21) of the output selection switch 21a is set to the Hiz state. However, in the capacitance element c21, the charge of the voltage difference (VDDH - VGND) accumulated in the period T3B is held, and thus the gate-source voltage difference (VDDH - VGND) of the output selection switch 21a is held, and the output selection switch 11a maintains the on state throughout the period T4. Further, in the period T4, the switch 25 becomes the on state according to the control signal Sz21, and as shown in Figure 14 the negative electrode voltage signal Vn is supplied from the negative electrode voltage signal supply circuit 20A to the node Ns21. Further, in the period T4, the switch 15 is maintained in the off state by the control signal Sz11, and thus the supply of the voltage signal from the positive electrode voltage signal supply circuit 10A is continued to be blocked. Further, in the period T4, the gate voltage VGp of the output selection switch 21a changes with respect to the voltage of the node Ns21 in a state in which the voltage difference (VDDH - VGND) is maintained in linkage. Further, Figure 10 In the signal waveform of the control signal St21 in which the supply of the control signal St21 is blocked, the gate voltage waveform of the output selection switch 21a is indicated by a dotted line signal in the signal waveform of the period in which the supply of the control signal St21 is blocked.

[0223] Thus, in the period T4, as shown in Figure 14 the negative electrode voltage signal Vn is supplied to the output terminal DL1 via the output selection switch 21a, and the voltage of the output terminal DL1 changes from the reference power source voltage VGND to the negative electrode voltage signal Vn as shown in Figure 10 At this time, with respect to any negative electrode voltage signal Vn in the range from the reference power source voltage VGND to the negative power source voltage VDDL, the output selection switch 21a has the gate-source voltage difference (VDDH - VGND) in a state in which the low on-resistance is maintained, and thus can exhibit a high current supply capability (high driving capability). Further, in the period T4, even if the voltage value of the negative electrode voltage signal Vn changes, the output selection switch 21a can achieve a high current supply capability (high driving capability) in a state in which the low on-resistance is maintained.

[0224] Further, in the entire period T4, each terminal (gate, drain, source) of the switch 23a and the output selection switch 11a is controlled between the reference power supply voltage VGND and the negative power supply voltage VDDL. Each terminal of the switch 13a is controlled between the reference power supply voltage VGND and the positive power supply voltage VDDH. The drain and the source of each terminal of the output selection switch 21a are controlled between the reference power supply voltage VGND and the negative power supply voltage VDDL. The voltage of the gate of the output selection switch 21a with respect to the source is held at the positive side voltage VGp within the withstand voltage by the capacitor element c21 in the HiZ state. Thus, the output selection switch 11a, the output selection switch 21a, and the switches 13a and 23a, and the capacitor elements C11 and C21 are controlled within any withstand voltage range of the power supply voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH or the power supply voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0225] Figures 10-14 The driving control of the output terminal DL1 is characterized in that at least the switching period (T1) is provided at the time of switching from the supply period (T4) of the negative voltage signal Vn to the supply period (T2) of the positive voltage signal Vp. In the switching period (T1), the node Nsll, the node Ns21, and the output terminal DL1 are driven to the reference power supply voltage VGND. Further, in the first half (T1A) of the switching period, the gate of the output selection switch 11a is set to the reference power supply voltage VGND, and in the second half (T1B) of the switching period, the gate of the output selection switch 11a is set to the negative power supply voltage VDDL. Thus, in the second half (T1B) of the switching period, the gate-source voltage difference (VDDL - VGND) of the output selection switch 11a is maintained, and the charge capable of maintaining the on state is accumulated in the capacitor element C11. Next, in the supply period (T2) of the positive voltage signal Vp, the gate of the output selection switch 11a is set to the HiZ state, and the low on resistance of the output selection switch 11a is maintained by the gate-source voltage difference accompanying the charge held in the capacitor element C11. Thus, a high current supply capability (driving capability) can be achieved with respect to the positive voltage signal Vp having an arbitrary voltage value. Further, the output selection switch 11a, the output selection switch 21a, and the switches 13a and 23a, and the capacitor elements C11 and C21 can be controlled within any withstand voltage range of the power supply voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH or the power supply voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0226] Similarly, at the time of switching from the supply period (T2) of the positive voltage signal Vp to the supply period (T4) of the negative voltage signal Vn, at least a switching period (T3) is provided. In the switching period (T3), the node Nsll, the node Ns21, and the output terminal DLl are driven to the reference power supply voltage VGND. In the first half of the switching period (T3A), the gate of the output selection switch 21a is set to the reference power supply voltage VGND, and in the second half of the switching period (T3B), the gate of the output selection switch 21a is set to the positive power supply voltage VDDH. Thus, in the second half of the switching period (T3B), the gate-source voltage difference (VDDH - VGND) of the output selection switch 21a is maintained, and the charge capable of maintaining the on state is accumulated in the capacitor element C21. Next, in the supply period (T4) of the negative voltage signal Vn, the gate of the output selection switch 21a is set to the HiZ state, and the low on resistance of the output selection switch 21a is maintained by the gate-source voltage difference accompanying the charge maintained in the capacitor element C21. Thus, a high current supply capability (driving capability) can be achieved with respect to the negative voltage signal Vn having an arbitrary voltage value. Furthermore, the output selection switch 11a, the output selection switch 21a, and the switches 13a, 23a, and the capacitor elements Cll, C21 can be controlled within any voltage range of the power supply voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH or the power supply voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0227] Furthermore, by causing the positive voltage signal supply circuit 10A to operate with the power supply voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH and causing the negative voltage signal supply circuit 20A to operate with the power supply voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL, the output circuit 100-1 can be controlled within any voltage range of the power supply voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH or the power supply voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL. Therefore, the output circuit 100-1 can be constituted by low voltage elements having a voltage difference of, for example, about one-half with respect to the output voltage range (VDDL < DLl voltage < VDDH) of the output terminal DLl. The low voltage elements (transistors) can be reduced in size according to a scaling rule, for example, and thus the output circuit 100 constituted by low voltage elements can be greatly reduced in circuit area.

[0228] Furthermore, Figure 10In the period T2 during the positive electrode drive period, a drive control example in which one positive electrode voltage signal Vp is output to the output terminal DLl is shown, but drive control can also be performed in a manner in which a plurality of positive electrode voltage signals Vp having different voltage values are continuously output from the positive electrode voltage signal supply circuit 10A and output to the output terminal DLl. Similarly, in the period T4 during the negative electrode drive period, a drive example in which one negative electrode voltage signal Vn is output to the output terminal DLl is shown, but drive control can also be performed in a manner in which a plurality of negative electrode voltage signals Vn having different voltage values are continuously output from the negative electrode voltage signal supply circuit 20A and output to the output terminal DLl. Furthermore, other control can be added before or after the switching periods (Tl, T3) as necessary.

[0229] Furthermore, in the embodiment, a drive control example in which the positive electrode drive period and the negative electrode drive period are alternately switched is shown, but control corresponding to the rise or fall of the power supply voltage is performed at the time of power supply input or at the time of power supply disconnection. For example, at the time of rise or fall of the power supply voltage, in order to drive a capacitive load connected to the output terminal to the reference power supply voltage, control can also be performed in a manner in which the supply of voltage signals from the positive electrode voltage signal supply circuit 10A and the negative electrode voltage signal supply circuit 20A is blocked (both the switch 15 and the switch 25 are opened), and the output selection switch 11a, the output selection switch 21a, the switch 13a, and the switch 23a are all in the on state.

[0230] [Embodiment 5]

[0231] Figure 15 A circuit diagram showing the structure of an output circuit 100-2 which is a fifth embodiment of the output circuit of the present application. In addition, the output circuit 100-2 is structured such that a transistor gate capacitor Cll a is used in place of the capacitor element Cll of the output circuit 100-1 shown in FIG. 1, and a transistor gate capacitor C21a is used in place of the capacitor element C21. The other structures are the same as those shown in FIG. 1. Figure 9 Figure 9 Therefore, the description of the other structures except for the transistor gate capacitor Cll a and the transistor gate capacitor C21a is omitted.

[0232] The transistor gate capacitor Cll a includes a transistor of the same conductivity type, for example, a P-channel type, as the output selection switch 11a. That is, the transistor gate capacitor Cll a is composed of a P-channel transistor whose drain and source are connected to each other, and the connection point is connected to the node Nsl l, and the gate is connected to the gate of the output selection switch 11a (the node Ngll).

[0233] ​The gate capacitance C21a of the transistor includes a transistor of the same conductivity type as the output selection switch 21, for example, an N-channel type. That is, the gate capacitance C21a of the transistor is composed of an N-channel transistor whose drain and source are connected to each other, and the connection point is connected to the node Ns21, and the gate is connected to the gate (node Ng21) of the output selection switch 21a.

[0234] That is, Figure 15 In the output circuit 100-2 shown, the capacitances C11a and C21a are implemented using the gate capacitances of transistors, and the overall structure is the same as that of the output circuit 100-1 shown. Figure 9 By using the gate capacitances of transistors to compose the capacitances C11a and C21a, it is possible to form them using the process of transistors without adding a process (cost increase) for forming individual capacitor elements.

[0235] [Embodiment 6]

[0236] Figure 16 A circuit diagram showing the structure of an output circuit 100-3 as a sixth embodiment of the output circuit of the present application. In addition, the output circuit 100-3 is structured such that the switches 13 and 23 shown in Figure 1 are replaced by the switches 13a and 23a shown in Figure 9 are replaced by the output selection switches 11 and 21 shown in Figure 1 are replaced by the output selection switches 11a and 21a shown in Figure 9 The other structures and the overall operation of the circuit are the same as those of the output circuit 100-1 shown. However, in implementing the output circuit 100-3, at least the switches 13, 23, output selection switches 11, and output selection switches 21 are structured such that MOS structures formed on a semiconductor substrate such as a silicon substrate have a back gate. Figure 9

[0237] [Embodiment 7]

[0238] Figure 17 A circuit diagram showing the structure of an output circuit 100-4 as a seventh embodiment of the output circuit of the present application. In addition, the structure of the output circuit 100-4 is the same as that of the output circuit 100-1 shown except that Figure 9 the switch 131 included in the voltage control circuit 130 is replaced by the switch 131a, and the switch 141 included in the voltage control circuit 140 is replaced by the switch 141a.

[0239] ​The switch 131a connects the gate of the output selection switch 11a to the node Nsll in the on state. That is, the switch 131a shorts the source and the gate of the output selection switch 11a in the on state, and thus the output selection switch 11a is set to the off state as in the on state of the switch 131.

[0240] The switch 141a connects the gate of the output selection switch 21a to the node Ns21 in the on state. That is, the switch 141a shorts the source and the gate of the output selection switch 21a in the on state, and thus the output selection switch 21a is set to the off state as in the on state of the switch 141.

[0241] [Embodiment 8]

[0242] Figure 18 is a circuit diagram showing the structure of an output circuit 200-1 as an eighth embodiment of the output circuit of the present application. In addition, the output circuit 200-1 is an output circuit in which the output selection switches 11a, 12a, 21a, and 22a are formed of MOS transistors formed on a semiconductor substrate, and the switches 13a, 14a, 23a, and 24a are formed of MOS transistors formed on a semiconductor substrate. Figure 7 The output circuit in which the so-called polarity inversion drive is performed, that is, the positive voltage signal Vp is output from one of the output terminals DLl and DL2, the negative voltage signal Vn is output from the other output terminal, and the polarity of both is switched at a predetermined timing.

[0243] Figure 7 In the output circuit 200-1 shown, the switches 13a, 14a, 23a, and 24a are used instead of the switches 13, 14, 23, and 24 shown in Figure 7 In the output circuit 200-1 shown, the switches 13a, 14a, 23a, and 24a are used instead of the switches 13, 14, 23, and 24 shown in Figure 18 In the output circuit 200-1 shown, the switches 13a, 14a, 23a, and 24a are used instead of the switches 13, 14, 23, and 24 shown in Figure 18 In the output circuit 200-1 shown, the switches 13a, 14a, 23a, and 24a are used instead of the switches 13, 14, 23, and 24 shown in

[0244] In addition, in the output circuit 200-1 shown, the output selection switches 11a, 12a, 21a, and 22a are used instead of the output selection switches 11, 12, 21, and 22 shown in Figure 18In the output circuit 200-1 shown, capacitor elements C11, C12, C21 and C22 are individually connected between the gate and source of each of the output selection switches 11a, 12a, 21a and 22a.

[0245] and then, Figure 18 In the output circuit 200-1 shown, regarding control signals St11, St12, St21, and St22, including those related to... Figure 18 The same control unit 35A is generated by the voltage control circuit 130, voltage control circuit 130A, voltage control circuit 140 and voltage control circuit 140A contained in the control unit 35A.

[0246] in addition, Figure 18 The internal details of voltage control circuits 130, 130A, 140, and 140A are omitted, but voltage control circuits 130 and 130A respectively have the same characteristics as... Figure 18 The voltage control circuit 130 shown has the same internal structure as the voltage control circuit 140, and the voltage control circuit 140A has the same internal structure as the voltage control circuit 140. Figure 18 The voltage control circuit 140 shown has the same internal structure. Furthermore... Figure 20 The description of the control unit 35A is omitted.

[0247] Figure 18 The output circuit 200-1 shown is also... Figure 18 Similarly, the output circuit 100-1 shown is used in the same way. Figure 20 The drive control is shown. However, regarding the drive control for output terminal DL2, in Figure 18 In the drive control shown, the positive drive period and the negative drive period are interchanged. That is, when a positive voltage signal Vp is output to the output terminal DL1, the output selection switches 11a, 21a, 13a, 15, 23a, and 25 that control the output to the output terminal DL1 are respectively connected to... Figure 18 During the positive drive period (T1, T2), the same on / off control is applied. At this time, the output selection switches 12a, 22a, 14a, 16, 24a, and 26, which control the output to the output terminal DL2, each perform the same on / off control as... Figure 21During the negative drive periods (T3, T4) of output selection switches 11a, 21a, 13a, 15, 23a, and 25, the same control is applied to output terminal DL2 to output a negative voltage signal Vn. Furthermore, when outputting the negative voltage signal Vn to output terminal DL1, the output selection switches 11a, 21a, 13a, 15, 23a, and 25 controlling the output to output terminal DL1 each perform the same control as... Figure 21 During the negative drive period (T3, T4), the same on / off control is applied. At this time, the output selection switches 12a, 22a, 14a, 16, 24a, and 26 that control the output to the output terminal DL2 perform the same control as the output selection switches 11a, 21a, 13a, 15, 23a, and 25 during the positive drive period (T1, T2), and output a positive voltage signal Vp to the output terminal DL2.

[0248] Figure 21 The output circuit 200-1 shown is also... Figure 22 Similarly, the output circuit 100-1 shown can output to the output terminals DL1 and DL2 for any positive voltage signal Vp or negative voltage signal Vn, achieving a high current supply capability (drive capability). Furthermore, the components constituting the output circuit 200-1 can be controlled within any voltage range of the voltage difference between the reference power supply voltage VGND and the positive power supply voltage VDDH, or the voltage difference between the reference power supply voltage VGND and the negative power supply voltage VDDL.

[0249] [Example 9]

[0250] Figure 22 This is a circuit diagram illustrating the structure of the output circuit 300, which is the ninth embodiment of the output circuit of the present invention. Additionally, Figure 22 The output circuit 300 shown has the following structure: a positive voltage signal supply circuit 10C is used instead of a positive voltage signal supply circuit 10A, and a negative voltage signal supply circuit 20C is used instead of a negative voltage signal supply circuit 20A. Other structures are the same as... Figure 7 Same as shown.

[0251] Therefore, the description of the other structures is omitted, and the internal structure of the positive voltage signal supply circuit 10C and the negative voltage signal supply circuit 20C will be described below.

[0252] The positive voltage signal supply circuit 10C has the function of bearing Figure 7The positive voltage signal supply circuit 10A is shown as having internal switches 15a to 15d, a P-channel output transistor 17P, an N-channel output transistor 17N, and a differential amplification section 18, which function as the switch 15. The output transistors 17P and 17N constitute an output amplification section of the positive voltage signal supply circuit 10C. The drain of the P-channel output transistor 17P is connected to a node Nsll, and the source is connected to the positive power supply voltage VDDH. The drain of the N-channel output transistor 17N is connected to the node Nsll, and the source is connected to the reference power supply voltage VGND. The differential amplification section 18 receives the positive voltage signal Vpi at its own non-inverting input terminal, and receives the positive voltage signal output from the positive voltage signal supply circuit 10C as the voltage Vll at the node Nsll at its own inverting input terminal.

[0253] The differential amplification section 18 generates first and second differential output signals whose voltage values vary in correspondence with the voltage difference between the positive voltage signal Vpi and the voltage Vll, and supplies them to the gates of the output transistors 17P and 17N via the internal switches 15a and 15c. The internal switches 15b and 15d are connected between the gates and the sources of the output transistors 17P and 17N, respectively. The internal switches 15a and 15c and the internal switches 15b and 15d are controlled complementarily, and when the internal switches 15a and 15c are on, the internal switches 15b and 15d are off. At this time, the first and second differential output signals of the differential amplification section 18 are supplied to the gates of the output transistors 17P and 17N, and the output transistors 17P and 17N are activated to supply the positive voltage signal to the node Nsll. That is, the positive voltage signal supply circuit 10C is configured as a voltage follower structure that amplifies and outputs the positive voltage signal Vll corresponding to the positive voltage signal Vpi to the node Nsll. On the other hand, when the internal switches 15a and 15c are off, the internal switches 15b and 15d are on. At this time, the output transistors 17P and 17N are not activated, and the supply of the positive voltage signal to the node Nsll is stopped.

[0254] Here, in the positive voltage signal supply circuit 10C, by controlling the internal switches 15a and 15c to be on and the internal switches 15b and 15d to be off, a state equivalent to the on state of the switch 15 of the positive voltage signal supply circuit 10A of Figure 22 is realized. Also, in the positive voltage signal supply circuit 10C, by controlling the internal switches 15a and 15c to be off and the internal switches 15b and 15d to be on, a state equivalent to the off state of the switch 15 of the positive voltage signal supply circuit 10A of Figure 22The positive voltage signal supply circuit 10A is equivalent to the open state of switch 15.

[0255] according to Figure 22 The positive voltage signal supply circuit 10C shown is connected to... ​ Compared to the positive voltage signal supply circuit 10A shown, there is no switch 15 on the path from the output terminal of amplifier circuit 10 to output terminal DL1, resulting in a smaller output impedance for the positive voltage signal supply circuit 10C. Therefore, the driving capability of the positive voltage signal supply circuit 10C can be improved.

[0256] The negative voltage signal supply circuit 20C has the function of bearing ​ The negative voltage signal supply circuit 20A shown includes internal switches 25a-25d, a P-channel output transistor 27P, an N-channel output transistor 27N, and a differential amplifier section 28. Output transistors 27P and 27N constitute the output amplifier section of the negative voltage signal supply circuit 20C. The drain of the P-channel output transistor 27P is connected to node Ns21, and its source is connected to the reference power supply voltage VGND. The drain of the N-channel output transistor 27N is connected to node Ns21, and its source is connected to the negative power supply voltage VDDL. The differential amplifier section 28 receives the negative voltage signal Vni at its non-inverting input terminal and receives the negative voltage signal output from the negative voltage signal supply circuit 20C as the voltage V21 at node Ns21 at its inverting input terminal.

[0257] The differential amplification section 28 generates third and fourth differential output signals whose voltage values vary in correspondence with the voltage difference between the negative voltage signal Vni and the voltage V21, and supplies them to the gates of the output transistors 27P and 27N via the internal switches 25a and 25c. The internal switches 25b and 25d are connected between the gates and the sources of the output transistors 27P and 27N, respectively. The internal switches 25a and 25c are controlled complementarily to the internal switches 25b and 25d, and when the internal switches 25a and 25c are on, the internal switches 25b and 25d are off. At this time, the third and fourth differential output signals of the differential amplification section 28 are supplied to the gates of the output transistors 27P and 27N, and the output transistors 27P and 27N are activated to supply the negative voltage signal to the node Ns21. That is, the negative voltage signal supply circuit 20C is configured as a voltage follower that amplifies and outputs the negative voltage signal V21 corresponding to the negative voltage signal Vni to the node Ns11. On the other hand, when the internal switches 25a and 25c are off, the internal switches 25b and 25d are on. At this time, the output transistors 27P and 27N are not activated, and the supply of the negative voltage signal to the node Ns21 is stopped.

[0258] Here, in the negative voltage signal supply circuit 20C, by controlling the internal switches 25a and 25c to be on and the internal switches 25b and 25d to be off, a state equivalent to the on state of the switch 25 of the negative voltage signal supply circuit 20A of ​ can be realized. Also, in the negative voltage signal supply circuit 20C, by controlling the internal switches 25a and 25c to be off and the internal switches 25b and 25d to be on, a state equivalent to the off state of the switch 25 of the negative voltage signal supply circuit 20A of ​ can be realized.

[0259] According to the negative voltage signal supply circuit 20C shown in ​ , compared with the negative voltage signal supply circuit 20A shown in ​ , there is no switch 25 on the path from the output of the amplification circuit 20 to the output terminal DL1, and the output impedance of the negative voltage signal supply circuit 20C is small. Therefore, the driving capability of the negative voltage signal supply circuit 20C can be improved.

[0260] [Embodiment 10]

[0261] ​ is a circuit diagram showing the structure of an output circuit 300-1 as the tenth embodiment of the output circuit of the present application. Also,​ The output circuit 300-1 shown is structured by replacing the anode voltage signal supply circuit 10B with an anode voltage signal supply circuit 10D and replacing the cathode voltage signal supply circuit 20B with a cathode voltage signal supply circuit 20D. The other structures are the same as those shown in FIG. 3. Therefore, the description of the other structures is omitted, and the internal structures of the anode voltage signal supply circuit 10D and the cathode voltage signal supply circuit 20D are described below. ​

[0262] The anode voltage signal supply circuit 10D has internal switches 15a to 15d, an output transistor 17P of the P-channel type, an output transistor 17N of the N-channel type, and a differential amplification section 18, which assume the functions of the switches 15 of the anode voltage signal supply circuit 10A shown in FIG. 3. ​ The anode voltage signal supply circuit 10D has internal switches 15a to 15d, an output transistor 17P of the P-channel type, an output transistor 17N of the N-channel type, and a differential amplification section 18, which assume the functions of the switches 15 of the anode voltage signal supply circuit 10A shown in FIG. 3. ​ The anode voltage signal supply circuit 10D has internal switches 16a to 16d, an output transistor 19P of the P-channel type, an output transistor 19N of the N-channel type, a reset switch 57, and a reset switch 59, which assume the functions of the switches 16 of the anode voltage signal supply circuit 10A shown in FIG. 3.

[0263] The output transistors 17P, 17N, and 19P, 19N constitute a first output amplification section (17P, 17N) and a second output amplification section (19P, 19N) of the anode voltage signal supply circuit 10D. The drain of the output transistor 17P of the P-channel type is connected to a node Nsll, and the source is connected to the anode power supply voltage VDDH. The drain of the output transistor 17N of the N-channel type is connected to the node Nsll, and the source is connected to the reference power supply voltage VGND. The drain of the output transistor 19P of the P-channel type is connected to a node Ns 12, and the source is connected to the anode power supply voltage VDDH. The drain of the output transistor 19N of the N-channel type is connected to the node Ns 12, and the source is connected to the reference power supply voltage VGND. The differential amplification section 18 receives the anode voltage signal Vpi at its non-inverting input terminal and receives the anode voltage signal output from the anode voltage signal supply circuit 10D as the voltage Vll of the node Nsll or the voltage V12 of the node Ns 12 via the reset switch 57 or the reset switch 59 at its inverting input terminal.

[0264] ​The differential amplification section 18 generates first and second differential output signals whose voltage values vary in correspondence with the voltage difference between the voltage Vll or the voltage V12 and the positive voltage signal Vpi, and supplies them to the gates of the output transistors 17P and 17N via the internal switches 15a and 15c, respectively, or to the gates of the output transistors 19P and 19N via the internal switches 16a and 16c, respectively. The internal switches 15b and 15d are connected between the gates and the sources of the output transistors 17P and 17N, respectively, and the internal switches 16b and 16d are connected between the gates and the sources of the output transistors 19P and 19N, respectively.

[0265] Further, the internal switches 15a and 15c are controlled complementarily to the internal switches 15b and 15d, and when the internal switches 15a and 15c are on, the internal switches 15b and 15d are off. At this time, the first and second differential output signals of the differential amplification section 18 are supplied to the gates of the output transistors 17P and 17N, and the output transistors 17P and 17N are activated to supply the positive voltage signal to the node Nsll. On the other hand, when the internal switches 15a and 15c are off, the internal switches 15b and 15d are on. At this time, the output transistors 17P and 17N are not activated, and the supply of the positive voltage signal to the node Nsll is stopped.

[0266] Further, the internal switches 16a and 16c are controlled complementarily to the internal switches 16b and 16d, and when the internal switches 16a and 16c are on, the internal switches 16b and 16d are off. At this time, the first and second differential output signals of the differential amplification section 18 are supplied to the gates of the output transistors 19P and 19N, and the output transistors 19P and 19N are activated to supply the positive voltage signal to the node Ns 12. On the other hand, when the internal switches 16a and 16c are off, the internal switches 16b and 16d are on. At this time, the output transistors 19P and 19N are not activated, and the supply of the positive voltage signal to the node Ns 12 is stopped.

[0267] The reset switches 57 and 59 are periodically set to the on state or the off state complementarily. Here, in the case where the reset switch 57 is set to the on state and the reset switch 59 is set to the off state, the voltage Vll of the node Nsll is supplied to the inverting input terminal of the differential amplification section 18. On the other hand, in the case where the reset switch 57 is set to the off state and the reset switch 59 is set to the on state, the voltage V12 of the node Ns 12 is supplied to the inverting input terminal of the differential amplification section 18.

[0268] The negative voltage signal supply circuit 20D has internal switches 25a to 25d, an output transistor 27P of the P-channel type, an output transistor 27N of the N-channel type, and a differential amplification section 28, which assume the functions of the switches 25 of the negative voltage signal supply circuit 20A shown in FIG. 2. ​ The negative voltage signal supply circuit 20D has internal switches 25a to 25d, an output transistor 27P of the P-channel type, an output transistor 27N of the N-channel type, and a differential amplification section 28, which assume the functions of the switches 25 of the negative voltage signal supply circuit 20A shown in FIG. 2. ​ The negative voltage signal supply circuit 20D has internal switches 26a to 26d, an output transistor 29P of the P-channel type, an output transistor 29N of the N-channel type, a reset switch 67, and a reset switch 69, which assume the functions of the switches 26 of the negative voltage signal supply circuit 20A shown in FIG. 2.

[0269] The output transistors 27P, 27N, and 29P, 29N constitute a first output amplification section (27P, 27N) and a second output amplification section (29P, 29N) of the negative voltage signal supply circuit 20D. The drain of the output transistor 27P of the P-channel type is connected to the node Ns21, and the source is connected to the reference power supply voltage VGND. The drain of the output transistor 27N of the N-channel type is connected to the node Ns21, and the source is connected to the negative power supply voltage VDDL. The drain of the output transistor 29P of the P-channel type is connected to the node Ns22, and the source is connected to the reference power supply voltage VGND. The drain of the output transistor 29N of the N-channel type is connected to the node Ns22, and the source is connected to the negative power supply voltage VDDL. The differential amplification section 28 receives the negative voltage signal Vni at its own non-inverting input terminal, and receives the negative voltage signal output from the negative voltage signal supply circuit 20D as the voltage V21 of the node Ns21 or the voltage V22 of the node Ns22 at its own inverting input terminal via the reset switch 67 or the reset switch 69.

[0270] The differential amplification section 28 generates third and fourth differential output signals whose voltage values vary in correspondence with the voltage difference between the voltage V21 or the voltage V22 and the negative voltage signal Vni, and supplies them to the gates of the output transistors 27P, 27N via the internal switches 25a, 25c, or to the gates of the output transistors 29P, 29N via the internal switches 26a, 26c. The internal switches 25b, 25d are connected between the gates and the sources of the output transistors 27P, 27N, respectively, and the internal switches 26b, 26d are connected between the gates and the sources of the output transistors 29P, 29N, respectively.

[0271] Further, the internal switches 25a, 25c are controlled complementarily to the internal switches 25b, 25d, and when the internal switches 25a, 25c are on, the internal switches 25b, 25d are off. At this time, the third and fourth differential output signals of the differential amplification section 28 are supplied to the gates of the output transistors 27P, 27N, respectively, and the output transistors 27P, 27N are activated to supply the negative voltage signal to the node Ns21. On the other hand, when the internal switches 25a, 25c are off, the internal switches 25b, 25d are on. At this time, the output transistors 27P, 27N are not activated, and the supply of the positive voltage signal to the node Ns21 is stopped.

[0272] Further, the internal switches 26a, 26c are controlled complementarily to the internal switches 26b, 26d, and when the internal switches 26a, 26c are on, the internal switches 26b, 26d are off. At this time, the third and fourth differential output signals of the differential amplification section 28 are supplied to the gates of the output transistors 29P, 29N, respectively, and the output transistors 29P, 29N are activated to supply the negative voltage signal to the node Ns22. On the other hand, when the internal switches 26a, 26c are off, the internal switches 26b, 26d are on. At this time, the output transistors 29P, 29N are not activated, and the supply of the negative voltage signal to the node Ns22 is stopped.

[0273] The reset switches 67, 69 are periodically and complementarily set to the on state or the off state. Here, in the case where the reset switch 67 is set to the on state and the reset switch 69 is set to the off state, the voltage V21 of the node Ns21 is supplied to the inverting input terminal of the amplification circuit 28. On the other hand, in the case where the reset switch 67 is set to the off state and the reset switch 69 is set to the on state, the voltage V22 of the node Ns22 is supplied to the inverting input terminal of the amplification circuit 28.

[0274] Here, in the positive voltage signal supply circuit 10D, by controlling the internal switches 15a, 15c to the on state and the internal switches 15b, 15d to the off state and controlling the reset switch 57 to the on state, a state equivalent to the on state of the switch 15 of the positive voltage signal supply circuit 10B of ​ is realized. Further, in the positive voltage signal supply circuit 10D, by controlling the internal switches 16a, 16c to the on state and the internal switches 16b, 16d to the off state and controlling the reset switch 59 to the on state, a state equivalent to the on state of the switch 16 of the positive voltage signal supply circuit 10B of ​The on state of the switch 16 of the positive voltage signal supply circuit 10B is equivalent to the state.

[0275] Further, in the negative voltage signal supply circuit 20D, by controlling the internal switch 25a and the internal switch 25c to the on state, controlling the internal switch 25b and the internal switch 25d to the off state, and controlling the reset switch 67 to the on state, a state equivalent to the on state of the switch 25 of the negative voltage signal supply circuit 20B can be realized. ​ Further, in the negative voltage signal supply circuit 20D, by controlling the internal switch 26a and the internal switch 26c to the on state, controlling the internal switch 26b and the internal switch 26d to the off state, and controlling the reset switch 69 to the on state, a state equivalent to the on state of the switch 26 of the negative voltage signal supply circuit 10B can be realized. ​ The on state of the switch 26 of the negative voltage signal supply circuit 10B is equivalent to the state.

[0276] Therefore, according to the positive voltage signal supply circuit 10D shown in FIG. 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 15 on the path from the output terminal of the amplification circuit 10 to the output terminal DL1, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Further, according to the positive voltage signal supply circuit 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 16 on the path from the output terminal of the amplification circuit 10 to the output terminal DL2, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Therefore, the driving capability of the positive voltage signal supply circuit 10D can be improved. ​ Therefore, according to the positive voltage signal supply circuit 10D shown in FIG. 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 15 on the path from the output terminal of the amplification circuit 10 to the output terminal DL1, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Further, according to the positive voltage signal supply circuit 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 16 on the path from the output terminal of the amplification circuit 10 to the output terminal DL2, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Therefore, the driving capability of the positive voltage signal supply circuit 10D can be improved. ​ Therefore, according to the positive voltage signal supply circuit 10D shown in FIG. 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 15 on the path from the output terminal of the amplification circuit 10 to the output terminal DL1, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Further, according to the positive voltage signal supply circuit 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 16 on the path from the output terminal of the amplification circuit 10 to the output terminal DL2, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Therefore, the driving capability of the positive voltage signal supply circuit 10D can be improved. ​ Therefore, according to the positive voltage signal supply circuit 10D shown in FIG. 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 15 on the path from the output terminal of the amplification circuit 10 to the output terminal DL1, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Further, according to the positive voltage signal supply circuit 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 16 on the path from the output terminal of the amplification circuit 10 to the output terminal DL2, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Therefore, the driving capability of the positive voltage signal supply circuit 10D can be improved.

[0277] Therefore, according to the positive voltage signal supply circuit 10D shown in FIG. 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 15 on the path from the output terminal of the amplification circuit 10 to the output terminal DL1, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Further, according to the positive voltage signal supply circuit 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 16 on the path from the output terminal of the amplification circuit 10 to the output terminal DL2, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Therefore, the driving capability of the positive voltage signal supply circuit 10D can be improved. ​ Therefore, according to the positive voltage signal supply circuit 10D shown in FIG. 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 15 on the path from the output terminal of the amplification circuit 10 to the output terminal DL1, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Further, according to the positive voltage signal supply circuit 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 16 on the path from the output terminal of the amplification circuit 10 to the output terminal DL2, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Therefore, the driving capability of the positive voltage signal supply circuit 10D can be improved. ​ Therefore, according to the positive voltage signal supply circuit 10D shown in FIG. 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 15 on the path from the output terminal of the amplification circuit 10 to the output terminal DL1, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Further, according to the positive voltage signal supply circuit 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 16 on the path from the output terminal of the amplification circuit 10 to the output terminal DL2, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Therefore, the driving capability of the positive voltage signal supply circuit 10D can be improved. ​ Therefore, according to the positive voltage signal supply circuit 10D shown in FIG. 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 15 on the path from the output terminal of the amplification circuit 10 to the output terminal DL1, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Further, according to the positive voltage signal supply circuit 10D, compared with the positive voltage signal supply circuit 10B shown in FIG. 10B, there is no switch 16 on the path from the output terminal of the amplification circuit 10 to the output terminal DL2, and the output impedance of the positive voltage signal supply circuit 10D is smaller. Therefore, the driving capability of the positive voltage signal supply circuit 10D can be improved.

[0278] [Example 11]

[0279] ​ A block diagram showing the outline structure of a liquid crystal display device 400 including a data driver 80 having the output circuit of the present application.

[0280] ​ In the active matrix type display screen 90 including liquid crystal display devices of each pixel unit, m (m is a natural number of 2 or more) horizontal scan lines S1 to Sm elongated in a horizontal direction of a two-dimensional picture and n (n is a natural number of 2 or more) data lines D1 to Dn elongated in a vertical direction of the two-dimensional picture are formed. At each intersection of the horizontal scan lines and the data lines, a display unit as a pixel is formed. The display unit includes at least a switching element and a pixel electrode, and when the switching element becomes an on state according to a scan pulse of the horizontal scan line, a gray scale voltage signal of the data line is applied to the pixel electrode via the switching element, and the brightness of the liquid crystal display device is controlled according to the gray scale voltage applied to the pixel electrode. In addition, ​ In the present embodiment, the description of the structure of the specific display unit is omitted.

[0281] The drive control section 65 receives an image signal VD in which a control signal and the like are integrated, generates a timing signal based on a horizontal synchronization signal from the image signal VD, and supplies the timing signal to the scan driver 70. Further, the drive control section 65 generates various control signal groups and a series of pixel data PD representing the brightness levels of the pixels in, for example, 8-bit luminance gray scales, based on the image signal VD, and supplies them to the data driver 80.

[0282] The scan driver 70 applies horizontal scan pulses to each of the horizontal scan lines S1 to Sm of the display screen 90 in order, based on the timing signal supplied from the drive control section 65.

[0283] The data driver 80 is formed, for example, in a semiconductor device such as a Large Scale Integrated Circuit (LSI). The data driver 80 converts the pixel data PD supplied from the drive control section 65 into gray scale voltage signals G1 to Gn having gray scale voltages corresponding to the respective pixel data PD, in units of one horizontal scan line, that is, in units of n. Then, the data driver 80 applies the gray scale voltage signals G1 to Gn to the data lines D1 to Dn of the display screen 90.

[0284] Further, as for the scan driver 70 or the data driver 80, a part or all of the circuit can be integrally formed with the display screen. Further, the data driver 80 can also be constituted by a plurality of LSIs.

[0285] ​ A block diagram showing the internal structure of the data driver 80.

[0286] As ​As shown, the data driver 80 includes a shift register 600, a data register latch circuit 700, a level shift circuit 800, a level voltage generation circuit 500, a decoder circuit 900, and an output amplification circuit 2000. Also, an interface circuit (not shown) is included which receives a control signal or an image digital signal supplied from a display controller (not shown), generates a clock signal or a control signal required inside the driver, and outputs a signal group which has been subjected to timing adjustment with the image digital signal. ​ In the following description, details of the interface circuit are omitted for convenience of explanation.

[0287] The shift register 600 generates, based on a start pulse, a plurality of latch timing signals for selecting latches in synchronization with a clock signal CLK, and supplies the latch timing signals to the data register latch circuit 700.

[0288] The data register latch circuit 700 receives an image digital signal, a polarity inversion signal (POL), a timing control signal, and the like, and based on the respective latch timing signals supplied from the shift register 600, imports the image digital signal in a prescribed number of units, and supplies the prescribed number of image digital signals to the level shift circuit 800 in a latch timing.

[0289] Further, the data register latch circuit 700 selects output of the image digital signal to the level shifter 80P or the level shifter 80N corresponding to the positive or negative polarity based on the polarity inversion signal (POL).

[0290] The level shift circuit 800 includes a positive polarity level shifter 80P and a negative polarity level shifter 80N. The positive polarity level shifter 80P converts the image digital signal into a digital signal of a positive polarity analog voltage (VGND / VDDH) amplitude. The negative polarity level shifter 80N converts the image digital signal into a digital signal of a negative polarity analog voltage (VGND / VDDL) amplitude. The prescribed number of image digital data signals supplied from the data register latch circuit 700 are sent to the positive polarity level shifter 80P or the negative polarity level shifter 80N in accordance with the polarity inversion signal (POL), are expanded to an analog voltage amplitude corresponding to each polarity, and are sent to the positive polarity decoder 90P or the negative polarity decoder 90N.

[0291] The decoder circuit 900 is configured by the positive polarity decoder 90P and the negative polarity decoder 90N for each two outputs. Further, the arrangement order of the decoders 90P, 90N of each polarity within the decoder circuit 900 can be changed.

[0292] The level voltage generation circuit 500 generates a plurality of level voltages of different voltage values for the positive and negative polarities, and supplies the level voltages to the decoders 90P, 90N, respectively.

[0293] The decoder circuit 900 selects, in units of two outputs of the group of the positive decoder 90P and the negative decoder 90N, a level voltage corresponding to the image digital signal after the level shift processing from among the plurality of level voltages, and supplies the level voltage selected for each polarity to the output amplification circuit 2000.

[0294] The output amplification circuit 2000 is configured, for example, by the output circuit 200 of ​ The output amplification circuit 2000 receives the polarity inversion signal (POL) and the group of switch control signals, and amplifies the level voltage of each polarity selected by the decoder circuit 900, respectively, according to the polarity inversion signal (POL), and outputs the positive voltage signal (Vp) from one of every two output terminals of the data driver and the negative voltage signal (Vn) from the other, respectively. Further, the output amplification circuit 2000 controls the on / off of the switches 15, 16, 25, 26 according to the polarity inversion signal (POL) and the control signals Sz11, Sz12, Sz21, Sz22 of the output circuit 200 of ​

[0295] ​ In the block diagram of the data driver, the blocks having the voltage range of the analog voltage amplitude are the level shift circuit 800, the decoder circuit 900, the output amplification circuit 2000, and the level voltage generation circuit 500. Among them, the positive level shifter 80P and the positive decoder 90P operate in the positive analog voltage range (VGND ~ VDDH), and the negative level shifter 80N and the negative decoder 90N operate in the negative analog voltage range (VGND ~ VDDL).

[0296] Further, the level voltage generation circuit 500 can be configured to be divided into the positive analog voltage range (VGND ~ VDDH) and the negative analog voltage range (VGND ~ VDDL). The output amplification circuit 2000 can also be configured by the voltage-resistant elements of the positive analog voltage range (VGND ~ VDDH) and the negative analog voltage range (VGND ~ VDDL), respectively.

[0297] That is, ​ ​The data driver outputs liquid crystal drive voltage signals of the voltage range of VDDL to VDDH of the negative and positive voltage signals to the output terminal, but the elements constituting the data driver can also be constituted by low voltage resistance elements capable of operating in the positive analog voltage range (VGND to VDDH) or the negative analog voltage range (VGND to VDDL) of about one-half of the liquid crystal drive voltage range. In the case of a transistor of low voltage resistance, for example, the gate insulating film can be thinned, and the transistor constituting the drive circuit can be realized in a small area. Furthermore, by lowering the voltage resistance, the element spacing can also be narrowed. Thus, ​ The data driver can be constituted with a reduced area, and thus, low cost can be realized.

Claims

1. An output circuit characterized by comprising: comprises: a positive voltage signal supply circuit that supplies a positive voltage signal having a higher voltage than a reference power supply voltage to a first node, or blocks supply of the positive voltage signal to the first node; a negative voltage signal supply circuit that supplies a negative voltage signal having a lower voltage than the reference power supply voltage to a second node, or blocks supply of the negative voltage signal to the second node; a first output terminal; a first switch that connects the first output terminal to the first node in an on state, and blocks connection of the first output terminal to the first node in an off state; a second switch that connects the first output terminal to the second node in an on state, and blocks connection of the first output terminal to the second node in an off state; a third switch that applies the reference power supply voltage to the first node in an on state, and stops application of the reference power supply voltage to the first node in an off state; a fourth switch that applies the reference power supply voltage to the second node in an on state, and stops application of the reference power supply voltage to the second node in an off state; a first voltage control circuit that performs on-off control of the first switch; and a second voltage control circuit that performs on-off control of the second switch, the first switch is constituted by a P-channel transistor having a source connected to the first node and a drain connected to the first output terminal, the second switch is constituted by an N-channel transistor having a source connected to the second node and a drain connected to the first output terminal, the third switch is constituted by an N-channel transistor having a drain connected to the first node and a source to which the reference power supply voltage is applied, the fourth switch is constituted by a P-channel transistor having a drain connected to the second node and a source to which the reference power supply voltage is applied, the first voltage control circuit has a first control member that causes a gate voltage of the P-channel transistor to change in conjunction with a change in voltage supplied to the first node when the P-channel transistor is controlled to be in an on state, the second voltage control circuit has a second control member that causes a gate voltage of the N-channel transistor to change in conjunction with a change in voltage supplied to the second node when the N-channel transistor is controlled to be in an on state, the first control member is constituted by a first capacitive element connected between the gate of the P-channel transistor and the source of the P-channel transistor, the second control member is constituted by a second capacitive element connected between the gate of the N-channel transistor and the source of the N-channel transistor.

2. The output circuit according to claim 1, wherein the positive voltage signal supply circuit includes: a first differential amplification section that receives a first differential input signal; and a first output amplification section that is controlled to be active or inactive by a first internal switch group, an output node of the first output amplification section is connected to the first node, The first differential amplification section receives a positive input signal from the outside and the positive voltage signal output to the first node as the first differential input signal, The first output amplification section supplies the positive voltage signal to the first node when the first internal switch group is set to active, and blocks the supply of the positive voltage signal to the first node when the first internal switch group is set to inactive, The negative voltage signal supply circuit includes: A second differential amplification section that receives a second differential input signal, and a second output amplification section whose activity and inactivity are controlled by a second internal switch group, An output node of the second output amplification section is connected to the second node, The second differential amplification section receives a negative input signal from the outside and the negative voltage signal output to the second node as the second differential input signal, The second output amplification section supplies the negative voltage signal to the second node when the second internal switch group is set to active, and blocks the supply of the negative voltage signal to the second node when the second internal switch group is set to inactive.

3. The output circuit according to claim 1, characterized by including: A control section that controls the first to fourth switches, the positive voltage signal supply circuit and the negative voltage signal supply circuit, the first voltage control circuit and the second voltage control circuit to switch the positive voltage signal and the negative voltage signal at a predetermined timing and output from the first output terminal.

4. The output circuit according to claim 3, wherein The control section sets at least a first period, a second period, a third period and a fourth period as control periods, the first period is for switching the output from the negative voltage signal to the positive voltage signal, the second period is for outputting the positive voltage signal from the first output terminal, the third period is for switching the output from the positive voltage signal to the negative voltage signal, and the fourth period is for outputting the negative voltage signal from the first output terminal, In the first period, the supply of the positive voltage signal by the positive voltage signal supply circuit is blocked, the supply of the negative voltage signal by the negative voltage signal supply circuit is blocked, and at least the second to fourth switches are controlled to be in the on state, whereby the reference power supply voltage is supplied to the first node, the second node and the first output terminal, In the second period, the supply of the negative voltage signal by the negative voltage signal supply circuit is blocked, the positive voltage signal is supplied to the first node by the positive voltage signal supply circuit, the first voltage control circuit controls the first and fourth switches to be in the on state and controls the second and third switches to be in the off state, the positive voltage signal is supplied to the first output terminal via the first switch, and the reference power supply voltage is supplied to the second node via the fourth switch, In the third period, the supply of the positive voltage signal by the positive voltage signal supply circuit is blocked, the negative voltage signal is supplied to the second node by the negative voltage signal supply circuit, the second voltage control circuit controls the second and third switches to be in the on state and controls the first and fourth switches to be in the off state, the negative voltage signal is supplied to the first output terminal via the third switch, and the reference power supply voltage is supplied to the first node via the second switch, and In the fourth period, the supply of the negative voltage signal by the negative voltage signal supply circuit is blocked, the positive voltage signal is supplied to the first node by the positive voltage signal supply circuit, the first voltage control circuit controls the first and fourth switches to be in the on state and controls the second and third switches to be in the off state, the positive voltage signal is supplied to the first output terminal via the first switch, and the reference power supply voltage is supplied to the second node via the fourth switch. In the third period, the supply of the positive voltage signal by the positive voltage signal supply circuit is blocked, and the supply of the negative voltage signal by the negative voltage signal supply circuit is blocked, and the first switch, the third switch, and the fourth switch are controlled to be in the on state, thereby supplying the reference power supply voltage to the first node, the second node, and the first output terminal, In the fourth period, the supply of the positive voltage signal by the positive voltage signal supply circuit is blocked, and the negative voltage signal is supplied to the second node by the negative voltage signal supply circuit, and the second voltage control circuit controls the second switch to be in the on state, and controls the third switch to be in the on state, and controls the first switch and the fourth switch to be in the off state, the negative voltage signal is supplied to the first output terminal via the second switch, and the reference power supply voltage is supplied to the first node via the third switch.

5. The output circuit according to claim 1, characterized by Further comprising: a second output terminal; a third node and a fourth node; a fifth switch which connects the second output terminal to the third node when in the on state, and blocks the connection of the second output terminal to the third node when in the off state; a sixth switch which connects the second output terminal to the fourth node when in the on state, and blocks the connection of the second output terminal to the fourth node when in the off state; a seventh switch which applies the reference power supply voltage to the third node when in the on state, and stops applying the reference power supply voltage to the third node when in the off state; and an eighth switch which applies the reference power supply voltage to the fourth node when in the on state, and stops applying the reference power supply voltage to the fourth node when in the off state, the positive voltage signal supply circuit controls the supply or block of the positive voltage signal to the first node or the third node, the negative voltage signal supply circuit controls the supply or block of the negative voltage signal to the second node or the fourth node, the fifth switch is composed of a P-channel transistor whose source is connected to the third node and whose drain is connected to the second output terminal, the sixth switch is composed of an N-channel transistor whose source is connected to the fourth node and whose drain is connected to the second output terminal. including:

6. The output circuit according to claim 5, characterized by a control unit which switches between a state of outputting the positive voltage signal to the first output terminal and outputting the negative voltage signal to the second output terminal, and a state of outputting the positive voltage signal to the second output terminal and outputting the negative voltage signal to the first output terminal, at a predetermined timing.

7. A data driver, comprising: a plurality of output circuits according to claim 1, wherein a plurality of gray scale voltage signals having voltage values of positive polarity or negative polarity are output from the plurality of output circuits to drive a plurality of data lines of a liquid crystal display panel. including:

8. A display device, characterized by comprising: ​ A data driver includes a plurality of output circuits according to claim 1, outputs a plurality of gray scale voltage signals having positive or negative polarity voltage values from the plurality of output circuits, and Further A liquid crystal display panel having a plurality of data lines receiving the plurality of gray scale voltage signals.

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