Semiconductor device defect analysis method, device, readable medium and electronic device

Abstract

The embodiments of the present application provide a defect analysis method, apparatus, readable medium and electronic device for semiconductor devices. The defect analysis method comprises: obtaining multiple defect scanning results obtained by a defect scanning program scanning a semiconductor device through multiple scanning sizes, wherein one scanning size corresponds to one defect scanning result; obtaining the areas where the defect scanning program scans the semiconductor device respectively through the multiple scanning sizes to obtain the scanning areas corresponding to each scanning size; calculating the overlapping scanning areas corresponding to the multiple scanning sizes based on the scanning areas corresponding to the respective scanning sizes; and performing defect source analysis on the semiconductor device based on the defect data in the overlapping scanning areas respectively in the multiple defect scanning results. The technical solution of the embodiments of the present application can accurately locate the defect position in the semiconductor device, effectively improving the accuracy of defect analysis on the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular to a defect analysis method, apparatus, readable medium and electronic device for a semiconductor device. Background Art

[0002] As the core of modern electronic devices, the performance of semiconductor devices directly affects the efficiency and stability of electronic devices. However, from the manufacturing process to the operation of semiconductor devices, various factors may cause defects in the devices. These defects may come from problems with the materials themselves, or from environmental and process problems in the manufacturing process, or from aging, overload and other problems during operation. Therefore, the detection and identification of defects in semiconductor devices is the key to improving device performance and reliability, and Defect Source Analysis (DSA) is a method for detecting and analyzing defects in semiconductor devices. Through DSA, we can deeply understand the source and formation mechanism of defects, so as to take corresponding measures to improve the performance and reliability of devices.

[0003] However, the DSA scheme proposed in the related art cannot accurately analyze new defects in semiconductor devices, which affects the accuracy of defect analysis on semiconductor devices. Summary of the invention

[0004] The embodiments of the present application provide a defect analysis method, apparatus, readable medium and electronic device for a semiconductor device, which can accurately locate the defect position in the semiconductor device and effectively improve the accuracy of defect analysis on the semiconductor device.

[0005] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0006] According to a first aspect of an embodiment of the present application, a defect analysis method for a semiconductor device is provided, comprising: obtaining a plurality of defect scanning results obtained by a defect scanning program scanning a semiconductor device using a plurality of scanning sizes, wherein one scanning size corresponds to one defect scanning result; obtaining areas where the defect scanning program scans the semiconductor device respectively using the plurality of scanning sizes, to obtain scanning areas corresponding to each scanning size; calculating overlapping scanning areas corresponding to the plurality of scanning sizes based on the scanning areas corresponding to the respective scanning sizes; and performing defect source analysis on the semiconductor device based on defect data in the plurality of defect scanning results respectively located in the overlapping scanning areas.

[0007] In some embodiments of the present application, based on the aforementioned scheme, a defect source analysis is performed on the semiconductor device according to the defect data in the overlapping scanning area respectively in the multiple defect scanning results, including: respectively obtaining defect point information in the overlapping scanning area from the multiple defect scanning results; and determining the addition of defect points in the overlapping scanning area of ​​the multiple defect scanning results according to the defect point information in the overlapping scanning area respectively obtained from the multiple defect scanning results.

[0008] In some embodiments of the present application, based on the aforementioned scheme, according to the defect point information in the overlapping scanning area respectively obtained from the multiple defect scanning results, the newly added defect points in the overlapping scanning area of ​​the multiple defect scanning results are determined, including: if there are multiple overlapping scanning areas corresponding to the multiple scanning sizes, then according to the defect point information in each overlapping scanning area respectively obtained from the multiple defect scanning results, the newly added defect points in the multiple defect scanning results in each overlapping scanning area are determined.

[0009] In some embodiments of the present application, based on the aforementioned solution, the multiple scanning sizes include two scanning sizes, and the multiple defect scanning results include a first defect scanning result corresponding to the first scanning size, and a second defect scanning result corresponding to the second scanning size;

[0010] Based on the defect data in the overlapping scanning area respectively in the multiple defect scanning results, the defect source analysis of the semiconductor device is performed, including: obtaining the position information of the first defect point in the overlapping scanning area from the first defect scanning result, and obtaining the position information of the second defect point in the overlapping scanning area from the second defect scanning result; comparing the position information of the first defect point with the position information of the second defect point to determine a target defect point in the second defect point that has different position information from that of the first defect point; and using the target defect point as a defect point newly added in the overlapping scanning area when the second defect scanning result is compared with the first defect scanning result.

[0011] In some embodiments of the present application, based on the aforementioned scheme, the areas where the defect scanning program scans the semiconductor device respectively through the multiple scanning sizes are obtained to obtain the scanning areas corresponding to each scanning size, including: when the defect scanning program performs a defect scan on the semiconductor device through the various scanning sizes, the areas where the defect scanning program scans the semiconductor device are recorded to generate the scanning areas corresponding to the various scanning sizes.

[0012] In some embodiments of the present application, based on the aforementioned scheme, multiple defect scanning results obtained by a defect scanning program through scanning a semiconductor device at multiple scanning sizes are obtained, including: obtaining multiple defect scanning results obtained by the defect scanning program through scanning a semiconductor device when using different pixel sizes as scanning parameters, wherein one pixel size corresponds to one scanning size.

[0013] In some embodiments of the present application, based on the aforementioned solution, when the defect scanning program scans the semiconductor device through the multiple scanning sizes, the scanning process corresponding to at least some of the scanning sizes adopts a non-full coverage scanning method.

[0014] In some embodiments of the present application, based on the aforementioned solution, the defect analysis method further includes: when performing defect source analysis on the semiconductor device, discarding defect data that is not within the overlapping scanning area in the multiple defect scanning results.

[0015] According to a second aspect of an embodiment of the present application, a defect analysis device for a semiconductor device is provided, comprising: an acquisition unit, configured to acquire a plurality of defect scanning results obtained by a defect scanning program scanning a semiconductor device through a plurality of scanning sizes, wherein one scanning size corresponds to one defect scanning result; and to acquire areas where the defect scanning program scans the semiconductor device respectively through the plurality of scanning sizes, to obtain scanning areas corresponding to each scanning size; a calculation unit, configured to calculate overlapping scanning areas corresponding to the plurality of scanning sizes based on the scanning areas corresponding to the respective scanning sizes; and a processing unit, configured to perform defect source analysis on the semiconductor device based on defect conditions in the plurality of defect scanning results respectively located within the overlapping scanning areas.

[0016] According to a third aspect of an embodiment of the present application, a computer-readable medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the defect analysis method of a semiconductor device as described in the above embodiment is implemented.

[0017] According to a fourth aspect of an embodiment of the present application, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more computer programs, wherein when the one or more computer programs are executed by the one or more processors, the electronic device implements the defect analysis method of the semiconductor device as described in the above embodiments.

[0018] According to a fifth aspect of the embodiments of the present application, a computer program product is provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium. A processor of an electronic device reads and executes the computer program from the computer-readable storage medium, so that the electronic device performs the defect analysis method of a semiconductor device provided in the above-mentioned various optional embodiments.

[0019] In the technical solutions provided in some embodiments of the present application, multiple defect scanning results obtained by a defect scanning program through scanning a semiconductor device with multiple scanning sizes, as well as the scanning areas corresponding to each scanning size, can be obtained, and then the overlapping scanning areas corresponding to the multiple scanning sizes are calculated based on the scanning areas corresponding to the various scanning sizes, and then the defect source analysis of the semiconductor device is performed based on the defect data in the overlapping scanning areas in the multiple defect scanning results. It can be seen that in the technical solutions of the embodiments of the present application, the scanning areas corresponding to the multiple scanning processes of the defect scanning program can be analyzed to determine the overlapping scanning areas of the multiple scanning processes, and then the defect data in the overlapping scanning areas can be compared and analyzed, so as to avoid the inaccuracy of the defect source analysis caused by the scanning areas of the multiple scanning processes being not exactly the same, and then the defect position in the semiconductor device can be accurately located, effectively improving the accuracy of defect analysis of the semiconductor device.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram showing the principle of defect source analysis of semiconductor devices;

[0022] Figure 2 A schematic diagram showing the defect source analysis process;

[0023] Figure 3 A flowchart of a defect analysis method for a semiconductor device according to an embodiment of the present application is shown;

[0024] Figure 4 A flowchart of a defect analysis method for a semiconductor device according to an embodiment of the present application is shown;

[0025] Figure 5 A schematic diagram showing a recording process of a scanning area according to an embodiment of the present application is shown;

[0026] Figure 6 A defect source analysis comparison diagram of the technical solution of the embodiment of the present application and the technical solution in the related art is shown;

[0027] Figure 7A block diagram of a defect analysis device for a semiconductor device according to an embodiment of the present application is shown;

[0028] Figure 8 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] The exemplary embodiments are now described in a more comprehensive manner with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to these examples; on the contrary, the purpose of providing these embodiments is to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0030] In addition, the features, structures or characteristics described in the present application may be combined in one or more embodiments in any suitable manner. In the following description, there are many specific details so that the embodiments of the present application can be fully understood. However, those skilled in the art will appreciate that when implementing the technical scheme of the present application, all the detailed features in the embodiments may not be needed, one or more specific details may be omitted, or other methods, elements, devices, steps, etc. may be adopted.

[0031] In the embodiments of the present application, the term "module" or "unit" refers to a computer program or a part of a computer program with a predetermined function, and works together with other related parts to achieve a predetermined goal, and can be implemented in whole or in part by using software, hardware (such as processing circuits or memories) or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be part of an overall module or unit that includes the function of the module or unit.

[0032] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0033] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0034] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0035] The technical solution of the embodiment of the present application mainly relates to defect analysis of semiconductor devices, specifically, to defect source analysis (i.e., DSA) of semiconductor devices. When performing defect source analysis on semiconductor devices, it is necessary to use a defect scanning program (recipe) to scan the semiconductor devices, and then compare and analyze the results of multiple scans.

[0036] When a defect scanning program is used to scan a semiconductor device for defects, the size of a single scan by the defect scanning program (i.e., swath size, specifically, the height of the scan) is determined by the pixel size (i.e., pixelsize) set in the defect scanning program. And in order to increase the scanning speed, the defect scanning program can adopt a sampling method of 50% scan coverage (i.e., 50% COV), that is, only 50% of the area is scanned in one scanning process. In this case, if the pixel sizes used in the two scanning processes of the defect scanning program are different, then the actual scanning area (i.e., scan size) is also different, and then when DSA is used to analyze a new defect (i.e., adder defect), the DSA analysis result will be inaccurate due to the inconsistent coverage of the two scanning processes.

[0037] Specifically, for example Figure 1 In the DSA analysis process shown, step 1 uses a pixel size of 90 nm and a scanning coverage of 50% to scan the semiconductor device, so the semiconductor device area A and area B are scanned, while the scanning process of area C and area D is skipped. Step 2 uses a pixel size of 45 nm and a scanning coverage of 50% to scan the semiconductor device, so the semiconductor device area A and area C are scanned, while the scanning process of area B and area D is skipped.

[0038] In the related technology Figure 1When performing DSA analysis in the scenario shown, the defect point data obtained by scanning in step 2 is directly compared with the defect point data obtained by scanning in step 1 to determine whether there are new defect points. However, this method is not accurate because area C is not scanned in step 1, and the scan data of area C in step 1 is missing, while area B is not scanned in step 2, and the scan data of area B in step 2 is missing. Therefore, if the defect point data obtained by scanning in step 2 is directly compared with the defect point data obtained by scanning in step 1, the accuracy of DSA analysis will be low due to the different scanning areas.

[0039] In a specific example, Figure 2 As shown, it is assumed that after scanning in step 1, 2 defect points are found in area A, no defect points are found in area B, and the scanning process is skipped in area C and area D; after scanning in step 2, 2 defect points are found in area A, and the two defect points are at the same position as the defect points found in area A in step 1, and a defect point is found in area C, and the scanning process is skipped in area B and area D. Then, according to the scheme in the related art, step 2 adds 1 defect point (i.e., the defect point in area C) compared with step 1, but in fact, area C is not scanned in step 1, and the scanning data of area C in step 1 is missing. Therefore, if the conclusion that the defect point in area C in step 2 is a newly added defect point is directly determined to be inaccurate, it affects the accuracy of defect analysis of semiconductor devices.

[0040] Based on the problems existing in the related technology, the technical solution of the embodiment of the present application proposes a new defect analysis solution for semiconductor devices, which can analyze the scanning areas corresponding to multiple scanning processes of the defect scanning program to determine the overlapping scanning areas of the multiple scanning processes, and then compare and analyze the defect data in the overlapping scanning areas. This can avoid the inaccuracy of defect source analysis caused by the scanning areas of multiple scanning processes being not exactly the same, and then accurately locate the defect position in the semiconductor device, thereby improving the accuracy of defect analysis on the semiconductor device.

[0041] The implementation details of the technical solution of the embodiment of the present application are described in detail below:

[0042] Figure 3 A flowchart of a defect analysis method for a semiconductor device according to an embodiment of the present application is shown. The defect analysis method for a semiconductor device can be performed by an electronic device, which can be an electronic device running a defect scanning program. Figure 3 As shown, the defect analysis method of the semiconductor device at least includes steps S310 to S330, which are described in detail as follows:

[0043] In step S310, a plurality of defect scanning results are obtained by obtaining a defect scanning program by scanning a semiconductor device at a plurality of scanning sizes, wherein one scanning size corresponds to one defect scanning result; and an area where the defect scanning program scans the semiconductor device at a plurality of scanning sizes respectively is obtained to obtain a scanning area corresponding to each scanning size.

[0044] It should be noted that the semiconductor device in the embodiment of the present application can be a product chip. Generally speaking, a product chip usually refers to a chip product formed by different types of integrated circuits or a single type of integrated circuit. After packaging, these chip products can be used in various electronic devices, such as computers, mobile phones, televisions, etc. Product chips can be divided into two categories: analog chips and digital chips. Analog chips are chips that process analog signals. Common ones include integrated operational amplifiers, digital-to-analog converters, multipliers, integrated voltage regulators, timers, signal generators, comparators, etc. Digital chips are chips that process digital signals and can be divided into general-purpose digital ICs (Integrated Circuit) and special-purpose digital ICs. General-purpose digital ICs refer to circuits with a wide range of uses and standard types, such as memory, microcomponents (such as microprocessors, microcontrollers, digital processors, etc.), and logic circuits (such as gate arrays, display drivers, etc.). Special-purpose digital ICs refer to circuits designed for specific users, for a specific or special purpose.

[0045] Optionally, the semiconductor device in the embodiment of the present application can be a wafer (i.e., a wafer), which is a chip used to make silicon semiconductors, and can be processed into various circuit element structures on the wafer to become an integrated circuit product with specific functions. The semiconductor device can also be a bare chip (i.e., a die), which is a small piece cut from a wafer by laser, and is a crystal grain before the chip is packaged. Or it can also be other types of semiconductor devices.

[0046] In an embodiment of the present application, the defect scanning program performs defect scans on semiconductor devices by setting scanning parameters. For example, different pixel sizes can be set for the defect scanning program. The defect scanning program will then use the corresponding scanning size (specifically the scanning height) to scan the semiconductor device based on the set pixel size. That is, the pixel size set for the defect scanning program will affect the scanning size of the defect scanning program.

[0047] In some optional embodiments, the defect scanning program can be used to scan the semiconductor device at different scanning sizes (i.e., different pixel sizes are set for the defect scanning program), and each scanning size will obtain a defect scanning result, so that multiple defect scanning results obtained by the defect scanning program scanning the semiconductor device at multiple scanning sizes can be obtained. Optionally, the defect scanning result can include information such as the shape, size, location, and quantity of the defect point.

[0048] In some optional embodiments, when the defect scanning program scans the semiconductor device through multiple scanning sizes, the scanning process corresponding to at least some of the scanning sizes adopts a non-full coverage scanning method, which can improve the scanning speed of the defect scanning program. The scanning process corresponding to at least some of the scanning sizes adopts a non-full coverage scanning method, which means that a part of the scanning process adopts a non-full coverage scanning method, or all scanning processes adopt a full coverage scanning method. For example, if the defect scanning program scans the semiconductor device through two scanning sizes, then a non-full coverage scanning method can be used when scanning the semiconductor device through these two scanning sizes, or a non-full coverage scanning method can be used when scanning the semiconductor device through one of the scanning sizes.

[0049] It should be noted that the non-full coverage scanning method means that a scanning process of the defect scanning program does not completely cover the set scanning size, that is, a scanning process only covers a part of the area of ​​the set scanning size. For example, if the non-full coverage scanning method is a 50% scanning coverage method, then only 50% of the area (the area is the area size represented by the set scanning size) is scanned in a scanning process.

[0050] In some optional embodiments, when the defect scanning program performs defect scanning on the semiconductor device at various scanning sizes, the area scanned by the defect scanning program on the semiconductor device can be recorded to obtain the scanning area corresponding to each scanning size. For example, when the defect scanning program performs defect scanning on the semiconductor device at a scanning size, if the actual scanning area is area A and area B, then the scanning area corresponding to the scanning size can be recorded as area A and area B.

[0051] It can be seen that in Figure 3 In step S310 shown in , after the defect scanning program scans the semiconductor device through multiple scanning sizes, the defect scanning results corresponding to each scanning size can be obtained, and the scanning area corresponding to each scanning size can also be obtained. Then, the defect data (such as the number of defect points, defect point location information, etc.) contained in the scanning area corresponding to each scanning size can be obtained based on the defect scanning results.

[0052] Continue to refer to Figure 3 As shown, in step S320, overlapping scanning areas corresponding to multiple scanning sizes are calculated according to the scanning areas corresponding to each scanning size.

[0053] In some optional embodiments, according to the scanning area corresponding to each scanning size, calculating the overlapping scanning area corresponding to multiple scanning sizes is to find the area scanned together when the defect scanning program scans the semiconductor device through multiple scanning sizes. For example, when the defect scanning program scans the semiconductor device through scanning size 1, the area scanned (i.e., the scanning area corresponding to scanning size 1) is area A and area B; when the defect scanning program scans the semiconductor device through scanning size 2 (i.e., the scanning area corresponding to scanning size 2) is area A and area C, then the overlapping scanning area corresponding to scanning size 1 and scanning size 2 is area A.

[0054] In step S330, defect source analysis is performed on the semiconductor device according to defect data respectively located in overlapping scanning areas in the plurality of defect scanning results.

[0055] In some optional embodiments, the process of defect source analysis for semiconductor devices may be to obtain defect point information (such as the number of defect points, defect point location information, etc.) in the overlapping scanning area from multiple defect scanning results respectively, and then determine the addition of defect points in the overlapping scanning area of ​​multiple defect scanning results based on the defect point information in the overlapping scanning area obtained from the multiple defect scanning results respectively.

[0056] For example, continuing with the above example, assuming that the scanning areas corresponding to scanning size 1 are area A and area B, when the defect scanning program scans the semiconductor device using scanning size 1, 2 defect points are found in area A, and no defect points are found in area B; the scanning areas corresponding to scanning size 2 are area A and area C, when the defect scanning program scans the semiconductor device using scanning size 2, 3 defect points are found in area A (2 of the 3 defect points are the same as the defect points found in area A using scanning size 1), and 2 defect points are found in area C. Since the overlapping scanning area corresponding to scanning size 1 and scanning size 2 is area A, it can be determined that when the defect scanning program scans the semiconductor device using scanning size 2, 1 defect point is added in area A compared to scanning size 1.

[0057] Optionally, when performing defect source analysis on semiconductor devices, defect data that is not in the overlapping scanning area in multiple defect scanning results can be discarded. For example, in the above example, since the defect scanning program did not scan area C when scanning the semiconductor device with scanning size 1, and did not scan area B when scanning the semiconductor device with scanning size 2, the defect data in area B obtained by the defect scanning program by scanning the semiconductor device with scanning size 1 can be discarded, and the defect data in area C obtained by the defect scanning program by scanning the semiconductor device with scanning size 2 can be discarded. This can avoid the problem of inaccurate conclusions about new defect points caused by analyzing defect data in different scanning areas during multiple scanning processes. It should be noted that discarding defect data that is not in the overlapping scanning area in multiple defect scanning results means not using these defect data to perform defect source analysis.

[0058] In some optional embodiments, if there are multiple overlapping scanning areas corresponding to multiple scanning sizes, then the increase in defect points in each overlapping scanning area of ​​the multiple defect scanning results can be determined based on the defect point information in each overlapping scanning area obtained from the multiple defect scanning results, thereby ensuring the accuracy of the defect source analysis.

[0059] For example, the scanning areas corresponding to scanning size 1 are area A, area B, area C, and area D. When the defect scanning program scans the semiconductor device by scanning size 1, 2 defect points are found in area A, no defect points are found in area B, 1 defect point is found in area C, and 1 defect point is found in area D; the scanning areas corresponding to scanning size 2 are area A, area C, and area E. When the defect scanning program scans the semiconductor device by scanning size 2, 3 defect points are found in area A (2 of the 3 defect points are the same as the defect points found in area A by scanning size 1, for example, the position information of 2 of the 3 defect points is the same as the position information of the defect points found in area A by scanning size 1). The position information of the scanning size 1 is the same as that of the scanning size 2), 3 defect points are found in area C (one of the three defect points is the same as the defect point found in area C by scanning size 1, for example, the position information of one of the three defect points is the same as the position information of the defect point found in area C by scanning size 1), and no defect point is found in area E. Since the overlapping scanning areas corresponding to scanning size 1 and scanning size 2 are area A and area C, that is, there are multiple overlapping scanning areas, defect source analysis is performed on area A and area C respectively. That is to say, when the defect scanning program scans the semiconductor device by scanning size 2, compared with scanning size 1, one defect point is added in area A and two defect points are added in area C.

[0060] In a specific application scenario of the present application, the defect scanning program can scan the semiconductor device through two scanning sizes, and the obtained defect scanning results include a first defect scanning result corresponding to the first scanning size, and a second defect scanning result corresponding to the second scanning size. In this case, the process of defect source analysis of the semiconductor device can be: obtaining the position information of the first defect point in the overlapping scanning area from the first defect scanning result, and obtaining the position information of the second defect point in the overlapping scanning area from the second defect scanning result, and then comparing the position information of the first defect point with the position information of the second defect point to determine the target defect point in the second defect point that has different position information from the first defect point, and then using the target defect point as the defect point newly added in the overlapping scanning area compared with the first defect scanning result in the second defect scanning result.

[0061] For example, the scanning areas corresponding to the first scanning size are area A, area B, and area C. When the defect scanning program scans the semiconductor device using the first scanning size, 2 defect points are found in area A, no defect points are found in area B, and 2 defect points are found in area C; the scanning areas corresponding to the second scanning size are area A, area C, and area E. When the defect scanning program scans the semiconductor device using the second scanning size, 3 defect points are found in area A, 1 defect point is found in area C, and no defect points are found in area E. Since the overlapping scanning areas corresponding to the first scanning size and the second scanning size are area A and area C, if the position information of one of the three defect points found in area A by the second scanning size is different from the position information of the defect point found in area A by the first scanning size, then it means that a new defect point is found in area A by the second scanning size, that is, it can be determined that the number of new defect points added in the overlapping scanning area A by the second defect scanning result is 1 compared with the first defect scanning result; if the position information of one defect point found in area C by the second scanning size is the same as the position information of a defect point found in area C by the first scanning size, then it means that no new defect point is found in area C by the second scanning size, that is, it can be determined that no new defect point is added in the overlapping scanning area C by the second defect scanning result compared with the first defect scanning result.

[0062] It should be noted that, in the above-mentioned embodiment of the present application, if the position information of the three defect points found in area A by the second scanning size is different from the position information of the defect points found in area A by the first scanning size, it means that three defect points are newly found in area A by the second scanning size, so it can be determined that the number of newly added defect points in the overlapped scanning area A by the second defect scanning result is 3 compared with the first defect scanning result. That is, in the embodiment of the present application, determining whether new defect points are added in the same overlapped scanning area mainly depends on the position information of the defect points scanned by multiple scanning processes, and using this to determine whether defect points that were not scanned by the previous scanning process are found in the subsequent scanning process.

[0063] At the same time, it is worth noting that in the above-mentioned embodiments of the present application, the defect points are considered to be the same when the position information of the defect points is consistent. In other embodiments of the present application, judgment can also be made based on more attribute information of the defect points. For example, it can be determined whether the defect points are the same based on the position information and shape information of the defect points. That is, when the position information and shape information of the defect points scanned in multiple scanning processes are the same, they are identified as the same defect points.

[0064] It can be seen that the technical solution of the embodiment of the present application is mainly to record the scanned area when the defect scanning program scans the semiconductor device, and then analyze the scanning areas corresponding to the multiple scanning processes of the defect scanning program to determine the overlapping scanning areas of the multiple scanning processes, and then compare and analyze the defect data in the overlapping scanning area. This can avoid the inaccuracy of defect source analysis caused by the incomplete scanning areas of the multiple scanning processes, and thus accurately locate the defect position in the semiconductor device.

[0065] The following takes the example of a defect scanning program scanning a semiconductor device with two scanning sizes to further illustrate the implementation details of the technical solution of the embodiment of the present application:

[0066] like Figure 4 As shown, assuming that the defect scanning program scans the semiconductor device with different scanning sizes in step 1 and step 2 respectively, the specific defect analysis method may include:

[0067] S401, when the defect scanning program scans the semiconductor device through step 1, the scanning area is recorded, and then after the scanning is completed, the defect scanning result is saved in the database. Optionally, the defect scanning result may include information such as the shape, size, location (such as the scanning area, etc.), and quantity of the defect point.

[0068] S402, when the defect scanning program scans the semiconductor device through step 2, the scanning area is recorded, and then after the scanning is completed, the defect scanning result is saved in the database. Similarly, the defect scanning result can also include information such as the shape, size, location (such as the scanning area, etc.), and quantity of the defect point.

[0069] S403, when performing DSA analysis based on the defect scanning results of step 1 and step 2, it is necessary to use the result of processing the data of the scanning area. The processing of the data of the scanning area is to find the overlapping scanning area in step 1 and step 2, and eliminate the influence of the non-overlapping area, so that when performing DSA analysis (for example, using analysis software to perform overlay analysis on the defect scanning results of step 1 and step 2), the defect point situation in the overlapping scanning area can be accurately analyzed.

[0070] In some optional embodiments, the process of recording the scan area can be as follows: Figure 5 As shown, the recorded data corresponding to Layer1 is used to represent the scanning area information of the semiconductor device scanned in step 1 (i.e., the information obtained by scanning each die in the semiconductor device), and the recorded data corresponding to Layer2 is used to represent the scanning area information of the semiconductor device scanned in step 2. These recorded data are formed into a file (for example, a KLARF file, which is a text format for saving results) and then stored in the database. Then, when performing DSA analysis, the file will be obtained from the database to obtain the scanning areas of steps 1 and 2.

[0071] Specifically, Figure 6 As shown, step 1 uses a pixel size of 90nm and a scanning coverage of 50% to scan the semiconductor device, then the area A (assuming that 4 defect points are scanned) and area B (assuming that 4 defect points are scanned) of the semiconductor device will be scanned, and the scanning process will be skipped for area C and area D. Step 2 uses a pixel size of 45nm and a scanning coverage of 50% to scan the semiconductor device, then the area A (assuming that 13 defect points are scanned, and the position information of 4 defect points is the same as the position information of the 4 defect points scanned in area A in step 1, that is, 4 of the 13 defect points scanned in area A in step 2 are consistent with the defect points scanned in area A in step 1) and area C (assuming that 5 defect points are scanned) of the semiconductor device will be scanned, and the scanning process will be skipped for area B and area D.

[0072] In this case, when performing DSA analysis, the related technology directly uses the defect points scanned in step 2 to compare with the defect points scanned in step 1 to determine whether there are new defect points, that is, step 2 adds 9 (13-4 new defect points in area A) + 5 (5-0 new defect points in area C) = 14 defect points compared with step 1. However, this method is not accurate, because area C is not scanned in step 1, and the scanning data of area C in step 1 is missing. Therefore, if the defect point data scanned in step 2 is directly used to compare with the defect point data scanned in step 1, the accuracy of DSA analysis will be low due to the different scanning areas.

[0073] In the technical solution of the embodiment of the present application, the areas scanned by steps 1 and 2 are first analyzed to determine the area scanned jointly by steps 1 and 2 (i.e., the overlapping scanning area), that is, area A, and the data of the non-overlapping scanning area is discarded and not subjected to DSA analysis. Therefore, after adopting the technical solution of the embodiment of the present application, step 2 adds 9 defect points compared to step 1 (i.e., 13-4 defect points are added to area A, and the defect data in area C is discarded).

[0074] In summary, the technical solution of the embodiment of the present application can analyze the scanning area corresponding to multiple scanning processes of the defect scanning program to determine the overlapping scanning area of ​​the multiple scanning processes, and then perform comparative analysis on the defect data in the overlapping scanning area, thereby improving the accuracy of defect analysis of semiconductor devices.

[0075] The following describes an apparatus embodiment of the present application, which can be used to execute the defect analysis method of the semiconductor device in the above-mentioned embodiment of the present application. For details not disclosed in the apparatus embodiment of the present application, please refer to the above-mentioned embodiment of the defect analysis method of the semiconductor device of the present application.

[0076] Figure 7 A block diagram of a defect analysis apparatus for a semiconductor device according to an embodiment of the present application is shown.

[0077] Reference Figure 7 As shown, a defect analysis device 700 for a semiconductor device according to an embodiment of the present application includes: an acquisition unit 702 , a calculation unit 704 and a processing unit 706 .

[0078] Among them, the acquisition unit 702 is configured to acquire multiple defect scanning results obtained by the defect scanning program through scanning the semiconductor device through multiple scanning sizes, wherein one scanning size corresponds to one defect scanning result; and acquire the areas where the defect scanning program scans the semiconductor device respectively through the multiple scanning sizes to obtain the scanning areas corresponding to each scanning size; the calculation unit 704 is configured to calculate the overlapping scanning areas corresponding to the multiple scanning sizes based on the scanning areas corresponding to the respective scanning sizes; the processing unit 706 is configured to perform defect source analysis on the semiconductor device based on the defect conditions in the overlapping scanning areas in the multiple defect scanning results.

[0079] In some embodiments of the present application, based on the aforementioned scheme, the processing unit 706 is configured to: respectively obtain defect point information within the overlapping scanning area from the multiple defect scanning results; and determine the newly added defect points of the multiple defect scanning results within the overlapping scanning area based on the defect point information within the overlapping scanning area respectively obtained from the multiple defect scanning results.

[0080] In some embodiments of the present application, based on the aforementioned scheme, the processing unit 706 is configured as follows: if there are multiple overlapping scanning areas corresponding to the multiple scanning sizes, then according to the defect point information in each overlapping scanning area respectively obtained from the multiple defect scanning results, determine the newly added defect points in the multiple defect scanning results in each overlapping scanning area.

[0081] In some embodiments of the present application, based on the aforementioned solution, the multiple scanning sizes include two scanning sizes, and the multiple defect scanning results include a first defect scanning result corresponding to the first scanning size, and a second defect scanning result corresponding to the second scanning size;

[0082] The processing unit 706 is configured to: obtain the position information of the first defect point in the overlapping scanning area from the first defect scanning result, and obtain the position information of the second defect point in the overlapping scanning area from the second defect scanning result; compare the position information of the first defect point with the position information of the second defect point to determine a target defect point in the second defect point whose position information is different from that of the first defect point; and use the target defect point as a defect point newly added in the overlapping scanning area when the second defect scanning result is compared with the first defect scanning result.

[0083] In some embodiments of the present application, based on the aforementioned scheme, the acquisition unit 702 is configured to: when the defect scanning program performs a defect scan on the semiconductor device through the various scanning sizes, record the area scanned by the defect scanning program on the semiconductor device to generate a scanning area corresponding to the various scanning sizes.

[0084] In some embodiments of the present application, based on the aforementioned scheme, the acquisition unit 702 is configured to: acquire multiple defect scanning results obtained by scanning the semiconductor device when the defect scanning program adopts different pixel sizes as scanning parameters, wherein one pixel size corresponds to one scanning size.

[0085] In some embodiments of the present application, based on the aforementioned solution, when the defect scanning program scans the semiconductor device through the multiple scanning sizes, the scanning process corresponding to at least some of the scanning sizes adopts a non-full coverage scanning method.

[0086] In some embodiments of the present application, based on the above-mentioned solution, the processing unit 706 is further configured to: when performing defect source analysis on the semiconductor device, discard defect data that is not in the overlapping scanning area among the multiple defect scanning results.

[0087] Figure 8 A schematic diagram of the structure of a computer system of an electronic device suitable for implementing an embodiment of the present application is shown. The electronic device may be the electronic device used to execute the defect analysis method of a semiconductor device in the aforementioned embodiment.

[0088] It should be noted that Figure 8 The computer system 800 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0089] like Figure 8 As shown, the computer system 800 may include a central processing unit (CPU) 801, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 802 or the program loaded from the storage part 808 to the random access memory (RAM) 803, such as executing the method described in the above embodiment. In the RAM 803, various programs and data required for system operation are also stored. The CPU 801, ROM 802 and RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0090] The following components can be connected to the I / O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed so that a computer program read therefrom is installed into the storage section 808 as needed.

[0091] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program is used to perform the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication section 809, and / or installed from a removable medium 811. When the computer program is executed by a central processing unit (CPU) 801, various functions defined in the system of the present application are executed.

[0092] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a computer program, which may be used by an instruction execution system, device or device or used in combination with it. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable computer program is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0093] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of the boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and a computer program.

[0094] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0095] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more computer programs, and when the above one or more computer programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

[0096] It should be noted that, although several modules or units of the equipment for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into being embodied by multiple modules or units.

[0097] Through the description of the above implementation methods, it is easy for those skilled in the art to understand that the example implementation methods described here can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the implementation methods of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable an electronic device to execute the method according to the implementation methods of the present application.

[0098] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application.

[0099] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A defect analysis method for a semiconductor device, characterized in that: include: Acquire a plurality of defect scanning results obtained by a defect scanning program scanning a semiconductor device through a plurality of scanning sizes, wherein one scanning size corresponds to one defect scanning result, and scanning processes corresponding to at least some of the scanning sizes adopt a non-full coverage scanning method; Acquire the areas where the defect scanning program scans the semiconductor device respectively through the multiple scanning sizes, and obtain the scanning area corresponding to each scanning size; Calculating overlapping scanning areas corresponding to the multiple scanning sizes according to the scanning areas corresponding to the respective scanning sizes; Defect data respectively located in the overlapping scanning area in the plurality of defect scanning results are compared to determine the defect status of the semiconductor device in the overlapping scanning area.

2. The defect analysis method of a semiconductor device according to claim 1, characterized in that: Comparing defect data respectively located in the overlapping scanning area in the plurality of defect scanning results to determine the defect situation of the semiconductor device in the overlapping scanning area includes: Respectively acquiring defect point information within the overlapping scanning area from the multiple defect scanning results; According to the defect point information respectively acquired from the multiple defect scanning results and located in the overlapping scanning area, the newly added defect points of the multiple defect scanning results in the overlapping scanning area are determined.

3. The defect analysis method of a semiconductor device according to claim 2, characterized in that: Determining, according to defect point information respectively obtained from the multiple defect scanning results and located in the overlapping scanning area, the newly added defect points of the multiple defect scanning results in the overlapping scanning area, comprises: If there are multiple overlapping scanning areas corresponding to the multiple scanning sizes, the newly added defect points of the multiple defect scanning results in each overlapping scanning area are determined based on the defect point information in each overlapping scanning area respectively obtained from the multiple defect scanning results.

4. The defect analysis method of a semiconductor device according to claim 1, characterized in that: The plurality of scanning sizes include two scanning sizes, and the plurality of defect scanning results include a first defect scanning result corresponding to the first scanning size, and a second defect scanning result corresponding to the second scanning size; Comparing defect data respectively located in the overlapping scanning area in the plurality of defect scanning results to determine the defect situation of the semiconductor device in the overlapping scanning area includes: Acquire location information of a first defect point in the overlapping scanning area from the first defect scanning result, and acquire location information of a second defect point in the overlapping scanning area from the second defect scanning result; Comparing the position information of the first defect point with the position information of the second defect point to determine a target defect point in the second defect point whose position information is different from that in the first defect point; The target defect point is taken as a defect point newly added in the overlapping scanning area by comparing the second defect scanning result with the first defect scanning result.

5. The defect analysis method of a semiconductor device according to claim 1, characterized in that: Acquiring the areas scanned by the defect scanning program on the semiconductor device respectively through the multiple scanning sizes to obtain the scanning areas corresponding to the respective scanning sizes, including: When the defect scanning program performs defect scanning on the semiconductor device using the various scanning sizes, the area scanned by the defect scanning program on the semiconductor device is recorded to generate scanning areas corresponding to the various scanning sizes.

6. The defect analysis method of a semiconductor device according to claim 1, characterized in that: A plurality of defect scanning results obtained by a defect scanning program scanning a semiconductor device at a plurality of scanning sizes are obtained, including: A plurality of defect scanning results are obtained by scanning a semiconductor device when a defect scanning program adopts different pixel sizes as scanning parameters, wherein one pixel size corresponds to one scanning size.

7. The defect analysis method of a semiconductor device according to any one of claims 1 to 6, characterized in that: The defect analysis method further comprises: When performing defect source analysis on the semiconductor device, defect data that is not within the overlapping scanning area in the plurality of defect scanning results is discarded.

8. A defect analysis device for a semiconductor device, characterized in that: include: An acquisition unit is configured to acquire a plurality of defect scanning results obtained by a defect scanning program scanning a semiconductor device at a plurality of scanning sizes, wherein one scanning size corresponds to one defect scanning result, and a scanning process corresponding to at least some of the scanning sizes adopts a non-full coverage scanning method; and acquire areas of the semiconductor device respectively scanned by the defect scanning program at the plurality of scanning sizes to obtain a scanning area corresponding to each scanning size; a calculation unit configured to calculate the overlapping scanning areas corresponding to the multiple scanning sizes according to the scanning areas corresponding to the respective scanning sizes; The processing unit is configured to compare the defect conditions of the plurality of defect scanning results respectively located in the overlapping scanning area to determine the defect condition of the semiconductor device in the overlapping scanning area.

9. A computer readable medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the defect analysis method of a semiconductor device according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more computer programs, which, when executed by the one or more processors, enables the electronic device to implement the defect analysis method for a semiconductor device as described in any one of claims 1 to 7.

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