Super junction IGBT devices

Abstract

The present invention discloses a superjunction IGBT device, comprising a superjunction structure and a first epitaxial layer at the bottom of the superjunction structure. The bottom surface of a second-conductivity-type column of the superjunction structure is located below the top surface of the first epitaxial layer. A first bottom doped region of the second conductivity type is formed at the bottom of the second-conductivity-type column. The first bottom doped region and the extension of the second-conductivity-type column into the first epitaxial layer contact and overlap to form a second bottom doped region. When the device is reverse biased, each second bottom doped region depletes the first epitaxial layer and forms a bottom voltage-withstand layer. The front structure of the superjunction IGBT device includes a channel region doped with the second conductivity type. A first top doped region doped with the first conductivity type is located between the channel region and the second-conductivity-type column. The first top doped region enables the second-conductivity-type column to have a floating structure. The present invention can improve the device's breakdown voltage while reducing process complexity, enabling the device's breakdown voltage to exceed 1200V.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, in particular to a super junction (SJ) insulated gate bipolar transistor (IGBT) device. Background Art

[0002] like Figure 1 FIG. 1 is a schematic diagram of the structure of an existing super junction IGBT device (SJ-IGBT); the existing super junction IGBT device includes:

[0003] The collector region 101 is formed by backside implantation. Taking an N-type device as an example, the collector region 101 is P-type doped and formed by P-type backside implantation. The implanted impurity is usually boron or BF2. The implantation energy is between 15 and 100 keV, and the implantation dose is usually 1e12 / cm 2 ~1e14 / cm 2 Generally, a higher backside implant dose results in a lower on-state voltage drop when the device is on, but a larger current tail and higher turn-off losses when the device is off. Therefore, for IGBT devices used in low-speed applications, the backside implant dose is usually higher, while for high-speed applications, the backside implant dose is usually lower.

[0004] The N-type epitaxial layer 102 forms the device's N-type drift region. Unlike conventional IGBTs, the SJ-IGBT also incorporates P-pillars 105 within the N-type epitaxial layer 102. These P-pillars, formed by alternating N-pillars between the N-type epitaxial layer 102, form a superjunction structure. The thickness t101 of the superjunction structure is equal to the thickness of the P-pillars 105. There are two common methods for implementing P-pillars 105: trench etching and P-type silicon filling. This method offers the advantage of fewer process steps, but the trench etching has a high aspect ratio and is complex. Furthermore, P-type silicon filling can easily introduce defects, resulting in high device leakage. Furthermore, the tilt angle of the trench etching is difficult to monitor, which greatly complicates process control. Another method relies on multiple epitaxy and ion implantation. This method offers the advantage of simple implementation, but also involves many steps and high costs. The breakdown voltage of SJ-IGBT is achieved by lateral depletion of the N-type drift region between the P-pillars 105 and 105, which reduces the equivalent doping concentration. This allows the doping concentration of the drift region to be significantly increased without reducing the breakdown voltage. Taking 650V IGBT as an example, the doping concentration of the drift region of traditional IGBT is usually 2e14 / cm 3 Below, the doping concentration of the drift region of the SJ-IGBT can be 2e15 / cm 3 Above, even reaching 1e16 / cm 3The P-pillar 105 is deep enough to quickly extract charge when the IGBT is turned off, improving the dv / dt during the turn-off process. However, to enhance the conductivity modulation effect of the IGBT, the P-pillar 105 is typically floating. This can be achieved through epitaxy or high-energy N-type ion implantation, forming an N-type doped region 112 on top of the P-pillar 105.

[0005] Figure 1 The gate structure is a trench gate, including a gate dielectric layer 103 formed on the inner surface of the gate trench and a polysilicon gate 104 filled in the gate trench. The gate dielectric layer 103 is usually a gate oxide layer, and the thickness of the gate oxide layer is usually nearby.

[0006] A P-type channel region 106 is formed on the top of the superjunction structure. In order to reduce the latch-up effect (Latch-Up) of the IGBT, the doping concentration of the channel region 106 is usually relatively high. The channel region 106 is formed by ion implantation, and the implantation dose is usually 1e13 / cm 2 ~1e14 / cm 2 between.

[0007] An N+ doped source region, namely an emitter region 107, is formed on the surface of the channel region 106. The emitter region 107 is usually implanted with arsenic at a dose of 1e15 / cm 2 ~1e16 / cm 2 The emitter region 107 is connected to the source electrode formed by the front metal layer 110 through a metal via 108. The metal via 108 is usually filled with tungsten. In order to make the metal via 108 form a good ohmic contact with the channel region 106, there is a channel lead-out region 109 formed by a through-hole injection. The through-hole injection is usually performed by BF2 injection. The injection energy is usually between 15 and 100 keV, and the injection dose is usually 1e14 / cm 2 ~5e15 / cm 2 between.

[0008] The doping concentration of the N-type epitaxial layer 102 corresponding to the drift region of the SJ-IGBT is more than five times that of a traditional IGBT. Its breakdown voltage is mainly achieved by the lateral depletion of the N-pillar and P-pillar 5 formed by the N-type epitaxial layer 102, which reduces the equivalent doping concentration of the drift region, thereby achieving the corresponding breakdown voltage (BV). Therefore, its breakdown voltage mainly depends on the depth t101 of the P-pillar 5. Generally, for a 650V SJ-IGBT, its depth t101 needs to be greater than 40μm. If a 1200V SJ-IGBT is to be realized, its depth t101 needs to be greater than 80μm. This brings great difficulties to the implementation of the process. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a super junction IGBT device, which can improve the breakdown voltage of the device and reduce the process difficulty at the same time, and can make the breakdown voltage of the device reach above 1200V.

[0010] To solve the above technical problems, the present invention provides a super junction IGBT device comprising: a first epitaxial layer doped with a first conductivity type and a second epitaxial layer doped with the first conductivity type formed on a top surface of the first epitaxial layer.

[0011] A plurality of second conductive type columns are formed in the second epitaxial layer, and the second conductive type columns are formed by the second epitaxial layer between the second conductive type columns. The first conductive type columns and the second conductive type columns are alternately arranged to form a super junction structure.

[0012] The doping concentration of the second conductive type column matches the doping concentration of the second epitaxial layer so that the charges of the first conductive type column and the second conductive type column are matched. When the device is reverse biased, the super junction structure is depleted and a top voltage-resistant layer is formed.

[0013] The bottom surface of the second conductive type column is located below the top surface of the first epitaxial layer. A first bottom doped region of the second conductive type is formed in the first epitaxial layer below the bottom surface of each second conductive type column.

[0014] The first bottom doped region and the extended portion of the second conductive type column extending into the first epitaxial layer are in contact and overlap to form a second bottom doped region. When the device is reverse biased, each second bottom doped region depletes the first epitaxial layer and forms a bottom voltage-resistant layer. The doping concentration of the second conductive type column has fluctuations caused by the process, and the doping concentration of the first bottom doped region satisfies the requirement of sufficient depletion of the first epitaxial layer for voltage resistance when the device is reverse biased when the doping concentration of the second conductive type column is the lowest value of the fluctuation.

[0015] The front side structure of the super junction IGBT device includes a channel region doped with the second conductivity type.

[0016] A first top doped region of the first conductive type is provided between the channel region and the second conductive type column. The first top doped region separates the second conductive type column from the channel region and enables the second conductive type column to present a floating structure.

[0017] The back side structure of the super junction IGBT device is formed on the back side of the first epitaxial layer.

[0018] A further improvement is that the component structure of the second conductive type column includes a third epitaxial layer of the second conductive type filled in the super junction trench.

[0019] A further improvement is that the bottom surface of the second conductive type column is determined by the bottom surface of the super junction trench, and the bottom surface of the super junction trench is located below the top surface of the first epitaxial layer.

[0020] The first bottom doped region is an ion implantation region of the second conductivity type formed in a self-aligned manner at the bottom of the super junction trench.

[0021] A further improvement is that the ion implantation energy of the first bottom doping region is 50keV to 200keV, and the implantation dose is 5e11cm -2 ~2e12cm -2 .

[0022] A further improvement is that the resistivity of the first epitaxial layer is more than 5 times the resistivity of the second epitaxial layer.

[0023] A further improvement is that the resistivity of the first epitaxial layer is more than 10 times the resistivity of the second epitaxial layer.

[0024] A further improvement is that the front structure further includes: a gate structure, an emitter region heavily doped with the first conductivity type, an interlayer film, a through hole passing through the interlayer film, and an emitter and a gate formed by patterning the front metal layer.

[0025] The gate structure includes a gate dielectric layer and a gate conductive material layer.

[0026] The emitter region is formed on the surface of the channel region and is self-aligned with the gate structure.

[0027] The emitter region is connected to the emitter electrode through the corresponding through hole at the top.

[0028] The gate conductive material layer is connected to the gate through the corresponding through hole on the top.

[0029] A further improvement is that the through hole corresponding to the emitter region also passes through the emitter region and contacts the channel region; a channel lead-out region heavily doped with the second conductive type is also formed at the bottom of the through hole corresponding to the emitter region, and the channel lead-out region and the through hole at the top form an ohmic contact, and the channel region contacts the through hole through the channel lead-out region.

[0030] A further improvement is that the gate structure adopts a trench gate, the trench gate further includes a gate trench, the gate dielectric layer is formed on the inner surface of the gate trench, and the gate conductive material layer fills the gate trench.

[0031] Components of the drift region include the first top doped region at the bottom of the channel region, the first conductive type column, and the first epitaxial layer.

[0032] The gate trench passes through the channel region longitudinally, and the side surface of the channel region covered by the side surface of the trench gate is used to form a conductive channel connecting the emitter region and the drift region.

[0033] A further improvement is that the gate structure adopts a planar gate.

[0034] A fourth epitaxial layer doped with a first conductive type is formed on the top of the super junction structure, the first top doped region is composed of the fourth epitaxial layer, and the channel region is formed in a selected region of the fourth epitaxial layer.

[0035] Components of the drift region include the first top doped region at the bottom of the channel region, the fourth epitaxial layer between the channel regions, and the first conductive type column and the first epitaxial layer at the bottom.

[0036] The planar gate is formed on the front side of the channel region and extends to the surface of the drift region. The surface of the channel region covered by the front side of the planar gate is used to form a conductive channel connecting the emitter region and the drift region.

[0037] A further improvement is that the step of the super junction structure is the sum of the width of the first conductive type column and the width of the second conductive type column.

[0038] The step of the trench gate is the sum of the width of the gate trench and the spacing between the gate trenches.

[0039] The stepping of the trench gate is independent of the stepping of the super junction structure, so that the stepping of the trench gate is smaller than, equal to, or larger than the stepping of the super junction structure.

[0040] A further improvement is that at least one emitter trench is provided between at least some of the gate trenches.

[0041] A second dielectric layer is formed on the inner surface of the emitter trench and is filled with an emitter conductive material layer. The emitter conductive material layer is connected to the emitter through the corresponding through hole at the top.

[0042] A further improvement is that the front structure further includes: a carrier storage layer heavily doped with the first conductivity type, wherein the carrier storage layer is arranged between the channel region and the first top doped region.

[0043] A further improvement is that the back structure includes:

[0044] The collector region is heavily doped with the second conductivity type.

[0045] A back metal layer is formed on the back side of the collector region, and a collector electrode is led out from the back metal layer.

[0046] A further improvement is that the back structure includes:

[0047] A buffer layer doped with a first conductive type, the buffer layer being located between a top surface of the first epitaxial layer and a top surface of the collector region, the doping concentration of the buffer layer being greater than the doping concentration of the first epitaxial layer, preventing the device from being punched through when the first epitaxial layer is completely depleted when the device is reverse biased.

[0048] A further improvement is that the buffer layer is formed on the back side of the first epitaxial layer by back ion implantation, the back ion implantation energy of the buffer layer is 100keV to 2MeV, and the implantation dose is 1e12cm -2 ~3e13cm -2 .

[0049] A further improvement is that the super junction IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the super junction IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0050] The superjunction IGBT device of the present invention uses a top voltage-resistant layer formed by depletion of the superjunction structure and a bottom voltage-resistant layer formed by depletion of the first epitaxial layer at the bottom of the superjunction structure to achieve voltage resistance when reverse biased. This can increase the breakdown voltage of the device while avoiding the defect of increased process difficulty caused by simply increasing the thickness of the superjunction structure to increase the voltage resistance. Therefore, the present invention can reduce the process difficulty while increasing the breakdown voltage of the device, and can make the breakdown voltage of the device reach more than 1200V.

[0051] In the present invention, depletion of the first epitaxial layer is achieved by using an extension portion of the second conductive type column extending downward into the first epitaxial layer. Since the doping concentration of the second conductive type column needs to ensure that it meets the charge matching requirements of the first conductive type column, the doping concentration of the second conductive type column cannot be adjusted according to the depletion requirements of the first epitaxial layer. In order to ensure sufficient depletion of the first epitaxial layer, the present invention adds a first bottom doping region at the bottom of the second conductive type column. The first bottom doping region can compensate for insufficient depletion of the first epitaxial layer when the doping concentration of the second conductive type column fluctuates, thereby ensuring that even when the doping concentration of the second conductive type column is at the lowest value of the fluctuation, sufficient depletion of the first epitaxial layer can still be achieved, thereby ensuring that the breakdown voltage reaches the required value; in addition, the first bottom doping region can be formed at the bottom of the second conductive type column by self-alignment through ion implantation, so it has the advantage of simple process.

[0052] The present invention can easily achieve sufficient depletion of the first epitaxial layer by setting the first bottom doping region. At the same time, in order to avoid the device punch-through problem caused by the complete depletion of the first epitaxial layer, the present invention can also add a buffer layer with a doping concentration greater than that of the first epitaxial layer at the bottom of the first epitaxial layer. The buffer layer can prevent the device from punching through, and in turn is beneficial to the setting of the first epitaxial layer and the first bottom doping region, making the device process simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0054] Figure 1 It is a schematic diagram of the structure of an existing super junction IGBT device;

[0055] Figure 2A This is a schematic structural diagram of the first bottom doping region of the IGBT device after implantation and before diffusion according to the first embodiment of the present invention;

[0056] Figure 2B 1 is a schematic structural diagram of an IGBT device according to a first embodiment of the present invention;

[0057] Figure 3 1 is a schematic structural diagram of an IGBT device according to a second embodiment of the present invention;

[0058] Figure 4 It is a schematic structural diagram of an IGBT device according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0059] like Figure 2B FIG. 1 is a schematic structural diagram of an IGBT device according to a first embodiment of the present invention; Figure 2A It is a structural schematic diagram of the first bottom doped region 12 of the IGBT device of the first embodiment of the present invention after injection and before diffusion; the super junction IGBT device of the first embodiment of the present invention includes: a first epitaxial layer 11 doped with a first conductive type and a second epitaxial layer 2 doped with a first conductive type formed on the top surface of the first epitaxial layer 11.

[0060] A plurality of second conductivity type columns 5 are formed in the second epitaxial layer 2 , and the second conductivity type columns 5 are formed by the second epitaxial layer 2 between the second conductivity type columns 5 . The first conductivity type columns and the second conductivity type columns 5 are alternately arranged to form a super junction structure.

[0061] The doping concentration of the second conductivity type pillar 5 matches the doping concentration of the second epitaxial layer 2, thereby matching the charge of the first conductivity type pillar and the second conductivity type pillar 5. When the device is reverse biased, the superjunction structure is depleted and a top voltage-sustaining layer is formed. Charge matching of the first conductivity type pillar and the second conductivity type pillar 5 means that when the device is reverse biased, the first conductivity type pillar and the second conductivity type pillar 5 can laterally deplete each other.

[0062] The bottom surface of the second conductive type column 5 is located below the top surface of the first epitaxial layer 11 . A first bottom doped region 12 of the second conductive type is formed in the first epitaxial layer 11 below the bottom surface of each second conductive type column 5 . Figure 2B In the figure, the thickness t is the thickness of the second conductive type column 5 , and the effective thickness of the super junction structure is equal to the thickness of the second conductive type column 5 on the top surface of the first epitaxial layer 11 .

[0063] The first bottom doped region 12 and the extended portion of the second conductive type column 5 extending into the first epitaxial layer 11 are in contact and overlapped to form a second bottom doped region. When the device is reverse biased, each second bottom doped region depletes the first epitaxial layer 11 and forms a bottom voltage-resistant layer. The doping concentration of the second conductive type column 5 has fluctuations caused by the process. The doping concentration of the first bottom doped region 12 satisfies the requirement of sufficient depletion for voltage-resistant performance of the first epitaxial layer 11 when the device is reverse biased when the doping concentration of the second conductive type column 5 is the lowest value of the fluctuation. According to the common knowledge of those skilled in the art, in the prior art, a super junction structure and the first epitaxial layer 11 at the bottom are often directly stacked to form a voltage-resistant layer. The disadvantage of this structure is that it is not easy to control the depletion of the first epitaxial layer 11 well. This is because the first epitaxial layer 11 is completely depleted by the extension part of the second conductive type column 5, which will limit the doping concentration and thickness of the first epitaxial layer 11, making it difficult to set the doping concentration and thickness of the first epitaxial layer 11; at the same time, even if the doping concentration and thickness of the first epitaxial layer 11 are set to be depleted by the extension part of the second conductive type column 5, after the actual process, the parameters will often fluctuate. For example, the doping concentration of the second conductive type column 5 will fluctuate around the design value, and when the doping concentration of the second conductive type column 5 fluctuates to a lower value, it is often impossible to achieve the required depletion of the first epitaxial layer 11. Therefore, it is more difficult for the prior art to control the depletion of the first epitaxial layer 11. In the first embodiment of the present invention, by independently setting the first bottom doping region 12, the first bottom doping 12 can be easily set according to the depletion requirement of the first epitaxial layer 11, thereby ensuring that the first epitaxial layer 11 can be fully depleted, so that the withstand voltage of the first epitaxial layer 11 is guaranteed.

[0064] The front structure of the super junction IGBT device includes a channel region 6 doped with the second conductivity type.

[0065] A first top doped region 15 doped with the first conductivity type is located between the channel region 6 and the second conductivity type pillar 5. The first top doped region 15 separates the second conductivity type pillar 5 from the channel region 6 and thereby provides a floating structure for the second conductivity type pillar 5. In some embodiments, the first top doped region 15 is formed by an epitaxial layer doped with the first conductivity type. In some embodiments, the first top doped region 15 can also be formed by ion implantation of the first conductivity type dopant into the epitaxial layer.

[0066] The backside structure of the super junction IGBT device is formed on the backside of the first epitaxial layer 11 .

[0067] In the first embodiment of the present invention, the second conductivity type pillar 5 is composed of a third epitaxial layer of the second conductivity type filled in the super junction trench.

[0068] The bottom surface of the second conductivity type pillar 5 is determined by the bottom surface of the super junction trench, and the bottom surface of the super junction trench is located below the top surface of the first epitaxial layer 11 .

[0069] The first bottom doped region 12 is a second conductivity type ion implantation region formed in a self-aligned manner at the bottom of the super junction trench. Figure 2A As shown, the ion-implanted region 12a is a second-conductivity-type ion-implanted region formed self-aligned at the bottom of the superjunction trench, corresponding to the first bottom doped region 12. Typically, the ion-implanted region 12a is relatively small after implantation, with its width typically approaching the bottom width of the superjunction trench. However, due to the low doping concentration of the first epitaxial layer 11, the ion-implanted region 12a undergoes significant diffusion after thermal processing. The diffused ion-implanted region 12a then forms the first bottom doped region 12.

[0070] In some embodiments, the ion implantation energy of the first bottom doping region 12 is 50keV to 200keV, and the implantation dose is 5e11cm -2 ~2e12cm -2 .

[0071] In some embodiments, the resistivity of the first epitaxial layer 11 is more than five times the resistivity of the second epitaxial layer 2. Resistivity corresponds to doping concentration, and from the perspective of doping concentration, it can be described as follows: the doping concentration of the first epitaxial layer 11 is less than one-fifth of the doping concentration of the second epitaxial layer 2. In some preferred embodiments, the resistivity of the first epitaxial layer 11 is more than ten times the resistivity of the second epitaxial layer 2.

[0072] In the first embodiment of the present invention, the front structure also includes: a gate structure, an emitter region 7 heavily doped with the first conductive type, an interlayer film 14, a through hole 8 passing through the interlayer film 14, and an emitter and a gate (not shown) patterned by the front metal layer 10. Figure 2BThe front metal layer 10 corresponding to the emitter is shown in the figure, while the front metal layer corresponding to the gate is not shown.

[0073] The gate structure includes a gate dielectric layer 3 and a gate conductive material layer 4. In some embodiments, the gate dielectric layer 3 is a gate oxide layer, and the gate conductive material layer 4 is a polysilicon gate.

[0074] The emitter region 7 is formed on the surface of the channel region 6 and is self-aligned with the gate structure.

[0075] The emitter region 7 is connected to the emitter through a corresponding through hole 8 at the top.

[0076] The gate conductive material layer 4 is connected to the gate via a corresponding through hole 8 at the top.

[0077] The through hole 8 corresponding to the emitter region 7 also passes through the emitter region 7 and contacts the channel region 6; a channel lead-out region 9 heavily doped with the second conductive type is also formed at the bottom of the through hole 8 corresponding to the emitter region 7, and the channel lead-out region 9 forms an ohmic contact with the through hole 8 at the top, and the channel region 6 contacts the through hole 8 through the channel lead-out region 9.

[0078] In the first embodiment of the present invention, the gate structure adopts a trench gate, which further includes a gate trench. The gate dielectric layer 3 is formed on the inner surface of the gate trench, and the gate conductive material layer 4 fills the gate trench.

[0079] Components of the drift region include a first top doped region 15 at the bottom of the channel region 6 , a first conductivity type column, and a first epitaxial layer 11 .

[0080] The gate trench passes through the channel region 6 longitudinally, and the side surfaces of the channel region 6 covered by the side surfaces of the trench gate are used to form a conductive channel connecting the emitter region 7 and the drift region.

[0081] In other embodiments, the gate structure may also adopt a planar gate. A fourth epitaxial layer doped with the first conductivity type is formed on top of the superjunction structure, the first top doped region 15 is composed of the fourth epitaxial layer, and the channel region 6 is formed in a selected area of ​​the fourth epitaxial layer. The components of the drift region include the first top doped region 15 at the bottom of the channel region 6, the fourth epitaxial layer between the channel regions 6, and the first conductivity type column and the first epitaxial layer 11 at the bottom. The planar gate is formed on the front of the channel region 6 and extends to the surface of the drift region. The surface of the channel region 6 covered by the front of the planar gate is used to form a conductive channel connecting the emitter region 7 and the drift region.

[0082] In the first embodiment of the present invention, the step width of the super junction structure is the sum of the width of the first conductivity type column and the width of the second conductivity type column 5 .

[0083] The pitch of the trench gate is the sum of the gate trench width and the gate trench pitch.

[0084] The stepping of the trench gate is independent of the stepping of the super junction structure, so that the stepping of the trench gate is smaller than, equal to, or larger than the stepping of the super junction structure.

[0085] Figure 2B In the first embodiment of the present invention, the trench gate stepping is set equal to the stepping of the superjunction structure. The trench gate is typically positioned directly above the first conductivity type pillar. In this case, the thickness of the first top doped region 15 can be relatively thin, and the bottom of the gate trench can extend into the top region of the first conductivity type pillar.

[0086] In other embodiments, the step size of the trench gate can be set to be smaller than that of the super junction structure; or the step size of the trench gate can be set to be larger than that of the super junction structure. The specific setting can be flexibly selected according to actual needs.

[0087] In the first embodiment of the present invention, the back surface structure includes:

[0088] The collector region 1 is heavily doped with the second conductivity type.

[0089] A back metal layer (not shown) is formed on the back side of the collector region 1 and a collector electrode is led out from the back metal layer.

[0090] A buffer layer 13 doped with the first conductivity type is located between the top surface of the first epitaxial layer 11 and the top surface of the collector region 1. The doping concentration of the buffer layer 13 is greater than the doping concentration of the first epitaxial layer 11. This prevents device punchthrough when the first epitaxial layer 11 is completely depleted when the device is reverse biased. By providing the buffer layer 13, device punchthrough is prevented, thereby improving device performance. This, in turn, can further simplify the configuration of the first bottom doped region 12 and the first epitaxial layer 11. For example, the first bottom doped region 12 can be increased to ensure that the first epitaxial layer 11 can be completely depleted when reverse biased. The thickness of the first epitaxial layer 11 when completely depleted is fixed, so the withstand voltage capability of the first epitaxial layer 11 is also fixed. In contrast, if the buffer layer 13 is not provided, the depletion of the first epitaxial layer 11 by the doping of the first bottom doping region 12 needs to be controlled to prevent device punchthrough. Device punchthrough occurs when the emitter region 7 and the collector region 1 of the device are punched through the depletion region.

[0091] In some embodiments, the buffer layer 13 is formed on the back side of the first epitaxial layer 11 by back ion implantation. The implantation energy of the back ion implantation of the buffer layer 13 is 100 keV to 2 MeV, and the implantation dose is 1e12 cm -2 ~3e13cm -2 .

[0092] In the first embodiment of the present invention, the superjunction IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the superjunction IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0093] The super-junction IGBT device of the first embodiment of the present invention uses a top voltage-resistant layer formed by depletion of the super-junction structure and a bottom voltage-resistant layer formed by depletion of the first epitaxial layer 11 at the bottom of the super-junction structure to achieve voltage resistance when reverse biased. This can improve the breakdown voltage of the device while avoiding the defect of increased process difficulty brought about by increasing the thickness of the super-junction structure alone to increase the voltage resistance. Therefore, the first embodiment of the present invention can reduce the process difficulty while improving the breakdown voltage of the device, and can make the breakdown voltage of the device reach more than 1200V.

[0094] In the first embodiment of the present invention, depletion of the first epitaxial layer 11 is achieved by using the extension portion of the second conductive type column 5 extending downward into the first epitaxial layer 11. Since the doping concentration of the second conductive type column 5 needs to ensure that it meets the charge matching requirement of the first conductive type column, the doping concentration of the second conductive type column 5 cannot be adjusted according to the depletion requirement of the first epitaxial layer 11. In order to ensure sufficient depletion of the first epitaxial layer 11, the first embodiment of the present invention adds a first bottom doping region 12 at the bottom of the second conductive type column 5. The first bottom doping region 12 can compensate for the insufficient depletion of the first epitaxial layer 11 when the doping concentration of the second conductive type column 5 fluctuates, thereby ensuring that even when the doping concentration of the second conductive type column 5 is at the lowest value of the fluctuation, the first epitaxial layer 11 can still be fully depleted, thereby ensuring that the breakdown voltage reaches the required value; in addition, the first bottom doping region 12 can be formed at the bottom of the second conductive type column 5 by self-alignment through ion implantation, so it has the advantage of simple process.

[0095] The first embodiment of the present invention can easily achieve sufficient depletion of the first epitaxial layer 11 by setting the first bottom doping region 12. At the same time, in order to avoid the device punch-through problem caused by the complete depletion of the first epitaxial layer 11, the first embodiment of the present invention can also add a buffer layer 13 with a doping concentration greater than that of the first epitaxial layer 11 at the bottom of the first epitaxial layer 11. The buffer layer 13 can prevent the device from punching through, and at the same time, it is beneficial to the setting of the first epitaxial layer 11 and the first bottom doping region 12, making the device process simpler.

[0096] The following takes a 1200V super junction IGBT as an example to further illustrate the relevant parameters of the device of the first embodiment of the present invention:

[0097] The thickness of the second epitaxial layer 2, that is, the length of the drift region composed of the second epitaxial layer 2, is 50 microns, and the corresponding doping concentration is 2Ω*cm (resistivity is used here to represent the doping concentration). The lateral depletion of the first conductive type column and the second conductive type column 5 formed by the second epitaxial layer 2 is used to withstand approximately half of the breakdown voltage.

[0098] The other half is realized by the first epitaxial layer 11; the doping concentration of the first epitaxial layer 11 is 110Ω*cm, and the corresponding thickness is 55μm.

[0099] Because the doping concentration of the second conductive type column 5 has certain fluctuations, this will result in the bottom of the second conductive type column 5 being lower than the ideal value, such as Figure 2B The electric field strength at position A is relatively low; this will weaken the depletion capability of the drift region formed by the first epitaxial layer 11, resulting in a decrease in breakdown voltage. To solve this problem, a P-type ion implantation is performed at the bottom of the second conductive type column 5. Its purpose is to ensure that the first epitaxial layer 11 can be fully depleted even when the doping concentration of the second conductive type column 5 changes, thereby ensuring that the device has sufficient withstand voltage. The injection energy of the first bottom doped region 12 is usually between 50 and 200 keV, and the implanted dose is usually 5e11 / cm 2 to 2e12 / cm 2 The first bottom doped region 12 and the second conductive type column 5 form a P-type whole. The location of the P-type ion implantation in the body must be at the location of the first epitaxial layer 11, such as Figure 2A As shown. Due to the huge difference in doping concentration between the first epitaxial layer 11 and the second epitaxial layer 2, the width of the P-type region formed in the body by the first bottom doping region 12 is increased, as shown in FIG. Figure 2B shown.

[0100] In the existing SJ-IGBT, the drift region is directly composed of the second epitaxial layer 2 with a high doping concentration, so there is no need to worry about the problem of punch-through. However, in the first embodiment of the present invention, the doping concentration of the first epitaxial layer 11 is low. If it is depleted, the device is prone to punch-through. In order to solve this problem, a buffer layer 13 can be added between the first epitaxial layer 11 and the collector region 1. The first epitaxial layer 1 is usually formed on the surface of a semiconductor substrate such as a silicon wafer. This buffer layer 13 is usually formed by back ion implantation after the silicon wafer is thinned. The common impurity implanted by ion implantation in the buffer layer 13 is phosphorus. The implantation energy is usually between 100keV and 2MeV, and the implantation dose is usually 1e12 / cm 2 ~3e13 / cm 2 In order to reduce the spike during the turn-off process, proton implantation can also be used, which can implant deeper into the junction.

[0101] In the first embodiment of the present invention, the pitch of the superjunction structure is primarily limited by the second conductivity type pillars 5 and the distance between them. Taking a typical silicon 1200V superjunction IGBT (SJ-IGBT) as an example, the width of the P-pillars (i.e., the second conductivity type pillars 5) is typically 4μm, the distance between them is 5μm, and the depth of the P-pillars is 45μm; the corresponding pitch is 9μm.

[0102] In the first embodiment of the present invention, the trench gate pitch is equal to that of the superjunction structure, and therefore also 9μm. In other embodiments, the trench gate pitch can also be 3μm, 1.8μm, or 2μm. The flexibility of the trench gate pitch is not lost due to the fixed pitch of the P-pillar. This is different from an SJ MOSFET because when an SJ-IGBT is turned on, electrons and holes are injected into the entire drift region.

[0103] like Figure 3 FIG. 1 is a schematic structural diagram of an IGBT device according to a second embodiment of the present invention. The difference between the IGBT device according to the second embodiment of the present invention and the IGBT device according to the first embodiment of the present invention is that the IGBT device according to the second embodiment of the present invention further includes:

[0104] One or more emitter trenches are disposed between at least some of the gate trenches.

[0105] A second dielectric layer 3a is formed on the inner surface of the emitter trench and is filled with an emitter conductive material layer 4a. The emitter conductive material layer 4a is connected to the emitter through a corresponding through hole 8 at the top.

[0106] The emitter trench and the gate trench have the same process structure and are formed simultaneously. The second dielectric layer 3 a and the gate dielectric layer 3 have the same process structure and are formed simultaneously. The emitter conductive material layer 4 a has the same process structure and is formed simultaneously.

[0107] The difference between the gate conductive material layer 4 and the emitter conductive material 4a is that no emitter region 7 is formed on the side of the emitter conductive material layer 4a, and the top of the emitter conductive material layer 4a is connected to the emitter. In this way, no conductive channel is formed in the channel region 6 on the side of the emitter trench.

[0108] At the same time, the top of the emitter conductive material layer 4a is connected to the emitter, which can reduce Cgc. Cgc is the parasitic capacitance between the gate and the collector. Cgc is related to the depletion area of ​​the gate conductive material layer 4 in the drift region. After adding the emitter conductive material layer 4a, the depletion area of ​​the gate conductive material layer 4 in the drift region is reduced, so Cgc can be reduced. The depletion of the drift region by the emitter conductive material layer 4a will form Cec. Cgc is the parasitic capacitance between the emitter and the collector. Since Cgc, as the Miller capacitance of the device, has a significant impact on the switching speed, the switching speed of the device is improved by reducing Cgc.

[0109] In addition, if there are two or more emitter trenches between two adjacent gate trenches, the channel region 6 between the emitter trenches will not be connected to the emitter or other electrodes, so it is in a floating state. Figure 3 In the figure, the floating channel region is marked separately with a marker 6a. The floating channel region 6a increases the carrier injection storage effect, which reduces the on-state voltage, but correspondingly increases the turn-off loss. The floating channel region 6a needs to be set according to actual needs.

[0110] like Figure 4 FIG. 1 is a schematic structural diagram of an IGBT device according to a third embodiment of the present invention. The difference between the IGBT device according to the third embodiment of the present invention and the IGBT device according to the second embodiment of the present invention is that the IGBT device according to the third embodiment of the present invention further includes:

[0111] The front structure further includes a heavily doped carrier storage layer 16 of the first conductivity type, which is disposed between the channel region 6 and the first top doped region 15 .

[0112] The carrier storage layer 16 can be implemented by ion implantation. In some preferred embodiments, the first top doped region 15 is implemented by ion implantation. The specific implementation process can be carried out using any existing disclosed process.

[0113] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A super junction IGBT device, characterized in that: include: a first epitaxial layer doped with a first conductivity type and a second epitaxial layer doped with the first conductivity type formed on a top surface of the first epitaxial layer; A plurality of second conductivity type pillars are formed in the second epitaxial layer, and the second conductivity type pillars are formed by the second epitaxial layer between the second conductivity type pillars; the first conductivity type pillars and the second conductivity type pillars are alternately arranged to form a super junction structure; The doping concentration of the second conductive type column matches the doping concentration of the second epitaxial layer so that the charges of the first conductive type column and the second conductive type column are matched, and when the device is reverse biased, the super junction structure is depleted and forms a top voltage-resistant layer; The bottom surface of the second conductive type column is located below the top surface of the first epitaxial layer, and a first bottom doped region of the second conductive type is formed in the first epitaxial layer below the bottom surface of each second conductive type column; The first bottom doped region and the extension portion of the second conductive type column extending into the first epitaxial layer are in contact and overlapped to form a second bottom doped region. When the device is reverse biased, each of the second bottom doped regions depletes the first epitaxial layer and forms a bottom voltage-resistant layer. The doping concentration of the second conductive type column has fluctuations caused by the process. The doping concentration of the first bottom doped region satisfies the requirement of sufficient depletion of the first epitaxial layer for voltage resistance when the device is reverse biased when the doping concentration of the second conductive type column is at the lowest value of the fluctuation. The front structure of the super junction IGBT device includes a channel region doped with a second conductivity type; A first top doped region of the first conductive type is provided between the channel region and the second conductive type column, wherein the first top doped region separates the second conductive type column from the channel region and makes the second conductive type column present a floating structure; The back side structure of the super junction IGBT device is formed on the back side of the first epitaxial layer; The component structure of the second conductive type column includes a third epitaxial layer of the second conductive type filled in the super junction trench; A bottom surface of the second conductive type pillar is determined by a bottom surface of the super junction trench, and the bottom surface of the super junction trench is located below a top surface of the first epitaxial layer; The first bottom doped region is an ion implantation region of the second conductivity type formed in a self-aligned manner at the bottom of the super junction trench; The resistivity of the first epitaxial layer is 5 times or more than the resistivity of the second epitaxial layer.

2. The super junction IGBT device according to claim 1, wherein: The ion implantation energy of the first bottom doping region is 50keV to 200keV, and the implantation dose is 5e11cm -2 ~2e12cm -2 .

3. The super junction IGBT device according to claim 1, wherein: The resistivity of the first epitaxial layer is 10 times or more than the resistivity of the second epitaxial layer.

4. The super junction IGBT device according to claim 1, wherein: The front structure further includes: a gate structure, an emitter region heavily doped with a first conductivity type, an interlayer film, a through hole passing through the interlayer film, and an emitter and a gate formed by patterning the front metal layer; The gate structure includes a gate dielectric layer and a gate conductive material layer; The emitter region is formed on the surface of the channel region and is self-aligned with the gate structure; The emitter region is connected to the emitter electrode via the corresponding through hole at the top; The gate conductive material layer is connected to the gate through the corresponding through hole on the top.

5. The super junction IGBT device according to claim 4, wherein: The through hole corresponding to the emitter region also passes through the emitter region and contacts the channel region; a channel lead-out region heavily doped with a second conductive type is also formed at the bottom of the through hole corresponding to the emitter region, and the channel lead-out region forms an ohmic contact with the through hole at the top, and the channel region contacts the through hole through the channel lead-out region.

6. The super junction IGBT device according to claim 4, wherein: The gate structure adopts a trench gate, the trench gate further includes a gate trench, the gate dielectric layer is formed on the inner surface of the gate trench, and the gate conductive material layer fills the gate trench; Components of the drift region include the first top doped region at the bottom of the channel region, the first conductive type column, and the first epitaxial layer; The gate trench passes through the channel region longitudinally, and the side surface of the channel region covered by the side surface of the trench gate is used to form a conductive channel connecting the emitter region and the drift region.

7. The super junction IGBT device according to claim 4, wherein: The gate structure adopts a planar gate; A fourth epitaxial layer doped with a first conductivity type is formed on the top of the super junction structure, the first top doped region is composed of the fourth epitaxial layer, and the channel region is formed in a selected region of the fourth epitaxial layer; Components of the drift region include the first top doped region at the bottom of the channel region, the fourth epitaxial layer between the channel regions, and the first conductive type pillar and the first epitaxial layer at the bottom; The planar gate is formed on the front side of the channel region and extends to the surface of the drift region. The surface of the channel region covered by the front side of the planar gate is used to form a conductive channel connecting the emitter region and the drift region.

8. The super junction IGBT device according to claim 6, wherein: The stepping of the super junction structure is the sum of the width of the first conductive type column and the width of the second conductive type column; The step of the trench gate is the sum of the width of the gate trench and the spacing between the gate trenches; The stepping of the trench gate is independent of the stepping of the super junction structure, so that the stepping of the trench gate is smaller than, equal to, or larger than the stepping of the super junction structure.

9. The super junction IGBT device according to claim 8, wherein: One or more emitter trenches are further provided between at least some of the gate trenches; A second dielectric layer is formed on the inner surface of the emitter trench and is filled with an emitter conductive material layer. The emitter conductive material layer is connected to the emitter through the corresponding through hole at the top.

10. The super junction IGBT device according to claim 4, wherein: The front structure further includes: a carrier storage layer heavily doped with the first conductivity type, wherein the carrier storage layer is arranged between the channel region and the first top doped region.

11. The super junction IGBT device according to claim 1, wherein: The back structure includes: A collector region heavily doped with a second conductivity type; A back metal layer is formed on the back side of the collector region, and a collector electrode is led out from the back metal layer.

12. The super junction IGBT device according to claim 11, wherein: The back structure includes: A buffer layer doped with a first conductive type, the buffer layer being located between a top surface of the first epitaxial layer and a top surface of the collector region, the doping concentration of the buffer layer being greater than the doping concentration of the first epitaxial layer, preventing the device from being punched through when the first epitaxial layer is completely depleted when the device is reverse biased.

13. The super junction IGBT device according to claim 12, wherein: The buffer layer is formed on the back side of the first epitaxial layer by back ion implantation. The back ion implantation energy of the buffer layer is 100keV to 2MeV, and the implantation dose is 1e12cm -2 ~3e13cm -2 .

14. The super junction IGBT device according to claim 12, wherein: The super junction IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the super junction IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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