Precise masking and adjustment of on-chip timers in low-power states

Abstract

The present invention relates to an integrated circuit (IC) comprising a first circuit including a timer for receiving an adjustable clock signal. In response to leaving a non-operating power state to enter a power state in which the adjustable clock has a lower frequency than a reference clock, the first circuit adjusts the frequency of the adjustable clock to a higher frequency than the lower frequency, and then receives an elapsed time associated with the non-operating power state and starts the timer using the adjusted timer value.

Description

Background Art

[0001] Computer systems utilize a variety of peripheral components for different input / output and communication functions. A system on a chip (SOC) combines data processing circuitry such as a central processing unit (CPU) core and a graphics processing unit (GPU) with peripheral controllers and memory interfaces on a single integrated circuit chip and is well suited for portable, battery-powered operation. For example, an SOC may incorporate a display controller, an image signal processor (ISP), and other peripheral controllers on the SOC to enable input and output of information to and from the computer system. In such large and complex SOCs, devices typically transfer data between resources such as memory by routing accesses throughout a large on-chip routing circuitry, or "data fabric."

[0002] The diversity of circuits on a typical SOC poses a problem for implementing power-saving modes. Operational and power-saving modes are used in many parts of a computer system, where different modes provide different operating capabilities, such as the processing power for a processor core, or the signaling data rate for a communication bus, or different power-saving levels when not in use. Both operational and non-operational power-saving modes are referred to herein as "power states." A common standard for managing such power modes is the Advanced Configuration and Power Interface (ACPI), which is a power management and configuration model for computers such as personal computers (PCs) and servers. ACPI allows a computer operating system to control the amount of power consumed by each device by changing the device's operating mode from a limited set of modes. For example, such changes can include changing the device's clock speed to a higher or lower frequency or placing the device in standby or power-off mode. Although ACPI is an industry standard that provides a set of general controls exposed to the operating system, it does not include specific features intended to optimize the power consumption or performance of a particular data processing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 illustrates, in block diagram form, an accelerated processing unit (APU) and memory system known in accordance with some embodiments;

[0004] Figure 2 A portion of an APU is illustrated in block diagram form, showing elements for managing power state transitions of a circuit with a timer according to an exemplary embodiment;

[0005] Figure 3 shows a flow chart of a process for transitioning to a non-operational power state according to some embodiments;

[0006] Figure 4 shows a flow chart of a process for transitioning out of a non-operational power state according to some embodiments; and

[0007] Figure 5 A timing diagram is shown of signals involved in backing up and restoring timer values for non-operational power states according to some embodiments.

[0008] In the following description, the same reference numerals are used in different drawings to indicate similar or identical items. Unless otherwise specified, the word "couple" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also means an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0009] An integrated circuit includes a power state controller and a first circuit. The first circuit includes a timer that receives an adjustable clock signal and has a non-operational power state in which the adjustable clock signal is lost. In response to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than a reference clock, the first circuit adjusts the frequency of the adjustable clock to a higher frequency than the lower frequency, and then receives an adjusted timer value associated with the non-operational power state and starts a timer using the adjusted timer value.

[0010] A method includes causing a first circuit to enter a non-operational power state in which an adjustable clock signal for the first circuit is gated on or off. The method includes causing the first circuit to exit the non-operational power state and resuming a timer with an adjusted timer value. When the first circuit exits the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than a reference clock, the method first adjusts the adjustable clock to a higher frequency than the lower frequency and then receives an elapsed time value associated with the non-operational power state.

[0011] A data processing system includes a plurality of processor cores, a first circuit coupled to the plurality of processor cores, and a power state controller. The first circuit includes a timer that receives an adjustable clock signal and has a non-operational power state in which the adjustable clock signal is lost. In response to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than a reference clock, the first circuit adjusts the frequency of the adjustable clock to a higher frequency than the lower frequency, and then receives an elapsed time value associated with the non-operational power state and starts the timer using the adjusted timer value.

[0012] Figure 1An accelerated processing unit (APU) 100 and a memory system 130 are shown in block diagram form according to some embodiments. The APU 100 is an integrated circuit suitable for use as a processor in a host data processing system and generally includes a central processing unit (CPU) core complex 110, a graphics core 120, a set of display engines 122, a data fabric 125, a memory management hub 140, a set of peripheral controllers 160, a set of peripheral bus controllers 170 and a system management unit (SMU) 180, and a system power state controller 182.

[0013] The CPU core complex 110 includes a CPU core 112 and a CPU core 114. In this example, the CPU core complex 110 includes two CPU cores, but in other embodiments, the CPU core complex 110 may include any number of CPU cores. Each of the CPU cores 112 and 114 is bidirectionally connected to a system management network (SMN) (which forms a control fabric) and a data fabric 125, and can provide memory access requests to the data fabric 125. Each of the CPU cores 112 and 114 can be a unitary core, or can be a core complex with two or more unitary cores that share certain resources, such as cache.

[0014] The graphics core 120 is a high-performance graphics processing unit (GPU) that can perform graphics operations such as vertex processing, fragment processing, shading, texture blending, etc. in a highly integrated and parallel manner. The graphics core 120 is bidirectionally connected to the SMN and the data texture 125 and can provide memory access requests to the data texture 125. In this regard, the APU 100 can support a unified memory architecture in which the CPU core complex 110 and the graphics core 120 share the same memory space, or a memory architecture in which the CPU core complex 110 and the graphics core 120 share a portion of the memory space while the graphics core 120 also uses private graphics memory that the CPU core complex 110 cannot access.

[0015] Display engine 122 renders and rasterizes objects generated by graphics core 120 for display on a monitor. Graphics core 120 and display engine 122 are bidirectionally connected to a common memory management hub 140 via data texture 125 for unified translation into appropriate addresses in memory system 130.

[0016] The data fabric 125 includes a crossbar switch for routing memory access requests and memory responses between any memory access agents and the memory management hub 140. The data fabric also includes a system memory map defined by the basic input / output system (BIOS) for determining the destination of memory accesses based on the system configuration, and a buffer for each virtual connection.

[0017] Peripheral controllers 160 include a Universal Serial Bus (USB) controller 162 and a Serial Advanced Technology Attachment (SATA) interface controller 164, each of which is bidirectionally connected to a system hub 166 and the SMN bus. These two controllers are merely examples of peripheral controllers that may be used with APU 100.

[0018] Peripheral bus controller 170 includes a system controller or "South Bridge" (SB) 172 and a Peripheral Component Interconnect Express (PCIe) controller 174, each of which is bidirectionally connected to an input / output (I / O) hub 176 and the SMN bus. I / O hub 176 is also bidirectionally connected to system hub 166 and data fabric 125. Thus, for example, a CPU core can program registers in USB controller 162, SATA interface controller 164, SB 172, or PCIe controller 174 via accesses routed through I / O hub 176 via data fabric 125. Software and firmware for APU 100 are stored in a system data drive or system BIOS memory (not shown), which can be any of a variety of non-volatile memory types, such as read-only memory (ROM), flash electrically erasable programmable ROM (EEPROM), etc. Typically, BIOS memory is accessed via the PCIe bus, and the system data drive is accessed via the SATA interface.

[0019] SMU 180 is a local controller that controls the operation of resources on APU 100 and synchronizes communications between these resources. SMU 180 manages the power-up sequencing of the various processors on APU 100 and controls a number of off-chip devices via reset, enable, and other signals. SMU 180 includes one or more clock sources (not shown), such as a phase-locked loop (PLL), to provide clock signals to each component of APU 100. SMU 180 also manages the ACPI power states of the various processors and other functional blocks and can receive measured power consumption values from CPU cores 112 and 114 and graphics core 120 to determine the appropriate power state.

[0020] System power state controller 182 is bidirectionally connected to the SMN for communicating with local power state controllers in various parts of APU 200 to control the power states of peripheral circuits in APU 200 independently of the ACPI power states controlled by SMU 180. The power states controlled by system power state controller 182 differ from the various ACPI processor states and performance states defined in the ACPI specification in that they are additional power states that are not typically exposed to the operating system or, under the ACPI specification, can be controlled by its operating system-directed configuration and power management (OSPM) system. The power states controlled by local power state controller 270 include an idle state and a "deep idle" state (which includes powering off designated circuit blocks), which are coordinated by system power state controller 182 with the power states of other blocks in APU 100, as described further below.

[0021] In this embodiment, a memory management hub 140 and its associated physical interfaces (PHYs) 151 and 152 are integrated with the APU 100. The memory management hub 140 includes memory channels 141 and 142 and a power engine 149. The memory channel 141 includes a host interface 145, a memory channel controller 143, and a physical interface 147. The host interface 145 bidirectionally connects the memory channel controller 143 to the data fabric 125 via a serial presence detect link (SDP). The physical interface 147 bidirectionally connects the memory channel controller 143 to the PHY 151 and conforms to the DDR PHY Interface (DFI) specification for configuring the PHY 151. The memory channel 142 includes a host interface 146, a memory channel controller 144, and a physical interface 148. The host interface 146 bidirectionally connects the memory channel controller 144 to the data fabric 125 via another SDP. The physical interface 148 bidirectionally connects the memory channel controller 144 to the PHY 152 and conforms to the DFI specification. Power engine 149 is bidirectionally connected to SMU 180 via the SMN bus, to PHY 151 and PHY 152 via Advanced Peripheral Bus (APB) interface 254, and also bidirectionally connected to memory channel controllers 143 and 144. PHY 151 has a bidirectional connection to memory channel 131. PHY 152 has a bidirectional connection to memory channel 133.

[0022] The memory management hub 140 is an instantiation of a memory controller having two memory channel controllers and uses a shared power engine 149 to control the operation of both memory channel controller 143 and memory channel controller 144 in a manner further described below. Each of the memory channels 141 and 142 can be connected to existing technology DDR memories such as fifth generation DDR (DDR5), fourth generation DDR (DDR4), low power DDR4 (LPDDR4), fifth generation graphics DDR (GDDR5), and high bandwidth memory (HBM), and can be adapted for future memory technologies. These memories provide high bus bandwidth and high-speed operation. At the same time, they also provide a low power mode to save power for battery-powered applications such as laptops, and also provide built-in thermal monitoring.

[0023] The various processor cores, controllers, and interfaces may include an interrupt controller, such as an Advanced Programmable Interrupt Controller (APIC). The APIC is a family of interrupt controllers that can be used in multiprocessor systems. It is one of several architectural designs designed to address the problem of interrupt routing efficiency in multiprocessor computer systems. The APIC is a split architectural design in which the Local Component APIC (LAPIC) is typically integrated into the processor itself, and an optional I / O APIC is located on the system bus.

[0024] Memory system 130 includes memory channel 131 and memory channel 133. Memory channel 131 includes a set of dual inline memory modules (DIMMs), including representative DIMMs 134, 136, and 138, connected to DDRx bus 132, which correspond to individual memory ranks in this example. Similarly, memory channel 133 includes a set of DIMMs, including representative DIMMs 135, 137, and 139, connected to DDRx bus 129.

[0025] The APU 100 operates as the central processing unit (CPU) of the host data processing system and provides various buses and interfaces available in modern computer systems. These interfaces include two double data rate (DDRx) memory channels, a PCIe root complex for connecting to a PCIe link, a USB controller for connecting to a USB network, and an interface to a SATA mass storage device.

[0026] APU 100 also implements various system monitoring and power conservation functions. Specifically, one system monitoring function is thermal monitoring. For example, if APU 100 becomes hot, SMU 180 can reduce the frequency and voltage of CPU cores 112 and 114 and / or graphics core 120. If APU 100 becomes overheated, it can be completely shut down. SMU 180 can also receive thermal events from external sensors via the SMN bus and, in response, reduce clock frequency and / or power supply voltage.

[0027] Figure 2 A portion of an APU 200 is shown in block diagram form, illustrating elements for managing power state transitions of circuits having timers, according to an exemplary embodiment. The depicted portion of the APU 200 includes a central processing unit (CPU) core complex 110, a data fabric 125, an SMU 180, an SMN, a system power state controller 182, an I / O hub 176, a memory channel controller 144, and blocks indicating other peripherals 240 that also include timers suitable for use with the timer synchronization techniques described herein.

[0028] CPU cores 112 and 114 are each bidirectionally connected to data fabric 125. CPU core complex 110 is also bidirectionally connected to the SMN, typically at the individual core level. As indicated by the ellipsis, CPU core complex 110 typically includes more than two cores. In some embodiments, other types of processor cores are also employed, such as GPU cores and artificial intelligence or neural network processing cores. In some embodiments, the processor cores include timers, such as APIC timers, suitable for use with the timer synchronization techniques described herein.

[0029] The system power state controller 182 is bidirectionally connected to the SMN for communicating with local power state controllers in various parts of the APU 200 to control the power state of peripheral circuits in the APU 200 independently of the ACPI power states controlled by the SMU 180. At least some of these power state transitions are transparent to the operating system and have low exit latencies, so that they can be frequently employed based on the system workload to save power without a large impact on system performance. For example, the two non-operating power states controlled by the system power state controller 182 have exit latencies of 350μs and 1ms, respectively, allowing them to be used at a much higher frequency than ACPI power states (which typically have higher exit latencies) or other power states with higher exit latencies. The system power state controller 182 may also include direct sideband connections to specific circuits (such as local APIC timers). Although Figure 2Only certain system peripherals are shown, but various other system blocks also include local power state controllers configured to control entry into and exit from power states, including saving and restoring configuration and state data for their respective system blocks in response to commands from system power state controller 182. System power state controller 182 provides two ways to save and restore configuration and state data, either by saving to system DRAM or by saving to on-chip SRAM 204.

[0030] On-chip SRAM 204 has a bidirectional connection to the SMN for receiving configuration and state data to be stored during low-power states from various circuits in APU 200. Although SRAM is used in this embodiment, any suitable form of RAM operating at speeds on the order of SRAM speeds may be used to store configuration and state data.

[0031] A reference clock 186 ("REFCLK") provides a clock signal to the system power state controller 182 and continues to operate during designated non-operational power states. Preferably, REFCLK 186 is a crystal oscillator, non-spread spectrum clock circuit that provides a clock signal at a relatively high frequency compared to the time stamp counter (TSC) clock typically used for coarse timing of system events. This clock signal is used as the basis for generating a base timer rate for the APIC timer of the APU 200. In each particular peripheral component, the base timer rate can typically be further modified by dividing down, depending on the operating power state of the peripheral component. Although an APIC timer is described in this embodiment, other types of timers are used in other embodiments. Although the term APIC generally refers to a peripheral controller that includes a timer, an APIC timer may be employed in various embodiments that do not have a complete APIC peripheral controller and only include a subset of features related to the APIC timer.

[0032] The data fabric 125 includes a fabric controller 220, a local APIC timer 230, and a data fabric phase-locked loop ("DF PLL") 236. Other parts of the data fabric 125, such as ports and a crossbar router, are not shown to focus on relevant features. However, the data fabric generally includes multiple master ports for generating memory access requests on behalf of requesters connected to the data fabric 125, multiple slave ports for fulfilling such requests from memory devices connected to the data fabric 125, and a crossbar router that forms virtual connections between the master ports and the slave ports based on the destination address of the request. The fabric controller 220 is bidirectionally connected to the SMN and to various control circuits used to control and configure the data fabric, including the local APIC timer 230 and the DF PLL 236. The local APIC timer 230 includes a counter 234 and a cross-domain synchronization circuit 232 ("SYNC"). The counter 234 is connected to the DF PLL 236 and uses the DF PLL as the clock source on which the counter operates. The DF PLL 236 is an adjustable PLL that supplies an adjustable clock signal to at least the local APIC timer 230, and preferably provides clock signals to all data textures 125. The cross-domain synchronization circuit 232 is connected to the shadow timer 184 and the counter 234 of the system power state controller 182. The cross-domain synchronization circuit 232 is preferably configured as a synchronizer that includes a plurality of synchronization flip-flops for preventing metastable states from occurring across clock domains, and control logic operable to synchronize the circuit with the system power state controller 182 during certain clock synchronization procedures, as further described below.

[0033] The texture controller 220 operates in response to commands from the system power state controller 182 to place the data texture 125 into selected operational and non-operational power states. In some embodiments, the texture controller 220 monitors traffic on the data texture 125 and, based on detecting conditions where the data texture 125 may be idle, places the data texture 125 into a selected power state, such as a light idle state. For example, in some embodiments, a light idle state is permitted where certain ports are disconnected while other ports are enabled to "stuck" traffic by allowing traffic to accumulate in buffers. In some designated non-operational power states, the DF PLL 236 signal is lost because it is gated or the PLL is powered down. In some designated non-operational power states, entire peripheral circuits or intellectual property (IP) blocks (such as the texture controller) are powered down. The APIC timer 230 can be backed up, tracked, and restored with adjusted timer values during transitions to and from non-operational power states indicated by the system power state controller 182. During these transitions, the system power state controller 182 stores the timer value from the APIC timer 230 in a memory such as on-chip SRAM 204, starts the shadow timer 184 to measure the time associated with the designated non-operating power state, and restores the APIC timer 320 with the adjusted timer value after the designated non-operating power state. Operational power states include states in which the frequency of the DF PLL 236 is equal to or higher than the REFCLK 186 and the clock signal edges of the DF PLL 236 are synchronized with the clock edges of the REFCLK. Such states may be referred to as "low error" states because the error in saving and restoring the timer value of the local APIC timer 230 is low. Other power states include operational power states and idle power states in which the frequency of the DF PLL 236 is lower than the REFCLK 186. While the DF PLL 236 frequency provides sufficient granularity for timer accuracy in some of these states, these power states are referred to herein as "high error" power states because potentially high accumulated errors of unknown magnitude may result when saving and restoring timer values from these states. This error is due to the slower clock signal of DF PLL 236 and its unsynchronized relationship to the clock signal edges of REFCLK 186. Importantly, such errors are incremental, so they can accumulate over time and ultimately cause unpredictable operational issues, depending on the specific use of the timer. The more frequently non-operating power states are used, the larger such incremental errors become. In this embodiment, the depicted local APIC timer 230 and shadow timer 184 are used in conjunction with a process to mitigate incremental errors.

[0034] The I / O hub 176 and other peripheral circuits 240 such as memory controllers, graphics processing units (GPUs), and deep learning processing units (DLPs) may also include timers constructed similarly to the local APIC timer 230 including cross-domain synchronization circuitry 232. The timer tracking and adjustment processes herein may be used with any suitable timer that is part of a circuit having a non-operational power state in which power or a clock signal to the timer is lost.

[0035] Figure 3 A flowchart 300 is shown of a process for transitioning to a non-operational power state, according to some embodiments. The process is suitable for use with the APU 100 and APU 200 described above, or with another suitable integrated circuit including peripheral circuitry with a timer, and is executed under the control of the system power state controller 182 and a local power state controller for the IP block in question (such as the texture controller 220). The process is initiated at block 302 by the system power state controller, which typically initiates a transition to a non-operational power state in response to detecting a condition that allows a circuit or intellectual property (IP) block within the APU 200 to enter an idle state or non-operational power state. Typically, the entire IP block in question (such as the data texture 125) is placed in a non-operational power state. However, in some embodiments, "circuitry" may refer to only a portion of an IP block.

[0036] As shown in block 304, for each IP block requiring a timer save and restore sequence, the process performs blocks 306, 308, 310, 312, and 314. Various other steps (not shown) are included, such as saving state data and clearing buffers, depending on the specific IP block involved.

[0037] At block 306, the process determines whether the IP block's PLL is already in a low-error state, in which the PLL operates at the REFCLK frequency or another suitable frequency so that synchronization with REFCLK 186 can be performed with low error. For example, if a particular IP block is in a low-power state (such as a light idle state with a reduced clock frequency relative to the clock frequency of REFCLK 186), then at block 310, the reduced frequency is considered a high-error state. For a low-error state, the process proceeds to block 310. For a high-error state, the process proceeds to block 308, where the process places the IP block's PLL in a low-error state by adjusting the circuit PLL frequency. From block 308, the process proceeds to block 310.

[0038] At block 310, the process receives a timer value from the circuit under conversion at the system power state controller 182 and stores the timer value in memory. In some embodiments, on-chip memory such as SRAM memory 204 ( Figure 2 ), or local memory within the system power state controller 182 may be used.

[0039] Next, at block 312, the process starts a shadow timer 184 operating on the REFCLK signal to measure the time associated with the designated non-operating power state. At block 312, the process also starts a wakeup timer for the earliest desired wakeup time among the IP blocks being transitioned to the non-operating power state. This wakeup time is adjusted to account for wakeup latency. Next, at block 314, the process causes the IP blocks for which the circuit is transitioning to enter a non-operating power state in which the circuit's PLL or adjustable clock is gated or powered down.

[0040] Figure 3 The process is used for each IP block that enters a non-operational power state and has a timer configured for backup and recovery. Typically, the timers that this process is suitable for use include all APIC timers or other similar timers in the IP block being transitioned to a non-operational power state. Figure 2 ), the timer backup process is preferably performed by dedicated sideband signaling for each IP block rather than via the SMN in order to achieve predictable delays in both saving and restoring timer values.

[0041] Figure 4 A flowchart 400 is shown of a process for transitioning out of a non-operating power state according to some embodiments. The process is suitable for use with APU 200 and a Figure 3 This can be used with a conversion process or other system designs that use an adjustable clock with a local timer that can benefit from a more accurate backup and recovery process.

[0042] At block 402, the process initiates an exit from a non-operational power state for circuitry of an IP block for which at least one timer value has been saved and shadowed with a shadow timer 184. As shown in block 404, the exit process is typically initiated with a timer wake-up event on the shadow timer 184, which triggers a power state change and clock recovery. However, other triggering events, such as the system power state controller 182 detecting a condition requiring an exit from a low-power state, may also trigger a power state change and clock recovery.

[0043] In response to the trigger at block 404, at block 406, the system power state controller 182 retrieves the timer value for the resuming timer from memory. The system power state controller 182 may also initiate other power state transition circuits in the resuming IP block in parallel with the depicted process. For example, depending on the specific circuitry exiting the non-operational power state, other circuits are powered on, initialized, and loaded with state data, such as the contents of queues and registers.

[0044] At block 408, the process places the circuit's PLL or other adjustable clock for the first circuit being recovered into a low error state in which the clock can be accurately synchronized with the REFCLK signal. Then, at block 410, the elapsed time indicative of the time tracked by the shadow timer is read from the power state controller.

[0045] At block 412, the process includes synchronizing the first circuit with the power state controller using the cross-domain synchronization circuit. In some embodiments, block 412 may occur simultaneously with or out of sequence with block 410. Preferably, synchronizing the first circuit with the system power state controller 182 includes sending a timer read signal to the system power state controller 182 via the cross-domain synchronization circuit 232 and receiving an acknowledgement signal from the system power state controller 182 via the cross-domain synchronization circuit 232.

[0046] At block 414, the process calculates an adjusted timer value based on calculating the elapsed time using several factors, including a synchronization time for the cross-domain synchronization circuit, a first error value associated with the delay in receiving the timer value, and a second error value associated with the delay in recovering the timer value. The first error value and the second error value are preferably estimated and combined to form a single adjustment, which is a configuration value used at the first circuit when calculating the adjusted timer value. With this design, each IP block can calculate its own adjusted timer value. Although in this embodiment, the adjusted timer value is calculated at the IP block based on the retrieved timer value, the elapsed time, and the other adjustments discussed above, the specific location where the adjusted timer value is calculated may vary. In some embodiments, the adjusted timer value is calculated at the system power state controller 182.

[0047] At block 416, the adjusted timer value is loaded into the timer and the timer is initialized to restore the timer to a value that includes the period of the shadow timing during the non-operating power state. Preferably, this step is performed immediately after the synchronization at block 412 so that the delay associated with loading the timer is predictable.

[0048] At block 418, the process determines whether the circuit is exiting a non-operating power state to enter an operating power state in which the adjustable clock has a lower frequency than the reference clock. If so, the process proceeds to block 420, where the process adjusts the PLL or adjustable clock to a desired lower frequency, driving the circuit at this lower frequency, in a high-error state. For example, if the circuit is exiting a non-operating power state to enter a lightly idle state or a low-power operating power state with a clock frequency lower than REFCLK, blocks 408 through 420 first adjust the adjustable clock to a frequency higher than the target lower frequency and receive the adjusted timer value, and then adjust the adjustable clock to the lower frequency. This technique increases the precision and accuracy of the timer shadowing process. The process then ends at block 422. If the circuit is not entering a high-error state at block 418, for example, if it is exiting a non-operating power state to enter an operating power state at a frequency where the PLL is in a low-error state, the process proceeds from block 418 to block 42241.

[0049] Figure 5 A timing diagram 500 is shown of signals involved in backing up and restoring timer values for a non-operational power state, according to some embodiments. Diagram 500 shows a "CPU Wake" signal, a "Shadow Timer Wake" signal, a "Timer Set" signal, a "Timer Read" signal, a "Timer Acknowledge" signal, an "APIC Timer [n]" signal, an "APIC Snapshot [n]" signal, a "Wake Time" signal, a "Shadow Timer" value, an "Elapsed Time" signal, a "DRAM Value [n]" signal, and a "Voltage Rail" supply voltage. The non-operational power state depicted in diagram 500 is entered when a host system, such as an APU 200, is in a power state, such as the ACPI "PC6" (package C6) idle state. In prior art systems, the PC6 idle state would not allow the APIC timer to power down because the exit from PC6 is triggered by the APIC timer. Using the techniques herein, by placing selected IP blocks in a non-operational power state during PC6 and exiting that non-operational power state at the appropriate time when the system exits the PC6 state, improved exit latency allows for greater power savings.

[0050] At block 502, upon determining that one or more IP blocks including timers are to enter a non-operational power state, the system power state controller 182 causes a snapshot timer value for each of the number "n" APIC timers to be stored in memory, as indicated by the APIC snapshot [n] signal having a value of "FC" being stored in a memory location indicated as DRAM value [n] at block 504. The system power state controller 182 also subtracts a programmable wake-up time offset from the earliest wake-up time of all APIC timers to account for power-up delays. This wake-up time value (labeled "EA" on the wake-up time signal) provides the wake-up time for the shadow timer 184. Also at this point, as indicated by block 502, the timer set signal starts the shadow timer 184.

[0051] The voltage rail then transitions from the ON state to the OFF state, shutting off the voltage supply to the associated IP blocks. (Additional signaling is required for each of the involved IP blocks to enter a non-operational power state, but such signaling is not depicted here to focus on the timer backup process.) At this point, the IP blocks are in a non-operational power state, as indicated by the shaded areas associated with the IP block's signals, while shadow timer 184 is running.

[0052] At block 506, the value of the shadow timer 184 reaches the wakeup setting as indicated by the clock cycle labeled "EA" on the shadow timer signal. In response, the voltage supply rail changes from the OFF state to the ON state, thereby powering up the IP blocks that were powered down in the non-operating power state and restoring their PLLs.

[0053] Then, at block 508, the APIC timer snapshot is restored from memory. Upon reaching an appropriate point in the initialization process, with the IP block PLL at a low-error frequency, each IP block asserts a timer read signal through its cross-domain synchronization circuit 232. The shadow timer provides an elapsed time value to measure the time that has elapsed while the IP block's timer is inactive. As shown in block 510, the system power state controller 182 latches the elapsed time, depicted by the label "F4," onto the elapsed time signal connection to the counter 234 and asserts a timer acknowledge signal through the cross-domain synchronization circuit 232 to indicate that the elapsed time signal is valid.

[0054] Next, at block 512, each APIC timer is initialized with the adjusted timer value on the edge of the timer acknowledge signal. The APIC timer with the earliest wake-up time setting then reaches its wake-up timer value and triggers a CPU wake-up signal, as shown in block 514. In this example, the CPU wake-up signal goes to the SMU 180 to initiate an exit from a CPU low-power state (such as the PC6 idle power state). However, in other embodiments, other types of events are initiated by the timer wake-up of the IP block.

[0055] While this particular signaling and timing arrangement is depicted as an example, many other signaling and timing arrangements may be employed to implement the timer backup and recovery capabilities and procedures described herein.

[0056] Figure 2 The APU 200 or any portion thereof (such as the system power state controller 182 and the data fabric 125) can be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, the data structure can be a behavioral-level description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL, or a register transfer level (RTL) description. The description can be read by a synthesis tool, which can synthesize the description to produce a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represents the functionality of the hardware comprising the integrated circuit. The netlist can then be placed and routed to produce a data set that describes the geometry to be applied to the mask. The mask can then be used in various semiconductor manufacturing steps to produce the integrated circuit. Alternatively, the database on the computer-accessible storage medium can be a netlist (with or without a synthesis library) or a data set (as needed) or Graphics Data System (GDS) II data.

[0057] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, although APIC timers have been described, in various embodiments, various types of timers are backed up and restored. Figure 1 Any of the depicted IP blocks can support power states where local timers are backed up and restored as described herein.It is therefore intended that the appended claims cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. An integrated circuit, comprising: a first circuit including a timer that receives an adjustable clock signal, the first circuit having a non-operational power state in which the adjustable clock signal is lost, wherein, in response to leaving the non-operational power state to enter a power state in which the adjustable clock signal has a lower frequency than a reference clock signal, the first circuit adjusts the frequency of the adjustable clock signal to a frequency higher than the lower frequency, and then receives an elapsed time value associated with the non-operational power state and starts the timer using the adjusted timer value.

2. The integrated circuit of claim 1 , further comprising a power state controller including a shadow timer that receives the reference clock signal, wherein the power state controller stores a timer value from the timer in a memory, starts the shadow timer to measure the elapsed time value associated with the non-operating power state, and resumes the timer with the adjusted timer value after the non-operating power state.

3. The integrated circuit of claim 2, wherein: The first circuit includes a cross-domain synchronization circuit operable to synchronize with the power state controller prior to receiving the elapsed time value, and The first circuit is operable to, when synchronized with the power state controller, send a timer read signal to the power state controller through the cross-domain synchronization circuit and receive an acknowledgement signal from the power state controller through the cross-domain synchronization circuit.

4. The integrated circuit of claim 3 , wherein the first circuit calculates the adjusted timer value based on the timer value stored in the memory, the shadow timer, a synchronization time for the cross-domain synchronization circuit, a first error value associated with receiving the timer value, and a second error value associated with restoring the timer.

5. The integrated circuit of claim 1 , wherein the power state in which the tunable clock signal has a lower frequency than the reference clock signal is a light idle state in which the tunable clock signal is supplied to the timer but is gated by at least some of the first circuitry.

6. The integrated circuit of claim 2, further comprising: a second circuit including a second timer that receives a second tunable clock signal, the second circuit having a non-operational power state in which the second tunable clock signal is lost, and a plurality of power states in which the second tunable clock signal operates at different respective frequencies, wherein the power state controller is operable to command the second circuit to enter the non-operating power state, store a timer value from the second timer in a memory, and set a timer wake-up value for the shadow timer based on an earliest wake-up time selected from between the timer and the second timer and a non-operating power state exit delay value.

7. A method comprising: causing a first circuit to enter a non-operational power state in which an adjustable clock signal for the first circuit is gated on or powered off; causing the first circuit to leave the non-operational power state and resuming a timer with the adjusted timer value; and When the first circuit leaves the non-operational power state to enter a power state in which the adjustable clock signal has a lower frequency than a reference clock signal, the adjustable clock signal is first adjusted to a frequency higher than the lower frequency, and then an elapsed time value associated with the non-operational power state is received.

8. The method of claim 7 , wherein the power state in which the tunable clock signal has a lower frequency than the reference clock is a light idle state in which the tunable clock signal is supplied to the timer but is gated by at least a portion of the first circuit.

9. The method of claim 7 , further comprising, at a power state controller, receiving a timer value from the first circuit, storing the timer value in a memory, and starting a shadow timer operating on a reference clock signal to measure the elapsed time value associated with the non-operational power state.

10. The method according to claim 9, further comprising: prior to receiving the elapsed time value, synchronizing the first circuit with the power state controller using a cross-domain synchronization circuit; as well as When synchronizing the first circuit with the power state controller, a timer read signal is sent to the power state controller through the cross-domain synchronization circuit, and a confirmation signal is received from the power state controller through the cross-domain synchronization circuit.

11. The method of claim 7 , further comprising, when the first circuit leaves a power state in which the adjustable clock signal has a lower frequency than the reference clock signal, first adjusting the frequency of the adjustable clock signal to the frequency higher than the lower frequency, and then transmitting the timer value to a power state controller.

12. A data processing system, comprising: Multiple processor cores; and a first circuit coupled to the plurality of processor cores and including a timer that receives an tunable clock signal, the first circuit having a non-operational power state in which the tunable clock signal is lost, wherein, in response to leaving the non-operational power state to enter a power state in which the adjustable clock signal has a lower frequency than a reference clock signal, the first circuit is operable to adjust the frequency of the adjustable clock signal to a higher frequency than the lower frequency, and then receive an elapsed time value and start the timer using the adjusted timer value.

13. The data processing system of claim 12 , wherein the power state in which the tunable clock signal has a lower frequency than the reference clock signal is a light idle state, in which the tunable clock signal is supplied to the timer but is gated by at least a portion of the first circuit.

14. The data processing system according to claim 13, wherein: The first circuit includes a cross-domain synchronization circuit operable to synchronize with the power state controller prior to receiving the elapsed time value, and The first circuit is operable to, when synchronized with the power state controller, send a timer read signal to the power state controller through the cross-domain synchronization circuit and receive an acknowledgement signal from the power state controller through the cross-domain synchronization circuit.

15. The data processing system of claim 14 , wherein the first circuit calculates the adjusted timer value based on the timer value stored in a memory, the elapsed time value, a synchronization time for the cross-domain synchronization circuit, a first error value associated with receiving the timer value, and a second error value associated with resuming the timer.

16. The data processing system of claim 12 , further comprising a power state controller comprising a shadow timer that receives the reference clock signal, wherein the power state controller stores a timer value from the timer in a memory, starts the shadow timer to measure an elapsed time value associated with the non-operating power state, and resumes the timer with the adjusted timer value after the non-operating power state.

17. The data processing system of claim 16 , wherein the first circuit is operable to, upon leaving a power state in which the adjustable clock signal has a lower frequency than the reference clock signal, first adjust the frequency of the adjustable clock signal to the frequency higher than the lower frequency, and then transmit the timer value to the power state controller.

18. The data processing system according to claim 16, further comprising: a second circuit including a second timer that receives a second tunable clock signal, the second circuit having a non-operational power state in which the second tunable clock signal is lost, and a plurality of power states in which the second tunable clock signal operates at different respective frequencies, wherein the power state controller is operable to store a timer value from the second timer in a memory when the second circuit enters the non-operating power state, and to set a timer wake-up value for the shadow timer based on an earliest wake-up time selected from between the timer and the second timer and a non-operating power state exit delay value.

19. The data processing system of claim 18, wherein the first circuit is a data fabric, and the second circuit is one of a memory controller, an input / output controller, and a processor core.

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