Random number generation based on threshold voltage randomness

Abstract

The present application relates to random number generation based on threshold voltage randomness. For example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage until the applied voltage meets a threshold voltage associated with the chalcogenide element. The memory device may detect the state of an oscillating signal at the time the applied voltage meets the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. The threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and thus the state of the oscillating signal at the time the applied voltage reaches the threshold voltage may also vary in a statistically random manner, and thus the corresponding logic value output may be a random value suitable for random number generation.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 17 / 818,617, filed by TORTORELLI et al. on August 9, 2022, entitled “RANDOM NUMBER GENERATION BASED ON THRESHOLDVOLTAGE RANDOMNESS,” which is assigned to its assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to random number generation based on threshold voltage randomness. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access information stored by a memory device, a component can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component can write (e.g., program, set, assign) one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be described according to either a volatile configuration or a non-volatile configuration. Volatile memory cells (e.g., DRAM) may lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND) can maintain their programmed state for extended periods of time even in the absence of an external power source. Summary of the Invention

[0006] A method is described. The method may include applying a voltage to a chalcogenide element of a memory system; increasing the applied voltage at least until the applied voltage meets a threshold voltage associated with the chalcogenide element; detecting when the applied voltage meets the threshold voltage associated with the chalcogenide element; detecting a state of an oscillating signal as of the time when the applied voltage meets the threshold voltage; and outputting a logic value based at least in part on the state of the oscillating signal as of the time when the applied voltage meets the threshold voltage.

[0007] An apparatus is described. The apparatus may include: a chalcogenide element of a memory system; a voltage component configured to apply a voltage to the chalcogenide element at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element; a signal component configured to generate an oscillating signal; and a latch component configured to: detect when the applied voltage satisfies the threshold voltage associated with the chalcogenide element; detect a state of the oscillating signal as of the time when the applied voltage satisfies the threshold voltage; and output a logic value based at least in part on the state of the oscillating signal as of the time when the applied voltage satisfies the threshold voltage.

[0008] Another apparatus is described. The apparatus may include: a chalcogenide element; a controller configured to cause the apparatus to increase a voltage applied to the chalcogenide element at least until the voltage satisfies a threshold voltage associated with the chalcogenide element; and a latch component configured to output a logic value based at least in part on a state of an oscillating signal as of the time the applied voltage satisfies the threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting random number generation based on threshold voltage randomness according to examples as disclosed herein is described.

[0010] Figure 2 An example of a memory die supporting random number generation based on threshold voltage randomness according to examples as disclosed herein is illustrated.

[0011] Figure 3 Examples of memory cells supporting random number generation based on threshold voltage randomness according to examples as disclosed herein are described.

[0012] Figure 4 An example of a random number generator diagram is illustrated that supports random number generation based on threshold voltage randomness according to examples as disclosed herein.

[0013] Figure 5A 、 5Band 5C illustrate an example of a random number generator diagram supporting random number generation based on threshold voltage randomness according to examples as disclosed herein.

[0014] Figure 6 A block diagram is shown of a memory system supporting random number generation based on threshold voltage randomness according to examples as disclosed herein.

[0015] Figure 7 A flow chart showing a method of supporting random number generation based on threshold voltage randomness according to examples as disclosed herein. DETAILED DESCRIPTION

[0016] Random numbers can be generated by a memory device or a host device to assist in various applications, including, but not limited to, cryptography, simulation and modeling of complex systems, or for selecting random samples from a data set. For example, random numbers can be used to generate encryption keys for accessing (e.g., decoding) encrypted data. In some cases, an algorithm or set of logic procedures can generate random numbers, such that generating the random numbers can be associated with latency or resource consumption (e.g., processing bandwidth) at the memory device or the host device, or both. It may be desirable to use the memory device's hardware to generate random numbers to conserve resource consumption, reduce associated latency, or achieve other potential benefits.

[0017] A memory device may include one or more chalcogenide elements. As used herein, a chalcogenide element may refer to any portion (e.g., a block, sheet, or mass) of a chalcogenide material. For example, in some memory devices, memory cells may each include a chalcogenide element. In some cases, a chalcogenide element may become conductive once a voltage applied to the chalcogenide element satisfies a threshold voltage. For example, when the applied voltage across the chalcogenide element is below the threshold voltage, the chalcogenide element may exhibit a relatively high resistance (low conductivity), while when the applied voltage is above the threshold voltage, the chalcogenide element may exhibit a relatively low resistance (high conductivity). The difference between the two resistances may be large enough that the chalcogenide element may be considered non-conductive when the applied voltage is below the threshold voltage, and conductive when the applied voltage is above the threshold voltage. In some cases, when the applied voltage reaches a threshold voltage (e.g., increases to a magnitude equal to the threshold voltage after being below the threshold voltage), the current through the chalcogenide element may detectably increase (e.g., spike), which in some cases may be referred to as the chalcogenide element "mutating." Thus, as used herein, chalcogenide element mutation may refer to the voltage across the chalcogenide element reaching the threshold voltage of the chalcogenide element, or any related phenomenon (e.g., an associated current spike). Thus, mutation of a chalcogenide element may be detected by an associated decrease in detection resistance or an increase in current, among other possibilities.

[0018] The threshold voltage of a chalcogenide element can be inherently random, such that the threshold voltage of the chalcogenide element can vary in a random (e.g., statistically random) manner from one voltage application to the next within a range of statistically expected values ​​(which can be referred to as an expected range). That is, a first voltage can be applied to the chalcogenide element and increased until the chalcogenide element abruptly changes for the first time, and a second voltage can thereafter be applied to the chalcogenide element and increased until the chalcogenide element abruptly changes for the second time, and due to the random variation in the threshold voltage of the chalcogenide element, the two abrupt changes can occur at different (e.g., slightly different) voltages. Thus, for example, a voltage applied to the chalcogenide element can meet the threshold voltage at a random voltage within an expected threshold voltage interval (e.g., within a range of statistically expected values ​​of the threshold voltage), and the chalcogenide element can become conductive (e.g., abruptly change) at the statistically random voltage.

[0019] According to examples disclosed herein, a random number can be generated by a memory device using a random threshold voltage associated with a chalcogenide element. For example, the memory device may include a voltage source configured to apply a voltage to the chalcogenide element and increase the voltage at least until a threshold voltage is met. The memory device may include a signal generator configured to generate an oscillating signal, wherein the oscillating signal can alternate between two states (e.g., a high state and a low state). The oscillating signal can alternate multiple times simultaneously with increasing the voltage applied to the chalcogenide element (e.g., at a high frequency relative to the ramp rate of increasing the applied voltage), such that the state of the oscillating signal can change multiple times during an expected threshold voltage interval (e.g., a statistically expected range of threshold voltages). In this way, the state of the oscillating signal (e.g., whether it is high or low) at the time the chalcogenide element is abruptly changed can be unpredictable and change in a random manner consistent with the random variation in the threshold voltage of the chalcogenide element.

[0020] A memory device may include a latch configured to detect the state of an oscillating signal at the time when an applied voltage meets the threshold voltage of a chalcogenide element, where this time may be subject to some degree of random variation as explained herein. For example, the latch may detect the time when the applied voltage meets the threshold voltage of the chalcogenide element based on sensing when the magnitude of a current through or otherwise associated with the chalcogenide element exceeds a threshold (or based on detecting some other event associated with a sudden change in the chalcogenide element), and the latch may determine (e.g., sample) the value of the oscillating signal at that time (e.g., detecting whether the oscillating signal was in a high state, a low state, or some other detectable state at the time of the sudden change). The latch may output a logic value (e.g., 0 or 1) corresponding to (e.g., indicating or representing) the state of the oscillating signal, which may be a random logic value (e.g., 0 or 1) due to the random variation in the threshold voltage and, correspondingly, the random variation in the time at which the state of the oscillating signal is detected. Among other potential benefits, using hardware components of a memory device and the methods described herein to generate random numbers can alleviate resource allocation (e.g., processing bandwidth) and reduce the latency associated with generating random numbers using other means. Furthermore, the memory devices described herein can utilize chalcogenide elements already implemented in the memory architecture, so the chalcogenide elements can support random number generation without requiring additional cell programming or pre-processing.

[0021] The features of this disclosure were originally described in reference Figures 1 to 3 The features of the present disclosure are described in the context of the memory systems, dies, and arrays described herein. Figure 4 、 5A , 5B and 5C are described in the context of the random number generator diagrams described in FIG. These and other features of the present disclosure are described by reference to Figures 6 to 7 The device diagram and flow chart related to random number generation based on threshold voltage randomness are further illustrated and described.

[0022] Figure 1 An example of a system 100 that supports random number generation based on threshold voltage randomness according to examples disclosed herein is described. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data for one or more other components of system 100.

[0024] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system on chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0025] Memory device 110 may be a standalone device or component operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme used to modulate signals, various pin configurations for communicating signals, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 may act as a helper or slave type device for host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0027] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using a bus 135.

[0028] The processor 125 is operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 can be implemented by or be part of the processor 125.

[0029] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and the various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sectors), each of which is operable to store at least one bit of data. A memory device 110 that includes two or more memory dies 160 may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0031] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may combine with the local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0032] In some examples, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command indicating that memory device 110 is to store data for host device 105, or a read command indicating that memory device 110 is to provide data stored in memory die 160 to the host device.

[0033] The local memory controller 165 (e.g., local to the memory die 160) may include circuitry, logic, or components operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., to receive or transmit data or commands or both). In some examples, the memory device 110 may not include a device memory controller 155 and a local memory controller 165, or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0034] The external memory controller 120 is operable to enable communication of one or more of information, data, or commands between a component of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between the components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or their functionality described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is described as being external to the memory device 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0035] Components of host device 105 can exchange information with memory device 110 using one or more channels 115. Channels 115 are operable to support communication between external memory controller 120 and memory device 110. Each channel 115 is an example of a transmission medium that carries information between host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path is an example of a conductive path that is operable to carry a signal. For example, a channel 115 can include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin is an example of a conductive input or output point of a device of system 100, and a pin can be operable to serve as part of a channel.

[0036] Lanes 115 (and associated signal paths and terminals) can be dedicated to conveying one or more types of information. For example, lanes 115 may include one or more command and address (CA) lanes 186, one or more clock signal (CK) lanes 188, one or more data (DQ) lanes 190, one or more other lanes 192, or a combination thereof. In some examples, signaling can be conveyed via lanes 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal can be registered for each clock cycle (e.g., on either the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0037] In some examples, CA channel 186 is operable to communicate commands between host device 105 and memory device 110, the commands including control information associated with the commands (e.g., address information). For example, CA channel 186 may include a read command with the address of desired data. In some examples, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) to decode one or more of the address or command data.

[0038] In some examples, clock signal channel 188 is operable to communicate one or more clock signals between host device 105 and memory device 110. Each clock signal is operable to oscillate between a high state and a low state and can support coordination (e.g., in time) between the actions of host device 105 and memory device 110. In some examples, the clock signal can be single-ended. In some examples, the clock signal can provide a timing reference for command and address operations for memory device 110 or other system-wide operations for memory device 110. Therefore, the clock signal can be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal can be generated by a system clock, which can include one or more hardware components (e.g., an oscillator, a crystal, logic gates, transistors).

[0039] In some examples, data channel 190 is operable to communicate one or more of data or control information between host device 105 and memory device 110. For example, data channel 190 may communicate information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110.

[0040] Channel 115 may include any number of signal paths, including a single signal path. In some examples, channel 115 may include multiple individual signal paths. For example, a channel may be x4 (e.g., including 4 signal paths), x8 (e.g., including 8 signal paths), x16 (including 16 signal paths), and so on.

[0041] Signals communicated over channel 115 may be modulated using one or more different modulation schemes. In some examples, a binary symbol (or binary level) modulation scheme may be used to modulate signals communicated between host device 105 and memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to 2. Each symbol of the binary symbol modulation scheme may be operable to represent one digital data bit (e.g., a symbol may represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), or others.

[0042] In some examples, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between host device 105 and memory device 110. A multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of a multi-symbol modulation scheme is operable to represent more than one digital data bit (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme including at least three levels to encode more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0043] According to examples disclosed herein, a random number can be generated by memory device 110 using a random threshold voltage associated with a chalcogenide element (e.g., a memory cell). For example, memory device 110 can include a voltage source configured to apply a voltage to the chalcogenide element and increase the voltage until the threshold voltage is met (e.g., until a sudden change in the chalcogenide element is detected, or until the applied voltage exceeds an expected range associated with the threshold voltage). Memory device 110 can include a signal generator configured to generate an oscillating signal, wherein the oscillating signal can alternate between two or more states (e.g., a high state and a low state). The oscillating signal can change state (e.g., alternate) multiple times while memory device 110 increases the voltage applied to the chalcogenide element, such that the state can change multiple times during a time period in which the magnitude of the applied voltage is within the expected threshold voltage interval for the chalcogenide element. Memory device 110 can include a latch configured to detect the state of the oscillating signal when the threshold voltage of the chalcogenide element is met. The latch can output the state of the oscillating signal as a random logic value (e.g., 0 or 1) when a threshold voltage is met. Using the components of memory device 110 and the methods described herein to generate random numbers can alleviate resource allocation (e.g., processing bandwidth) and reduce the latency associated with generating random numbers using other means. Furthermore, the memory device 110 described herein can use chalcogenide elements that are already implemented in the memory architecture, so the chalcogenide elements can support random number generation without requiring additional cell programming or pre-processing.

[0044] Figure 2 An example of a memory die 200 supporting random number generation based on threshold voltage randomness according to an example disclosed herein is illustrated. The memory die 200 may be a reference Figure 11 . An example of a memory die 160 is described. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 may include one or more memory cells 205, each of which may be programmed to store a different logic state (e.g., a programmed one of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell 205) may be operable to store more than one bit of information at a time (e.g., a logic 00, a logic 01, a logic 10, a logic 11). In some examples, the memory cells 205 may be arranged in an array, such as with reference to FIG. Figure 1 Memory array 170 is described.

[0045] The memory cell 205 may use a configurable material to store a logic state, and the configurable material may be referred to as a memory element, a memory storage element, a material element, a material storage element, a material portion, or a polarity write material portion, etc. The configurable material of the memory cell 205 may be referred to as a chalcogenide-based storage component, as described in reference to FIG. Figure 3 For example, chalcogenide storage elements can be used in phase change memory (PCM) cells, thresholded memory cells, or self-selected memory cells.

[0046] Memory die 200 may include access lines (e.g., row lines 210 and column lines 215) arranged in a pattern, such as a grid-like pattern. The access lines may be formed from one or more conductive materials. In some examples, row lines 210 may be referred to as word lines. In some examples, column lines 215 may be referred to as digit lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, may be interchangeable without loss of understanding or operation. Memory cells 205 may be positioned at the intersection of row lines 210 and column lines 215.

[0047] By activating or selecting an access line, such as one or more of the row lines 210 or the column lines 215, operations such as reading and writing can be performed on the memory cells 205. By biasing the row lines 210 and the column lines 215 (e.g., applying a voltage to the row lines 210 and the column lines 215), a single memory cell 205 can be accessed at their intersection. The intersection of the row lines 210 and the column lines 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of the memory cell 205. The access line can be a conductive line coupled to the memory cell 205 and can be used to perform access operations on the memory cell 205.

[0048] Sensing component 230 is operable to detect the state of memory cell 205 (e.g., material state, resistance, threshold state) and determine the logic state of memory cell 205 based on the stored state. Sensing component 230 may include one or more sense amplifiers to amplify or otherwise convert the signal originating from accessing memory cell 205. Sensing component 230 may compare the signal detected from memory cell 205 with a reference signal 235 (e.g., a reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 230 (e.g., to input / output 240) and may be indicated to another component of a memory device including memory die 200. In some cases, sensing component 230 may be an example of a latch component as described herein.

[0049] The local memory controller 245 can control access to the memory cell 205 through various components (eg, row decoder 220, column decoder 225, sensing component 230). The local memory controller 245 can be a reference Figure 1 1. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 230 can be co-located with the local memory controller 245. The local memory controller 245 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 245 can generate row signals and column address signals to activate the target row lines 210 and the target column lines 215. The local memory controller 245 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may vary or may be different for the various operations discussed in operating the memory die 200 .

[0050] The local memory controller 245 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 245 in response to various access commands (e.g., from the host device 105). The local memory controller 245 may be operable to perform other access operations not listed here, or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0051] The local memory controller 245 is operable to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, the logic state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 245 can identify the target memory cell 205 on which the read operation is to be performed. The local memory controller 245 can identify the target row line 210 and the target column line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 245 can activate the target row line 210 and the target column line 215 (e.g., apply a voltage to the row line 210 or the column line 215) to access the target memory cell 205. The sensing component 230 can detect a signal received from the memory cell 205 based on a pulse applied to the row line 210, a pulse applied to the column line, or the resistance or threshold characteristics of the memory cell 205. The sensing component 230 can amplify the signal. The local memory controller 245 can activate the sensing component 230 (e.g., latch the sensing component) and, thus, compare the signal received from the memory cell 205 to the reference signal 235. Based on the comparison, the sensing component 230 can determine the logic state stored on the memory cell 205. The pulse used as part of the read operation can include one or more voltage levels for a duration.

[0052] According to examples disclosed herein, a random number can be generated by a memory device using a random threshold voltage associated with a chalcogenide element (e.g., memory cell 205). For example, the memory device may include a voltage source configured to apply a voltage to the chalcogenide element and increase the voltage until a threshold voltage is met. The memory device may include a signal generator configured to generate an oscillating signal, wherein the oscillating signal can alternate between two or more states (e.g., a high state and a low state). The oscillating signal can alternate simultaneously with increasing the voltage applied to the chalcogenide element or otherwise change state multiple times, such that the state can change multiple times during a desired threshold voltage. The memory device may include a latch configured to detect the state of the oscillating signal when the threshold voltage of the chalcogenide element is met. The latch can output the state of the oscillating signal as a random logic value (e.g., 0 or 1) when the threshold voltage is met. Generating random numbers using the components of a memory device and the methods described herein can alleviate resource allocation (e.g., processing bandwidth) and reduce latency associated with generating random numbers using other means. Furthermore, the memory devices described herein can utilize chalcogenide elements already implemented in the memory architecture, and thus the chalcogenide elements can support random number generation without requiring additional cell programming or pre-processing.

[0053] Figure 3 An example of a memory array 300 according to an example disclosed herein is illustrated. The memory array 300 may be a reference Figure 1 and 2 Memory array 300 may include a first level 305 of memory cells positioned above a substrate (not shown) and a second level 310 of memory cells located on top of the first array or level 305. Although the example of memory array 300 includes two levels 305, 310, memory array 300 may include any number of levels (e.g., one or more than two).

[0054] The memory array 300 may further include row lines 210-a, row lines 210-b, row lines 210-c, row lines 210-d, column lines 215-a, and column lines 215-b, which may be as shown in FIG. Figure 2 10 and column lines 215. One or more memory cells in the first and second layers 305 and 310 may include one or more chalcogenide materials in the pillars between the access lines. For example, a single stack between the access lines may include one or more of a first electrode, a first chalcogenide material (e.g., a selector element), a second electrode, a second chalcogenide material (e.g., a storage element), or a third electrode. Figure 3Some elements contained in the drawings are labeled with numerical indicators while other corresponding elements are not labeled, but are the same or will be understood to be similar, and this is done to improve visibility and clarity of the features being depicted.

[0055] One or more memory cells in the first layer 305 may include one or more of an electrode 325-a, a storage element 320-a, or an electrode 325-b. One or more memory cells in the second layer 310 may include an electrode 325-c, a storage element 320-b, and an electrode 325-d. The storage element 320 may be an example of a chalcogenide material, such as a phase change memory element, a thresholded memory element, or a self-select memory element. The storage element 320 may be an example of a chalcogenide element as described herein. In some examples, the memory cells in the first layer 305 and the second layer 310 may have a common conductive line, so that corresponding memory cells in one or more layers 305 and one or more layers 310 may share a column line 215 or a row line 210. For example, the first electrode 325-c of the second layer 310 and the second electrode 325-b of the first layer 305 may be coupled to the column line 215-a, so that the column line 215-a can be shared by vertically adjacent memory cells.

[0056] In some examples, the material of the memory element 320 may include a chalcogenide material or other alloy including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material primarily composed of selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some examples, a SAG alloy may also include silicon (Si), and such a chalcogenide material may be referred to as a SiSAG alloy. In some examples, a SAG alloy may include silicon or indium (In), or a combination thereof, and such a chalcogenide material may be referred to as a SiSAG alloy or an InSAG alloy, respectively, or a combination thereof. In some examples, the chalcogenide glass may include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0057] In some examples, the storage element 320 may be an example of a phase change memory cell. In such examples, the material used in the storage element 320 may be based on an alloy (such as the alloys listed above) and may be operable to undergo a phase change, or change to a different physical state, during normal operation of the memory cell. For example, a phase change memory cell may have an amorphous state (e.g., a relatively disordered atomic configuration) and a crystalline state (e.g., a relatively ordered atomic configuration).

[0058] Phase-change memory cells can exhibit a significant difference in resistance between the crystalline and amorphous states of a phase-change material (which may be a chalcogenide material). The material in the crystalline state may have atoms arranged in a periodic structure, which can result in relatively low resistance. In contrast, the material in the amorphous state may have no or a relatively less periodic atomic structure, which can result in relatively higher resistance.

[0059] The difference in resistance between a material's amorphous and crystalline states can be significant. For example, a material in its amorphous state can have a resistance that is one or more orders of magnitude greater than the resistance of the material in its crystalline state. In some examples, a material can be partially amorphous and partially crystalline, and the resistance can have a value somewhere between the resistance of the material in either the fully crystalline or fully amorphous states. In such examples, the material can be used to store more than two logical states (e.g., three or more logical states).

[0060] During a programming (write) operation of a phase-change memory cell (e.g., electrode 325-a, storage element 320-a, electrode 325-b), various parameters of a programming pulse can influence (e.g., determine, set, program) a specific behavior or characteristic of the material of the storage element 320, such as the material's threshold voltage or the material's resistance. To program a low-resistance state (e.g., a relatively crystalline state) in the phase-change memory cell, a programming pulse can be applied that heats or melts the material of the storage element 320, which can be associated with at least temporarily forming a relatively disordered (e.g., amorphous) atomic arrangement. The amplitude of the programming pulse can be reduced (e.g., relatively slowly) over a duration to allow the material to form a crystalline structure as it cools, thereby forming a stable crystalline material state. To program a high-resistance state (e.g., a relatively amorphous state) in the phase-change memory cell, a programming pulse can be applied that heats or melts the material of the storage element 320. The amplitude of the programming pulse can be reduced more rapidly than the programming pulse for the low-resistance state. In such a scenario, the material may be cooled with the atoms in a more disordered atomic arrangement because the atoms are unable to form a crystalline structure until the material reaches a stable state, thereby forming a stable amorphous material state. The difference in threshold voltage or resistance of the material of the memory element 320 depending on the logical state stored by the material of the memory element 320 may correspond to a read window of the memory element 320. In some cases, a portion of the memory element may undergo a material change associated with the logical state.

[0061] In some examples, such as for thresholding memory cells or self-selecting memory cells, some or all of a set of logical states supported by the memory cell may be associated with an amorphous state of the chalcogenide material (e.g., the material in a single state is operable to store different logical states). In some examples, the storage element 320 may be an example of a self-selecting memory cell. In such examples, the material used in the storage element 320 may be based on an alloy (e.g., the alloys listed above) and may be operable to undergo changes to different physical states during normal operation of the memory cell. For example, the self-selecting memory cell may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logical state (e.g., a RESET state), and the low threshold voltage state may correspond to a second logical state (e.g., a SET state).

[0062] During a programming (writing) operation of a self-selected memory cell (e.g., including electrode 325-a, storage element 320-a, and electrode 325-b), the polarity used for the writing operation can affect (determine, set, program) a specific behavior or characteristic of the material of storage element 320, such as the material's threshold voltage. The difference in the threshold voltage of the material of storage element 320 depending on the logical state stored by the material of storage element 320 (e.g., the difference between the threshold voltage when the material stores a logic state of '0' and the threshold voltage when the material stores a logic state of '1') can correspond to a read window of storage element 320.

[0063] In some examples, the architecture of memory array 300 may be referred to as a cross-point architecture, in which memory cells are formed at the topological intersections between row lines 210 and column lines 215. This cross-point architecture can provide relatively high-density data storage and have lower production costs compared to other memory architectures. For example, the cross-point architecture can have memory cells of reduced area and, therefore, increased memory cell density compared to other architectures. The architecture can have a memory cell area of ​​4F2, where F is the minimum feature size, compared to other architectures (e.g., architectures with three-terminal selector elements) having a memory cell area of ​​6F2, where F is the minimum feature size. For example, DRAM can use a transistor (which is a three-terminal device) as the selector element for each memory cell and can have a larger memory cell area than the cross-point architecture.

[0064] although Figure 3 The example of shows two memory levels, but other configurations are possible. In some examples, a single memory level of memory cells can be constructed above a substrate, which can be referred to as a two-dimensional memory. In some examples, two or more levels of memory cells can be configured in a similar manner in a three-dimensional cross-point architecture. Additionally, in some cases, Figure 3 Shown or referenced in Figure 3 The elements described may be electrically coupled to each other as shown or described, but physically rearranged (e.g., storage element 320 and possibly select element or electrode 325 may be electrically in series between row line 210 and column line 215, but may not be in a pillar or stacked configuration).

[0065] According to examples disclosed herein, a random number can be generated by a memory device using a random threshold voltage associated with a chalcogenide element (e.g., memory element 320). Memory element 320 may be an example of a chalcogenide element that processes a random threshold voltage and can be used for random number generation. For example, the memory device may include a voltage source configured to apply a voltage to the chalcogenide element and increase the voltage until a threshold voltage is met. The memory device may include a signal generator configured to generate an oscillating signal, wherein the oscillating signal can alternate between two or more states (e.g., a high state and a low state). The oscillating signal can alternate multiple times while the memory device increases the voltage applied to the chalcogenide element, such that the state can change multiple times during a period in which the magnitude of the applied voltage is within the expected threshold voltage associated with access element 320. The memory device may include a latch configured to detect the state of the oscillating signal when the threshold voltage of the chalcogenide element is met. The latch may output the state of the oscillating signal as a random logic value (e.g., 0 or 1) when the threshold voltage is met. Using components of a memory device and the methods described herein to generate random numbers can alleviate resource allocation (e.g., processing bandwidth) and reduce the latency associated with generating random numbers using other means. Furthermore, the memory devices described herein can utilize chalcogenide elements already implemented in memory architectures, thus supporting random number generation without requiring additional cell programming or pre-processing.

[0066] Figure 4 An example of a random number generator diagram 400 supporting random number generation based on threshold voltage randomness according to an example disclosed herein is illustrated. The random number generator diagram 400 may be provided by a reference to Figure 1 Similarly, the random number generator diagram 400 may include the random number generators 100 and 100 as described in the respective references. Figure 1 、 2 3. For clarity of description, the system 100, memory die 200 or memory array 300 may be described in detail. Figure 4 Aspects or components of random number generator diagram 400 are omitted. Random number generator diagram 400 may describe operations at a memory device implementing a chalcogenide element with a random threshold voltage for random number generation.

[0067] Random number generator diagram 400 may describe a method at a memory device that includes a chalcogenide element (e.g., not shown), a voltage source (e.g., not shown), a signal generator (e.g., not shown), and a latch 405. The chalcogenide element may be a piece of chalcogenide material, such as memory element 320, as described with reference to FIG. Figure 3 4. A memory device controller may include or control the voltage source. A signal generator may be configured to generate an oscillating signal 415, wherein the oscillating signal 415 may alternate between two states (e.g., high and low, high and medium, medium and low, 1 and 0, among other examples) over time. A latch 405 may be coupled to the chalcogenide element and the oscillating signal 415, and the latch 415 may monitor the voltage 410 or the current or both at the chalcogenide element and the oscillating signal 415.

[0068] At t1, the voltage source may apply a voltage 410 (e.g., a read voltage) to the chalcogenide element. The voltage source may then increase the voltage 410 applied to the chalcogenide element. For example, the voltage source may initially apply a voltage 410 of 4 V at t1 and increase the voltage 410 to 5 V at a constant rate over a period of time until t5.

[0069] The chalcogenide element may have a random (e.g., stochastic) threshold voltage 420. The threshold voltage 420 may be based on one or more physical properties of the chalcogenide element and may indicate a voltage value at which the chalcogenide element becomes conductive (e.g., abruptly). For example, when the threshold voltage 420 is met, the chalcogenide element may become significantly more conductive, and the latch 405 may detect a current spike from the chalcogenide element.

[0070] Threshold voltage 420 may be satisfied by voltage values ​​within an expected threshold voltage interval 425 (e.g., a normal quantile distribution), such that threshold voltage 420 has a high statistical probability of being satisfied during the expected threshold voltage interval 425. For example, expected threshold voltage interval 425 may have a lower boundary value (e.g., 4.2 V) and a higher boundary value (e.g., 4.8 V) where threshold voltage 420 is likely (e.g., 99% probability) to be satisfied by voltage 410 (e.g., 4.5 V). The lower boundary value may be reached by voltage 410 corresponding to time t2, and the upper boundary value may be reached by voltage 410 corresponding to time t4. Based on the physical properties of chalcogenide devices, threshold voltage 420 may exhibit slight and random variations, such that the voltage at which threshold voltage 420 is satisfied may vary between read operations (e.g., may be statistically distributed as a Gaussian bounce model). In some cases, threshold voltage 420 may be satisfied by voltage 410 at a lower voltage value corresponding to a time closer to t2, and in other cases, threshold voltage 420 may be satisfied by voltage 410 at a higher voltage value corresponding to a time closer to t4.

[0071] At t3, the voltage 410 applied to the chalcogenide element may increase to a point where the threshold voltage 420 is met, where the threshold voltage 420, and therefore the time t3, may vary randomly, as described herein. The chalcogenide element may begin to become conductive at t3, and a latch 405 coupled to the chalcogenide element may detect a current spike or other associated event at t3. Thus, the latch 405 may detect the time t3 at which the threshold voltage 420 is met. Similarly, when the threshold voltage 420 is met, the latch device 405 may detect the state of the oscillating signal 415 at time t3. In some cases, the latch 405 may include a detection component configured to detect the time t3, the state of the oscillating signal 415, or both.

[0072] Oscillating signal 415 may fluctuate between two or more states (e.g., voltage states), such that the amplitude of oscillating signal 415 may vary (e.g., alternate) between two or more voltage values. For example, oscillating signal 415 may be a binary signal configured to alternate between a first voltage value (e.g., 1 V) and a second voltage value (e.g., 0 V). In some examples, oscillating signal 415 may alternate between a first voltage value of a first polarity and a second voltage value of a second polarity (e.g., different from or the same as the first polarity). The state of oscillating signal 415 may be defined based on comparing the amplitude of oscillating signal 415 to a threshold. For example, if the amplitude of oscillating signal 415 is above the threshold, oscillating signal 415 may be in a first state (e.g., high) or a first voltage value, while if the amplitude of oscillating signal 415 is below the threshold, oscillating signal 415 may be in a second state (e.g., low) or a second voltage value. The rate at which oscillating signal 415 alternates between the two states may be significantly faster than the rate of increase (e.g., ramp rate) of voltage 410. For example, the oscillating signal 415 may alternate between the first state and the second state multiple times (e.g., thousands of times) during the desired threshold voltage interval 425, such that it is unpredictable what state the oscillating signal 415 will be in as of t3 (when the randomly variable threshold voltage 420 is satisfied) and, therefore, exhibits random variation.

[0073] Furthermore, at or after t3, the latch 405 may output a logic value (e.g., one or more bits, which may be considered random bits) representing the state of the oscillating signal 415 as detected at t3. Due to the multiple fluctuations of the oscillating signal 415 between the two states during the expected threshold voltage interval 425 and the random variations in the threshold voltage 420, the state of the oscillating signal 415 detected by the latch 405 may exhibit random variations based on the random nature of the threshold voltage 420. That is, for example, the logic value corresponding to the state of the oscillating signal 415 detected by the latch 405 may be a random logic value due to the randomness of the moments when the threshold voltage 420 is met and the random chance of whether the first state or the second state of the oscillating signal 415 is detected at time t3.

[0074] The voltage source may cease applying voltage 410 in response to threshold voltage 420 being met, or when voltage 410 is sufficiently greater than an upper boundary of expected threshold voltage interval 425. For example, the voltage source may remove voltage 410 from the chalcogenide element at t3 or at t5.

[0075] Using a chalcogenide element with a random threshold voltage 420 to latch 405 the state of an oscillating signal 415 can provide advantages associated with generating random numbers, such as those described herein. In some cases, the threshold voltage 420 can remain random despite changes in other physical properties of the chalcogenide element. For example, the randomness of the threshold voltage 420 can be unaffected by voltage drift, aging, electrical distance, or physical wear (e.g., degradation) associated with the chalcogenide element. Furthermore, the chalcogenide element may not be configured to be reconditioned between uses for generating random numbers.

[0076] In some cases, an unbalanced duty cycle can be used to control (e.g., weight) the randomness of the methods described herein. For example, the oscillating signal 415 can be configured by the signal generator to generate one of the two states for a longer duration during the expected threshold voltage interval 425, thereby changing the probability (e.g., weighted probability) of one of the states being selected by the latch 405 at the time the threshold voltage 420 is met. The signal generator can control the probability by changing the timing offset of the oscillating signal 415, the frequency of the oscillating signal 415, the phase of the oscillating signal 415, or any combination thereof. In some cases, by using the hardware (e.g., physical components) of the memory device rather than an algorithm to generate random numbers, a host device or system (e.g., including the memory device) can benefit from reduced resource allocation (e.g., processing bandwidth) and reduced latency associated with random number generation.

[0077] Figure 5A 、 5B 5C illustrate examples of random number generator diagrams 500-a, 500-b, and 500-c, respectively, supporting random number generation based on threshold voltage randomness according to examples disclosed herein. The random number generator diagrams 500-a, 500-b, and 500-c may be provided by reference to Figure 1 Similarly, random number generators 500-a, 500-b, and 500-c may include the random number generators 500-a, 500-b, and 500-c as described with reference to FIG. Figure 1 、 2 3. The random number generator diagrams 500-a, 500-b, and 500-c may implement aspects of the random number generator diagram 400, such as the latch 405, as described with reference to FIG. Figure 4 For clarity of description, aspects or components of the random number generator diagrams 500-a, 500-b, and 500-c may be viewed from Figures 5A to 5C Random Number Generator

[0066] Diagrams 500-a, 500-b, and 500-c may describe operations at a memory device implementing a chalcogenide element with a random threshold voltage for generating a plurality of random numbers (eg, a sequence of random numbers).

[0078] Random number generator diagrams 500-a, 500-b, and 500-c may depict variations of the random number generator diagram 400, as described with reference to FIG. Figure 4 Each random number generator diagram 500-a, 500-b, and 500-c may include at least one of each of the following: a chalcogenide element (e.g., not shown), a voltage source (e.g., not shown), a signal generator (e.g., not shown), and a latch 505. The voltage source may be configured to apply at least a voltage 510 (e.g., voltages 510-a-1, 510-a-2, 510-b, 510-c-1, and 510-c-2) to at least one chalcogenide element, wherein the voltage source increases at least the voltage 510 with respect to time. The signal generator may be configured to generate at least one oscillating signal 515 (e.g., oscillating signals 515-a, 515-b-1, 515-b-2, 515-b-3, 515-c-1, 515-c-2), wherein the at least one oscillating signal 515 may alternate between two states (e.g., high and low, high and medium, medium and low, 1 and 0, etc.) over time. A latch 505 (e.g., latches 505-a, 505-b, 505-c) may be coupled to at least one chalcogenide device and the at least one oscillating signal 515, and may monitor voltage or current, or both, at the one or more chalcogenide devices and the one or more oscillating signals 515.

[0079] Figure 5A Illustrating an example of a random number generator diagram 400 that implements serial voltage applications on a single chalcogenide element to generate multiple random values, which in some cases can be combined to form a single multi-bit random number or sequence, where each of the voltage applications is as described with respect to Figure 4 In random number generator diagram 500-a, a voltage source may apply a first voltage 510-a-1 to a chalcogenide element and increase the first voltage 510-a-1. At a first time after increasing the first voltage 510-a-1, the first voltage 510-a-1 may meet a first threshold voltage 520-a-1 associated with the chalcogenide element, at which point the chalcogenide element may become conductive (e.g., abruptly). The first threshold voltage 520-a-1 may be randomly met at a voltage within an expected threshold voltage interval 525-a-1. A latch 505-a may detect the state of an oscillating signal 515-a at the first time the first threshold voltage 520-a-1 is met and output a first logic value corresponding to the state of the oscillating signal 515-a at the first time. The voltage source may stop applying the first voltage 510-a-1 in response to the first threshold voltage 520-a-1 being met, or at a later time when the first voltage 510-a-1 is sufficiently greater than the upper boundary value of the expected threshold voltage interval 525-a-1, and the chalcogenide element may no longer conduct electricity.

[0080] The voltage source may apply a second voltage 510-a-2 to the chalcogenide element after ceasing application of the first voltage 510-a-1, and the voltage source may increase the second voltage 510-b-2. At a second time after increasing the second voltage 510-a-2, the second voltage 510-a-2 may meet a second threshold voltage 520-a-2 associated with the chalcogenide element, at which point the chalcogenide element may become conductive again (e.g., abruptly). Based on random variations associated with the chalcogenide element, the second threshold voltage 520-a-2 may differ from the first threshold voltage 520-a-1. Furthermore, the second threshold voltage 520-a-2 may be randomly met at a voltage within the expected threshold voltage interval 525-a-2. The latch 505-a may monitor the state of the oscillating signal 515-a at the second time when the second threshold voltage 520-a-2 is met, and output a second logic value (e.g., the same as or different from the first logic value) corresponding to the state of the oscillating signal 515-a at the second time. The first logic value and the second logic value can be combined (e.g., by latch 505-a) to form a random number sequence. The voltage source can stop applying the second voltage 510-a-2 in response to the second threshold voltage 520-a-2 being met, or at a later time when the second voltage 510-a-2 is sufficiently greater than the upper boundary value of the expected threshold voltage interval 525-a-2. Additional voltages 510-a can then be applied similarly to the above-described method to create additional logic values ​​of the random number sequence.

[0081] Figure 5B Illustrating an example of a random number generator diagram 400, the random number generator diagram 400 implements multiple oscillating signals 515-b (e.g., oscillating signals 515-b-1, 515-b-2, 515-b-3) for a single chalcogenide element to generate multiple random values, which in some cases can be combined to form a single multi-bit random number or sequence, where each oscillating signal 515 is as described with respect to Figure 4The oscillating signals 515-b may be offset from one another in phase, initial timing, amplitude, frequency, or any combination thereof. Furthermore, the oscillating signals 515-b-1, 515-b-2, and 515-b-3 may be three oscillating signals 515-b of a plurality of oscillating signals 515-b coupled to the latch 505-b. In the random number generator diagram 500-b, a voltage source may apply a voltage 510-b to the chalcogenide element and increase the voltage 510-b. At a time after increasing the voltage 510-b, the voltage 510-b may meet a threshold voltage 520-b associated with the chalcogenide element, at which point the chalcogenide element may become conductive (e.g., abruptly). The threshold voltage 520-b may be randomly met at a voltage within the expected threshold voltage interval 525-b. Latch 505 - b may detect the states of oscillating signals 515 - b - 1 , 515 - b - 2 , and 515 - b - 3 at times when threshold voltage 520 - b is met.

[0082] Latch 505-b may output a first logic value corresponding to the state of oscillating signal 515-b-1 at the time threshold voltage 520-b is met. Latch 505-b may output a second logic value corresponding to the state of oscillating signal 515-b-2 at the time threshold voltage 520-b is met. Furthermore, latch 505-b may output a third logic value corresponding to the state of oscillating signal 515-b-3 at the time threshold voltage 520-b is met. The first logic value, the second logic value, and the third logic value may be combined (e.g., by latch 505-b) to form a random number sequence. The voltage source may cease applying voltage 510-b in response to threshold voltage 520-b being met, or at a later time when voltage 510-b is sufficiently greater than the upper boundary value of the expected threshold voltage interval 525-b, and the chalcogenide element may no longer conduct electricity.

[0083] Figure 5C An example of a random number generator diagram 400 is illustrated that implements two chalcogenide elements to generate multiple random values ​​with each of a voltage application, which in some cases can be combined to form a single multi-bit random number or sequence, where each of the chalcogenide elements is as described with respect to Figure 4In random number generator diagram 500-c, a voltage source may apply a first voltage 510-c-1 to a first chalcogenide element and increase the first voltage 510-c-1. The voltage source, or a second voltage source, may apply a second voltage 510-c-2 to a second chalcogenide element while applying the first voltage 510-c-1 to the first chalcogenide element, and increase the second voltage 510-c-2 simultaneously with increasing the first voltage 510-c-1. At a first time after increasing the first voltage 510-c-1, the first voltage 510-c-1 may meet a first threshold voltage 520-c-1 associated with the first chalcogenide element, at which point the first chalcogenide element may become conductive (e.g., abruptly). The first threshold voltage 520-c-1 may be randomly met at a voltage within an expected threshold voltage interval 525-c-1. The latch 505-c may detect the state of the oscillating signal 515-c-1 at a first time when the first threshold voltage 520-c-1 is satisfied, and output a first logic value corresponding to the state of the oscillating signal 515-c-1 at the first time. The voltage source may stop applying the first voltage 510-c-1 in response to the first threshold voltage 520-c-1 being satisfied, or at a later time when the first voltage 510-c-1 is sufficiently greater than the upper boundary value of the expected threshold voltage interval 525-c-1, and the first chalcogenide element may no longer conduct electricity.

[0084] Additionally, at a second time after increasing the second voltage 510-c-2, the second voltage 510-c-2 may meet a second threshold voltage 520-c-2 associated with the chalcogenide element, at which point the second chalcogenide element may become conductive (e.g., abruptly). The second time may be the same time as the first time or a different time. The second threshold voltage 520-c-2 may be randomly met at a voltage within the expected threshold voltage interval 525-c-2. In some cases, the latch 505-c may detect the state of the oscillating signal 515-c-2 at the second time when the second threshold voltage 520-c-2 is met. In such cases, the latch 505-c may output a second logic value corresponding to the state of the oscillating signal 515-c-2 at the second time. The oscillating signal 515-c-2 may be offset from the oscillating signal 515-c-1 in phase, initial timing, amplitude, frequency, or any combination thereof. In other cases, latch 505-c may instead detect the state of oscillating signal 515-c-1 at a second time when second threshold voltage 520-c-2 is met (e.g., when one oscillating signal 515 is present for both chalcogenide elements). In such cases, latch 505-c may output a second logic value corresponding to the state of oscillating signal 515-c-1 at that time. Latch 505-c may output a second logic value corresponding to the state of oscillating signal 515-c-1 at the second time. In some cases, a second latch 505-c may be coupled to a second chalcogenide element and may instead detect the state of oscillating signal 515-c (e.g., oscillating signals 515-c-1 and 515-c-2) and output a second logic value. The second logic value may be the same as or different from the first value. The first and second logic values ​​may be combined (e.g., by latch 505-c) to form a random number sequence. The voltage source may cease applying the second voltage 510-c-2 in response to the second threshold voltage 520-c-2 being met, or at a later time when the second voltage 510-c-2 is sufficiently greater than the upper boundary value of the expected threshold voltage interval 525-c-2, and the second chalcogenide element may no longer be conductive. Additional chalcogenide elements may be used similarly to methods described herein to create additional logical values ​​for the random number sequence.

[0085] In some cases, the random number sequence may be a multi-bit sequence that includes many logical values ​​generated using the methods described herein. In some examples, the random number sequence may be generated based on a demand from a host device. For example, a memory device may recognize (e.g., from a command from the host device) a demand for a specific number of logical values ​​for use at a later time and generate a corresponding set of logical values ​​(e.g., a set of logical values ​​that includes at least as many logical values ​​as associated with the demand) before the later time. In this example, the set of logical values ​​may be stored in a memory cache associated with the memory device so that it is available (e.g., already generated) when it is used (e.g., requested) at a later time.

[0086] In some cases, the memory may implement the Figures 5A to 5C For example, a memory device may be combined with two chalcogenide elements (e.g., Figure 5C ) of a plurality of oscillating signals 515 (e.g., Figure 5B ) to implement serial voltage application (e.g., Figure 5A . In this example, the memory device may apply a first voltage 410 and subsequently a second voltage 410 to the first chalcogenide element, and a third voltage 410 and subsequently a fourth voltage 410 to the second chalcogenide element. One or more latches 505-c may detect each state of the plurality of oscillating signals 515 at a first time when the first chalcogenide element is mutated (e.g., a threshold voltage is met and the chalcogenide element becomes conductive), a second time when the first chalcogenide element is mutated, a third time when the second chalcogenide element is mutated, and a fourth time when the second chalcogenide element is mutated. The one or more latches 505-c may output logic values ​​corresponding to these times, such that the logic values ​​may form a multi-bit random number sequence.

[0087] Figure 6 A block diagram 600 is shown of a memory system 620 that supports random number generation based on threshold voltage randomness according to an example disclosed herein. The memory system 620 may be a memory system 620 as described in reference to FIG. Figure 1 5. Memory system 620 or its various components may be examples of means for performing various aspects of random number generation based on threshold voltage randomness as described herein. For example, memory system 620 may include voltage component 625, latch component 630, logic value cache 635, chalcogenide element 640, signal component 645, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0088] The voltage component 625 can be configured as or otherwise support means for applying a voltage to the chalcogenide element 640 of the memory system. In some examples, the voltage component 625 can be configured as or otherwise support means for increasing the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element 640. The latch component 630 can be configured as or otherwise support means for detecting when the applied voltage satisfies a threshold voltage associated with the chalcogenide element 640. In some examples, the latch component 630 can be configured as or otherwise support means for detecting a state of an oscillating signal (which can be generated by the signal component 645) as of the time the applied voltage satisfies the threshold voltage. In some examples, the latch component 630 can be configured as or otherwise support means for outputting a logical value based at least in part on the state of the oscillating signal as of the time the applied voltage satisfies the threshold voltage.

[0089] In some examples, voltage component 625 can be configured as or otherwise support means for ceasing to apply voltage to a chalcogenide element 640 of the memory system based at least in part on the applied voltage satisfying a threshold voltage associated with chalcogenide element 640 .

[0090] In some examples, voltage component 625 may be configured to or otherwise support means for applying a second voltage to chalcogenide element 640 of the memory system after application of the voltage has ceased. In some examples, voltage component 625 may be configured to or otherwise support means for increasing the applied second voltage at least until the applied second voltage satisfies a second threshold voltage associated with chalcogenide element 640. In some examples, latch component 630 may be configured to or otherwise support means for detecting a second time at which the applied voltage satisfies the second threshold voltage associated with chalcogenide element 640. In some examples, latch component 630 may be configured to or otherwise support means for detecting a second state of the oscillating signal as of a second time at which the applied second voltage satisfies the second threshold voltage. In some examples, latch component 630 may be configured to or otherwise support means for outputting a second logic value based at least in part on the second state of the oscillating signal as of a second time at which the applied second voltage satisfies the second threshold voltage.

[0091] In some examples, latch component 630 can be configured as or otherwise support means for generating a multi-bit digital sequence using the logical value and the second logical value.

[0092] In some examples, the second threshold voltage is different from the threshold voltage based on random variations associated with the chalcogenide element 640 .

[0093] In some examples, latch component 630 can be configured to or otherwise support means for detecting a second state of the second oscillating signal generated by signal component 645 as of the time the applied voltage satisfies the threshold voltage. In some examples, latch component 630 can be configured to or otherwise support means for outputting a second logic value based at least in part on the second state of the second oscillating signal as of the time the applied voltage satisfies the threshold voltage. In some examples, latch component 630 can be configured to or otherwise support means for generating a multi-bit digital sequence using the logic value and the second logic value.

[0094] In some examples, the signal component 645 can generate the oscillating signal such that the second oscillating signal is offset from the oscillating signal in phase, time, frequency, or any combination thereof.

[0095] In some examples, the voltage component 625 may be configured as or otherwise support means for applying a second voltage to the second chalcogenide element 640 of the memory system. In some examples, the voltage component 625 may be configured as or otherwise support means for increasing the applied second voltage at least until the applied second voltage satisfies a second threshold voltage associated with the second chalcogenide element 640, the increase in the applied second voltage being at least partially concurrent with the increase in the applied voltage. In some examples, the latch component 630 may be configured as or otherwise support means for detecting a second time when the applied second voltage satisfies the second threshold voltage associated with the second chalcogenide element 640. In some examples, the latch component 630 may be configured as or otherwise support means for detecting a second state of the oscillating signal as of a second time when the applied second voltage satisfies the second threshold voltage. In some examples, the latch component 630 may be configured as or otherwise support means for outputting a second logic value based at least in part on the second state of the oscillating signal as of a second time when the applied second voltage satisfies the second threshold voltage. In some examples, latch component 630 can be configured as or otherwise support means for generating a multi-bit digital sequence using the logical value and the second logical value.

[0096] In some examples, the threshold voltage is within a threshold voltage range associated with chalcogenide element 640 , and the oscillating signal changes between the high state and the low state multiple times when the applied voltage is within the threshold voltage range.

[0097] In some examples, latch component 630 may be configured to or otherwise support means for identifying, at a first time, a number of logic values ​​used at a second time later than the first time, where the logic value comprises one of a set of logic values ​​used at the second time, the set of logic values ​​including the identified number of logic values. In some examples, logic value cache 635 may be configured to or otherwise support means for storing the set of logic values ​​within the memory system before the second time for use at the second time.

[0098] In some examples, the oscillating signal generated by the signal component 645 can have an unbalanced duty cycle.

[0099] Figure 7 A flowchart of a method 700 for supporting random number generation based on threshold voltage randomness according to an example disclosed herein is shown. The operations of the method 700 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 700 may be implemented by a memory system or components thereof as described herein. Figures 1 to 6 In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0100] At 705, the method may include applying a voltage to a chalcogenide element of the memory system. Operation 705 may be performed according to examples as disclosed herein. In some examples, aspects of operation 705 may be performed as described in reference to Figure 6 The voltage component 625 described above is implemented.

[0101] At 710, the method may include increasing the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. Operation 710 may be performed according to examples as disclosed herein. In some examples, aspects of operation 710 may be implemented as described in reference to Figure 6 The voltage component 625 described above is implemented.

[0102] At 715, the method may include detecting when the applied voltage satisfies a threshold voltage associated with the chalcogenide element. Operation 715 may be performed according to examples as disclosed herein. In some examples, aspects of operation 715 may be performed as described in reference to Figure 6 The latch component 630 described above is implemented.

[0103] At 720, the method may include detecting a state of the oscillating signal up to the time when the applied voltage satisfies the threshold voltage. Operation 720 may be performed according to examples as disclosed herein. In some examples, aspects of operation 720 may be implemented as described in reference to Figure 6 The latch component 630 described above is implemented.

[0104] At 725, the method may include outputting a logic value based at least in part on the state of the oscillating signal up to the time when the applied voltage satisfies the threshold voltage. Operation 725 may be performed according to examples as disclosed herein. In some examples, aspects of operation 725 may be implemented as described in reference to Figure 6 The latch component 630 described above is implemented.

[0105] In some examples, an apparatus described herein may perform a method such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0106] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: applying a voltage to a chalcogenide element of a memory system; increasing the applied voltage at least until the applied voltage meets a threshold voltage associated with the chalcogenide element; detecting a time when the applied voltage meets the threshold voltage associated with the chalcogenide element; detecting a state of an oscillating signal as of the time when the applied voltage meets the threshold voltage; and outputting a logic value based at least in part on the state of the oscillating signal as of the time when the applied voltage meets the threshold voltage.

[0107] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for ceasing to apply the voltage to the chalcogenide element of the memory system based at least in part on the applied voltage satisfying the threshold voltage associated with the chalcogenide element.

[0108] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of Aspect 2, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: applying a second voltage to the chalcogenide element of the memory system after ceasing to apply the voltage; increasing the applied second voltage at least until the applied second voltage satisfies a second threshold voltage associated with the chalcogenide element; detecting a second time at which the applied voltage satisfies the second threshold voltage associated with the chalcogenide element; detecting a second state of the oscillating signal as of the second time at which the applied second voltage satisfies the second threshold voltage; and outputting a second logic value based at least in part on the second state of the oscillating signal as of the second time at which the applied second voltage satisfies the second threshold voltage.

[0109] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of aspect 3, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for generating a multi-bit digital sequence using the logic value and the second logic value.

[0110] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 3-4, wherein the second threshold voltage is different from the threshold voltage based on random variations associated with the chalcogenide element.

[0111] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: detecting a second state of a second oscillating signal as of the time at which the applied voltage satisfies the threshold voltage; outputting a second logic value based at least in part on the second state of the second oscillating signal as of the time at which the applied voltage satisfies the threshold voltage; and generating a multi-bit digital sequence using the logic value and the second logic value.

[0112] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of aspect 6, wherein the second oscillating signal is offset from the oscillating signal in phase, time, frequency, or any combination thereof.

[0113] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 7, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: applying a second voltage to a second chalcogenide element of the memory system; increasing the applied second voltage at least until the applied second voltage meets a second threshold voltage associated with the second chalcogenide element, the increase in the applied second voltage being at least partially concurrent with the increase in the applied voltage; detecting a second time at which the applied second voltage meets the second threshold voltage associated with the second chalcogenide element; detecting a second state of the oscillating signal as of the second time at which the applied second voltage meets the second threshold voltage; outputting a second logic value based at least in part on the second state of the oscillating signal as of the second time at which the applied second voltage meets the second threshold voltage; and generating a multi-bit digital sequence using the logic value and the second logic value.

[0114] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 8, wherein the threshold voltage is within a threshold voltage range associated with the chalcogenide element, and when the applied voltage is within the threshold voltage range, the oscillating signal changes between a high state and a low state multiple times.

[0115] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 9, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for identifying, at a first time, a number of logic values ​​used at a second time that is later than the first time, wherein the logic value includes one of the number of logic values ​​used at the second time, and prior to the second time, storing the number of logic values ​​within the memory system for use at the second time.

[0116] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-10, wherein the oscillating signal has an unbalanced duty cycle.

[0117] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0118] A device is described. The following provides an overview of aspects of the device as described herein:

[0119] Aspect 12: An apparatus comprising: a chalcogenide element of a memory system; a voltage component configured to apply a voltage to the chalcogenide element at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element; a signal component configured to generate an oscillating signal; and a latch component configured to: detect when the applied voltage satisfies the threshold voltage associated with the chalcogenide element; detect a state of the oscillating signal as of the time the applied voltage satisfies the threshold voltage; and output a logic value based at least in part on the state of the oscillating signal as of the time the applied voltage satisfies the threshold voltage.

[0120] Aspect 13: The apparatus of claim 12, wherein the voltage component is further configured to cease applying the voltage to the chalcogenide element based at least in part on the applied voltage satisfying the threshold voltage associated with the chalcogenide element.

[0121] Aspect 14: The apparatus of Aspect 13, wherein: the voltage component is further configured to apply a second voltage to the chalcogenide element and increase the applied second voltage at least until the applied second voltage satisfies a second threshold voltage associated with the chalcogenide element; and the latch component is further configured to output a second logic value based at least in part on detecting a second state of the oscillating signal as of a second time at which the applied second voltage satisfies the second threshold voltage.

[0122] Aspect 15: The apparatus of aspect 14, wherein the latch component is further configured to generate a multi-bit digital sequence using the logic value and the second logic value.

[0123] Aspect 16: An apparatus according to any one of Aspects 12 to 15, wherein: the signal component is further configured to generate a plurality of oscillating signals; and the latch component is further configured to output a plurality of logic values ​​based at least in part on detecting a respective state of each of the plurality of oscillating signals up to the time when the applied voltage satisfies the threshold voltage, and the plurality of logic values ​​are used to generate a multi-bit digital sequence.

[0124] Aspect 17: The apparatus of aspect 16, wherein each oscillating signal of the plurality of oscillating signals is offset in phase or time from each other oscillating signal of the plurality of oscillating signals.

[0125] Aspect 18: The apparatus of any one of Aspects 12 to 17, further comprising: a second chalcogenide element of the memory system, wherein: the voltage component is further configured to apply the second voltage to the second chalcogenide element at least until the applied second voltage satisfies a second threshold voltage associated with the second chalcogenide element; and the latch component is further configured to: detect a second time at which the applied second voltage satisfies the second threshold voltage associated with the chalcogenide element; detect a second state of the oscillating signal as of the second time at which the applied second voltage satisfies the second threshold voltage; output a second logic value based at least in part on the second state of the oscillating signal as of the second time at which the applied second voltage satisfies the second threshold voltage; and generate a multi-bit digital sequence using the logic value and the second logic value.

[0126] Aspect 19: The apparatus of any one of aspects 12 to 18, wherein the threshold voltage is within a threshold voltage range associated with the chalcogenide element, and the oscillating signal is configured to change between a high state and a low state a plurality of times when the applied voltage is within the threshold voltage range.

[0127] Aspect 20: The apparatus of any of aspects 12-19, wherein the chalcogenide element is configured such that the threshold voltage exhibits random variation across different voltage applications.

[0128] A device is described. The following provides an overview of aspects of the device as described herein:

[0129] Aspect 21: An apparatus comprising: a chalcogenide element; a controller configured to cause the apparatus to increase a voltage applied to the chalcogenide element at least until the voltage satisfies a threshold voltage associated with the chalcogenide element; and a latch component configured to output a logic value based at least in part on a state of an oscillating signal as of the time the applied voltage satisfies the threshold voltage.

[0130] Aspect 22: The apparatus of Aspect 21, wherein: the controller is further configured to cause the apparatus, after ceasing to apply the voltage to the chalcogenide element, to increase a second voltage applied to the chalcogenide element, at least until the second voltage satisfies a second threshold voltage associated with the chalcogenide element; the latch component is further configured to output a second logic value based at least in part on a second state of the oscillating signal as of a second time at which the second voltage satisfies the second threshold voltage; and the apparatus further includes a sequence component configured to generate a multi-bit digital sequence using the logic value and the second logic value.

[0131] Aspect 23: An apparatus according to any one of Aspects 21 to 22, further comprising: a second latch component configured to output a second logic value based at least in part on a second state of a second oscillating signal up to the time at which the voltage satisfies the threshold voltage; and a sequence component configured to generate a multi-bit digital sequence using the logic value and the second logic value.

[0132] Aspect 24: The apparatus of any one of Aspects 21 to 23, further comprising: a second chalcogenide element, wherein the controller is further configured to cause the apparatus to increase a second voltage applied to the second chalcogenide element at least until the second voltage satisfies a second threshold voltage associated with the chalcogenide element; a second latch component configured to output a second logic value based at least in part on a second state of a second oscillating signal as of a second time at which the second voltage satisfies the second threshold voltage; and a sequence component configured to generate a multi-bit digital sequence using the logic value and the second logic value.

[0133] Aspect 25: The apparatus of any of aspects 21-24, further comprising: a detection component configured to detect the time when the applied voltage satisfies the threshold voltage based at least in part on a magnitude of a current associated with the chalcogenide element.

[0134] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have various bit widths.

[0135] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components may be considered to be in electronic communication with each other (or in conductive contact, connected, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact, connected, or coupled to each other) may be open or closed, depending on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components, such as switches or transistors.

[0136] The term "coupling" refers to a condition that transitions from an open-circuit relationship between components (where signals are currently unable to pass between the components via conductive paths) to a closed-circuit relationship between the components (where signals can pass between the components via conductive paths). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signal flow.

[0137] The term "isolation" refers to a relationship between components where signals are unable to flow between them. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is open, the components separated by the switch are isolated from one another. When a controller isolates two components, it causes a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0138] As used herein, the term "substantially" means that the modified property (eg, the verb or adjective modified by the term substantially) need not be absolute, but is close enough to achieve the advantage of the property.

[0139] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0140] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices, including a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "off" or "deactivated."

[0141] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0142] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label without regard to the second reference label.

[0143] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0144] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0145] As used herein, including in the claims, "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be understood as a reference to a closed set of conditions. For example, an example step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "based at least in part on."

[0146] Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired process code devices in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. In addition, any connection is properly referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are used to transmit software from a website, server, or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0147] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: applying a voltage to a chalcogenide element of the memory system; increasing the applied voltage at least until the applied voltage meets a threshold voltage associated with the chalcogenide element; detecting when the applied voltage meets the threshold voltage associated with the chalcogenide element; detecting a state of an oscillation signal up to the time when the applied voltage meets the threshold voltage; as well as A logical value is output based at least in part on the state of the oscillating signal up to the time when the applied voltage satisfies the threshold voltage.

2. The method according to claim 1, further comprising: Applying the voltage to the chalcogenide element of the memory system is ceased based at least in part on the applied voltage satisfying the threshold voltage associated with the chalcogenide element.

3. The method according to claim 2, further comprising: applying a second voltage to the chalcogenide element of the memory system after ceasing application of the voltage; increasing the applied second voltage at least until the applied second voltage satisfies a second threshold voltage associated with the chalcogenide element; detecting a second time when the applied voltage satisfies the second threshold voltage associated with the chalcogenide element; detecting a second state of the oscillation signal up to a second time when the applied second voltage meets the second threshold voltage; as well as A second logic value is output based at least in part on the second state of the oscillating signal by the second time the applied second voltage satisfies the second threshold voltage.

4. The method according to claim 3, further comprising: The logic value and the second logic value are used to generate a multi-bit digital sequence. 5 . The method of claim 3 , wherein the second threshold voltage is different from the threshold voltage based on random variations associated with the chalcogenide element.

6. The method according to claim 1, further comprising: detecting a second state of a second oscillating signal up to the time when the applied voltage meets the threshold voltage; outputting a second logic value based at least in part on the second state of the second oscillating signal up to the time when the applied voltage satisfies the threshold voltage; as well as The logic value and the second logic value are used to generate a multi-bit digital sequence.

7. The method of claim 6, wherein the second oscillating signal is offset from the oscillating signal in phase, time, frequency, or any combination thereof.

8. The method according to claim 1, further comprising: applying a second voltage to a second chalcogenide element of the memory system; increasing the applied second voltage at least until the applied second voltage satisfies a second threshold voltage associated with the second chalcogenide element, the increase in the applied second voltage being at least partially concurrent with the increase in the applied voltage; detecting a second time at which the applied second voltage satisfies the second threshold voltage associated with the second chalcogenide element; detecting a second state of the oscillation signal up to a second time when the applied second voltage meets the second threshold voltage; outputting a second logic value based at least in part on the second state of the oscillating signal as of the second time at which the applied second voltage satisfies the second threshold voltage; as well as The logic value and the second logic value are used to generate a multi-bit digital sequence.

9. The method of claim 1, wherein the threshold voltage is within a threshold voltage range associated with the chalcogenide element, and the oscillating signal changes between a high state and a low state a plurality of times when the applied voltage is within the threshold voltage range.

10. The method of claim 1, further comprising: identifying, at a first time, a number of logical values ​​used at a second time that is later than the first time, wherein the logical value comprises one of a set of logical values ​​used at the second time, the set of logical values ​​comprising the identified number of logical values; as well as Prior to the second time, the set of logic values ​​is stored within the memory system for use at the second time. The method of claim 1 , wherein the oscillating signal has an unbalanced duty cycle.

12. A device comprising: Chalcogenide components for memory systems; a voltage component configured to apply a voltage to the chalcogenide element at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element; a signal component configured to generate an oscillating signal; and A latch component configured to: detecting when the applied voltage meets the threshold voltage associated with the chalcogenide element; detecting a state of the oscillation signal up to the time when the applied voltage meets the threshold voltage; as well as A logical value is output based at least in part on the state of the oscillating signal up to the time when the applied voltage satisfies the threshold voltage.

13. The apparatus of claim 12, wherein the voltage component is further configured to cease applying the voltage to the chalcogenide element based at least in part on the applied voltage satisfying the threshold voltage associated with the chalcogenide element.

14. The apparatus of claim 13, wherein: The voltage component is further configured to apply a second voltage to the chalcogenide element and increase the applied second voltage at least until the applied second voltage satisfies a second threshold voltage associated with the chalcogenide element; and The latch component is further configured to output a second logic value based at least in part on detecting a second state of the oscillating signal by a second time that the applied second voltage satisfies the second threshold voltage.

15. The apparatus of claim 14, wherein the latch component is further configured to generate a multi-bit digital sequence using the logic value and the second logic value.

16. The apparatus of claim 12, wherein: The signal component is further configured to generate a plurality of oscillating signals; and The latch component is further configured to output a plurality of logic values ​​based at least in part on detecting a respective state of each of the plurality of oscillating signals up to a time when the applied voltage satisfies the threshold voltage, and to generate a multi-bit digital sequence using the plurality of logic values.

17. The apparatus of claim 16, wherein each oscillating signal of the plurality of oscillating signals is offset in phase or time from each other oscillating signal of the plurality of oscillating signals.

18. The apparatus of claim 12, further comprising: a second chalcogenide component of the memory system, wherein: The voltage component is further configured to apply a second voltage to the second chalcogenide element at least until the applied second voltage satisfies a second threshold voltage associated with the second chalcogenide element; and The latch component is further configured to: detecting a second time at which the applied second voltage satisfies the second threshold voltage associated with the chalcogenide element; detecting a second state of the oscillation signal up to a second time when the applied second voltage meets the second threshold voltage; outputting a second logic value based at least in part on the second state of the oscillating signal as of the second time the applied second voltage satisfies the second threshold voltage; and The logic value and the second logic value are used to generate a multi-bit digital sequence.

19. The apparatus of claim 12, wherein the threshold voltage is within a threshold voltage range associated with the chalcogenide element, and the oscillating signal is configured to change between a high state and a low state a plurality of times when the applied voltage is within the threshold voltage range.

20. The apparatus of claim 12, wherein the chalcogenide element is configured such that the threshold voltage exhibits random variation across different voltage applications.

21. An apparatus comprising: Chalcogenide components; a controller configured to cause the apparatus to increase a voltage applied to the chalcogenide element at least until the voltage satisfies a threshold voltage associated with the chalcogenide element; and A latch component is configured to output a logic value based at least in part on a state of an oscillating signal up to a time when the applied voltage meets the threshold voltage.

22. The apparatus of claim 21, wherein: The controller is further configured to cause the apparatus, after ceasing to apply the voltage to the chalcogenide element, to increase a second voltage applied to the chalcogenide element at least until the second voltage satisfies a second threshold voltage associated with the chalcogenide element; The latch component is further configured to output a second logic value based at least in part on a second state of the oscillating signal by a second time when the second voltage satisfies the second threshold voltage; and The apparatus further includes a sequence component configured to generate a multi-bit digital sequence using the logic value and the second logic value.

23. The apparatus of claim 21, further comprising: a second latch component configured to output a second logic value based at least in part on a second state of a second oscillating signal up to the time when the voltage satisfies the threshold voltage; and A sequence component is configured to generate a multi-bit digital sequence using the logic value and the second logic value.

24. The apparatus of claim 21, further comprising: a second chalcogenide element, wherein the controller is further configured to cause the apparatus to increase a second voltage applied to the second chalcogenide element at least until the second voltage satisfies a second threshold voltage associated with the chalcogenide element; a second latch component configured to output a second logic value based at least in part on a second state of a second oscillating signal as of a second time when the second voltage satisfies the second threshold voltage; and A sequence component is configured to generate a multi-bit digital sequence using the logic value and the second logic value.

25. The apparatus of claim 21, further comprising: A detection component is configured to detect the time when the applied voltage meets the threshold voltage based at least in part on a magnitude of a current associated with the chalcogenide element.

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