Heterojunction battery and preparation method thereof

Abstract

The present invention relates to the technical field of solar cells, and specifically provides a heterojunction solar cell and a preparation method thereof. The heterojunction solar cell comprises: a semiconductor substrate layer; a first conductive film layer, located on at least one side of the semiconductor substrate layer; a gate electrode, located on a side surface of a portion of the first conductive film layer away from the semiconductor substrate layer; a second conductive film layer, located on a side surface of a portion of the first conductive film layer away from the semiconductor substrate layer and surrounding the gate electrode, the orthographic projection of the second conductive film layer on the first conductive film layer and the orthographic projection of the gate electrode on the first conductive film layer together completely cover the surface of the first conductive film layer, and the second conductive film layer and the gate electrode are complementary in area relative to the first conductive film layer; the second conductive film layer and the gate electrode are electrically connected. The present invention ensures that the contact area between the gate electrode and the conductive film layer is increased while avoiding the increase in the shading area of ​​the gate electrode to the heterojunction solar cell, thereby improving the photoelectric conversion efficiency of the heterojunction solar cell.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell preparation, and in particular to a heterojunction cell and a preparation method thereof. Background Art

[0002] Heterojunction technology (HJT) is the most disruptive new technology for photovoltaic solar cells. It forms a PN junction between crystalline silicon and amorphous silicon thin film. Therefore, it has both the excellent light absorption performance of crystalline silicon cells and the passivation performance of thin film cells. It has multiple advantages such as high conversion efficiency, large efficiency improvement space, strong power generation capacity, and short process flow. From the conventional heterojunction solar cell structure, we can know that the heterojunction solar cell structure is usually composed of a stacked semiconductor substrate layer, a passivation layer, a doping layer, a transparent conductive film layer, and a gate electrode; from the process flow of conventional heterojunction solar cells, we can know that the gate electrode is formed after the transparent conductive film layer and is formed on the surface of the transparent conductive film layer. This structure determines that the gate electrode has only one contact surface with the transparent conductive film layer, and the contact area is mainly determined by the width of the gate electrode. The main function of the gate electrode is to collect and conduct the current generated by the heterojunction solar cell. In order to increase the gate electrode to collect more carriers and lead out current, the width of the gate electrode must be increased to increase the contact area between the gate electrode and the transparent conductive film layer.

[0003] However, increasing the width of the gate electrode will increase the light shielding area of ​​the gate electrode to the heterojunction solar cell, which will reduce the amount of photons of incident light entering the heterojunction solar cell, thereby causing poor photoelectric conversion efficiency of the heterojunction solar cell. Summary of the invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defect in the prior art that the gate line electrode has a large carrier collection rate, while the gate line electrode will also increase the shading area of ​​the heterojunction solar cell, resulting in poor photoelectric conversion efficiency of the heterojunction solar cell, thereby providing a heterojunction cell and a preparation method thereof.

[0005] The present invention provides a heterojunction solar cell, comprising: a semiconductor substrate layer; a first conductive film layer, located on at least one side of the semiconductor substrate layer; a gate electrode, located on a surface of a portion of the first conductive film layer away from the semiconductor substrate layer; a second conductive film layer, located on a surface of a portion of the first conductive film layer away from the semiconductor substrate layer and surrounding the gate electrode, wherein the orthographic projection of the second conductive film layer on the first conductive film layer and the orthographic projection of the gate electrode on the first conductive film layer together completely cover the surface of the first conductive film layer, and the second conductive film layer and the gate electrode are complementary in area relative to the first conductive film layer; and the second conductive film layer and the gate electrode are electrically connected.

[0006] Optionally, the orthographic projection area of ​​the gate line electrode on the first conductive film layer is less than or equal to 50% of the surface area of ​​the first conductive film layer; and the width of the gate line electrode is 5 μm-50 μm.

[0007] Optionally, the thickness of the second conductive film layer is less than the height of the gate line electrode; the thickness of the second conductive film layer is 0.03%-3.6% of the height of the gate line electrode; the height of the gate line electrode is 5 μm-30 μm.

[0008] Optionally, the sum of the thickness of the first conductive film layer and the thickness of the second conductive film layer is 20nm-200nm; the thickness of the first conductive film layer is 1nm-80nm; and the thickness of the second conductive film layer is 10nm-180nm.

[0009] Optionally, the first conductive film layer includes one or more of an indium oxide layer doped with tin, an indium oxide layer doped with tungsten, a zinc oxide layer doped with aluminum, a tin oxide layer doped with fluorine, a tin oxide layer doped with antimony, a silicon dioxide layer, and a silicon nitride layer; the second conductive film layer includes one or more of an indium oxide layer doped with tin, an indium oxide layer doped with tungsten, a zinc oxide layer doped with aluminum, a tin oxide layer doped with fluorine, a tin oxide layer doped with antimony, a silicon dioxide layer, and a silicon nitride layer.

[0010] Optionally, it also includes: an intrinsic semiconductor layer located between the semiconductor substrate layer and the first conductive film layer; and a doped semiconductor layer located between the intrinsic semiconductor layer and the first conductive film layer.

[0011] The present invention provides a method for preparing a heterojunction solar cell, comprising: providing a semiconductor substrate layer; forming a first conductive film layer on at least one side of the semiconductor substrate layer; forming a gate electrode on a surface of a part of the first conductive film layer away from the semiconductor substrate layer; forming a second conductive film layer on a surface of a part of the first conductive film layer away from the semiconductor substrate layer, wherein the second conductive film layer surrounds the gate electrode, an orthographic projection of the second conductive film layer on the first conductive film layer and an orthographic projection of the gate electrode on the first conductive film layer together completely cover the surface of the first conductive film layer, and the second conductive film layer and the gate electrode are complementary in area relative to the first conductive film layer; and the second conductive film layer and the gate electrode are electrically connected.

[0012] Optionally, the process of forming the first conductive film layer and the process of forming the second conductive film layer both include a magnetron sputtering process; the parameters of forming the first conductive film layer and the process of forming the second conductive film layer both include: the gas used includes a mixed gas of oxygen and argon, and the chamber pressure is 0.1Pa-10Pa; in the process of forming the first conductive film layer and the process of forming the second conductive film layer, the flow rate of the oxygen is 0sccm-200sccm, and the flow rate of the argon is 100sccm-3000sccm; the power of forming the first conductive film layer and the process of forming the second conductive film layer is 1000W-10000W; the temperature of forming the first conductive film layer and the process of forming the second conductive film layer is 100℃-500℃.

[0013] Optionally, during the process of forming the second conductive film layer, a surface of the gate line electrode away from the semiconductor substrate layer is shielded.

[0014] Optionally, before forming the first conductive film layer on at least one side of the semiconductor substrate layer, the method further includes: forming an intrinsic semiconductor layer on at least one side of the semiconductor substrate layer, wherein the intrinsic semiconductor layer is located between the semiconductor substrate layer and the first conductive film layer; and forming a doped semiconductor layer on a side of the intrinsic semiconductor layer away from the semiconductor substrate layer, wherein the doped semiconductor layer is located between the intrinsic semiconductor layer and the first conductive film layer.

[0015] The beneficial effects of the present invention are:

[0016] The present invention provides a heterojunction solar cell, wherein a gate electrode is located on a side surface of a portion of the first conductive film layer away from the semiconductor substrate layer, and the bottom surface of the gate electrode contacts a portion of the first conductive film layer; a second conductive film layer is arranged on a side surface of a portion of the first conductive film layer away from the semiconductor substrate layer and surrounds the gate electrode, the orthographic projection of the second conductive film layer on the first conductive film layer and the orthographic projection of the gate electrode on the first conductive film layer together completely cover the surface of the first conductive film layer, and the second conductive film layer and the gate electrode are complementary in area relative to the first conductive film layer; and the second conductive film layer The layer is electrically connected to the gate electrode, so that the contact area between the gate electrode and the conductive film layer is increased. On the one hand, the mechanical strength between the gate electrode and the heterojunction solar cell is increased, and the reliability of the gate electrode pulling force is improved. On the other hand, the series resistance of the heterojunction solar cell is reduced, and the probability of the gate electrode collecting carriers is increased, thereby increasing the extraction current and improving the performance of the heterojunction solar cell. Secondly, there is no need to increase the width of the gate electrode, which can avoid increasing the shading area of ​​the heterojunction solar cell by the gate electrode, increase the amount of photons of incident light entering the heterojunction solar cell, and thus improve the photoelectric conversion efficiency of the heterojunction solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 Schematic diagram of the structure of a heterojunction solar cell in Example 1 of the present invention;

[0019] Figure 2 This is a flow chart of a method for preparing a heterojunction solar cell in Example 2 of the present invention.

[0020] Reference numerals:

[0021] 11-semiconductor substrate layer; 21-first intrinsic semiconductor layer; 31-first doped semiconductor layer; 61-front conductive film layer; 41-first conductive film layer; 51-second conductive film layer; 71-gate line electrode; 22-second intrinsic semiconductor layer; 32-second doped semiconductor layer; 62-back conductive film layer. DETAILED DESCRIPTION

[0022] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0024] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] Example 1

[0027] This embodiment provides a heterojunction solar cell, referring to Figure 1 , including: a semiconductor substrate layer 11; a first conductive film layer 41, located on at least one side of the semiconductor substrate layer 11; a gate line electrode 71, located on a side surface of a portion of the first conductive film layer 41 away from the semiconductor substrate layer 11; a second conductive film layer 51, located on a side surface of a portion of the first conductive film layer 41 away from the semiconductor substrate layer 11 and surrounding the gate line electrode 71, the orthographic projection of the second conductive film layer 51 on the first conductive film layer 41 and the orthographic projection of the gate line electrode 71 on the first conductive film layer 41 together completely cover the surface of the first conductive film layer 41, and the second conductive film layer 51 and the gate line electrode 71 are complementary in area relative to the first conductive film layer 41; and the second conductive film layer 51 and the gate line electrode 71 are electrically connected.

[0028] In this embodiment, the gate line electrode 71 is located on a side surface of a portion of the first conductive film layer 41 away from the semiconductor substrate layer 11, and the bottom surface of the gate line electrode 71 is in contact with a portion of the first conductive film layer 41; a second conductive film layer 51 is provided on a side surface of a portion of the first conductive film layer 41 away from the semiconductor substrate layer 11 and surrounding the gate line electrode 71, the orthographic projection of the second conductive film layer 51 on the first conductive film layer 41 and the orthographic projection of the gate line electrode 71 on the first conductive film layer 41 together completely cover the surface of the first conductive film layer 41, and the second conductive film layer 51 and the gate line electrode 71 are complementary in area relative to the first conductive film layer 41; the second conductive film layer 51 and the gate line electrode 71 are complementary in area relative to the first conductive film layer 41; The second conductive film layer 51 is electrically connected to the gate electrode 71, so that the contact area between the gate electrode 71 and the conductive film layer is increased. On the one hand, the mechanical strength between the gate electrode 71 and the heterojunction solar cell is increased, and the reliability of the tension of the gate electrode 71 is improved. On the other hand, the series resistance of the heterojunction solar cell is reduced, and the probability of the gate electrode 71 collecting carriers is increased, thereby increasing the extraction current and improving the performance of the heterojunction solar cell. Secondly, there is no need to increase the width of the gate electrode 71, which can avoid increasing the shading area of ​​the heterojunction solar cell by the gate electrode 71, increase the amount of photons of the incident light entering the heterojunction solar cell, and thus improve the photoelectric conversion efficiency of the heterojunction solar cell.

[0029] It should be noted that the semiconductor substrate layer has a first surface and a second surface that are arranged opposite to each other. In the present embodiment, the first conductive film layer 41 and the second conductive film layer 51 are both located on one side of the first surface of the semiconductor substrate layer 11; and, in the present embodiment, the first surface is the front side of the heterojunction solar cell, and the second surface is the back side of the heterojunction solar cell, wherein the front side refers to the light-facing side of the heterojunction solar cell, and the back side refers to the backlight side of the heterojunction solar cell.

[0030] In other embodiments, the first conductive film layer may be located on the second surface side of the semiconductor substrate layer, and the second conductive film layer may be located on the second surface side of the semiconductor substrate layer; the first surface may be the back side of the heterojunction solar cell, and the second surface may be the front side of the heterojunction solar cell.

[0031] In this embodiment, continue to refer to Figure 1, the heterojunction solar cell further comprises: a first conductive film layer 41 and a second conductive film layer 51 located on one side of the second surface of the semiconductor substrate layer 11. The heterojunction solar cell further comprises: a gate electrode 71 located on a side surface of a portion of the first conductive film layer 41 away from the semiconductor substrate layer 11; a second conductive film layer 51 located on a side surface of a portion of the first conductive film layer 41 away from the semiconductor substrate layer 11 and surrounding the gate electrode 71, the orthographic projection of the second conductive film layer 51 on the first conductive film layer 41 and the orthographic projection of the gate electrode 71 on the first conductive film layer 41 together completely cover the surface of the first conductive film layer 41; and the second conductive film layer and the gate electrode are complementary in area relative to the first conductive film layer, and the second conductive film layer 51 and the gate electrode 71 are electrically connected.

[0032] It should be noted that the gate electrode 71 is located on the first surface side of the semiconductor substrate layer 11, that is, the gate electrode on the front side of the heterojunction solar cell; the gate electrode 71 is located on the second surface side of the semiconductor substrate layer 11, that is, the gate electrode on the back side of the heterojunction solar cell. The first conductive film layer 41 and the second conductive film layer 51 are located on the first surface side of the semiconductor substrate layer 11, that is, the first conductive film layer 41 and the second conductive film layer 51 are located on the front side of the heterojunction solar cell; the first conductive film layer 41 and the second conductive film layer 51 are located on the second surface side of the semiconductor substrate layer 11, that is, the first conductive film layer 41 and the second conductive film layer 51 are located on the back side of the heterojunction solar cell.

[0033] The first conductive film layer 41 and the second conductive film layer 51 constitute a front conductive film layer 61 of a heterojunction solar cell; the first conductive film layer 41 and the second conductive film layer 51 constitute a back conductive film layer 62 of a heterojunction solar cell.

[0034] In one embodiment, the orthographic projection area of ​​the gate electrode 71 on the first conductive film layer 41 is less than or equal to 50% of the surface area of ​​the first conductive film layer 41. The smaller the orthographic projection area of ​​the gate electrode 71 on the first conductive film layer 41, the better the effect of preventing the gate electrode 71 from increasing the shading area of ​​the heterojunction solar cell.

[0035] In this embodiment, the orthographic projection area of ​​the gate electrode 71 on the first conductive film layer 41 is less than or equal to 50% of the surface area of ​​the first conductive film layer 41. The smaller the orthographic projection area of ​​the gate electrode 72 on the first conductive film layer 41, the better the effect of preventing the gate electrode 71 from increasing the shading area of ​​the heterojunction solar cell.

[0036] In one embodiment, the width of the gate electrode 71 is 5 μm-50 μm. The width of the gate electrode 71 should be as small as possible, so that the shielding area of ​​the gate electrode 71 to the heterojunction solar cell is smaller, the more photons of incident light enter the heterojunction solar cell, and the higher the photoelectric conversion efficiency of the heterojunction solar cell.

[0037] In one embodiment, the thickness of the second conductive film layer 51 is less than the height of the gate electrode 71. The purpose is to avoid disposing the second conductive film layer 51 close to the surface of the gate electrode 71 away from the semiconductor substrate layer 11 to avoid weakening the conductive performance of the gate electrode 71.

[0038] Specifically, the thickness of the second conductive film layer 51 is 0.03%-3.6% of the height of the gate line electrode 71 , for example, 0.03%, 0.06%, 1%, 1.3%, 1.6%, 2%, 2.5%, 3% or 3.6%.

[0039] In one embodiment, the height of the gate electrode 71 is 5 μm-30 μm, for example, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm or 30 μm. If the height of the gate electrode 71 is too small, the conductive performance of the gate electrode 71 is weak; if the height of the gate electrode 71 is too large, more slurry is required, and the process cost is high.

[0040] In one embodiment, the sum of the thickness of the first conductive film layer 41 and the thickness of the second conductive film layer 51 is 20 nm-200 nm, for example, 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 130 nm, 160 nm or 200 nm.

[0041] Specifically, the thickness of the first conductive film layer 41 is 1nm-80nm, for example, 1nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm or 80nm; the thickness of the second conductive film layer 51 is 10nm-180nm, for example, 10nm, 30nm, 60nm, 90nm, 110nm, 130nm, 150nm or 180nm.

[0042] In one embodiment, the first conductive film layer 41 includes one or more of an indium oxide layer doped with tin, an indium oxide layer doped with tungsten, a zinc oxide layer doped with aluminum, a tin oxide layer doped with fluorine, a tin oxide layer doped with antimony, a silicon dioxide layer, and a silicon nitride layer; the second conductive film layer 51 includes one or more of an indium oxide layer doped with tin, an indium oxide layer doped with tungsten, a zinc oxide layer doped with aluminum, a tin oxide layer doped with fluorine, a tin oxide layer doped with antimony, a silicon dioxide layer, and a silicon nitride layer.

[0043] In one embodiment, taking the first conductive film layer 41 and the second conductive film layer 51 as an example where both the first conductive film layer 41 and the second conductive film layer 51 are indium oxide layers doped with tin, the mass ratio of tin to indium in the indium oxide layers doped with tin is 0.01-0.1, for example, 0.01, 0.03, 0.06, 0.09 or 0.1.

[0044] It should be noted that although silicon dioxide and silicon nitride are non-conductive, when the first conductive film layer 41 is a silicon dioxide layer or a silicon nitride layer and the second conductive film layer 51 is a silicon dioxide layer or a silicon nitride layer, and the first conductive film layer 41 and / or the second conductive film layer 51 are very thin (single-digit nanometer level), a special tunneling effect will occur, and carriers can pass through the first conductive film layer 41 and / or the second conductive film layer 51 and be collected by the gate line electrode 71.

[0045] In this embodiment, the heterojunction solar cell further includes: an intrinsic semiconductor layer located between the semiconductor substrate layer and the first conductive film layer; and a doped semiconductor layer located between the intrinsic semiconductor layer and the first conductive film layer.

[0046] Specifically, refer to Figure 1 The intrinsic semiconductor layer includes a first intrinsic semiconductor layer 21 and a second intrinsic semiconductor layer 22; the first intrinsic semiconductor layer 21 is located between the semiconductor substrate layer 11 and the first conductive film layer 41; the second intrinsic semiconductor layer 22 is located between the semiconductor substrate layer 11 and the first conductive film layer 41. The doped semiconductor layer includes a first doped semiconductor layer 31 and a second doped semiconductor layer 32; the first doped semiconductor layer 31 is located between the first intrinsic semiconductor layer 21 and the first conductive film layer 41; the second doped semiconductor layer 32 is located between the second intrinsic semiconductor layer 22 and the first conductive film layer 41.

[0047] Example 2

[0048] This embodiment provides a method for preparing a heterojunction solar cell. Figure 2 ,include:

[0049] S1: providing a semiconductor substrate layer;

[0050] S2: forming a first conductive film layer on at least one side of the semiconductor substrate layer;

[0051] S3: forming a gate line electrode on a surface of a portion of the first conductive film layer away from the semiconductor substrate layer;

[0052] S4: A second conductive film layer is formed on a surface of a portion of the first conductive film layer away from the semiconductor substrate layer, the second conductive film layer surrounds the gate line electrode, the orthographic projection of the second conductive film layer on the first conductive film layer and the orthographic projection of the gate line electrode on the first conductive film layer together completely cover the surface of the first conductive film layer, and the second conductive film layer and the gate line electrode are complementary in area relative to the first conductive film layer; the second conductive film layer and the gate line electrode are electrically connected.

[0053] In this embodiment, after the gate electrode 71 is formed on the surface of a part of the first conductive film layer 41 away from the semiconductor substrate layer 11, the bottom surface of the gate electrode 71 contacts the part of the first conductive film layer 41; after the second conductive film layer 51 is formed on the surface of a part of the first conductive film layer 41 away from the semiconductor substrate layer 11, the second conductive film layer 51 surrounds the part of the gate electrode 71, the orthographic projection of the second conductive film layer 51 on the first conductive film layer 41 and the orthographic projection of the gate electrode 71 on the first conductive film layer 41 together completely cover the surface of the first conductive film layer 41, and the second conductive film layer 51 and the gate electrode 71 are complementary in area relative to the first conductive film layer 41; the second conductive film layer 51 and the gate electrode 71 are electrically connected, so that the contact area between the gate electrode 71 and the conductive film layer is increased without increasing the width of the gate electrode 71, which can avoid increasing the shading area of ​​the heterojunction solar cell by the gate electrode 71, increase the amount of photons of incident light entering the heterojunction solar cell, and thus improve the photoelectric conversion efficiency of the heterojunction solar cell.

[0054] In the present embodiment, the processes for forming the first conductive film layer 41 and the processes for forming the second conductive film layer 51 both include a magnetron sputtering process. Specifically, the parameters for forming the first conductive film layer 41 and the processes for forming the second conductive film layer 51 both include: the gas used includes a mixed gas of oxygen and argon, the chamber pressure is 0.1Pa-10Pa, for example, 0.1Pa, 0.5Pa, 1Pa, 3Pa, 5Pa, 7Pa, 9Pa or 10Pa; in the processes for forming the first conductive film layer 41 and the processes for forming the second conductive film layer 51, the flow rate of the oxygen is 0sccm-200sccm, for example, 10sccm, 50sccm, 100sccm, 150sccm or 200sccm, and the flow rate of the argon is 100sccm-3000sccm, for example, 100sccm, 500sccm, 1000sccm, 1500sccm, 2000sccm, 2500sccm or 3000sccm; the powers for forming the first conductive film layer and the second conductive film layer are both 1000W-10000W, for example, 1000W, 3000W, 6000W, 9000W or 10000W; the temperatures for forming the first conductive film layer and the second conductive film layer are both 100℃-500℃, for example, 100℃, 200℃, 300℃, 400℃ or 500℃.

[0055] In other embodiments, the processes for forming the first conductive film layer and the second conductive film layer both include a chemical vapor deposition process or a pulsed laser deposition process. The parameters for forming the first conductive film layer and the second conductive film layer include: using water vapor. The water vapor can introduce H atoms and O atoms during the process, and the H atoms and O atoms are conducive to forming a denser first conductive film layer and a second conductive film layer during the process.

[0056] It should be noted that, in the process of forming the first conductive film layer 41, the first conductive film layer 41 can be formed by one deposition or multiple depositions, and in the process of forming the second conductive film layer 51, the second conductive film layer 51 can be formed by one deposition or multiple depositions.

[0057] In one embodiment, taking the first conductive film layer 41 and the second conductive film layer 51 as an example where both the first conductive film layer 41 and the second conductive film layer 51 are indium oxide layers doped with tin, the mass ratio of tin to indium in the indium oxide layers doped with tin is 0.01-0.1, for example, 0.01, 0.03, 0.06, 0.09 or 0.1.

[0058] In this embodiment, during the formation of the second conductive film layer 51, the surface of the gate electrode 71 away from the semiconductor substrate layer 11 is shielded. The main purpose is to prevent the second conductive film layer 51 from being deposited on the top surface of the gate electrode 71 to avoid weakening the conductive performance of the gate line.

[0059] In one embodiment, the step of shielding the surface of the gate electrode 71 away from the semiconductor substrate layer 11 includes: providing a mask; forming a mask on the surface of the gate electrode 71 away from the semiconductor substrate layer 11. Under the protection of the mask, a second conductive film layer is formed on a surface of a part of the first conductive film layer away from the semiconductor substrate layer.

[0060] In one embodiment, before forming the first conductive film layer 41 on at least one side of the semiconductor substrate layer 11, it also includes: forming an intrinsic semiconductor layer on at least one side of the semiconductor substrate layer 11, wherein the intrinsic semiconductor layer is located between the semiconductor substrate layer and the first conductive film layer; and forming a doped semiconductor layer on a side of the intrinsic semiconductor layer away from the semiconductor substrate layer, wherein the doped semiconductor layer is located between the intrinsic semiconductor layer and the first conductive film layer.

[0061] Specifically, refer to Figure 1 Before forming the first conductive film layer 41 on one side of the first surface of the semiconductor substrate layer 11, the method further includes: forming a first intrinsic semiconductor layer 21 on the first surface of the semiconductor substrate layer 11, wherein the first intrinsic semiconductor layer 21 is located between the semiconductor substrate layer 11 and the first conductive film layer 41; and forming a first doped semiconductor layer 31 on a surface of the first intrinsic semiconductor layer 21 away from the semiconductor substrate layer 11, wherein the first doped semiconductor layer 31 is located between the first intrinsic semiconductor layer 21 and the first conductive film layer 41.

[0062] The heterojunction solar cell also includes: a first conductive film layer 41 is formed on one side of the second surface of the semiconductor substrate layer 11; a gate electrode 72 is formed on a surface of a portion of the first conductive film layer 41 away from the semiconductor substrate layer 11; a second conductive film layer 51 is formed on a surface of a portion of the first conductive film layer 41 away from the semiconductor substrate layer 11, the second conductive film layer 51 surrounds the gate electrode 71, the orthographic projection of the second conductive film layer 51 on the first conductive film layer 41 and the orthographic projection of the gate electrode 71 on the first conductive film layer 41 together completely cover the surface of the first conductive film layer 41; and the second conductive film layer and the gate electrode are complementary in area relative to the first conductive film layer, and the second conductive film layer 51 and the gate electrode 71 are electrically connected.

[0063] Before forming the first conductive film layer 41 on one side of the second surface of the semiconductor substrate layer 11, the heterojunction solar cell also includes: forming a second intrinsic semiconductor layer 22 on the second surface of the semiconductor substrate layer 11, the second intrinsic semiconductor layer 22 is located between the semiconductor substrate layer 11 and the first conductive film layer 41; forming a second doped semiconductor layer 32 on a surface of the second intrinsic semiconductor layer 22 away from the semiconductor substrate layer 11, the second doped semiconductor layer 32 is located between the second intrinsic semiconductor layer 22 and the first conductive film layer 41.

[0064] It should be noted that the process of forming the first conductive film layer 41 is the same as that of forming the first conductive film layer 41 and the parameters are the same; the process of forming the second conductive film layer 51 is the same as that of forming the second conductive film layer 51 and the parameters are the same; the process of forming the first intrinsic semiconductor layer 21 and the process of forming the second intrinsic semiconductor layer 22 are the same, and the process of forming the first doped semiconductor layer 31 and the process of forming the second doped semiconductor layer 32 are the same, and they are all conventional technologies in the field and will not be repeated here.

[0065] The process of forming the gate line electrode 71 includes a screen printing process or an evaporation coating process.

[0066] In one embodiment, the material of the gate line electrodes 71 includes silver.

[0067] The method for preparing a heterojunction solar cell further includes: before forming an intrinsic semiconductor layer on at least one side of the semiconductor substrate layer 11, performing a cleaning and texturing treatment on the semiconductor substrate layer 11. The cleaning and texturing treatment includes performing a surface pre-cleaning treatment and a texturing treatment on the semiconductor substrate layer 11. The surface pre-cleaning treatment and the texturing treatment are both conventional techniques in the art and will not be described in detail herein.

[0068] The present invention is different from the existing heterojunction solar cell, and the contact area between the gate electrode and the conductive film layer can be increased without increasing the width of the gate electrode. Specifically, the gate electrode is arranged on the surface of a part of the first conductive film layer away from the semiconductor substrate layer; the second conductive film layer is arranged on the surface of a part of the first conductive film layer away from the semiconductor substrate layer, and the second conductive film layer surrounds the gate electrode, so that the positive projection of the second conductive film layer on the first conductive film layer and the positive projection of the gate electrode on the first conductive film layer completely cover the surface of the first conductive film layer, and the second conductive film layer and the gate electrode form an electrical connection, and the contact area between the gate electrode and the conductive film layer can be increased without increasing the width of the gate electrode, so the probability of the gate electrode shading the heterojunction solar cell is small, and the photoelectric conversion efficiency of the heterojunction solar cell is improved; the contact area between the gate electrode and the conductive film layer is increased, so that the gate electrode has a large carrier collection rate, and the short-circuit current of the heterojunction solar cell is improved.

[0069] According to the test, compared with the existing heterojunction solar cells, the short-circuit current of the heterojunction solar cells provided by the present invention can be increased by 100mA-1500mA, and the photoelectric conversion efficiency can be increased by 0.2%-3%. The specific experimental data comparison effect is shown in the following table:

[0070] Grouping Eta(%) FF(%) Voc(mV) Isc(A) Experimental Group 1 25.22 84.40 748.7 10.942 Experimental Group 2 25.09 84.27 748.6 10.902 Control group 24.72 84.08 747.7 10.780

[0071] Among them, the control group is a heterojunction solar cell prepared by the existing technology, and the experimental group 1 and the experimental group 2 are heterojunction solar cells prepared by the above-mentioned heterojunction solar cell preparation method. Voc is the open circuit voltage, Isc is the short circuit current, FF is the fill factor, and Eta is the conversion efficiency.

[0072] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A heterojunction solar cell, characterized in that: include: Semiconductor substrate layer; A first conductive film layer, located on at least one side of the semiconductor substrate layer; A gate line electrode is located on a surface of a portion of the first conductive film layer away from the semiconductor substrate layer; A second conductive film layer is located on a side surface of a portion of the first conductive film layer away from the semiconductor substrate layer and surrounds the gate electrode, an orthographic projection of the second conductive film layer on the first conductive film layer and an orthographic projection of the gate electrode on the first conductive film layer together completely cover the surface of the first conductive film layer, and the second conductive film layer and the gate electrode are complementary in area relative to the first conductive film layer; the second conductive film layer and the gate electrode are electrically connected; The orthographic projection area of ​​the gate line electrode on the first conductive film layer is less than or equal to 50% of the surface area of ​​the first conductive film layer; the width of the gate line electrode is 5 μm-50 μm; The thickness of the second conductive film layer is less than the height of the gate line electrode; the thickness of the second conductive film layer is 0.03%-3.6% of the height of the gate line electrode; The height of the gate line electrode is 5 μm-30 μm; The sum of the thickness of the first conductive film layer and the thickness of the second conductive film layer is 20nm-200nm; The thickness of the first conductive film layer is 1nm-80nm; the thickness of the second conductive film layer is 10nm-180nm.

2. The heterojunction solar cell according to claim 1, characterized in that: The first conductive film layer includes one or more of an indium oxide layer doped with tin, an indium oxide layer doped with tungsten, a zinc oxide layer doped with aluminum, a tin oxide layer doped with fluorine, a tin oxide layer doped with antimony, a silicon dioxide layer, and a silicon nitride layer; The second conductive film layer includes one or more of an indium oxide layer doped with tin, an indium oxide layer doped with tungsten, a zinc oxide layer doped with aluminum, a tin oxide layer doped with fluorine, a tin oxide layer doped with antimony, a silicon dioxide layer, and a silicon nitride layer.

3. The heterojunction solar cell according to claim 1, characterized in that: Also includes: An intrinsic semiconductor layer, located between the semiconductor substrate layer and the first conductive film layer; The doped semiconductor layer is located between the intrinsic semiconductor layer and the first conductive film layer.

4. A method for preparing a heterojunction solar cell, for preparing the heterojunction solar cell according to claim 1, characterized in that: The method comprises: providing a semiconductor substrate layer; forming a first conductive film layer on at least one side of the semiconductor substrate layer; forming a gate line electrode on a surface of a portion of the first conductive film layer away from the semiconductor substrate layer; A second conductive film layer is formed on a surface of a portion of the first conductive film layer away from the semiconductor substrate layer, the second conductive film layer surrounds the gate line electrode, the orthographic projection of the second conductive film layer on the first conductive film layer and the orthographic projection of the gate line electrode on the first conductive film layer together completely cover the surface of the first conductive film layer, and the second conductive film layer and the gate line electrode are complementary in area relative to the first conductive film layer; the second conductive film layer and the gate line electrode are electrically connected.

5. The method for preparing a heterojunction solar cell according to claim 4, characterized in that: The processes of forming the first conductive film layer and forming the second conductive film layer both include a magnetron sputtering process; The parameters for forming the first conductive film layer and the second conductive film layer include: the gas used includes a mixed gas of oxygen and argon, and the chamber pressure is 0.1Pa-10Pa; In the process of forming the first conductive film layer and forming the second conductive film layer, the flow rate of the oxygen gas is 0 sccm-200 sccm, and the flow rate of the argon gas is 100 sccm-3000 sccm; The power for forming the first conductive film layer and the power for forming the second conductive film layer are both 1000W-10000W; the temperature for forming the first conductive film layer and the temperature for forming the second conductive film layer are both 100°C-500°C.

6. The method for preparing a heterojunction solar cell according to claim 4, characterized in that: During the process of forming the second conductive film layer, the surface of the gate line electrode away from the semiconductor substrate layer is shielded.

7. The method for preparing a heterojunction solar cell according to claim 4, characterized in that: Before forming the first conductive film layer on at least one side of the semiconductor substrate layer, the method further includes: Forming an intrinsic semiconductor layer on at least one side surface of the semiconductor substrate layer, wherein the intrinsic semiconductor layer is located between the semiconductor substrate layer and the first conductive film layer; A doped semiconductor layer is formed on a surface of the intrinsic semiconductor layer away from the semiconductor substrate layer, and the doped semiconductor layer is located between the intrinsic semiconductor layer and the first conductive film layer.

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