Circuit and method for calibrating a digital-to-analog converter

Abstract

The present disclosure relates to circuits and methods for calibrating a digital-to-analog converter. An apparatus includes a digital-to-analog converter (DAC) configured to convert a digital signal to an analog signal. In an aspect, the apparatus includes a first circuit configured to generate a first signal. In an aspect, the apparatus includes a second circuit coupled to the first circuit. The second circuit can be configured to generate a second signal based on the first signal. The second signal can have a first edge according to the first signal. In an aspect, the apparatus includes a third circuit coupled to the second circuit. The third circuit can be configured to generate a third signal having a second edge in response to the first edge of the second signal. In an aspect, an amplitude of the third signal can correspond to 1 bit.

Description

Technical Field

[0001] This disclosure generally relates to systems and methods for digital-to-analog conversion, and more specifically, to calibration for digital-to-analog conversion. Background Technology

[0002] A digital-to-analog converter (DAC) is a circuit that converts a first signal represented digitally into a second signal represented analogly. The signal can be one or more voltages, one or more currents, or any combination thereof. An analog signal (or analog analog representation) indicates data values ​​from a continuous range of values, while a digital signal (or digital representation) indicates data values ​​from a finite set of values. Analog signals can provide a more accurate representation of data (e.g., audio data, image data, video data, or any data) than digital signals because digital signals are obtained through quantization involving certain numbers of truncated values. However, analog signals are more susceptible to noise than digital signals. Summary of the Invention

[0003] The various embodiments disclosed herein relate to an apparatus. In some embodiments, the apparatus includes a first circuit configured to generate a first signal. In some embodiments, the apparatus includes a second circuit coupled to the first circuit. In some embodiments, the second circuit is configured to generate a second signal based on the first signal. The second signal may have a first edge relative to the first signal. In some embodiments, the apparatus includes a third circuit coupled to the second circuit. In some embodiments, the third circuit is configured to generate a third signal having a second edge in response to the first edge of the second signal. The amplitude of the third signal may correspond to one bit.

[0004] In some embodiments, the second circuit includes a fourth circuit configured to provide a first drive strength of the second circuit according to the first signal. In some embodiments, the second circuit is configured to generate the first edge of the second signal according to the first drive strength.

[0005] In some embodiments, the first circuit is configured to generate a fourth signal. In some embodiments, the second circuit includes a fifth circuit configured to provide a second drive strength of the second circuit according to the fourth signal. In some embodiments, the second circuit is configured to generate a third edge of the second signal according to the second drive strength. In some embodiments, the third edge of the second signal follows the first edge of the second signal. In some embodiments, the third circuit is configured to generate a fourth edge of the third signal in response to the third edge of the second signal. In some embodiments, the fourth edge follows the second edge of the third signal.

[0006] In some embodiments, the fourth circuit includes a first transistor configured to provide a second drive strength. In some embodiments, the fourth circuit includes a second transistor configured to provide a third drive strength. In some embodiments, the fourth circuit is configured to provide the first drive strength based on the second drive strength and the third drive strength.

[0007] In some embodiments, the fourth circuit includes a third transistor series coupled to the first transistor. The third transistor can be configured to enable or disable the first transistor based on the one bit. In some embodiments, the fourth circuit includes a fourth transistor series coupled to the second transistor. The fourth transistor can be configured to enable or disable the second transistor based on the one bit.

[0008] In some embodiments, the first signal includes a first voltage applied to the first gate electrode of the first transistor. The first voltage corresponds to the second drive strength. In some embodiments, the first signal includes a second voltage applied to the second gate electrode of the second transistor. The second voltage may correspond to the third drive strength.

[0009] In some embodiments, the first circuit includes a first multiplexer configured to select a third voltage from a first group of voltages. In some embodiments, the first circuit includes a second multiplexer configured to select a fourth voltage from a second group of voltages. In some embodiments, the first circuit includes a third multiplexer configured to select either the third voltage or the fourth voltage as the first voltage. In some embodiments, the first circuit includes a fourth multiplexer configured to select either the third voltage or the fourth voltage as the second voltage.

[0010] In some embodiments, the first circuit is configured to provide a fourth signal to the third circuit. In some embodiments, the third circuit is configured to set the amplitude of the third signal according to the fourth signal.

[0011] In some embodiments, the third circuit includes a fifth circuit configured to set a first current in the third circuit according to the fourth signal. The amplitude of the third signal may be set according to the first current.

[0012] In some embodiments, the fifth circuit includes a third transistor configured to provide a second current. In some embodiments, the fifth circuit includes a fourth transistor configured to provide a third current. The fifth circuit may be configured to provide the first current based on the second current and the third current.

[0013] In some embodiments, the fifth circuit includes a resistor coupled to the third transistor and the fourth transistor.

[0014] In some embodiments, the fourth signal includes a first voltage applied to a first gate electrode of the third transistor. The third transistor may be configured to provide the second current based on the first voltage at the first gate electrode of the third transistor. In some embodiments, the fourth signal includes a second voltage applied to a second gate electrode of the fourth transistor. The fourth transistor may be configured to provide the third current based on the second voltage at the second gate electrode of the fourth transistor.

[0015] In some embodiments, the first circuit includes a first multiplexer configured to select a third voltage from a first group of voltages. In some embodiments, the first circuit includes a second multiplexer configured to select a fourth voltage from a second group of voltages. In some embodiments, the first circuit includes a third multiplexer configured to select either the third voltage or the fourth voltage as the first voltage. In some embodiments, the first circuit includes a fourth multiplexer configured to select either the third voltage or the fourth voltage as the second voltage.

[0016] In some embodiments, the first signal includes a fifth voltage applied to the third gate electrode of the first transistor. The fifth voltage may correspond to the second drive strength. In some embodiments, the first signal includes a sixth voltage applied to the fourth gate electrode of the second transistor. The sixth voltage may correspond to the third drive strength. In some embodiments, the first circuit includes a fifth multiplexer configured to select a seventh voltage from a third set of voltages. In some embodiments, the first circuit includes a sixth multiplexer configured to select an eighth voltage from a fourth set of voltages. In some embodiments, the first circuit includes a seventh multiplexer configured to select either the seventh voltage or the eighth voltage as the fifth voltage. In some embodiments, the first circuit includes an eighth multiplexer configured to select either the seventh voltage or the eighth voltage as the sixth voltage.

[0017] The various embodiments disclosed herein relate to an apparatus. In some embodiments, the apparatus includes a first circuit configured to generate a first signal. In some embodiments, the apparatus includes a second circuit coupled to the first circuit. In some embodiments, the second circuit is configured to generate a second signal based on the first signal. The second signal may indicate the timing of a third signal. In some embodiments, the apparatus includes a third circuit coupled to the second circuit. In some embodiments, the third circuit is configured to generate the third signal according to the timing indicated by the second signal. The amplitude of the third signal may correspond to one bit.

[0018] In some embodiments, the second circuit includes a fourth circuit configured to provide a first drive strength of the second circuit according to the first signal. In some embodiments, the second circuit is configured to generate a first edge of the second signal according to the first drive strength. The first edge may indicate the timing of the second edge of the third signal.

[0019] In some embodiments, the fourth circuit includes a first transistor configured to provide a second drive strength. In some embodiments, the fourth circuit includes a second transistor configured to provide a third drive strength. In some embodiments, the fourth circuit is configured to provide the first drive strength based on the second drive strength and the third drive strength.

[0020] In some embodiments, the fourth circuit includes a third transistor series coupled to the first transistor. In some embodiments, the third transistor is configured to enable or disable the first transistor based on the one bit. In some embodiments, the fourth circuit includes a fourth transistor series coupled to the second transistor. The fourth transistor may be configured to enable or disable the second transistor based on the one bit.

[0021] The various embodiments disclosed herein relate to an apparatus. In some embodiments, the apparatus includes a first circuit configured to generate a first signal and a second signal. In some embodiments, the apparatus includes a second circuit coupled to the first circuit. In some embodiments, the second circuit is configured to generate a third signal based on the first signal. The third signal may have a first edge according to the first signal. In some embodiments, the apparatus includes a third circuit coupled to the second circuit. In some embodiments, the third circuit is configured to generate a fourth signal having a second edge and an amplitude according to the second signal and the third signal. The second edge of the fourth signal may correspond to the first edge of the third signal. The amplitude of the fourth signal may be set according to the second signal.

[0022] In some embodiments, the device is a transmitter. In some embodiments, the transmitter includes a digital-to-analog converter, which includes the first circuit, the second circuit, and the third circuit. Attached Figure Description

[0023] The various objects, aspects, features, and advantages of this disclosure will become more apparent and better understood through a detailed description taken in conjunction with the accompanying drawings, in which all like reference numerals identify corresponding elements. In the drawings, like reference numerals generally indicate like, functionally similar, and / or structurally similar elements.

[0024] Figure 1 This is a block diagram of a communication system including a base station and a client device according to some embodiments.

[0025] Figure 2 This is a block diagram of an apparatus for communicating via a wireless communication link, according to some embodiments.

[0026] Figure 3 This is a schematic diagram of a transmitter according to some embodiments.

[0027] Figure 4 This is a schematic diagram of a digital-to-analog converter (DAC) unit according to some embodiments.

[0028] Figure 5 This is a schematic diagram of a driver circuit including an adjustable transconductance circuit according to some embodiments.

[0029] Figure 6 This is a schematic diagram of an adjustable transconductance circuit for timing control of a DAC unit according to some embodiments.

[0030] Figure 7 It is configured to, according to some embodiments, direct to Figure 6 A schematic diagram of a bias control circuit that provides a bias voltage for timing control of the DAC unit using an adjustable transconductance circuit.

[0031] Figure 8 This is a schematic diagram of an adjustable transconductance circuit for amplitude control of a DAC unit according to some embodiments.

[0032] Figure 9 It is configured to, according to some embodiments, direct to Figure 8 A schematic diagram of a bias control circuit that provides a bias voltage for amplitude control of the DAC unit using an adjustable transconductance circuit.

[0033] Figure 10 This is a flowchart illustrating the operation of calibrating a DAC unit according to some embodiments.

[0034] Details of various embodiments of the method and system are set forth in the accompanying drawings and the following description. Detailed Implementation

[0035] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, in various instances, reference numerals and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0036] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “top,” “bottom,” and similar terms may be used herein to describe the relationship between one element or feature and another element or feature(s), as illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein shall therefore be interpreted in the same manner.

[0037] The disclosure herein relates to the calibration of a DAC comprising multiple DAC units. A unit, as used herein, refers to a unit circuit having a set of components in a specific arrangement. Each DAC unit can be configured to receive a corresponding one of a plurality of data bits and provide a current corresponding to the received one bit. On one hand, currents from different DAC units can be combined to represent multiple data bits. For example, the amplitude of the combined current, expressed in analog form, can correspond to multiple data bits, expressed in digital form. On the other hand, calibration can be performed on each DAC unit to reduce errors during digital-to-analog conversion.

[0038] In some embodiments, the DAC unit includes bias control circuitry, driver circuitry (or latch), and current guiding circuitry. The bias control circuitry may be circuitry configured to provide one or more bias voltages for configuring the driver circuitry and current guiding circuitry. The bias voltage may be a voltage used to set the current amount or drive strength (e.g., transconductance (gm)) of a transistor or circuit. The drive strength may be the amount of change in current provided in response to a change in applied voltage. The driver circuitry may be circuitry configured to provide a second signal with a first edge based on a first signal (e.g., bias voltage) from the bias control circuitry. The edge of the signal may be a change in signal state from one state to another. A rising edge may be a change from a low state (e.g., 0V) to a high state (e.g., 1V), and a falling edge may be a change from a high state (e.g., 1V) to a low state (e.g., 0V). On one hand, a falling edge occurring after a rising edge may be an edge following a rising edge, and another rising edge occurring after a falling edge may be an edge following a falling edge. The first edge of the second signal may be set or adjusted according to the drive strength of the driver circuitry. For example, the second signal can have a faster edge by increasing the drive strength of the driver circuit. On one hand, the driver circuit includes an adjustable current source or adjustable transconductance circuit whose drive strength can be set according to the first signal (e.g., bias voltage). On the other hand, the current guiding circuit can be a circuit configured to generate or provide a current corresponding to one data bit. The current guiding circuit can be configured to generate a third signal with a second edge in response to a first edge of the second signal.

[0039] Advantageously, each DAC unit can be individually calibrated to reduce timing errors in digital-to-analog conversion. On one hand, timing errors or timing differences in the current generated by different DAC units can lead to errors in the combination of currents from different DAC units and can result in inaccurate generation of analog signals corresponding to digital signals. The apparatus and methods disclosed herein allow for high-granular adjustment of the timing of the generation of a third signal for each DAC unit, such that timing errors or timing differences in the current generated by different DAC units can be reduced. On one hand, a first edge (e.g., a rising edge) of the second signal indicates the timing of the second edge (e.g., a rising edge) of the third signal. For example, when the first edge of the second signal occurs, the DAC unit can generate the second edge of the third signal. Therefore, by adjusting the drive strength of the driver circuit of the DAC unit, the first edge of the second signal can be adjusted, and thus the timing of the second edge of the third signal can be adjusted. On one hand, the driver circuit includes an adjustable transconductance circuit whose drive strength can be adjusted with high granularity. For example, the adjustable transconductance circuit includes a set of transconductance circuits providing different currents or different drive strengths. The combined current or combined drive strength from the transconductance circuit set can correspond to the drive strength of the second circuit. The first circuit can provide different bias voltages to the transconductance circuit group, allowing the current or drive strength provided by the transconductance circuit group to be individually configured or controlled. By individually configuring or controlling different transconductance circuits, the drive strength of the driver circuit in the DAC can be set or adjusted with high granularity. In addition, different DAC units can be calibrated to reduce timing errors in digital-to-analog conversion.

[0040] On the one hand, each DAC unit can be individually calibrated to reduce amplitude errors in digital-to-analog conversion. On the other hand, amplitude errors or differences in the currents provided by different DAC units can lead to amplitude errors in the combined currents from different DAC units and can cause inaccuracies in the analog signal generated based on the amplitude of the combined currents. The apparatus and methods disclosed herein allow for high-granular adjustment of the amplitude of a third signal for each DAC unit, thereby reducing amplitude errors or differences in the currents provided by different DAC units. On the one hand, a bias control circuit provides a fourth signal (e.g., a bias voltage) to the current pilot circuit. On the other hand, the current pilot circuit includes an adjustable current source that can be adjusted with high granularity to correspond to a current of one bit. For example, the adjustable current source includes a set of current sources (or a set of transconductance circuits) providing different currents. The amplitude of the combined current from the set of current sources can represent or correspond to one bit. A first circuit can provide different bias voltages to the set of current sources, such that the currents provided by the set of current sources can be individually configured or controlled. By individually configuring or controlling different current sources, the amplitude of the current output by the current pilot circuit can be set or adjusted with high granularity. In addition, different DAC units can be calibrated to reduce amplitude errors in digital-to-analog conversion.

[0041] On the one hand, DACs are implemented for wireless communication. For example, DACs can be implemented in transmitters used for radio frequency (RF) communication, such as cellular communication (3G, 4G, 5G, 6G, etc.), Wi-Fi communication, Bluetooth communication, etc. In some embodiments, the transmitter is a base station providing wireless communication (e.g., eNodeB (eNB), gNodeB (gNB), etc.). On the other hand, DACs can operate at high speeds (e.g., more than 5 gigabits per second) and can convert digitally represented RF modulated signals into analog signals. DACs can provide analog signals to preamplifiers or power amplifiers for transmission via antennas, eliminating the need for analog upconverters or analog mixers. By omitting analog upconverters or analog mixers, transmitters can reduce power consumption, improve linearity, provide design flexibility, and can be implemented in small sizes. Furthermore, the modulation or upconversion of signals from baseband frequencies (e.g., 100MHz to 1GHz) to RF frequencies (e.g., 1 to 10GHz) can be performed by digital logic circuits that are less susceptible to noise than analog circuits, allowing transmitters to improve signal quality. In some embodiments, the DAC is provided in an integrated circuit package (e.g., a multi-chip module or a single-chip package). Although the DAC disclosed herein is provided to a transmitter for wireless communication, the DAC can be implemented for various applications. For example, the DAC disclosed herein can be implemented for wired communication, optical communication, or any computing device that performs high-speed digital-to-analog conversion.

[0042] In some embodiments, one or more components may be embodied as one or more transistors. The implemented transistor may be an N-type transistor or a P-type transistor. An N-type transistor may be a transistor that utilizes electrons as the majority carrier. A P-type transistor may be a transistor that utilizes holes as the majority carrier. The transistor may be any suitable transistor, including (but not limited to) metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, FinFETs, GaaFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, or the like. Furthermore, one or more transistors shown or described herein may be embodied as two or more transistors connected in parallel. On one hand, a transistor includes a source electrode, a drain electrode, and a gate electrode. The source and drain electrodes are interchangeable depending on the voltage applied to them. Therefore, the source electrode or drain electrode may be referred to herein as the source / drain electrode. Current may flow between the source and drain electrodes depending on the voltage applied to the gate electrode of the transistor. In some applications, the transistor may be implemented as a switch. For example, if the voltage difference between the gate and source electrodes of a transistor is greater than the transistor's threshold voltage, the transistor can be enabled to electrically couple the source and drain electrodes. Conversely, if the voltage difference between the gate and source electrodes is less than the transistor's threshold voltage, the transistor can be disabled to electrically decouple the source and drain electrodes.

[0043] Figure 1 This is a block diagram of a communication system 100 including a base station 120 and client devices 110A, 110B, and 110C according to some embodiments. The base station 120 and client devices 110A, 110B, and 110C can communicate via a wireless communication link. The wireless communication link can be a cellular communication link conforming to 3G, 4G, 5G, 6G, or other cellular communication protocols. On one hand, client devices 110A…110C are located within a geographical boundary 150 relative to the base station 120 and can communicate with or through the base station 120. In some embodiments, the communication system 100 includes… Figure 1 The number of base stations 120 and / or client devices 110 shown may be more, less, or different.

[0044] In some embodiments, the client device 110 may be a user device, such as a mobile phone, smartphone, personal digital assistant (PDA), tablet computer, laptop computer, wearable computing device (e.g., head-mounted display, smartwatch), etc. The client device 110 may also be referred to as a user equipment (UE). Each client device 110 can communicate with the base station 120 via a corresponding communication link. For example, the client device 110 may transmit or provide wireless signals to the base station 120 under RF via a wireless communication link (e.g., 3G, 4G, 5G, 6G, or other cellular communication links) and / or receive wireless signals from the base station 120 under RF via a wireless communication link (e.g., 3G, 4G, 5G, 6G, or other cellular communication links). The wireless signal may be a signal exchanged or provided through a wireless medium (e.g., air). The wireless signal may contain or carry data, such as audio data, image data, text, etc.

[0045] In some embodiments, base station 120 may be an apparatus configured to provide wireless communication to client devices 110 within a geographical boundary 150. Examples of base station 120 include eNB, gNB, etc. Base station 120 may be communicatively coupled to another base station 120 or other communication apparatus via a wireless communication link and / or a wired communication link. Base station 120 may receive wireless signals from client devices 110 or another base station 120 under RF conditions via a wireless communication link. Alternatively or additionally, base station 120 may transmit or provide wireless signals under RF conditions via a wireless communication link to another client device 110, another base station 120, or another communication apparatus. Thus, base station 120 allows communication between client devices 110 associated with base station 120 or other client devices 110 associated with different base stations 120.

[0046] Figure 2 This is a block diagram of an apparatus 210 for communicating via a wireless communication link according to some embodiments. In some embodiments, apparatus 210 may be a base station 120, a client device 110, or any device that can communicate via a wireless communication link. In some embodiments, apparatus 210 includes an antenna 215, a wireless interface 220, a processor 230, and a memory device 240. These components may be embodied in hardware, software, firmware, or a combination thereof. In some embodiments, apparatus 210 includes a... Figure 2 The device may display more, fewer, or different components. For example, device 210 may include an electronic display and / or input device. For example, device 210 may include, in addition to Figure 2 In addition to the antenna 215 and the additional wireless interface 220 shown in the image.

[0047] In some embodiments, antenna 215 is a component that can receive and / or transmit wireless signals over a wireless medium (e.g., air) in the RF environment. Antenna 215 may be a dipole antenna, patch antenna, loop antenna, or any antenna suitable for wireless communication. On one hand, a single antenna 215 is used for both transmitting and receiving wireless signals. For receiving wireless signals, antenna 215 can detect wireless signals having electromagnetic wave variations in a wireless medium (e.g., air) and provide an electrical signal to wireless interface 220 having a voltage and / or current corresponding to the detected electromagnetic wave variations in the RF environment. The electrical signal in the RF environment may be referred to herein as an RF signal. For transmitting wireless signals, antenna 215 can receive electrical signals having voltage and / or current in the RF environment from wireless interface 220 and transmit wireless signals having electromagnetic wave variations corresponding to the electrical signals over a wireless medium (e.g., air). In some embodiments, different antennas 215 may be used for transmitting and receiving wireless signals. In some embodiments, multiple antennas 215 may be used to support multiple-input multiple-output (MIMO) communication.

[0048] In some embodiments, wireless interface 220 is a circuit or component that provides RF signals to or receives RF signals from antenna 215. In some embodiments, wireless interface 220 includes transmitter 224 and receiver 228. In one embodiment, transmitter 224 and receiver 228 may be implemented in the same integrated circuit. In some embodiments, transmitter 224 and receiver 228 may be implemented in different integrated circuits. Transmitter 224 may be a circuit or component that generates or provides RF signals for transmitting data. On one hand, transmitter 224 may receive from processor 230 a baseband signal containing or representing data (e.g., audio data, image data, text, or any data) for transmission at a baseband frequency (e.g., 0 to 1 GHz) and up-convert the baseband signal to generate an RF signal. Transmitter 224 may provide the RF signal to antenna 215 for transmission. Receiver 228 may be a circuit or component that receives RF signals for receiving data. On one hand, receiver 228 can receive RF signals from antenna 215 under RF conditions and downconvert the RF signals to a baseband frequency (e.g., 0 to 1 GHz) to obtain a downconverted signal at the baseband frequency. The downconverted signal at the baseband frequency may contain or represent data (e.g., audio data, image data, text, or any data) generated by another device (e.g., another base station 120, another client device 110, etc.). Receiver 228 can provide the downconverted signal to processor 230. In one configuration, transmitter 224 and receiver 228 may be coupled to the same antenna 215. In another configuration, transmitter 224 and receiver 228 may be coupled to different antennas 215.

[0049] Processor 230 is a data processing component. Processor 230 may be embodied in an FPGA, ASIC, logic circuit, etc. Processor 230 can obtain instructions from memory device 240 and execute those instructions. On one hand, processor 230 can receive down-converted signals from wireless interface 220 at baseband frequency and decode or process data contained in or represented by the down-converted signals. For example, processor 230 can obtain audio data or image data from the down-converted signals. On the other hand, processor 230 can generate or obtain data for transmission at baseband frequency and encode or process the data. For example, processor 230 can encode or process image data or audio data at baseband frequency and provide baseband signals containing or representing the encoded or processed data to wireless interface 220 for transmission.

[0050] Memory device 240 is a component for storing data. Memory device 240 may be embodied as RAM, flash memory, ROM, EPROM, EEPROM, register, hard disk, portable hard disk, CD-ROM, or any device capable of storing data. Memory device 240 may be embodied as a non-transitory computer-readable medium storing instructions executable by processor 230 for performing the various functions of device 210 disclosed herein. In some embodiments, memory device 240 and processor 230 are integrated as a single component (or integrated circuit). In some embodiments, memory device 240, processor 220, and wireless interface 220 are integrated as a single component (or integrated circuit). In some embodiments, memory device 240, processor 220, and wireless interface 220 are implemented as discrete components (or separate integrated circuits).

[0051] Figure 3 This is a schematic diagram of a transmitter 224 according to some embodiments. In some embodiments, the transmitter 224 includes a DAC 310 (also referred to as "DAC circuit 310"), a modulator 320, an interface circuit 370, and a power amplifier (PA) 380. These components can operate together to generate an RF signal 385 for transmission. On one hand, the modulator 320 operates in the digital domain, while the interface circuit 370 and PA 380 operate in the analog domain. The DAC circuit 310 can operate in both the analog and digital domains and can be operated as an interface between the modulator 320 operating in the digital domain and the interface circuit 370 and PA 380 operating in the analog domain. In some embodiments, the transmitter 224 includes a... Figure 3 The diagram shows more, fewer, or different components. For example, modulator 320 may be implemented as part of processor 230.

[0052] In some embodiments, modulator 320 is a circuit or component capable of receiving a baseband signal comprising K-bit data In_A…In_K in digital representation and performing modulation or upconversion on the K-bit data In_A…In_K. Modulation or upconversion may involve multiplying the value represented by the K-bit data In_A…In_K by a sine or cosine function of the carrier frequency under RF. The carrier frequency may be a frequency under which wireless signals can be transmitted (e.g., 2 to 60 GHz). In one method, modulator 320 may perform the multiplication of the value represented by the K-bit data In_A…In_K with a sine or cosine function of the carrier frequency via digital logic circuitry to obtain N-bit data D_A…D_N representing the upconverted signal under RF. Modulator 320 may provide the N-bit data D_A…D_N in digital representation to DAC circuit 310.

[0053] In some embodiments, the DAC circuit 310 is a circuit or component capable of performing digital-to-analog conversion. In some embodiments, the DAC circuit 310 includes a plurality of DAC units 325A…325N, a resistor ladder 330, a detector 340, and a calibrator 350. These components can operate together to receive N-bit data D_A…D_N in digital representation and provide signals 335A, 335B in analog representation corresponding to the N-bit data D_A…D_N. For example, the voltage amplitudes of signals 335A, 335B may represent or correspond to the values ​​of the N-bit data D_A…D_N. In some embodiments, the DAC circuit 310 includes a ratio Figure 3 The more, fewer, or different components are displayed.

[0054] In some embodiments, DAC unit 325 is a circuit or component capable of receiving 1 bit of data D and generating a current 328 corresponding to 1 bit of data D. In one configuration, DAC unit 325 includes an input port coupled to modulator 320 and an output port coupled to a corresponding resistor of resistor ladder 330. The port may be a pad, metal rail, or any conductive component capable of receiving or providing an electrical signal (e.g., voltage or current). The input port may be a port for receiving a signal, while the output port may be a port for providing or outputting a signal. In this configuration, DAC unit 325 may receive 1 bit of data D and provide a current 328 having an amplitude corresponding to 1 bit of data D. For example, in response to 1 bit of data D having a value '0', DAC unit 325 may bypass providing current. For example, in response to 1 bit of data D having a value '1', DAC unit 325 may provide a current 328 with a specific amplitude to resistor ladder 330. The following discusses... Figure 4 A detailed description of the implementation and operation of DAC unit 325 is provided.

[0055] In some embodiments, the resistor ladder 330 is a circuit or component that provides voltage signals 335A, 335B corresponding to currents 328A…328N from a group of DAC units 325A…325N. In one configuration, the resistor ladder 330 includes various resistors connected in an R-2R configuration. In one configuration, the output ports of different DAC units 325A are coupled to corresponding resistors of the resistor ladder 330. In one configuration, the resistor ladder 330 includes an output port coupled to an input port of interface circuitry 370. In this configuration, the resistor ladder 330 can combine currents 328A…328N from the DAC unit group 325 and generate or provide voltage signals 335A, 335B corresponding to the combined currents. The voltage signals 335A, 335B can be differential signals having opposite phases to each other. On one hand, the amplitude of the combined current corresponds to the amplitude of the voltage signals 335A, 335B. For example, for the 4-bit input data '0001' corresponding to the value '1', the amplitude difference between voltage signals 335A and 335B can be 100mV corresponding to the current from a single DAC unit 325. For example, for the 4-bit input data '0111' corresponding to the value '3', the amplitude difference between voltage signals 335A and 335B can be 300mV corresponding to the current from three DAC units 325. The resistor ladder 330 can provide voltage signals 335A and 335B at its output port.

[0056] In some embodiments, detector 340 is a circuit or component capable of detecting errors in one or more DAC units 325. Detector 340 may be implemented as analog circuitry, digital logic circuitry, or a combination of analog and digital logic circuitry. In one configuration, detector 340 includes one or more input ports coupled to a resistor ladder 330 and an output port coupled to an input port of calibrator 350. In this configuration, detector 340 can detect characteristics of one or more DAC units 325. Examples of characteristics of DAC units 325 include the timing of providing current 328, the amplitude of current 328, etc. Detector 340 can generate one or more feedback signals indicating the detection characteristics of DAC units 325 and provide one or more feedback signals to calibrator 350.

[0057] In some embodiments, the calibrator 350 is a circuit or component capable of performing calibration of the DAC unit 325. On one hand, each DAC unit 325 may have errors due to process angle variations, voltage variations, temperature variations, or combinations thereof. Examples of errors may include timing errors and amplitude errors. For example, timing errors, or timing differences in the currents 328A…328N provided by different DAC units 325, can cause errors in the combination of currents 328A…, 328N from different DAC units 325 and can cause inaccurate generation of voltage signals 335A, 335B corresponding to N bits of data. For example, if a particular DAC unit 325 provides current 328 later than other DAC units 325 or does not provide current 328 during the time allocated for providing current 328, then the currents 328 from the DAC units 325 cannot be properly combined and can cause the amplitudes of the voltage signals 335A, 335B to represent incorrect values ​​of N bits of data. For example, amplitude errors, or differences in the amplitude of currents 328A…328N provided by different DAC units 325A…325N, can cause amplitude errors in the combined currents from the different DAC units 325A…325N, and can also cause inaccuracies in the amplitudes of voltage signals 335A, 335B based on the combined currents. For example, if a particular DAC unit 325 provides a current 328 with an amplitude that is smaller or larger than the current 328 from other DAC units 325, then the amplitudes of the voltage signals 335A, 335B based on the combined currents can represent an error value for N bits of data. On the one hand, the calibrator 350 can configure or adjust each DAC unit 325 to reduce timing and amplitude errors.

[0058] On one hand, the calibrator 350 can receive one or more feedback signals from the detector 340 indicating the characteristics of one or more DAC units 325 and adjust the configuration or setting of each DAC unit 325 according to the one or more feedback signals. Examples of configuration or setting of the DAC unit 325 include configurations for adjusting the drive strength of generating or providing current 328 and / or configurations for adjusting the amplitude of current 328. The calibrator 350 can determine a target configuration or target setting for each DAC unit 325 and provide a configuration signal indicating the determined configuration or setting to each DAC unit 325. For example, if the calibrator 350 determines based on one or more feedback signals that a particular DAC unit 325 is slower than other DAC units 325, then the calibrator 350 can generate a configuration signal that causes the DAC unit 325 to increase the drive strength to provide current 328 faster. For example, if the calibrator 350 determines, based on one or more feedback signals, that a particular DAC unit 325 provides a current 328 with an amplitude greater than that provided by other DAC units 325, then the calibrator 350 may generate a configuration signal such that the DAC unit 325 provides a current 328 with a lower amplitude.

[0059] In some embodiments, interface circuitry 370 is a circuit or component that can interface between DAC circuitry 310 and PA 380. Examples of interface circuitry 370 include baluns, impedance matching circuitry, etc. In one configuration, interface circuitry 370 includes a first input port coupled to a first output port of resistor ladder 330, a second input port coupled to a second output port of resistor ladder 330, and an output port coupled to an input port of PA 380. In this configuration, interface circuitry 370 can convert differential signals 335A, 335B into signal 375. For example, interface circuitry 370 can obtain the amplitude difference between signals 335A, 335B and provide the difference as signal 375. On the other hand, interface circuitry 370 can provide impedance matching between DAC circuitry 310 and PA 380, such that the input port of PA 380 can have a specific impedance within a range (e.g., 40 to 60 ohms) to ensure proper operation of PA 380.

[0060] In some embodiments, PA 380 is a circuit or component that amplifies signal 375 to obtain RF signal 385 for driving antenna 215. In some embodiments, PA 380 includes a single amplifier circuit or two or more amplifier circuits cascaded together. In one configuration, PA 380 includes an input port coupled to the output port of interface circuit 370 and an output port coupled to antenna 215. In this configuration, PA 380 amplifies the amplitude of signal 375 to obtain RF signal 385 with amplified amplitude and provides RF signal 385 to antenna 215 for transmission.

[0061] Figure 4 This is a schematic diagram of a DAC unit 325X according to some embodiments. The DAC unit 325X may be one of DAC units 325A…325N. In some embodiments, the DAC unit 325X includes a current guiding circuit 430, a driver circuit 410, and a bias control circuit 460. These components can operate together to provide currents 328X, 328Xb corresponding to input signals InX, InXb. In some embodiments, the DAC unit 325X includes a... Figure 4 The more, fewer, or different components are displayed.

[0062] On one hand, the input signals InX and InXb can be or correspond to one of bits D_A…D_N. The input signals InX and InXb can be provided by modulator 320. The input signals InX and InXb can be differential signals with opposite phases to represent one bit. For example, depending on the value of the bit to be represented, the input signal InX can have one of a first voltage (e.g., VDD or 1V) or a second voltage lower than the first voltage (e.g., GND or 0V), and the input signal InXb can have the other of the first voltage or the second voltage. For example, an input signal InX with the first voltage and an input signal InXb with the second voltage lower than the first voltage can represent the value "1" of one bit. For example, an input signal InX with the second voltage and an input signal InXb with the first voltage higher than the second voltage can represent the value "0" of one bit.

[0063] In some embodiments, the bias control circuit 460 is a circuit or component that can provide bias voltages to the driver circuit 410 and / or the current guiding circuit 430. The bias control circuit 460 may include or be implemented as one or more logic circuits. The bias control circuit 460 may receive a configuration signal 432 from the calibrator 350 indicating the configuration or setting of the DAC unit 325X, and determine or select one or more bias voltages for the driver circuit 410 and / or the current guiding circuit 430 based on the configuration or setting indicated by the configuration signal 432. Based on the configuration or setting indicated by the configuration signal 432, the bias control circuit 460 may provide or apply one or more bias voltages 412A, 412B to the driver circuit 410 and provide or apply one or more bias voltages 414 to the current guiding circuit 430. For example, for a configuration signal 432 indicating that the DAC unit 325X has a specific timing for generating currents 328X and 328Xb, the bias control circuit 460 may provide one or more bias voltages 412A and 412B to the driver circuit 410, so that the driver circuit 410 can adjust the timing of generating currents 328X and 328Xb according to a specific drive strength of the one or more bias voltages 412A and 412B. For example, for a configuration signal 432 indicating that the DAC unit 325X provides currents 328X and 328Xb with a specific amplitude, the bias control circuit 460 may provide one or more bias voltages 414 to the current guiding circuit 430, so that the current guiding circuit 430 can set or adjust the amplitude of currents 328X and 328Xb according to the one or more bias voltages 414. In some embodiments, the bias control circuit 460 may also generate bias voltages Bias0, Bias1, and Bias2 and provide these bias voltages to the current guiding circuit 430. The following section discusses... Figure 7 and 9 A detailed description of an example implementation of the bias control circuit 460 is provided.

[0064] In some embodiments, driver circuit 410 is a circuit or component capable of providing signals 420A and 420B corresponding to input signals InX and InXb to current-directing circuit 430 in response to a clock signal CLK. In some embodiments, driver circuit 410 may include a latch or a flip-flop. Driver circuit 410 may also include or be coupled to a level shifter. The level shifter may shift the voltage levels of signals 420A and 420B to have a specific voltage amplitude and / or common-mode voltage suitable for driving current-directing circuit 430. Signals 420A and 420B may be differential signals with opposite phases. On one hand, signals 420A and 420B may correspond to one bit represented by input signals InX and InXb. For example, in response to input signal InX having a voltage higher than input signal InXb, signal 420A may have a voltage higher than signal 420B. For example, in response to the input signal InXb having a voltage higher than the input signal InX, signal 420B may have a voltage higher than signal 420A. On one hand, driver circuit 410 receives input signals InX and InXb and provides signals 420A and 420B according to the timing indicated by clock signal CLK. Clock signal CLK may be a signal that periodically switches between two voltages. On the other hand, depending on the state, voltage, or edge of clock signal CLK, driver circuit 410 may receive input signals InX and InXb and provide signals 420A and 420B to current guiding circuit 430. For example, in response to clock signal CLK having a first voltage (e.g., VDD or 1V), driver circuit 410 may receive input signals InX and InXb and provide signals 420A and 420B corresponding to input signals InX and InXb to current guiding circuit 430. For example, in response to the clock signal CLK having a second voltage (e.g., GND or 0V), the driver circuit 410 may not provide the current guiding circuit 430 with signals 420A and 420B corresponding to the input signals InX and InXb.

[0065] On one hand, the driver circuit 410 can set, change, or adjust the drive strength to adjust the timing of providing signals 420A and 420B. The drive strength (or transconductance gm) can be the amount of change in current provided in response to a change in applied voltage. In some embodiments, the driver circuit 410 includes a first drive control circuit 425A and a second drive control circuit 425B. The first drive control circuit 425A can be a circuit that controls or adjusts the timing of the edges of signal 420A. The second drive control circuit 425B can be a circuit that controls or adjusts the timing of the edges of signal 420B. On the other hand, the first drive control circuit 425A can receive one or more bias voltages 412A from the bias control circuit 460 and set or adjust the drive strength of the generated signal 420A according to the one or more bias voltages 412A. According to the drive strength of the generated signal 420A, the driver circuit 410 can change or set the timing of the edges of the generated signal 420A. On one hand, the second drive control circuit 425B can receive one or more bias voltages 412B from the bias control circuit 460 and set or adjust the drive strength of the generated signal 420B according to the one or more bias voltages 412B. Based on the drive strength of the generated signal 420B, the driver circuit 410 can change or set the timing of the edges of the generated signal 420B. The following section discusses... Figure 5 and 6 A detailed description of an example implementation of the driver circuit 410 is provided.

[0066] In some embodiments, the current-directing circuit 430 is a circuit or component that provides indications of a single bit of current 328X, 328Xb represented by input signals InX, InXb. In some embodiments, the current-directing circuit 430 includes transistors M1 to M10, resistors R2, R3, and an adjustable current source 490. These components can operate together to receive signals 420A, 420B and provide currents 328X, 328Xb according to signals 420A, 420B. In some embodiments, the current-directing circuit 430 includes a ratio of Figure 4 The more, fewer, or different components are displayed.

[0067] On one hand, currents 328X and 328Xb can correspond to one of currents 328A…328N. Currents 328X and 328Xb can be differential signals with opposite phases to indicate the values ​​represented by input signals InX and InXb. For example, current 328X being greater than current 328Xb or having a larger amplitude than current 328Xb can correspond to a bit “1” represented by input signals InX and InXb. For example, current 328Xb being greater than current 328X or having a larger amplitude than current 328X can correspond to a bit “0” represented by input signals InX and InXb.

[0068] On one hand, the adjustable current source 490 is a circuit or component that provides current according to one or more bias voltages 414. In some embodiments, the adjustable current source 490 includes a resistor R1 and an adjustable transconductance circuit 440. The current provided by the adjustable current source 490 may correspond to current 328X, current 328Xb, or a combination of currents 328X and 328Xb. The resistor R1 may be a component that provides a resistance. The adjustable transconductance circuit 440 may be a circuit or component that provides transconductance corresponding to one or more bias voltages 414. The adjustable transconductance circuit 440 may include or be implemented as one or more transistors. In one configuration, the resistor R1 includes a first electrode coupled to a metal rail that provides a ground voltage (e.g., GND or 0V) and a second electrode coupled to the adjustable transconductance circuit 440. In one configuration, the adjustable transconductance circuit 440 includes a first port coupled to a bias control circuit 460 to receive one or more bias voltages 414, a second port coupled to a second electrode of a resistor R1, and a third port coupled to transistors M1 and M2. In this configuration, the adjustable transconductance circuit 440 can conduct current through the resistor R1 according to one or more bias voltages 414. For example, the amplitude of the current through the resistor R1 can be set or adjusted according to one or more bias voltages 414. On the other hand, the current through the resistor R1 can flow through transistors M1, M2, or both.

[0069] On one hand, transistors M1 and M2 can operate as a differential pair circuit to guide current from the adjustable current source 490. Transistors M1 and M2 can be MOSFETs, FinFETs, GaaFETs, or any type of transistor. Transistors M1 and M2 can be N-type transistors. In some embodiments, transistors M1 and M2 can be implemented as P-type transistors. In one configuration, transistor M1 includes i) a source electrode coupled to the adjustable current source 490, ii) a gate electrode coupled to the driver circuit 410 to receive signal 420A, and iii) a drain electrode coupled to transistor M3. In one configuration, transistor M2 includes i) a source electrode coupled to the adjustable current source 490, ii) a gate electrode coupled to the driver circuit 410 to receive signal 420B, and iii) a drain electrode coupled to transistor M4. In this configuration, either transistor M1 or transistor M2 can be selectively enabled to guide current from the adjustable current source 490. For example, if signal 420A has a higher voltage than signal 420B, then transistor M1 can conduct or provide a larger portion of the current from the adjustable current source 490 than transistor M2. Similarly, if signal 420B has a higher voltage than signal 420A, then transistor M2 can conduct or provide a larger portion of the current from the adjustable current source 490 than transistor M1. The current conducted or provided by transistor M1 can be current 328X, and the current conducted or provided by transistor M2 can be current 328Xb. On the other hand, the sum of currents 328X and 328Xb can be the current provided by the adjustable current source 490.

[0070] On one hand, transistors M3 to M8 can operate as common-source, common-gate transistors to protect transistors M1 and M2. Transistors M3 to M8 can be MOSFETs, FinFETs, GaAFETs, or any type of transistor. Transistors M3 to M8 can be N-type transistors. In some embodiments, some of transistors M3 to M8 can be implemented as P-type transistors. In some embodiments, transistors M7 and M8, transistors M5 to M8, or transistors M3 to M8 can be omitted.

[0071] In one configuration, transistor M3 includes i) a source electrode coupled to the drain electrode of transistor M1, ii) a gate electrode coupled to the gate electrode of transistor M4, and iii) a drain electrode coupled to the source electrode of transistor M5. In another configuration, transistor M4 includes i) a source electrode coupled to the drain electrode of transistor M2, ii) a gate electrode coupled to the gate electrode of transistor M3, and iii) a drain electrode coupled to the source electrode of transistor M6. The gate electrodes of transistors M3 and M4 can be coupled to bias control circuit 460 to receive bias voltage Bias0.

[0072] In one configuration, transistor M5 includes i) a source electrode coupled to the drain electrode of transistor M3, ii) a gate electrode coupled to the gate electrode of transistor M6, and iii) a drain electrode coupled to the source electrode of transistor M7. In another configuration, transistor M6 includes i) a source electrode coupled to the drain electrode of transistor M4, ii) a gate electrode coupled to the gate electrode of transistor M5, and iii) a drain electrode coupled to the source electrode of transistor M8. The gate electrodes of transistors M5 and M6 can be coupled to bias control circuit 460 to receive bias voltage Bias1.

[0073] In one configuration, transistor M7 includes i) a source electrode coupled to the drain electrode of transistor M5, ii) a gate electrode coupled to the gate electrode of transistor M8, and iii) a drain electrode coupled to one or more resistors of resistor ladder 330. In another configuration, transistor M8 includes i) a source electrode coupled to the drain electrode of transistor M6, ii) a gate electrode coupled to the gate electrode of transistor M7, and iii) a drain electrode coupled to one or more resistors of resistor ladder 330. The gate electrodes of transistors M7 and M8 may be coupled to bias control circuit 460 to receive bias voltage Bias2.

[0074] In this configuration, transistors M3, M5, and M7 operate as cascode transistors series-coupled to transistor M1. Similarly, transistors M4, M6, and M8 operate as cascode transistors series-coupled to transistor M2. Cascode transistors help mitigate voltage stress. In one instance, a voltage across the source and drain electrodes of a transistor with an amplitude greater than the transistor's allowable stress voltage can damage the transistor. By implementing one or more cascode transistors, a large voltage can be distributed among the series-connected transistors. For example, the voltage between the source electrode of transistor M1 and the drain electrode of transistor M7 can be shared or distributed among transistors M1, M3, M5, and M7, thus protecting transistor M1. Similarly, the voltage between the source electrode of transistor M2 and the drain electrode of transistor M8 can be shared or distributed among transistors M2, M4, M6, and M8, thus protecting transistor M2.

[0075] On one hand, when the current from the adjustable current source 490 is provided as current 328Xb through transistors M2, M4, M6, and M8, transistor M9 and resistor R2 can operate together to provide current to ensure proper operation of cascode transistors M3, M5, and M7. The current provided by transistor M9 and resistor R2 can be referred to as the discharge current. The discharge current can be 5% to 10% of the current provided by the adjustable current source 490. Transistor M9 can be a MOSFET, FinFET, GaaFET, or any transistor. Transistor M9 can be an N-type transistor. In some embodiments, transistor M9 can be implemented as a P-type transistor. In one configuration, resistor R2 includes a first electrode coupled to a metal rail providing a ground voltage (e.g., GND or 0V) and a second electrode coupled to the source electrode of transistor M9. In one configuration, transistor M9 includes i) a source electrode coupled to the second electrode of resistor R2, ii) a gate electrode for receiving signal 480A, and iii) a drain electrode coupled to the drain electrode of transistor M1. Signal 480A may be or correspond to signal 420B. In this configuration, transistor M9 can operate as a switch. For example, when signal 420B has a voltage higher than signal 420A, causing current from adjustable current source 490 to flow as current 328Xb through transistors M2, M4, M6, and M8, transistor M9 can be enabled to provide a lower amount of current (or discharge current) sufficient to ensure proper operation of transistors M3, M5, and M7. For example, when signal 420A has a voltage higher than signal 420B, causing current from adjustable current source 490 to flow as current 328X through transistors M1, M3, M5, and M7, transistor M9 cannot provide current (or discharge current).

[0076] On one hand, when the current from the adjustable current source 490 is provided as current 328X through transistors M1, M3, M5, and M7, transistor M10 and resistor R3 can operate together to provide current to ensure proper operation of cascode transistors M4, M6, and M8. The current provided by transistor M10 and resistor R3 can be referred to as the discharge current. Transistor M10 can be a MOSFET, FinFET, GaaFET, or any transistor. Transistor M10 can be an N-type transistor. In some embodiments, transistor M10 can be implemented as a P-type transistor. In one configuration, resistor R3 includes a first electrode coupled to a metal rail providing a ground voltage (e.g., GND or 0V) and a second electrode coupled to the source electrode of transistor M10. In one configuration, transistor M10 includes i) a source electrode coupled to the second electrode of resistor R3, ii) a gate electrode for receiving signal 480B, and iii) a drain electrode coupled to the drain electrode of transistor M2. Signal 480B can be or correspond to signal 420A. In this configuration, transistor M10 can operate as a switch. For example, when signal 420A has a voltage higher than signal 420B, causing current from adjustable current source 490 to flow as current 328X through transistors M1, M3, M5, and M7, transistor M10 can be enabled to provide a lower amount of current (or discharge current) sufficient to ensure proper operation of transistors M4, M6, and M8. For example, when signal 420B has a voltage higher than signal 420A, causing current from adjustable current source 490 to flow as current 328Xb through transistors M2, M4, M6, and M8, transistor M10 cannot provide current (or discharge current).

[0077] Figure 5 This is a schematic diagram of a driver circuit 500 including adjustable transconductance circuits 510A and 510B according to some embodiments. The driver circuit 500 may be... Figure 4 The driver circuit 500 includes a driver circuit 410. In some embodiments, the driver circuit 500 includes transistors M51, M52, M53, M54, M55, M56 and adjustable transconductance circuits 510A and 510B. In some embodiments, the adjustable transconductance circuits 510A and 510B may be a second drive control circuit 425B and a first drive control circuit 425A, respectively. These components can operate together to receive input signals InX and InXb representing one bit and a clock signal CLK and generate signals 420A and 420B for driving the current guiding circuit 430 according to the timing indicated by the clock signal CLK. In some embodiments, transistors M51, M52, M53, M54, M55, and M56 may be MOSFETs, FinFETs, GaAFETs, or any transistor. Transistors M51 and M52 may be N-type transistors, and transistors M53, M54, M55, and M56 may be P-type transistors. In some embodiments, the driver circuit 500 includes a driver circuit 410. Figure 5 The diagram shows more, fewer, or different components. For example, some of transistors M51, M52, M53, M54, M55, and M56 can be implemented with... Figure 5 The different types of transistors shown in the image.

[0078] In one configuration, transistor M55 includes i) a source electrode coupled to a metal rail providing a supply voltage (e.g., VDD or 1V), ii) a gate electrode for receiving an input signal InX, and iii) a drain electrode coupled to the source electrode of transistor M53. In one configuration, transistor M53 includes i) a source electrode coupled to the drain electrode of transistor M55, ii) a gate electrode coupled to the drain electrode of transistor M54, and iii) a drain electrode coupled to the drain electrode of transistor M51. In one configuration, transistor M51 includes i) a source electrode coupled to an adjustable transconductance circuit 510A, ii) a gate electrode coupled to the gate electrode of transistor M52 to receive a clock signal CLK, and iii) a drain electrode coupled to the drain electrode of transistor M53. On one hand, the voltage at the drain electrodes of transistors M53 and M51 can be signal 420B. In one configuration, the adjustable transconductance circuit 510A is coupled between the source electrode of transistor M51 and a metal rail providing a ground voltage (e.g., GND or 0V).

[0079] In one configuration, transistor M56 includes i) a source electrode coupled to a metal rail providing a supply voltage (e.g., VDD or 1V), ii) a gate electrode for receiving an input signal InXb, and iii) a drain electrode coupled to the source electrode of transistor M54. In one configuration, transistor M54 includes i) a source electrode coupled to the drain electrode of transistor M56, ii) a gate electrode coupled to the drain electrode of transistor M53, and iii) a drain electrode coupled to the drain electrode of transistor M52. In one configuration, transistor M52 includes i) a source electrode coupled to an adjustable transconductance circuit 510B, ii) a gate electrode coupled to the gate electrode of transistor M51 to receive a clock signal CLK, and iii) a drain electrode coupled to the drain electrode of transistor M54. On one hand, the voltage at the drain electrodes of transistors M54 and M52 can be signal 420A. In one configuration, the adjustable transconductance circuit 510B is coupled between the source electrode of transistor M52 and a metal rail providing a ground voltage (e.g., GND or 0V).

[0080] In this configuration, the driver circuit 500 can operate as a latch. For example, in response to a clock signal CLK, transistors M51 and M52 can operate as switches to enable or disable the current through adjustable transconductance circuits 510A and 510B. For example, in response to a first voltage (e.g., VDD or 1V) on the clock signal CLK, transistors M51 and M52 can be enabled to allow adjustable transconductance circuits 510A and 510B to adjust or change the voltages of signals 420B and 420A, respectively. For example, in response to a second voltage (e.g., GND or 0V) on the clock signal CLK, transistors M51 and M52 can be disabled to prevent adjustable transconductance circuits 510A and 510B from adjusting or changing the voltages of signals 420B and 420A. When transistors M51 and M52 are enabled, adjustable transconductance circuits 510A and 510B can conduct current to decrease or pull down the voltages of signals 420B and 420A, respectively, according to input signals InX and InXb. Transistors M55 and M56 can increase or pull up the voltages of signals 420B and 420A respectively based on input signals InX and InXb. Transistors M53 and M54 can have a cross-coupling configuration to help pull up the voltages of signals 420B and 420A respectively. In one example, when the clock signal CLK has a first voltage to enable transistors M51 and M52, if the input signal InX has a voltage higher than the input signal InXb, then the adjustable transconductance circuit 510A can provide current through transistor M51 to pull down or decrease the voltage of signal 420B, and transistor M56 can increase the voltage of signal 420A. In another example, when the clock signal CLK has a first voltage to enable transistors M51 and M52, if the input signal InXb has a voltage higher than the input signal InX, then the adjustable transconductance circuit 510B can provide current through transistor M52 to pull down or decrease the voltage of signal 420A, and transistor M55 can increase the voltage of signal 420B.

[0081] On one hand, the adjustable transconductance circuits 510A and 510B are components that can set or change the drive strength according to one or more bias voltages 412A. In some embodiments, each of the adjustable transconductance circuits 510A and 510B is implemented as two or more current sources connected in parallel. Each of the adjustable transconductance circuits 510A and 510B can set or adjust the current supplied so that the drive strength can be changed accordingly. For example, the adjustable transconductance circuits 510A and 510B can provide more current to increase the drive strength, so that signals 420A and 420B can be edge-generated faster. For example, the adjustable transconductance circuits 510A and 510B can provide less current to decrease the drive strength, so that signals 420A and 420B can be edge-generated slower. The following is about Figure 6 Provides a detailed description of the implementation and operation of adjustable transconductance circuits 510A and 510B.

[0082] Figure 6 This is a schematic diagram of an adjustable transconductance circuit 510A for timing control of a DAC unit according to some embodiments. In some embodiments, the adjustable transconductance circuit 510A includes transistors M61, M62, M63, M64, M65, M66, and M67. These components can operate together to receive an input signal InX representing one bit and bias voltages Vb62, Vb64, and Vb66, and generate or provide a combined current 620B based on the input signal InX and the bias voltages Vb62, Vb64, and Vb66. The bias voltages Vb62, Vb64, and Vb66 may be a bias voltage 412A from a bias control circuit 460 or may be a portion of said bias voltage. The combined current 620B can be provided to the source electrode of transistor M51. In some embodiments, transistors M61, M62, M63, M64, M65, and M66 may be MOSFETs, FinFETs, GaAFETs, or any transistor. Transistors M61, M62, M63, M64, M65, and M66 may be N-type transistors. In some embodiments, the adjustable transconductance circuit 510A includes a ratio Figure 6 The diagram shows more, fewer, or different components. For example, some of transistors M61, M62, M63, M64, M65, and M66 can be implemented as... Figure 6 The diagram illustrates different transistor types. For example, the adjustable transconductance circuit 510A may include an additional transistor to provide additional current. In some embodiments, the adjustable transconductance circuit 510B has the same configuration to generate or provide a combined current to the source electrode of transistor M52 based on the input signal InXb and the corresponding bias voltage, which may be the same as or different from the bias voltages Vb62, Vb64, and Vb66.

[0083] On one hand, transistor M61 operates as a transconductance circuit. In one configuration, transistor M61 includes i) a source electrode coupled to a metal rail providing a ground voltage (e.g., GND or 0V), ii) a gate electrode for receiving the input signal InX, and iii) a drain electrode coupled to the source electrode of transistor M51. In this configuration, transistor M61 can be enabled to provide current or transconductance in response to the voltage of the input signal InX being greater than the threshold voltage of transistor M61. In response to the voltage of the input signal InX being less than the threshold voltage of transistor M61, transistor M61 can be disabled and not provide current or transconductance.

[0084] On one hand, transistors M63 and M62 operate as digitally configurable transconductance circuits. In one configuration, transistor M62 includes i) a source electrode coupled to a metal rail providing a ground voltage (e.g., GND or 0V), ii) a gate electrode for receiving a bias voltage Vb62, and iii) a drain electrode coupled to the source electrode of transistor M63. In another configuration, transistor M63 includes i) a source electrode coupled to the drain electrode of transistor M62, ii) a gate electrode for receiving a signal InX, and iii) a drain electrode coupled to the drain electrode of transistor M61. In this configuration, transistor M62 is operable as a transconductance circuit. Depending on the input signal InX, transistor M63 is operable as a switch to enable or disable transistor M62 from providing current or transconductance. For example, in response to a voltage having a first voltage (e.g., VDD or 1V) in response to the input signal InX, transistor M62 can be enabled to provide current or transconductance corresponding to the bias voltage Vb62. On the one hand, the current or transconductance provided by transistor M62 can be adjusted or changed according to the bias voltage Vb62. For example, if the voltage of the input signal InX has a second voltage (e.g., GND or 0V), transistor M62 cannot provide current or transconductance.

[0085] Transistors M65 and M64 can be configured and operated in a similar manner to transistors M63 and M62, except that transistor M64 can provide current or transconductance corresponding to the bias voltage Vb64 instead of the bias voltage Vb62. Similarly, transistors M67 and M66 can be configured and operated in a similar manner to transistors M63 and M62, except that transistor M66 can provide current or transconductance corresponding to the bias voltage Vb66 instead of the bias voltage Vb62. Therefore, for the sake of brevity, detailed descriptions of their repeated parts are omitted in this document.

[0086] On one hand, the currents provided by transistors M61, M62, M64, and M66 can be combined at the drain electrode of transistor M61, and the combined current 620B can be provided to the source electrode of transistor M51 to adjust the drive strength of the adjustable transconductance circuit 510A. The combined current 620B can correspond to or contribute to the combined transconductance used to generate signal 420B. On the other hand, each of transistors M62, M64, and M66 can be individually controlled according to the different applied bias voltages Vb62, Vb64, and Vb66, so that the combined current 620B can be set, controlled, or adjusted with high granularity. For example, if a single transistor or a single transconductance circuit is implemented to provide current 620B, then this single transistor or single transconductance circuit can be sensitive to the applied bias voltage, and the amount or amplitude of current 620B can vary greatly. By implementing different transconductance circuits connected in parallel, each transconductance circuit can be individually tuned or adjusted so that the drive strength or combined transconductance of the adjustable transconductance circuit 510A used to change or set the timing of the edge of the generated signal 420B can be adjusted with high granularity. In some embodiments, transistors M62, M64, and M66 may have different sizes (e.g., channel width and / or channel length) so that transistors M62, M64, and M66 can provide different amounts of current or transconductance in response to the same applied voltage. By implementing transistors M62, M64, and M66 with different sizes (e.g., channel width and / or channel length), the configurability or granularity of adjusting the drive strength of the adjustable transconductance circuit 510A can be improved.

[0087] Figure 7 This is a schematic diagram of a bias control circuit 700A configured, according to some embodiments, to provide bias voltages Vb62, Vb64, Vb66 to an adjustable transconductance circuit 510A for timing control of a DAC unit 325X. In some embodiments, the bias control circuit 700A is part of a bias control circuit 460. In some embodiments, the bias control circuit 700A includes a series of resistors R7A, R7B…R7L, L-bit multiplexers 710A, 710B, and 2-bit multiplexers 720A, 720B, 720C. These components can operate together to provide bias voltages Vb62, Vb64, Vb66. In some embodiments, the bias control circuit 700A includes a ratio of… Figure 7 The diagram shows more, fewer, or different components. For example, the bias control circuit 700A may contain more than... Figure 7 The additional multiplexer shown in the figure. In some embodiments, the bias control circuit 460 may also include an additional multiplexer having a similar configuration to multiplexers 710A, 710B, 720A, 720B, 720C to provide a bias voltage to the adjustable transconductance circuit 510B. The bias voltage provided to the adjustable transconductance circuit 510B may be the same as or different from the bias voltages Vb62, Vb64, Vb66 provided to the adjustable transconductance circuit 510A.

[0088] In some embodiments, the resistor string R7A, R7B…R7L provides various voltages V7A, V7B, V7C…V7L, V7L+1. In one configuration, the resistor string R7A, R7B…R7L comprises resistors R7A, R7B…R7L connected in series. In this configuration, the voltage difference between voltage V7L+1 and voltage V7A can be distributed or divided according to the number of resistors in the resistor string R7A, R7B…R7L. Voltages V7L+1 and V7A may be provided by a temperature compensation circuit (not shown). For example, assuming L is 5, voltage V7L+1 is 0.8V and voltage V7A is 0.3V, and each of resistors R7A, R7B...R7L has the same resistance, then the resistor series R7A, R7B...R7L can provide a set of voltages 0.3V, 0.4V, 0.5V, 0.6V, 0.7V, 0.8V as voltages V7A, V7B, V7C...V7L, V7L+1.

[0089] In some embodiments, the L-bit multiplexer 710A is a circuit or component capable of selecting a voltage from a first voltage range as voltage 715A and providing the selected voltage 715A. In one configuration, the L-bit multiplexer 710A receives a first subset of voltages V7A, V7B, V7C, ..., V7L, V7L+1 from a resistor string R7A, R7B...R7L. The first subset may be voltages V7B, V7C...V7L, V7L+1. On one hand, according to a control signal, the multiplexer 710A may select one of voltages V7B, V7C...V7L, V7L+1 as voltage 715A. The control signal may be a configuration signal provided by the calibrator 350.

[0090] In some embodiments, the L-bit multiplexer 710B is a circuit or component that can select a voltage from a second voltage range as voltage 715B and provides voltage 715B. In one configuration, the L-bit multiplexer 710B receives a second subset of voltages V7A, V7B, V7C, V7L, V7L+1 from a resistor series R7A, R7B…R7L. The second subset may be voltages V7A, V7B…V7L. According to a control signal, the multiplexer 710B may select one of voltages V7A, V7B…V7L as voltage 715B. The control signal may be a configuration signal provided by the calibrator 350. On one hand, the L-bit multiplexer 710B selects a voltage 715B that is lower than the voltage 715A selected by the L-bit multiplexer 710A.

[0091] In some embodiments, each of the two-bit multiplexers 720A, 720B, and 720C is a circuit or component that can select voltages between voltages 715A and 715B as bias voltages Vb62, Vb64, and Vb66, respectively. On one hand, the two-bit multiplexers 720A, 720B, and 720C can select different voltages as bias voltages Vb62, Vb64, and Vb66, respectively, according to a control signal. The control signal may be a configuration signal provided by the calibrator 350. On the other hand, the two-bit multiplexers 720A, 720B, and 720C can be individually controlled to select different voltages, such that different combinations of bias voltages Vb62, Vb64, and Vb66 can be provided to the adjustable transconductance circuits 510A and 510B. By providing different bias voltages Vb62, Vb64, and Vb66 to the adjustable transconductance circuits 510A and 510B, the driver circuit 410 can set or adjust its drive strength with high granularity.

[0092] Figure 8 This is a schematic diagram of an adjustable current source or adjustable transconductance circuit 440 for amplitude control of a DAC unit 325X according to some embodiments. In some embodiments, the adjustable transconductance circuit 440 includes transistors M81, M82…M88. These components can operate together to receive bias voltages Vb81, Vb82…Vb88 and generate or provide a combined current 820 based on the bias voltages Vb81, Vb82…Vb88. The bias voltages Vb81, Vb82…Vb88 may be a bias voltage 414 from a bias control circuit 460 or may be a portion of said bias voltage. In some embodiments, transistors M81, M82…M88 may be MOSFETs, FinFETs, GaaFETs, or any transistor. Transistors M81, M82…M88 may be N-type transistors. In some embodiments, the adjustable transconductance circuit 440 includes a ratio of… Figure 8 The diagram shows more, fewer, or different components. For example, some of the transistors M81, M82…M88 can be implemented with… Figure 8 The different types of transistors shown in the image.

[0093] On one hand, each of transistors M81…M88 operates as a current source. In one configuration, transistors M81…M88 may be coupled in parallel between resistor R1 and the source electrodes of transistors M1, M2. For example, transistor M81 includes i) a source electrode coupled to resistor R1, ii) a gate electrode for receiving a bias voltage Vb81, and iii) a drain electrode coupled to the source electrodes of transistors M1, M2. In this configuration, transistor M81 can provide current or transconductance having an amplitude or amount corresponding to the bias voltage Vb81. Each of transistors M82…M88 may be arranged and operated in a similar manner for a corresponding bias voltage Vb82…Vb88. Therefore, for the sake of brevity, detailed descriptions of their repeated portions are omitted herein.

[0094] On the one hand, the currents provided by transistors M81, M82…M88 can be combined at the drain electrodes of transistors M81, M82…M88, and the combined current 820 can be provided to the source electrodes of transistors M1 and M2. On the other hand, depending on the different applied bias voltages Vb81, Vb82…Vb88, each of transistors M81, M82…M88 can be individually controlled, allowing the combined current 820 to be set, controlled, or adjusted with high granularity. For example, if a single transistor or a single current source is used to provide the current 820, then this single transistor or single current source can be sensitive to the applied bias voltage, and the amount or amplitude of the current 820 can vary greatly. By implementing different current sources or different transistors M81…M88 connected in parallel, each current source or each of transistors M81…M88 can be individually tuned or adjusted so that the current 820 can have a target amplitude or target amount. High-granularity adjustment of the amplitude of current 820, current 328X, or current 328Xb is also possible by allowing adjustment of the current 820. In some embodiments, transistors M81…M88 may have different sizes (e.g., channel width and / or channel length) such that transistors M81…M88 can provide different amounts of current in response to the same applied voltage. By implementing transistors M81…M88 with different sizes (e.g., channel width and / or channel length), the configurability or granularity of adjusting the amplitude of current 820 can be improved.

[0095] Figure 9 It is configured to, according to some embodiments, direct to Figure 8A schematic diagram of a bias control circuit 900, in which adjustable transconductance circuit 440 provides bias voltages Vb81, Vb82…Vb88 for amplitude control of DAC unit 325X, is shown. In some embodiments, bias control circuit 900 is part of bias control circuit 460. In some embodiments, bias control circuit 900 has a similar configuration to bias control circuit 700A, except that bias control circuit 900 includes i) K resistors R9A, R9B…R9K instead of L resistors R7A, R7B…R7L, ii) K-bit multiplexers 910A, 910B instead of L-bit multiplexers 710A, 710B, and iii) 2-bit multiplexers 920A, 920B…920H instead of 2-bit multiplexers 720A, 720B, 720C. Therefore, for the sake of brevity, detailed descriptions of repeated portions are omitted herein. These components can operate together to provide bias voltages Vb81, Vb82…Vb88. By providing different bias voltages Vb81, Vb82…Vb88 to the adjustable transconductance circuit 440, the amplitude of current 328X or current 328Xb can be adjusted with high granularity, allowing amplitude errors to be reduced or eliminated. In some embodiments, the bias control circuit 900 includes a ratio of… Figure 9 The more, fewer, or different components are displayed.

[0096] Figure 10 This is a flowchart illustrating operation 1000 of a calibration DAC unit 325X according to some embodiments. In some embodiments, operation 1000 is performed by bias control circuitry 460. In some embodiments, operation 1000 is performed by a different entity (e.g., calibrator 350). In some embodiments, operation 1000 includes... Figure 10 The steps shown may be more, fewer, or different. In some embodiments, operation 1000 is different from... Figure 10 The operations are executed in the order shown. For example, operations 1030 and 1050 can be executed before operation 1020.

[0097] In one approach, bias control circuit 460 receives configuration signal 432. Configuration signal 432 may be a signal indicating the configuration or setting of DAC unit 325X. For example, configuration signal 432 may indicate or correspond to multiplexers 710A, 710B, 720A, 720B, 720C of bias control circuit 700A. For example, configuration signal 432 may indicate or correspond to multiplexers 910A, 910B, 920A…920H of bias control circuit 900.

[0098] In one approach, bias control circuitry 460 determines one or more first bias voltages 1020 to set the drive strength based on configuration signal 432. The one or more first bias voltages may include voltages (e.g., Vb62, Vb64, Vb66) provided to adjustable transconductance circuits 510A and / or 510B. For example, multiplexers 710A, 710B, 720A, 720B, 720C may be configured according to configuration signal 432 to select bias voltages Vb62, Vb64, Vb66 from multiple voltage ranges V7A, V7B…V7L+1 to provide to the adjustable transconductance circuit 510A of driver circuitry 410.

[0099] In one approach, bias control circuitry 460 determines one or more second bias voltages (e.g., Vb81, Vb82…Vb88) based on configuration signal 432 to set the amplitude of current (e.g., currents 328X, 328Xb). For example, multiplexers 910A, 910B, 920A, 920B…920H can be configured based on configuration signal 432 to select bias voltages Vb82, Vb82…Vb88 from multiple voltage ranges V9A, V9B…V9K+1 to provide an adjustable current source 490 to current guiding circuitry 430.

[0100] In one method, bias control circuit 460 provides one or more first bias voltages (e.g., Vb62, Vb64, Vb66) to driver circuit 410. Based on the one or more first bias voltages (e.g., Vb62, Vb64, Vb66), driver circuit 410 may have corresponding drive strengths to adjust the timing of the generated current (e.g., currents 328X, 328Xb). On one hand, driver circuit 410 may generate signals with edges (e.g., signals 420A, 420B), wherein the edges or timing of the generated signals (e.g., signals 420A, 420B) can be controlled or adjusted according to the drive strength of driver circuit 410. For example, by increasing the drive strength, the signals (e.g., signals 420A, 420B) may have faster edges. For example, by decreasing the drive strength, the signals (e.g., signals 420A, 420B) may have slower edges. On one hand, the edges of signals (e.g., signals 420A, 420B) correspond to the timing of generating currents (e.g., currents 328X, 328Xb). For example, by providing signals (e.g., signals 420A, 420B) with faster edges, the current guiding circuit 430 can generate the edges of currents (e.g., currents 328X, 328Xb) faster. On the other hand, by providing signals (e.g., signals 420A, 420B) with slower edges, the current guiding circuit 430 can delay the edges of generating currents (e.g., currents 328X, 328Xb). Therefore, by adjusting the drive strength of the driver circuit 410, the timing of generating currents (e.g., currents 328X, 328Xb) can be adjusted. By adjusting the timing of generating currents (e.g., currents 328X, 328Xb) for each DAC unit 325, the accuracy of digital-to-analog conversion performed by the DAC circuit 310 can be improved.

[0101] In one approach, bias control circuitry 460 provides one or more second bias voltages (e.g., Vb81, Vb82…Vb88) to adjustable current source 490 of current guiding circuitry 430. Based on the one or more second bias voltages (e.g., Vb81, Vb82…Vb88), adjustable current source 490 can provide currents with corresponding amplitudes (e.g., currents 328X, 328Xb). By adjusting the amplitude of the current (e.g., currents 328X, 328Xb) in each DAC unit 325, the accuracy of digital-to-analog conversion performed by DAC circuitry 310 can be improved.

[0102] The term "coupling" and its variations include joining two components directly or indirectly to each other. The term "electrically coupled" and its variations include joining two components directly or indirectly to each other by means of a conductive material (e.g., metal or copper traces). This coupling can be static (e.g., permanent or fixed) or movable (e.g., removable or releasable). This coupling can be achieved by directly coupling two components to each other, by coupling two components to each other using a separate intermediary member and any additional intermediate member coupled to each other, or by coupling two components to each other using an intermediate member integrally formed with one of the two components as a single whole. If "coupling" or its variations are modified by an additional term (e.g., directly coupled), then the general definition of "coupling" provided above is modified by the plain meaning of the additional term (e.g., "directly coupled" means that two components are joined without any separate intermediary member), resulting in a narrower definition than the general definition of "coupling" provided above. This coupling can be mechanical, electrical, or fluid.

[0103] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from its spirit and scope.

Claims

1. An apparatus comprising: a digital-to-analog conversion unit comprising: a first circuit configured to generate a first signal, the first circuit being a bias circuit; a second circuit coupled to the first circuit, the second circuit configured to generate a second signal based on the first signal and an input bit, the second signal having a first edge positioned in response to the first signal, the second circuit being a driver circuit; and a third circuit coupled to the second circuit, the third circuit configured to generate a third signal having a second edge in response to the first edge of the second signal, an amplitude of the third signal corresponding to the input bit, the third circuit being a current steering circuit, wherein the second circuit includes a fourth circuit configured to provide a first drive strength of the second circuit as a function of the first signal, the second circuit configured to generate the first edge of the second signal as a function of the first drive strength.

2. The apparatus of claim 1, wherein the first circuit is configured to generate a fourth signal, wherein the second circuit includes a fifth circuit configured to provide a second drive strength of the second circuit as a function of the fourth signal, the second circuit configured to generate a third edge of the second signal as a function of the second drive strength, the third edge following the first edge of the second signal, and wherein the third circuit is configured to generate a fourth edge of the third signal in response to the third edge of the second signal, the fourth edge following the second edge of the third signal.

3. The apparatus of claim 1, wherein the fourth circuit comprises: a first transistor configured to provide a second drive strength, and a second transistor configured to provide a third drive strength, the fourth circuit configured to provide the first drive strength based on the second drive strength and the third drive strength.

4. The apparatus of claim 3, wherein the fourth circuit includes: a third transistor coupled in series to the first transistor, the third transistor configured to enable or disable the first transistor as a function of the input bit, and a fourth transistor coupled in series to the second transistor, the fourth transistor configured to enable or disable the second transistor as a function of the input bit.

5. The apparatus of claim 4, wherein the first signal comprises: a first voltage applied to a first gate electrode of the first transistor, the first voltage corresponding to the second drive strength, and a second voltage applied to a second gate electrode of the second transistor, the second voltage corresponding to the third drive strength.

6. The apparatus of claim 5, wherein the first circuit comprises: a first multiplexer configured to select a third voltage from a first set of voltages, a second multiplexer configured to select a fourth voltage from a second set of voltages, a third multiplexer configured to select one of the third voltage or the fourth voltage as the first voltage, and a fourth multiplexer configured to select one of the first voltage or the second voltage as the fourth voltage. a fourth multiplexer configured to select one of the third voltage or the fourth voltage as the second voltage.

7. The device of claim 3, wherein the first circuit is configured to provide a fourth signal to the third circuit, and wherein the third circuit is configured to set the amplitude of the third signal according to the fourth signal.

8. The device of claim 7, wherein the third circuit includes a fifth circuit configured to set a first current of the third circuit according to the fourth signal, and to set the amplitude of the third signal according to the first current.

9. The device of claim 8, wherein the fifth circuit comprises: a third transistor configured to provide a second current, and a fourth transistor configured to provide a third current, the fifth circuit configured to provide the first current based on the second current and the third current.

10. The device of claim 9, wherein the fourth signal comprises: a first voltage applied to a first gate electrode of the third transistor, the third transistor configured to provide the second current according to the first voltage at the first gate electrode of the third transistor, and a second voltage applied to a second gate electrode of the fourth transistor, the fourth transistor configured to provide the third current according to the second voltage at the second gate electrode of the fourth transistor.

11. The device of claim 10, wherein the first circuit comprises: a first multiplexer configured to select a third voltage from a first set of voltages, a second multiplexer configured to select a fourth voltage from a second set of voltages, a third multiplexer configured to select one of the third voltage or the fourth voltage as the first voltage, and a fourth multiplexer configured to select one of the third voltage or the fourth voltage as the second voltage.

12. The device of claim 11, wherein the first signal comprises: a fifth voltage applied to a third gate electrode of the first transistor, the fifth voltage corresponding to the second drive strength, and a sixth voltage applied to a fourth gate electrode of the second transistor, the sixth voltage corresponding to the third drive strength, and wherein the first circuit includes: a fifth multiplexer configured to select a seventh voltage from a third set of voltages, a sixth multiplexer configured to select an eighth voltage from a fourth set of voltages, a seventh multiplexer configured to select one of the seventh voltage or the eighth voltage as the fifth voltage, and an eighth multiplexer configured to select one of the seventh voltage or the eighth voltage as the sixth voltage.

13. A digital-to-analog converter cell device, comprising: a second circuit coupled to the first circuit configured to provide a first signal, the second circuit configured to generate a second signal based on the first signal, the second signal indicative of a timing of a third signal, the third signal a current representative of a bit input of the device, wherein the first signal affects a drive strength of the second circuit; and a third circuit coupled to the second circuit, the third circuit configured to generate the third signal according to the timing indicated by the second signal, an amplitude of the third signal corresponding to the bit input, the amplitude of the third signal a current level.

14. The device of claim 13, wherein the second circuit comprises a fourth circuit configured to provide a first drive strength of the second circuit according to the first signal, the second circuit configured to generate a first edge of the second signal according to the first drive strength, the first edge indicative of the timing of a second edge of the third signal.

15. The device of claim 14, wherein the fourth circuit comprises: a first transistor configured to provide a second drive strength, and a second transistor configured to provide a third drive strength, the fourth circuit configured to provide the first drive strength according to the second drive strength and the third drive strength.

16. The device of claim 15, wherein the fourth circuit comprises: a third transistor coupled in series to the first transistor, the third transistor configured to enable or disable the first transistor according to the bit input, and a fourth transistor coupled in series to the second transistor, the fourth transistor configured to enable or disable the second transistor according to the bit input.

17. A device comprising: a digital-to-analog converter unit comprising: a first biasing circuit configured to generate a first signal and a second signal; a driver circuit coupled to the first biasing circuit, the driver circuit configured to generate a third signal based on the first signal, the third signal having a first edge according to the first signal; and a current circuit coupled to the driver circuit, the current circuit configured to generate a fourth signal having a second edge and an amplitude according to the second signal and the third signal, the second edge of the fourth signal corresponding to the first edge of the third signal, the amplitude of the fourth signal related to the second signal.

18. The device of claim 17, wherein the driver circuit includes a fourth circuit configured to provide a first drive strength of the driver circuit according to the first signal, the driver circuit configured to generate the first edge of the second signal according to the first drive strength.

19. The device of claim 17, wherein the device is a transmitter.

20. The device of claim 19, wherein the transmitter includes a digital-to-analog converter, wherein the digital-to-analog converter includes the first biasing circuit, the driver circuit, and the current circuit, wherein the amplitude is a current quantity value of the third signal.

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