A monolithic integrated half-bridge circuit structure and a method for manufacturing the same

Abstract

The application discloses a monolithic integrated half-bridge circuit structure and a preparation method thereof, and relates to the technical field of monolithic integrated half-bridge circuits. The method comprises the following steps: a passivation layer and a base body provided with a groove; the passivation layer is arranged on the upper surface of the base body; the groove is filled with the passivation layer; the base body comprises, from bottom to top, a substrate electrode, a first P + substrate layer, an N ‑ substrate layer, a second P + substrate layer, a buffer layer, a GaN channel layer and an AlGaN barrier layer; the first P + substrate layer and the N ‑ substrate layer form a first PN junction; the N ‑ substrate layer and the second P + substrate layer form a second PN junction; the groove penetrates through the AlGaN barrier layer, the GaN channel layer, the buffer layer and the second P + substrate layer, and the bottom of the groove is located in the N ‑ substrate layer. The first P + substrate layer, the N ‑ substrate layer, the second P + substrate layer and the groove form a double-PN-junction substrate, which can reduce the dependence on the substrate potential and complete the isolation of the high-side transistor and the low-side transistor.

Description

Technical Field

[0001] This invention relates to the field of monolithic integrated half-bridge circuit technology, and in particular to a monolithic integrated half-bridge circuit structure and its fabrication method. Background Technology

[0002] In traditional monolithically integrated half-bridge circuits, the high-side and low-side high electron mobility transistors (HEMTs) are isolated only to a buffer layer, sharing the same substrate. Therefore, their common substrate potential can only be connected to either the high-side or low-side source, and connecting the common substrate potential to either source will cause crosstalk to the other device. If the common substrate is connected to the low-side source, the substrate potential is always 0. When the high-side HEMT is turned on and the low-side HEMT is turned off, the potential of SW (the output point in the half-bridge circuit is the point where the source of the high-side transistor and the drain of the low-side transistor are connected) is approximately equal to V. in At this point, for a high-side HEMT, the potential V from the high-side substrate to the source is... bs ≈-V in A value less than 0 will trigger the body effect or back-gate effect, causing a positive shift in the threshold voltage, where V in Here, SW is the potential (source potential of the high-side transistor). If the common substrate is connected to the source of the high-side transistor, then the substrate potential is equal to the potential at SW. When the high-side HEMT is on and the low-side HEMT is off, the substrate potential is approximately equal to the potential at SW, which is V. in At this point, for the lower-side HEMT, V bs ≈V in A value greater than 0 will cause electrons in the low-side HEMT to be injected from the source into the buffer layer and trapped by traps in the buffer layer. Due to the principle of electroneutrality, the trapped electrons in the buffer layer will deplete part of the two-dimensional electron gas (2DEG), resulting in a decrease in the device's drain current. Simultaneously, because traps are easy to trap but difficult to release electrons, the reduced drain current is difficult to recover in a short time, affecting device performance. Existing PN junction substrate isolation structures require the substrate electrode to always be equal to V to ensure that the substrate PN junction is always reverse-biased to isolate electrical crosstalk between the high and low-side HEMTs. in This has a negative impact on device packaging and heat dissipation. Summary of the Invention

[0003] The purpose of this invention is to provide a monolithic integrated half-bridge circuit structure and its fabrication method. By setting a double PN junction substrate, the dependence on substrate potential can be reduced, and isolation between high-side and low-side transistors can be achieved.

[0004] To achieve the above objectives, the present invention provides the following solution:

[0005] A monolithic integrated half-bridge circuit structure comprises: a passivation layer and a substrate provided with a trench;

[0006] The trench is arranged on the upper surface of the substrate; the passivation layer is arranged on the upper surface of the substrate; and the trench is filled with the passivation layer;

[0007] The substrate comprises, from bottom to top, a substrate electrode, a first P + substrate layer, an N - substrate layer, a second P + substrate layer, a buffer layer, a GaN channel layer and an AlGaN barrier layer;

[0008] The first P + substrate layer and the N - substrate layer form a first PN junction;

[0009] The N - substrate layer and the second P + substrate layer form a second PN junction;

[0010] The trench penetrates through the AlGaN barrier layer, the GaN channel layer, the buffer layer and the second P + substrate layer, and the bottom of the trench is located inside the N - substrate layer;

[0011] One side of the trench is provided with a high-side electrode group; the other side of the trench is provided with a low-side electrode group; the high-side electrode group and the low-side electrode group each comprise: a substrate electrode, a source electrode, a gate assembly and a drain electrode;

[0012] The source electrode, the gate assembly and the drain electrode are embedded in the passivation layer and in contact with the upper surface of the AlGaN barrier layer; and the substrate electrode is embedded in the passivation layer and the substrate through a substrate electrode hole;

[0013] The substrate electrode hole penetrates through the passivation layer, the AlGaN barrier layer, the GaN channel layer and the buffer layer; and the bottom of the substrate electrode hole is located inside the second P + substrate layer;

[0014] The drain electrode in the high-side electrode group is connected to a power supply;

[0015] The substrate electrode in the high-side electrode group and the drain electrode in the low-side electrode group are both connected to the source electrode in the high-side electrode group;

[0016] The substrate electrode in the low-side electrode group and the source electrode in the low-side electrode group are both grounded;

[0017] The potential range of the substrate electrode is 0-V in .

[0018] Optionally, the height of the gate assembly is greater than the thickness of the passivation layer; the height of the source and the height of the drain are both equal to the thickness of the passivation layer.

[0019] Optionally, the gate assembly includes a pGaN cap layer and a gate, arranged sequentially from bottom to top.

[0020] Optionally, the first P + The substrate material includes, but is not limited to, silicon, sapphire, silicon carbide, or self-supporting GaN.

[0021] Optionally, the N - The substrate layer includes, but is not limited to, silicon, sapphire, silicon carbide or self-supporting GaN materials.

[0022] Optionally, the second P + The substrate layer includes, but is not limited to, silicon, sapphire, silicon carbide or self-supporting GaN materials.

[0023] Optionally, the material of the buffer layer includes, but is not limited to, iron-doped gallium nitride, carbon-doped gallium nitride, iron-doped superlattice structure, or carbon-doped superlattice structure.

[0024] Optionally, the material of the passivation layer includes, but is not limited to, silicon tetranitride, silicon dioxide, or aluminum oxide.

[0025] A method for fabricating a monolithic integrated half-bridge circuit structure includes:

[0026] Obtain an N-substrate layer; the N-substrate layer is an N-type silicon wafer;

[0027] In N - The first P is fabricated on one side of the substrate. + Substrate layer; fabrication of the first P + The substrate layer can be grown epitaxially or by ion implantation followed by thermal diffusion.

[0028] In the first P + Metal is deposited on the side of the substrate layer away from the N-substrate layer and annealed at high temperature to achieve ohmic contact, forming a substrate electrode; the method of metal deposition is electron beam evaporation or magnetron sputtering.

[0029] In N - The second P is prepared on the other side of the substrate layer. + Substrate layer; fabrication of the second P + The substrate layer can be grown epitaxially or by ion implantation followed by thermal diffusion.

[0030] In the second P +The substrate layer grows a buffer layer, a GaN channel layer, an AlGaN barrier layer and a pGaN cap layer in sequence on the side away from the N-substrate layer;

[0031] Etching a groove and depositing a passivation layer, and mesa isolation; the method for etching the groove is dry etching, wet etching or dry-wet mixed etching process;

[0032] Etching the pGaN cap layer and depositing a passivation layer;

[0033] Etching low-edge source holes, low-edge drain holes, low-edge substrate holes, high-edge source holes, high-edge drain holes and high-edge substrate holes; the high-edge substrate holes and the low-edge substrate holes both penetrate through the passivation layer, the AlGaN barrier layer, the GaN channel layer and the buffer layer; and the bottoms of the high-edge substrate holes and the low-edge substrate holes are both located inside the second P+ substrate layer;

[0034] Depositing an ohmic contact metal and performing metal patterning to form low-edge metal connection lines and high-edge metal connection lines, and high-temperature annealing to form low-edge sources, low-edge drains, low-edge substrate electrodes, high-edge sources, high-edge drains and high-edge substrate electrodes, and depositing a passivation layer;

[0035] Etching to obtain a gate region through hole, depositing a metal, performing gate metal patterning to form low-edge gates and high-edge gates.

[0036] According to the specific embodiments provided by the present application, the following technical effects are disclosed:

[0037] The single-chip integrated half-bridge circuit structure and the preparation method thereof provided by the present application solve the high dependency of the existing PN junction substrate structure on the substrate potential, ensure excellent isolation performance when the potential of the substrate electrode is 0~V in . BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0039] Figure 1 It is a schematic diagram of the single-chip integrated half-bridge circuit structure in embodiment 1 of the present application.

[0040] Figure 2 It is a preparation method flow chart of the single-chip integrated half-bridge circuit structure in embodiment 2 of the present application.

[0041] Explanation of reference signs: Substrate electrode-1; first P + Substrate layer-2; N - Substrate layer-3; second P + Substrate layer-4; buffer layer-5; GaN channel layer-6; AlGaN barrier layer-7; pGaN cap layer-8; passivation layer-9; low-side gate-10; high-side gate-11; low-side source-12; high-side source-13; low-side drain-14 and high-side drain-15; low-side substrate electrode-16; high-side substrate electrode-17; low-side metal connecting line-18; high-side metal connecting line-19; trench-20. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0043] The purpose of the present application is to provide a monolithic integrated half-bridge circuit structure and a preparation method thereof, which can reduce the dependence on the substrate potential by setting a double PN junction substrate to complete the isolation of the high-side tube and the low-side tube.

[0044] In order to make the above-mentioned purposes, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0045] Embodiment 1

[0046] As Figure 1 shown, the present embodiment provides a monolithic integrated half-bridge circuit structure, which comprises: a passivation layer and a base body provided with a trench; the trench is arranged on the upper surface of the base body; the passivation layer is arranged on the upper surface of the base body; and the trench is filled with the passivation layer; the base body comprises, from bottom to top, a substrate electrode, a first P + substrate layer, an N - substrate layer, a second P + substrate layer, a buffer layer, a GaN channel layer and an AlGaN barrier layer; the first P + substrate layer and the N - substrate layer form a first PN junction; the N - substrate layer and the second P + substrate layer form a second PN junction; the trench penetrates through the AlGaN barrier layer, the GaN channel layer, the buffer layer and the second P + substrate layer, and the bottom of the trench is located in the N -The inner part of the substrate layer; one side of the trench is provided with a high-side electrode group; the other side of the trench is provided with a low-side electrode group; the high-side electrode group and the low-side electrode group each include: a substrate electrode, a source electrode, a gate assembly and a drain electrode; the source electrode, the gate assembly and the drain electrode are embedded in the passivation layer and contact the upper surface of the AlGaN barrier layer; the substrate electrode is embedded on the passivation layer and the base body through a substrate electrode hole; the substrate electrode hole penetrates the passivation layer, the AlGaN barrier layer, the GaN channel layer and the buffer layer; and the bottom of the substrate electrode hole is located in the second P + The inner part of the substrate layer; the drain electrode in the high-side electrode group is connected with a power supply; the substrate electrode in the high-side electrode group and the drain electrode in the low-side electrode group are connected with the source electrode in the high-side electrode group; the substrate electrode in the low-side electrode group and the source electrode in the low-side electrode group are grounded; the potential range of the substrate electrode is 0-V in .

[0047] The gate assembly includes: a pGaN cap layer 8 and a gate electrode arranged in sequence from bottom to top.

[0048] As an implementation manner, the height of the gate assembly is greater than the thickness of the passivation layer; the height of the source electrode and the height of the drain electrode are equal to the thickness of the passivation layer.

[0049] The first P + The material of the substrate layer 2 includes but is not limited to a silicon material, a sapphire material, a silicon carbide material or a self-supporting GaN material. - The substrate layer 3 includes but is not limited to a silicon material, a sapphire material, a silicon carbide material or a self-supporting GaN material. The second P + The substrate layer 4 includes but is not limited to a silicon material, a sapphire material, a silicon carbide material or a self-supporting GaN material. The material of the buffer layer 5 includes but is not limited to a gallium nitride doped with iron, a gallium nitride doped with carbon, a superlattice structure doped with iron or a superlattice structure doped with carbon. The material of the passivation layer 9 includes but is not limited to silicon nitride, silicon dioxide or aluminum oxide.

[0050] As Figure 1 shown, Figure 1 The middle 10 is a low-side gate, and 11 is a high-side gate; the monolithic integrated half-bridge circuit structure includes, from bottom to top, a substrate electrode 1, a first P + substrate layer 2, N - substrate layer 3, P + substrate layer 4, buffer layer 5, GaN channel layer 6, AlGaN barrier layer 7, pGaN cap layer 8 and passivation layer 9. Etching to N - The trench 20 of the substrate layer divides the entire device into a low-side HMET and a high-side HEMT, and the high-side and low-side HEMT share a substrate electrode 1, a first P + substrate layer 2 and N -Substrate layer 3, and due to the isolation of trench 20, the high and low sides each have independent substrate electrodes. On the AlGaN barrier layer 7, the two ends of the high and low side HEMTs are respectively provided with a low-side source 12, a high-side source 13, a low-side drain 14, and a high-side drain 15. Etched to P + The low-side substrate electrode 16 and high-side substrate electrode 17 of substrate layer 4 are connected to the low-side source electrode 12 and high-side source electrode 13 respectively via low-side metal interconnect 18 and high-side metal interconnect 19, so as to achieve the same potential between the high-side and low-side HEMT substrate electrodes and the source electrode. Simultaneously, the high-side metal interconnect 19 also connects the low-side drain electrode 14 and the high-side source electrode 13, and grounds the low-side source electrode and connects the high-side drain electrode to a high-level voltage V. in This enables the monolithic integration of the high-side HEMT and the low-side HEMT into a half-bridge circuit.

[0051] Substrate electrode 1 is located at the bottom of the entire structure to connect to the substrate potential. + The substrate layer 2 is placed on top of the substrate electrode 1, and may be, but is not limited to, made of silicon, sapphire, silicon carbide, or self-supporting GaN. - Substrate layer 3 is placed on P + Above substrate 2, with P + Substrate layer 2 forms a PN junction, ensuring N - The potential of substrate layer 3 is unaffected by the low potential of the substrate and provides support; it may be, but is not limited to, made of silicon, sapphire, silicon carbide, or self-supporting GaN. + Substrate layer 4 is placed in N - Above substrate 3, with N - Substrate layer 3 forms a PN junction, ensuring P + The potential of substrate layer 4 is not affected by N - The potential of substrate layer 3 may be affected by, but is not limited to, the use of silicon, sapphire, silicon carbide, and self-supporting GaN materials. Buffer layer 5 is located on P... +Above the substrate layer 4, a buffer layer is introduced to achieve stress release and dislocation filtering to obtain a better crystal quality, possibly but not limited to a gallium nitride layer doped with iron (Fe) or carbon (C) or an Al(Ga)N / GaN superlattice structure. The GaN channel layer 6 is located above the buffer layer 5. The AlGaN barrier layer 7 is located above the GaN channel layer 6 and generates a two-dimensional electron gas (2DEG) on the side close to the GaN channel layer 6 at the interface between the AlGaN barrier layer 7 and the GaN channel layer 6 through piezoelectric polarization and spontaneous polarization effects. The pGaN cap layer 8 is located above the AlGaN barrier layer 7 to increase the energy band at the heterojunction interface between the AlGaN barrier layer 7 and the GaN channel layer 6, depleting the two-dimensional electron gas in the area below the gate, thereby increasing the threshold voltage. The passivation layer 9 is present in the areas and regions within the trenches 20 between the low-side gate 10, the high-side gate 11, the low-side source 12, the high-side source 13, the low-side drain 14, the high-side drain 15, the low-side substrate 16, and the high-side substrate 17 above the AlGaN barrier layer 7 to reduce surface traps and laterally isolate the high-low side HEMT, which can be but is not limited to Si3N4, SiO2, or Al2O3.

[0052] The GaN HEMT monolithic integrated half-bridge circuit structure with the new double PN junction substrate (DJIS) can completely isolate the electrical crosstalk between the high-low side HEMTs and solve the high dependence of the existing PN junction substrate structure on the substrate potential, so that the potential of the substrate electrode can guarantee excellent isolation performance when the substrate potential is 0~V in .

[0053] The complete isolation of the electrical crosstalk between the high-low side HEMTs is due to the PN junction structure formed by the N - substrate layer 3 and the P + substrate layer 4. When the high-side HEMT is turned on and the low-side HEMT is turned off, the potential of the SW point is approximately equal to V in , at which time the potential of the high-side substrate 17 is the same as that of the SW, and the PN junction of the high-side HEMT substrate is positively biased, so that the potential of the N - substrate layer 3 is approximately equal to V in . At this time, for the low-side HEMT, since the potential of the low-side substrate 16 is 0, the PN junction of the low-side HEMT substrate is negatively biased, so that the potential of the N - substrate layer 3 does not affect the potential of the P + substrate layer 4; when the low-side HEMT is turned on and the high-side HEMT is turned off, the potential of the SW point is equal to 0, at which time the potential of the substrate electrode of the high-low side HEMT is 0, and thus the PN junction of the high-low side HEMT substrate is in a negatively biased state, so that the potential of the high-low side HEMT does not affect each other, thereby isolating the electrical crosstalk of the high-low side HEMT.

[0054] The potential of the substrate electrode is 0~Vin The excellent isolation performance is due to the N - substrate layer 3 and P + substrate layer 2 formed PN junction structure. When the high-side HEMT is turned on and the low-side HEMT is turned off, the potential of the SW point is about equal to V in , at this time, the potential of the high-side substrate electrode 17 is the same as the SW, and the PN junction of the high-side HEMT substrate is positively biased, so that the N - substrate layer 3 is about equal to V in , at this time, if the potential of the substrate electrode 1 is lower than the N - substrate layer 3, the potential of the N - substrate layer 3 and P + substrate layer 2 formed PN junction is reversely biased, and the potential of the substrate electrode 1 has no effect on the N - substrate layer 3, the N - substrate layer 3 still maintains the potential about equal to V in , thus the PN junction of the low-side HEMT substrate is reversely biased, and the crosstalk of the high-side HEMT to the low-side HEMT is isolated; if the potential of the substrate electrode 1 is higher than the N - substrate layer 3, the N - substrate layer 3 and P + substrate layer 2 formed PN junction is positively biased, and the potential of the N - substrate layer 3 is equal to the potential of the substrate electrode 1, thus the PN junction of the low-side HEMT substrate is still reversely biased, and the crosstalk of the high-side HEMT to the low-side HEMT is isolated; when the low-side HEMT is turned on and the high-side HEMT is turned off, the potential of the SW point is about equal to 0, at this time, the potential of the substrate electrodes of the high-side and low-side HEMT is always 0, thus the N - substrate layer 3 and P + substrate layer 2 formed PN junction is always positively biased, and the potential of the N - substrate layer 3 is equal to the potential of the substrate electrode, so that the N - substrate layer 3 and P + substrate layer 4 formed PN junction is always reversely biased, so that the potential of the high-side and low-side HEMT has no effect on each other, and thus the electrical crosstalk of the high-side and low-side HEMT is isolated. Therefore, the structure can guarantee excellent isolation performance when the potential of the substrate electrode is in the range of 0-V in .

[0055] Embodiment 2

[0056] The embodiment provides a preparation method of a monolithic integrated half-bridge circuit structure, comprising the following steps: obtaining an N-type substrate layer; the N-type substrate layer is an N-type silicon wafer; preparing a first P-type substrate layer on one side of the N - substrate layer; preparing a first P + substrate layer; preparing a first P +The method of the substrate layer is epitaxial growth or ion implantation + thermal diffusion method; the first P + The metal is deposited on the side of the substrate layer away from the N-substrate layer, and high-temperature annealing is performed to realize ohmic contact and form a substrate electrode; the method of depositing the metal is electron beam evaporation process or magnetron sputtering process; the N - The other side of the substrate layer is prepared as a second P + The substrate layer; the second P + The method of the substrate layer is epitaxial growth or ion implantation + thermal diffusion method; the second P + The buffer layer, GaN channel layer, AlGaN barrier layer and pGaN cap layer are sequentially grown on the side of the substrate layer away from the N-substrate layer; the trench is etched and the passivation layer 9 is deposited, and mesa isolation is performed; the method of etching the trench is dry etching, wet etching or dry-wet mixed etching process; the pGaN cap layer is etched and the passivation layer is deposited; the low-edge source hole, low-edge drain hole, low-edge substrate hole, high-edge source hole, high-edge drain hole and high-edge substrate hole are etched; the high-edge substrate hole and the low-edge substrate hole both penetrate the passivation layer, the AlGaN barrier layer, the GaN channel layer and the buffer layer; and the bottoms of the high-edge substrate hole and the low-edge substrate hole are both located inside the second P+ substrate layer; the ohmic contact metal is deposited and metal patterning is performed to form the low-edge metal connection line and the high-edge metal connection line, high-temperature annealing is performed to form the low-edge source, the low-edge drain, the low-edge substrate, the high-edge source, the high-edge drain and the high-edge substrate, and the passivation layer is deposited; the gate region through hole is etched, the metal is deposited, and the gate metal patterning is performed to form the low-edge gate and the high-edge gate.

[0057] To obtain the above-mentioned single-chip integrated half-bridge circuit structure with a novel double PN junction substrate (DJIS) and high-low edge tube isolation, the following manufacturing process is proposed, and the flow chart is as shown in Figure 2

[0058] Step 1: Select a low-doped N - type silicon wafer as the N - substrate layer 3.

[0059] Step 2: Ion implantation (including but not limited to boron implantation) + thermal diffusion (more than 1000℃) / epitaxial growth P + type epitaxial layer, forming a P + substrate layer 2.

[0060] Step 3: Electron beam evaporation / magnetron sputtering process is adopted to deposit metal (including but not limited to Ti / Al / Ni / Au, Ti / Al / Mo / Au and other certain metal or multiple metal stacks) on the P + substrate layer 2, and high-temperature annealing is performed to realize ohmic contact and form a substrate electrode 1.

[0061] ​Step 4: Flip the device, ion implantation (including but not limited to boron implantation) + thermal diffusion (over 1000℃) / epitaxial growth of P + type epitaxy, forming P + substrate layer 4.

[0062] Step 5: Epitaxial growth of buffer layer 5, GaN channel layer 6, AlGaN barrier layer 7 and pGaN cap layer 8 over P + substrate layer 4

[0063] Step 6: Deposition of SiO2 hard mask (including but not limited to PECVD deposition process), and etching of hard mask pattern (wet etching or dry etching or dry-wet mixed etching process).

[0064] Step 7: Etching (wet etching or dry etching or dry-wet mixed etching process) of trench 20, followed by deposition of passivation layer 9 (including but not limited to PECVD deposition process).

[0065] Step 8: Mesa isolation.

[0066] Step 9: Define trench position (including but not limited to electron beam lithography), etch pGaN cap layer 8 of high-low edge HEMT (wet etching or dry etching or dry-wet mixed etching process).

[0067] Step 10: Deposition of passivation layer 9 (including but not limited to PECVD deposition process).

[0068] Step 11: Remove passivation layer 9 under high-low edge HEMT source and drain regions by etching process (wet etching or dry etching or dry-wet mixed etching process), form source and drain region via, and etch high-low edge HEMT substrate region via (wet etching or dry etching or dry-wet mixed etching process).

[0069] Step 12: Deposition of metal (including but not limited to Ti / Al / Ni / Au, Ti / Al / Mo / Au and other certain metal or multiple metal stacks) by electron beam evaporation / magnetron sputtering process, and metal patterning (wet etching or dry etching or dry-wet mixed etching process), forming low edge metal connection line 18 and high edge metal connection line 19, and high temperature annealing to realize ohmic contact, forming low edge source 12, low edge drain 14, low edge substrate 16, high edge source 13, high edge drain 15 and high edge substrate 17.

[0070] Step 13: Deposition of passivation layer 9 (including but not limited to PECVD deposition process)

[0071] Step 14: etching to obtain a gate assembly via (wet etching or dry etching or dry-wet mixed etching process), depositing metal (including but not limited to Ni / Au and other certain metal or metal stack), and patterning the gate metal to form the low-side gate 10 and the high-side gate 11.

[0072] The various embodiments are described in a progressive manner in the specification, each of which focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part.

[0073] The principles and implementation manners of the present application are described by using specific examples in the specification, and the above embodiment description is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present application. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A monolithic integrated half-bridge circuit structure, characterized in that, include: Passivation layer and a substrate with trenches; The trench is disposed within the substrate; the passivation layer is disposed on the upper surface of the substrate and within the trench; The substrate includes a substrate electrode and a first P electrode arranged sequentially from bottom to top. + Substrate, N - Substrate, second P + Substrate layer, buffer layer, GaN channel layer and AlGaN barrier layer; The first P + Substrate and the N - The substrate layer forms the first PN junction; The N - Substrate layer and the second P + The substrate layer forms a second PN junction; The trench extends through the AlGaN barrier layer, the GaN channel layer, the buffer layer, and the second P. + The substrate layer, and the bottom of the trench is located at the N. - The interior of the substrate layer; A high-side electrode group is provided on one side of the trench; A low-side electrode group is provided on the other side of the trench; Both the high-side electrode group and the low-side electrode group include: a substrate electrode, a source electrode, a gate assembly, and a drain electrode; The source, the gate assembly, and the drain are all embedded in the passivation layer and in contact with the upper surface of the AlGaN barrier layer; The substrate electrode is embedded in the passivation layer and the substrate through a substrate electrode hole; The substrate via extends through the passivation layer, the AlGaN barrier layer, the GaN channel layer, and the buffer layer; and the bottom of the substrate via is located at the second P + The interior of the substrate layer; The drain of the high-side electrode group is connected to the power supply; The substrate electrode in the high-side electrode group and the drain electrode in the low-side electrode group are both connected to the source electrode in the high-side electrode group; Both the substrate electrode and the source electrode in the low-side electrode group are grounded; The potential range of the substrate electrode is 0 to V. in .

2. The monolithic integrated half-bridge circuit structure according to claim 1, characterized in that, The height of the gate assembly is greater than the thickness of the passivation layer; the height of the source and the height of the drain are both equal to the thickness of the passivation layer.

3. The monolithic integrated half-bridge circuit structure according to claim 1, characterized in that, The gate assembly includes a pGaN cap layer and a gate, arranged sequentially from bottom to top.

4. The monolithic integrated half-bridge circuit structure according to claim 1, characterized in that, The first P + The substrate material includes silicon, sapphire, silicon carbide, or self-supporting GaN.

5. The monolithic integrated half-bridge circuit structure according to claim 1, characterized in that, The N - The substrate layer includes silicon, sapphire, silicon carbide, or self-supporting GaN materials.

6. The monolithic integrated half-bridge circuit structure according to claim 1, characterized in that, The second P + The substrate layer includes silicon, sapphire, silicon carbide, or self-supporting GaN materials.

7. The monolithic integrated half-bridge circuit structure according to claim 1, characterized in that, The material of the buffer layer includes iron-doped gallium nitride, carbon-doped gallium nitride, iron-doped superlattice structure, or carbon-doped superlattice structure.

8. The monolithic integrated half-bridge circuit structure according to claim 3, characterized in that, The passivation layer is made of materials including silicon tetranitride, silicon dioxide, or aluminum oxide.

9. A method for fabricating a monolithic integrated half-bridge circuit structure, characterized in that, include: Obtain an N-substrate layer; the N-substrate layer is an N-type silicon wafer; In N - The first P is fabricated on one side of the substrate. + Substrate layer; fabrication of the first P + The substrate layer can be grown epitaxially or by ion implantation followed by thermal diffusion. Electron beam evaporation sputtering process was used in the first P + Metal is deposited on the side of the substrate layer away from the N-substrate layer and annealed at high temperature to achieve ohmic contact, forming the substrate electrode; The methods for depositing metals are electron beam evaporation or magnetron sputtering. In N - The second P is prepared on the other side of the substrate layer. + Substrate layer; fabrication of the second P + The substrate layer can be grown epitaxially or by ion implantation followed by thermal diffusion. In the second P + A buffer layer, a GaN channel layer, an AlGaN barrier layer, and a pGaN cap layer are sequentially grown on the side of the substrate layer away from the N-substrate layer. Etch trenches and deposit passivation layers, and perform mesa isolation; The methods for etching trenches include dry etching, wet etching, or a combination of dry and wet etching processes; Etch the pGaN cap layer and deposit a passivation layer; Etch low-edge source vias, low-edge drain vias, low-edge substrate vias, high-edge source vias, high-edge drain vias, and high-edge substrate vias; the high-edge substrate vias and the low-edge substrate vias both penetrate the passivation layer, the AlGaN barrier layer, the GaN channel layer, and the buffer layer; and the bottoms of the high-edge substrate vias and the low-edge substrate vias are both located inside the second P+ substrate layer; Deposit ohmic contact metal and perform metal patterning to form low-side metal interconnects and high-side metal interconnects, and anneal at high temperature to form low-side source, low-side drain, low-side substrate, high-side source, high-side drain and high-side substrate, and deposit passivation layer. Etching creates a via in the gate region, depositing metal, and patterning the gate metal to form a low-side gate and a high-side gate. The potential range of the substrate electrode is 0 to V. in .

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