Shift register and driving method thereof, gate driving circuit and display device

Abstract

Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register comprises a frame reset module configured to provide a signal of a third power supply end to a pull-up node under control of a frame reset signal end; a first pull-down control module coupled with a fourth node and a first pull-down node respectively, the fourth node being coupled with a first power supply end, configured to provide a signal of the fourth node to the first pull-down node under control of the fourth node, and further configured to provide a signal of the first pull-down node to the fourth node under control of the first pull-down node; a first level adjustment module coupled with the third node, the fourth node and a fifth node respectively, the fifth node being coupled with a third power supply end, the third node being coupled with the frame reset signal end, configured to provide a signal of the third power supply end to the fourth node under control of the third node; and a first noise reduction module configured to provide a signal of the third power supply end to the pull-up node under control of the first pull-down node.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register and its driving method, gate driving circuit and display device. Background Technology

[0002] GOA (Gate Drive On Array) technology is a technology that integrates the gate drive circuitry onto the array substrate, thereby replacing the gate drive chip to reduce power consumption and cost.

[0003] The active layer material of the thin-film transistors used in GOA circuits can be a-Si (amorphous silicon), LTPS (low-temperature polycrystalline silicon), or IGZO (Indium Gallium Zinc Oxide). Large-size displays typically use IGZO as the active layer material for the GOA circuit. However, as the display size and resolution increase further, oxide material thin-film transistors with higher mobility are required for the GOA circuit.

[0004] Existing products using oxide materials have defects such as abnormal screen scanning, which affects the quality of display products. Summary of the Invention

[0005] This disclosure provides a shift register and its driving method, a gate driving circuit, and a display device to solve or alleviate one or more technical problems in the prior art.

[0006] As a first aspect of the present disclosure, an embodiment of the present disclosure provides a shift register, including:

[0007] The input module is coupled to the signal input terminal and the pull-up node respectively, and is configured to provide the signal input terminal to the pull-up node under the control of the signal input terminal;

[0008] The frame reset module is coupled to the frame reset signal terminal, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the frame reset signal terminal.

[0009] The first pull-down module is coupled to the signal input terminal, the first pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide the signal of the third power supply terminal to the first pull-down node under the control of the signal input terminal and / or the pull-up node.

[0010] The first pull-down control module is coupled to the fourth node and the first pull-down node respectively. The fourth node is coupled to the first power supply terminal. The first pull-down control module is configured to provide the signal of the fourth node to the first pull-down node under the control of the fourth node. The first pull-down control module is also configured to provide the signal of the first pull-down node to the fourth node under the control of the first pull-down node.

[0011] The first level adjustment module is coupled to the third node, the fourth node and the fifth node respectively. The fifth node is coupled to the third power supply terminal and the third node is coupled to the frame reset signal terminal. The first level adjustment module is configured to provide the signal of the third power supply terminal to the fourth node under the control of the third node.

[0012] The first noise reduction module is coupled to the first pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the first pull-down node.

[0013] The output module is coupled to the pull-up node, the clock signal terminal and the first signal output terminal respectively, and is configured to provide the clock signal terminal to the first signal output terminal under the control of the pull-up node;

[0014] The output pull-down module is coupled to the first pull-down node, the fourth power supply terminal, and the first signal output terminal, respectively, and is configured to provide the signal of the fourth power supply terminal to the first signal output terminal under the control of the first pull-down node or the second pull-down node.

[0015] In some embodiments, a first capacitor is further included, which is coupled between the frame reset signal terminal and the third node, and the two plates of the first capacitor are coupled to the frame reset signal terminal and the third node, respectively.

[0016] In some embodiments, a resistor module is further included, with its two ends coupled to the fifth node and the third power supply terminal, respectively.

[0017] In some embodiments, it also includes:

[0018] The first reset module is coupled to the first reset signal terminal, the pull-up node and the third power supply terminal respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the first reset signal terminal.

[0019] The second reset module is coupled to the second reset signal terminal, the first signal output terminal and the fourth power supply terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first signal output terminal under the control of the second reset signal terminal.

[0020] In some embodiments, it also includes:

[0021] The second pull-down module is coupled to the signal input terminal, the second pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide the signal of the third power supply terminal to the second pull-down node under the control of the signal input terminal and / or the pull-up node;

[0022] The second pull-down control module is coupled to the sixth node and the second pull-down node respectively. The sixth node is coupled to the second power supply terminal. The second pull-down control module is configured to provide the signal of the sixth node to the second pull-down node under the control of the sixth node. The second pull-down control module is also configured to provide the signal of the second pull-down node to the sixth node under the control of the second pull-down node. The second power supply terminal and the first power supply terminal are at opposite potentials at the same time.

[0023] The second level adjustment module is coupled to the third node, the sixth node and the fifth node respectively. The second level adjustment module is configured to provide a signal from the third power supply terminal to the sixth node under the control of the third node.

[0024] The second noise reduction module is coupled to the second pull-down node, the pull-up node, and the third power supply terminal, respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the second pull-down node.

[0025] In some embodiments, at least one of the following is included:

[0026] The input module includes a first transistor, the gate of which is coupled to the signal input terminal, and the first and second terminals of the first transistor are coupled to the signal input terminal and the pull-up node, respectively.

[0027] The frame reset module includes a fifteenth transistor, the gate of which is coupled to the frame reset signal terminal, and the first and second terminals of the fifteenth transistor are coupled to the pull-up node and the third power supply terminal, respectively.

[0028] The first pull-down module includes a sixth transistor A and a seventh transistor A. The gate of the sixth transistor A is coupled to the pull-up node, and the first and second terminals of the sixth transistor A are coupled to the third power supply terminal and the first pull-down node, respectively. The gate of the seventh transistor A is coupled to the signal input terminal, and the first and second terminals of the seventh transistor A are coupled to the third power supply terminal and the first pull-down node, respectively.

[0029] The first pull-down control module includes a fifth transistor A. The gate of the fifth transistor A is coupled to both the first and second terminals of the fifth transistor A. The first terminal of the fifth transistor A is coupled to the fourth node, and the second terminal of the fifth transistor A is coupled to the first pull-down node.

[0030] The first level adjustment module includes a fourteenth transistor A, the gate of which is coupled to the third node, and the first and second terminals of the fourteenth transistor A are coupled to the fourth and fifth nodes, respectively.

[0031] The first noise reduction module includes an eighth transistor A, the gate of which is coupled to a first pull-down node, and the first and second terminals of the eighth transistor A are coupled to a third power supply terminal and a pull-up node, respectively.

[0032] The second pull-down module includes a sixth transistor B and a seventh transistor B. The gate of the sixth transistor B is coupled to the pull-up node, and the first and second terminals of the sixth transistor B are coupled to the third power supply terminal and the second pull-down node, respectively. The gate of the seventh transistor B is coupled to the signal input terminal, and the first and second terminals of the seventh transistor B are coupled to the third power supply terminal and the second pull-down node, respectively.

[0033] The second pull-down control module includes a fifth transistor B. The gate of the fifth transistor B is coupled to both the first and second terminals of the fifth transistor B. The first terminal of the fifth transistor B is coupled to the sixth node, and the second terminal of the fifth transistor B is coupled to the second pull-down node.

[0034] The second level adjustment module includes a fourteenth transistor B, the gate of which is coupled to the third node, and the first and second terminals of the fourteenth transistor B are coupled to the sixth and fifth nodes, respectively.

[0035] The second noise reduction module includes an eighth transistor B, whose gate is coupled to a second pull-down node, and whose first and second terminals are coupled to a third power supply terminal and a pull-up node, respectively.

[0036] In some embodiments,

[0037] The output module includes a third transistor and a bootstrap capacitor. The gate of the third transistor is coupled to the pull-up node, the first terminal of the third transistor is coupled to the clock signal terminal, and the second terminal of the third transistor is coupled to the first signal output terminal. The first and second terminals of the bootstrap capacitor are coupled to the pull-up node and the first signal output terminal, respectively.

[0038] The output pull-down module includes a thirteenth transistor A. The gate of the thirteenth transistor A is coupled to the first pull-down node. The first and second terminals of the thirteenth transistor A are coupled to the fourth power supply terminal and the first signal output terminal, respectively.

[0039] In some embodiments, the output pull-down module further includes a thirteenth transistor B, the gate of which is coupled to the second pull-down node, and the first and second terminals of the thirteenth transistor B are coupled to the fourth power supply terminal and the first signal output terminal, respectively.

[0040] In some embodiments,

[0041] The output module also includes an eleventh transistor and a second signal output terminal. The gate of the eleventh transistor is coupled to the pull-up node, the first terminal of the eleventh transistor is coupled to the clock signal terminal, and the second terminal of the eleventh transistor is coupled to the second signal output terminal.

[0042] The output pull-down module also includes a twelfth transistor A, the gate of which is coupled to the first pull-down node, the first terminal of which is coupled to the third power supply terminal, and the second terminal of which is coupled to the second signal output terminal.

[0043] The output pull-down module also includes a twelfth transistor B, whose gate is coupled to the second pull-down node, whose first terminal is coupled to the third power supply terminal, and whose second terminal is coupled to the second signal output terminal.

[0044] In some embodiments, during the display phase of the display device, the signals of the third power terminal and the fourth power terminal are the same, and during the power-off phase of the display device, the signal of the fourth power terminal is the same as the signal of the first power terminal.

[0045] As a second aspect of the present disclosure, the present disclosure provides a method for driving a shift register, applied to a shift register in any embodiment of the present disclosure, the method comprising:

[0046] The signal input terminal provides a low-level signal, the frame reset signal terminal provides a high-level signal, the first pull-down control module provides the first pull-down node signal to the fourth node under the control of the first pull-down node, and the first level adjustment module provides the third power supply terminal signal to the fourth node under the control of the third node.

[0047] As a third aspect of the present disclosure, the present disclosure provides a gate drive circuit including a plurality of cascaded shift registers as in any embodiment of the present disclosure.

[0048] In some embodiments, the signal input terminal of the first-stage shift register is coupled to the trigger signal, and the frame reset signal provided to the frame reset signal terminal is located before the trigger signal provided to the signal input terminal of the first-stage shift register.

[0049] As a fourth aspect of the present disclosure, the present disclosure provides a display device including a shift register of any embodiment of the present disclosure or a gate driving circuit of any embodiment of the present disclosure.

[0050] The technical solution of this disclosure can reduce the time when the first pull-down node is at a high level, extend the time when the first pull-down node is at a low level, suppress the characteristic drift of the first noise reduction module, reduce the discharge of the pull-up node through the first noise reduction module, reduce the leakage of the pull-up node, facilitate the full operation of the output module and provide the clock signal to the first signal output terminal, improve the signal attenuation distortion of the first signal output terminal, and improve the abnormal scanning display of the display device.

[0051] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0052] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0053] Figure 1a This is a schematic diagram of the circuit structure of a shift register in related technologies;

[0054] Figure 1b for Figure 1a The timing diagram of the shift register shown is shown below.

[0055] Figure 2 This is a schematic diagram of the structure of a shift register in one embodiment of the present disclosure;

[0056] Figure 3 This is a schematic diagram of the shift register structure in another embodiment of the present disclosure;

[0057] Figure 4 This is a schematic diagram of the shift register structure in another embodiment of the present disclosure;

[0058] Figure 5 This is a timing diagram of the shift register in one embodiment of the present disclosure;

[0059] Figure 6 This is a block diagram of the gate drive circuit in one embodiment of the present disclosure. Detailed Implementation

[0060] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are to be considered exemplary in nature and not restrictive.

[0061] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in these embodiments are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In these embodiments, the source (source electrode) is referred to as the first electrode, and the drain (drain electrode) as the second electrode; alternatively, the drain can be referred to as the first electrode, and the source as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the gate (also called the gate electrode), the signal input terminal as the source, and the signal output terminal as the drain. The switching transistors used in these embodiments can be P-type or N-type switching transistors. P-type switching transistors conduct when the gate is low and are cut off when the gate is high; N-type transistors conduct when the gate is high and are cut off when the gate is low. Furthermore, multiple signals in each embodiment of this invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential states of the signal and do not imply that the first potential or the second potential has a specific numerical value throughout the text. In this embodiment of the invention, the first potential is used as an example for explanation.

[0062] The coupling can include direct physical contact between the two ends or indirect connection between the two ends (such as establishing a connection between the two ends through a signal line). This embodiment of the invention does not limit the coupling method between the two ends.

[0063] GOA circuits can be used in display devices. A GOA circuit includes multiple cascaded shift registers, each with its signal output coupled to the gate line of a row of pixels to provide a gate drive signal, thereby driving the display device to display data. The shift registers include multiple thin-film transistors.

[0064] In order to apply oxide material thin-film transistors with higher mobility to GOA circuits, oxide processes have been developed in a more advanced direction, evolving from Mob10 to Mob20. Figure 1a This is a schematic diagram of the circuit structure of a shift register in related technologies. Figure 1b for Figure 1a The timing diagram of the shift register shown is as follows. Figure 1a As shown, the first power supply terminal VDDA and the second power supply terminal VDDB are at opposite phases at the same time. For example, at the same time, one of the first power supply terminals VDDA and the other of VDDB provides a high-level signal, while the other provides a low-level signal. Therefore, Figure 1a The first and second parts can work alternately to extend the lifespan of the fifth transistor.

[0065] The inventors of this case discovered that, affected by the fifth transistor M5 (A, B), during the process of switching from a high level VGH to a low level VGL at the first power supply terminal VDDA or the second power supply terminal VDDB, the gate of the fifth transistor M5 (A, B) is already turned off before it has fully switched to the low level VGL. This causes the low level signal of the first pull-down node PD1 or the second pull-down node PD2 to be less than the level signal of the third power supply terminal VGL, thereby causing leakage at the pull-up node PU.

[0066] Let's take the first part being in working condition as an example to illustrate. Figure 1a The shift register shown operates as follows: the first power supply terminal VDDA is high, and the second power supply terminal VDDB is low.

[0067] like Figure 1a and Figure 1b As shown, in stage T1, the signal input terminal INPUT provides a high level, the first transistor M1 is turned on, and the pull-up node PU is charged; the seventh transistor M7 (A, B) is turned on, and the signal of the third power supply terminal VGL is provided to the first pull-down node PD1 and the second pull-down node PD2, and the first pull-down node PD1 and the second pull-down node PD2 are discharged; under the control of the pull-up node PU, the third transistor M3 and the eleventh transistor M11 are both turned on, and the clock signal is provided to the first signal output terminal Gout and the second signal output terminal OC out.

[0068] In phase T2, the signal input terminal INPUT provides a low-level signal, the clock signal terminal CLK outputs a high-level signal, the first transistor M1 is turned off, the pull-up node PU stops charging, and the seventh transistors (M7A and M7B) are both turned off. The first signal output terminal Gout and the second signal output terminal OC out output a high level. Under the action of the bootstrap capacitor C1, the voltage of the pull-up node PU rises again, causing the sixth transistors M6A and M6B to be fully turned on, continuously providing the third power supply terminal VGL signal to the first pull-down node PD1 and the second pull-down node PD2. Under the control of the pull-up node PU, the third transistor M3 and the eleventh transistor M11 are both turned on, providing the clock signal terminal high-level signal to the first signal output terminal Gout and the second signal output terminal OC out. The first signal output terminal Gout outputs a high-level signal.

[0069] In the Mob process, oxide thin-film transistors exhibit left-shifting characteristics. Figure 1aIn the circuit, the eighth transistor (M8A and M8B) and the sixth transistor (M6A and M6B) exhibit left drift with amplitudes of approximately 1.4V and 0.5V, respectively, causing the threshold voltage Vth of the eighth transistor (M8A and M8B) to be less than 0V. The left drift of the eighth transistor M8B leads to continuous leakage at the pull-up node PU. The left drift of the sixth transistor (M6B) prevents the second pull-down node PD2 from being pulled low to the potential of the third power supply terminal VGL, resulting in the potential of the second pull-down node PD2 being greater than the potential of the third power supply terminal VGL. This, in turn, affects the leakage current of the third transistor M8B, causing continuous leakage at the pull-up node PU. Consequently, the third transistor M3 and the eleventh transistor M11 cannot be fully turned on. Furthermore, due to the influence of the cascaded shift registers in the gate drive circuit, the signals at the first signal output terminal Gout and the second signal output terminal OC out are attenuated and distorted, gradually losing output, resulting in abnormal screen scanning display.

[0070] Figure 2 This is a schematic diagram of the shift register structure in one embodiment of the present disclosure. In one embodiment, as shown in FIG1, the shift register includes an input module 11, a frame reset module 12, a first pull-down module 21, a first pull-down control module 23, a first level adjustment module 24, a first noise reduction module 22, an output module 14, and an output pull-down module 15.

[0071] The input module 11 is coupled to the signal input terminal INPUT and the pull-up node PU respectively. The input module 11 is configured to provide the signal of the signal input terminal INPUT to the pull-up node PU under the control of the signal input terminal INPUT.

[0072] The frame reset module 12 is coupled to the frame reset signal terminal TRST (Total RST), the third power supply terminal VGL, and the pull-up node PU, respectively. The frame reset module 12 is configured to provide the signal of the third power supply terminal VGL to the pull-up node PU under the control of the frame reset signal terminal TRST.

[0073] The first pull-down module 21 is coupled to the signal input terminal INPUT, the first pull-down node PD1, the pull-up node PU, and the third power supply terminal VGL. The first pull-down module 21 is configured to provide the signal of the third power supply terminal VGL to the first pull-down node PD1 under the control of the signal input terminal INPUT and / or the pull-up node PU.

[0074] The first pull-down control module 23 is coupled to the fourth node N4 and the first pull-down node PD1 respectively. The fourth node N4 is coupled to the first power supply terminal VDDA. The first pull-down control module 23 is configured to provide the signal of the fourth node N4 to the first pull-down node PD1 under the control of the fourth node N4. The first pull-down control module 23 is also configured to provide the signal of the first pull-down node PD1 to the fourth node N4 under the control of the first pull-down node PD1.

[0075] The first level adjustment module 24 is coupled to the third node N3, the fourth node N4 and the fifth node N5 respectively. The fifth node N5 is coupled to the third power supply terminal VGL. The third node N3 is coupled to the frame reset signal terminal TRST. The first level adjustment module 24 is configured to provide the signal of the third power supply terminal VGL to the fourth node N4 under the control of the third node N3.

[0076] The first noise reduction module 22 is coupled to the first pull-down node PD1, the pull-up node PU and the third power supply terminal VGL respectively. The first noise reduction module 22 is configured to provide the signal of the third power supply terminal VGL to the pull-up node PU under the control of the first pull-down node PD1.

[0077] The output module 14 is connected to the pull-up node PU, the clock signal terminal CLK, and the first signal output terminal Gout. The output module 14 is configured to provide the clock signal terminal CLK to the first signal output terminal Gout under the control of the pull-up node PU.

[0078] The output pull-down module 15 is coupled to the first pull-down node PD1, the fourth power supply terminal LVGL and the first signal output terminal Gout respectively. The output pull-down module 15 is configured to provide the signal of the fourth power supply terminal LVGL to the first signal output terminal Gout under the control of the first pull-down node PD1 or the second pull-down node PD2.

[0079] For example, when the first pull-down control module 23 provides the signal of the first pull-down node PD1 to the fourth node N4 under the control of the first pull-down node PD1, the first level adjustment module 24, under the control of the third node N3, provides the signal of the third power supply terminal VGL to the fourth node N4 through the fifth node N5, thereby discharging the fourth node N4, and then discharging the first power supply terminal VDDA and the first pull-down node PD1.

[0080] In this embodiment of the shift register, when the first pull-down node PD1 is at a high level, the first pull-down control module 23 can provide the signal of the first pull-down node PD1 to the fourth node N4 under the control of the first pull-down node PD1; when the frame reset signal terminal TRST provides a high level, the third node N3 can also provide a high level, and the first level adjustment module 24, under the control of the third node N3, provides the signal of the third power supply terminal VGL to the fourth node N4 through the fifth node N5, thereby discharging the fourth node N4, discharging the first power supply terminal VDDA, and discharging the first pull-down node PD1. Therefore, the shift register in this embodiment of the present disclosure can reduce the time when the first pull-down node PD1 is at a high level, prolong the time when the first pull-down node PD1 is at a low level, suppress the characteristic drift of the first noise reduction module 22, reduce the discharge of the pull-up node PU through the first noise reduction module 22, reduce the leakage current of the pull-up node PU, which is beneficial for the output module 14 to work fully and provide the clock signal terminal CLK to the first signal output terminal Gout, improve the signal attenuation distortion of the first signal output terminal Gout, and improve the abnormal screen scanning display of the display device.

[0081] In this embodiment of the present disclosure, the shift register and frame reset module 12 can provide the third power supply terminal VGL signal to the upward node PU under the control of the frame reset signal terminal TRST, so as to reset the shift registers of each stage in the gate drive circuit before the frame is generated, avoid the residue of the previous frame, and improve the display effect.

[0082] It should be noted that in the gate drive circuit of the display device, multiple shift registers are cascaded, and the signal input terminal INPUT of the first-stage shift register is connected to the trigger signal. In one embodiment, the frame reset signal provided to the frame reset signal terminal TRST precedes the trigger signal provided to the signal input terminal INPUT of the first-stage shift register. For example, if both the frame reset signal and the trigger signal are high-level signals, then the falling edge of the frame reset signal precedes the rising edge of the trigger signal.

[0083] Figure 3 This is a schematic diagram of the structure of a shift register according to another embodiment of this disclosure. In one embodiment, such as... Figure 3 As shown, the shift register may also include a first capacitor C2, which is coupled between the frame reset signal terminal TRST and the third node N3. The two plates of the first capacitor C2 are coupled to the frame reset signal terminal TRST and the third node N3, respectively.

[0084] The first capacitor C2 can store charge. When the frame reset signal terminal TRST provides a high level, TRST charges the first capacitor C2, and the voltage of the third node N3 rises. After reaching the threshold voltage, the first level module, under the control of the third node N3, provides the signal of the third power supply terminal VGL to the fourth node N4. When the frame reset signal terminal TRST changes from high level to low level, the first capacitor C2 slowly discharges. The stored charge can extend the working time of the first level adjustment module 24, extend the time for the fourth node N4 to discharge, and further extend the time for the first power supply terminal VDDA to discharge and for the first pull-down node PD1 to discharge.

[0085] By setting the first capacitor C2, the time when the first pull-down node PD1 is at a high level can be further reduced, the time when the first pull-down node PD1 is at a low level can be extended, the characteristic drift of the first noise reduction module 22 can be better suppressed, the leakage of the pull-up node PU can be further reduced, and the signal attenuation distortion of the first signal output terminal Gout and the abnormal scanning display in the display device can be further improved.

[0086] In one embodiment, the shift register further includes a resistor module R1, the two ends of which are coupled to the fifth node N5 and the third power supply terminal VGL, respectively.

[0087] In this embodiment of the disclosure, during the discharge process of the fourth node N4, the first power supply terminal VDDA, the fourth node N4, the first level adjustment module 24, the fifth node N5, and the third power supply terminal VGL constitute a discharge circuit. By setting the resistor module R1 at the fifth node N5 and the third power supply terminal VGL, the discharge current in the discharge circuit of the fourth node N4 can be reduced.

[0088] For example, resistor module R1 may include a single resistor, or resistor module R1 may include multiple resistors connected in series. The specific resistance value of resistor module R1 can be set as needed.

[0089] In one implementation, such as Figure 2 and Figure 3 As shown, the shift register may also include a first reset module 13 and a second reset module 16. The first reset module 13 is coupled to the first reset signal terminal RST1, the pull-up node PU, and the third power supply terminal VGL, respectively, and is configured to provide the signal of the third power supply terminal VGL to the pull-up node PU under the control of the first reset signal terminal RST1, thereby resetting the pull-up node PU.

[0090] The second reset module 16 is coupled to the second reset signal terminal RST2, the first signal output terminal Gout, and the fourth power supply terminal LVGL, respectively. It is configured to provide the signal of the fourth power supply terminal LVGL to the first signal output terminal Gout under the control of the second reset signal terminal RST2, so as to reset the first signal output terminal Gout.

[0091] By setting the first reset module 13 and the second reset module 16, the pull-up node PU and the first signal output terminal Gout can be reset respectively, ensuring that the first signal output terminal Gout has no drive signal output.

[0092] In one implementation, such as Figure 2 and Figure 3 As shown, the shift register may also include a second pull-down module 31, a second pull-down control module 33, a second level adjustment module 34, and a second noise reduction module 32.

[0093] The second pull-down module 31 is coupled to the signal input terminal INPUT, the second pull-down node PD2, the pull-up node PU, and the third power supply terminal VGL. The second pull-down module 31 is configured to provide the signal of the third power supply terminal VGL to the second pull-down node PD2 under the control of the signal input terminal INPUT and / or the pull-up node PU.

[0094] The second pull-down control module 33 is coupled to the sixth node N6 and the second pull-down node PD2, respectively. The sixth node N6 is coupled to the second power supply terminal VDDB. The second pull-down control module 33 is configured to provide the signal of the sixth node N6 to the second pull-down node PD2 under the control of the sixth node N6. The second pull-down control module 33 is also configured to provide the signal of the second pull-down node PD2 to the sixth node N6 under the control of the second pull-down node PD2. The second power supply terminal VDDB and the first power supply terminal VDDA are at opposite phases at the same time.

[0095] The second level adjustment module 34 is coupled to the third node N3, the sixth node N6 and the fifth node N5 respectively. The second level adjustment module 34 is configured to provide the third power supply terminal VGL signal to the sixth node N6 under the control of the third node N3.

[0096] The second noise reduction module 32 is coupled to the second pull-down node PD2, the pull-up node PU and the third power supply terminal VGL respectively. The second noise reduction module 32 is configured to provide the signal of the third power supply terminal VGL to the pull-up node PU under the control of the second pull-down node PD2.

[0097] In one embodiment, the output module 14 is also coupled to the second signal output terminal OC out, and the output module 14 is further configured to provide the clock signal terminal CLK to the second signal output terminal OC out under the control of the pull-up node PU.

[0098] In one embodiment, the output pull-down module 15 is also coupled to the second pull-down node PD2, and the output pull-down module 15 is also configured to provide the signal of the fourth power supply terminal LVGL to the second signal output terminal OC out under the control of the first pull-down node PD1 or the second pull-down node PD2.

[0099] Such shift registers, such as Figure 2 and Figure 3 As shown, the first pull-down module 21, the first pull-down control module 23, the first level adjustment module 24, and the first noise reduction module 22 can form the first part, and the second pull-down module 31, the second pull-down control module 33, the second level adjustment module 34, and the second noise reduction module 32 can form the second part.

[0100] For example, the first power supply terminal VDDA and the second power supply terminal VDDB are in opposite phase at the same time. For instance, when the first power supply terminal VDDA provides a high-level signal and the second power supply terminal VDDB provides a low-level signal, the first part is in the working state; when the first power supply terminal VDDA provides a low-level signal and the second power supply terminal VDDB provides a high-level signal, the second part is in the working state. With such a shift register, the first and second parts can work alternately, extending the lifespan of the devices in the first pull-down control module 23 and the second pull-down control module 33, and thus extending the lifespan of the shift register.

[0101] In this embodiment of the shift register, when the first part is in the working state, the first power supply terminal VDDA provides a high-level signal. When the frame reset signal terminal TRST provides a high level, the first level adjustment module 24 can, under the control of the third node N3, provide the third power supply terminal VGL signal to the fourth node N4 through the fifth node N5, thereby discharging the fourth node N4, and thus discharging the first power supply terminal VDDA and the first pull-down node PD1, reducing the time when the first pull-down node PD1 is at a high level, extending the low level time of the first pull-down node PD1, and suppressing the characteristic drift of the first noise reduction module 22.

[0102] When the second part is in operation, the second power supply terminal VDDB provides a high-level signal. When the frame reset signal terminal TRST provides a high level, the second level adjustment module 34 can, under the control of the third node N3, provide the signal of the third power supply terminal VGL to the sixth node N6 through the fifth node N5, thereby discharging the sixth node N6, and thus discharging the second power supply terminal VDDB and the second pull-down node PD2, reducing the time that the second pull-down node PD2 is at a high level, extending the time that the second pull-down node PD2 is at a low level, and suppressing the characteristic drift of the second noise reduction module 32.

[0103] Whether the first part or the second part is in working state, the technical solution disclosed herein suppresses the characteristic drift of the first noise reduction module 22 and the second noise reduction module 32, reduces the leakage current of the pull-up node PU, which is conducive to the full operation of the output module 14 and provides the clock signal terminal CLK to the first signal output terminal Gout, improves the signal attenuation distortion of the first signal output terminal Gout, and improves the abnormal screen scanning display of the display device.

[0104] Figure 4 This is a schematic diagram of the structure of a shift register according to another embodiment of this disclosure. In one embodiment, such as... Figure 4 As shown, the first drop-down module 21 includes a first drop-down submodule and a first auxiliary drop-down submodule.

[0105] For example, the first pull-down submodule is coupled to the pull-up node PU, the third power supply terminal VGL and the first pull-down node PD1 respectively, and is configured to provide the signal of the third power supply terminal VGL to the first pull-down node PD1 under the control of the pull-up node PU.

[0106] For example, the first auxiliary pull-down submodule is coupled to the signal input terminal INPUT, the third power supply terminal VGL and the first pull-down node PD1 respectively, and is configured to provide the signal of the third power supply terminal VGL to the first pull-down node PD1 under the control of the signal input terminal INPUT.

[0107] When a valid level signal is provided at the signal input terminal INPUT, the input module 11, under the control of the signal input terminal INPUT, provides the signal from the signal input terminal INPUT to the pull-up node PU, charging the pull-up node PU and thus raising its potential. Under the control of the signal input terminal INPUT, the first auxiliary pull-down submodule provides the signal from the third power supply terminal VGL to the first pull-down node PD1, causing the first pull-down node PD1 to discharge and thus lower its potential. After the pull-up node PU is pulled high, the first pull-down submodule, under the control of the pull-up node PU, provides the signal from the third power supply terminal VGL to the first pull-down node PD1, causing the first pull-down node PD1 to discharge and thus lower its potential. The first auxiliary pull-down submodule and the first pull-down submodule cooperate to ensure that during the phase when the pull-up node PU is pulled high, the first pull-down node PD1 is continuously pulled low and maintained at a low potential. Therefore, the first noise reduction module can be completely turned off under the control of the first pull-down node PD1, preventing the pull-up node PU from discharging through the first noise reduction module 22 and reducing the leakage current of the pull-up node PU.

[0108] In one embodiment, the second drop-down module 31 includes a second drop-down sub-module and a second auxiliary drop-down module.

[0109] For example, the second pull-down submodule is coupled to the pull-up node PU, the third power terminal VGL, and the second pull-down node PD2, respectively, and is configured to provide the signal of the third power terminal VGL to the second pull-down node PD2 under the control of the pull-up node PU.

[0110] For example, the second auxiliary pull-down submodule is coupled to the signal input terminal INPUT, the third power supply terminal VGL, and the second pull-down node PD2, and is configured to provide the signal of the third power supply terminal VGL to the second pull-down node PD2 under the control of the signal input terminal INPUT.

[0111] When the second part is in operation, the second auxiliary pull-down submodule and the second pull-down submodule cooperate with each other so that when the pull-up node PU is pulled up, the second pull-down node PD2 is continuously pulled down and maintained at a low potential. Therefore, the second noise reduction module 32 can be completely turned off under the control of the second pull-down node PD2, preventing the pull-up node PU from discharging through the second noise reduction module 3232 and reducing leakage current in the pull-up node PU.

[0112] In one implementation, such as Figure 4As shown, the input module 11 includes a first transistor M1. The gate of the first transistor M1 is coupled to the signal input terminal INPUT. The first terminal and the second terminal of the first transistor M1 are respectively coupled to the signal input terminal INPUT and the pull-up node PU. Exemplarily, the first transistor M1 can be turned on when the signal input terminal INPUT provides a valid level, providing the signal of the signal input terminal INPUT to the pull-up node PU of the first transistor M1.

[0113] In one implementation, such as Figure 4 As shown, the frame reset module 12 includes a fifteenth transistor M15. The gate of the fifteenth transistor M15 is coupled to the frame reset signal terminal TRST. The first and second terminals of the fifteenth transistor M15 are coupled to the pull-up node PU and the third power supply terminal VGL, respectively. Exemplarily, the fifteenth transistor M15 can be turned on when the frame reset signal terminal TRST provides a valid level, providing the signal of the third power supply terminal VGL to the pull-up node PU.

[0114] In one embodiment, such as Figure 4 As shown, the first pull-down module 21 includes a sixth transistor M6A and a seventh transistor M7A. The gate of the sixth transistor M6A is coupled to the pull-up node PU, and the first and second terminals of the sixth transistor M6A are coupled to the third power supply terminal VGL and the first pull-down node PD1, respectively. Exemplarily, the sixth transistor M6A can be turned on when the pull-up node PU is at an active level, providing the signal of the third power supply terminal VGL to the first pull-down node PD1. The gate of the seventh transistor M7A is coupled to the signal input terminal INPUT, and the first and second terminals of the seventh transistor M7A are coupled to the third power supply terminal VGL and the first pull-down node PD1, respectively. Exemplarily, the seventh transistor M7A can be turned on when the signal input terminal INPUT provides an active level, providing the signal of the third power supply terminal VGL to the first pull-down node PD1.

[0115] In one embodiment, such as Figure 4 As shown, the first pull-down control module 23 includes a fifth transistor M5A, whose gate is coupled to both its first and second terminals. The first terminal of the fifth transistor M5A is coupled to the fourth node N4, and its second terminal is coupled to the first pull-down node PD1. Exemplarily, the fifth transistor M5A can be turned on when the first power supply terminal VDDA is at an active level, providing the first power supply terminal VDDA signal to the first pull-down node PD1. Exemplarily, when discharging the fourth node N4 through the first level adjustment module 24, the fifth transistor M5A can be turned on under the control of the first pull-down node PD1, providing the first pull-down node PD1 signal to the fourth node N4.

[0116] In one embodiment, such as Figure 4 As shown, the first level adjustment module 24 includes a fourteenth transistor M14A. The gate of the fourteenth transistor M14A is coupled to the third node N3, and the first and second terminals of the fourteenth transistor M14A are coupled to the fourth node N4 and the fifth node N5, respectively. Exemplarily, the fourteenth transistor M14A can be turned on when the third node N3 provides an effective level, providing a signal to the third power supply terminal VGL of the fourth node N4, thus discharging the fourth node N4.

[0117] In one embodiment, such as Figure 4 As shown, the first noise reduction module 22 includes an eighth transistor M8A. The gate of the eighth transistor M8A is coupled to the first pull-down node PD1, and the first and second terminals of the eighth transistor M8A are coupled to the third power supply terminal VGL and the pull-up node PU, respectively. Exemplarily, the eighth transistor M8A can be turned on when the first pull-down node PD1 is at an active level, providing the signal of the third power supply terminal VGL to the pull-up node PU.

[0118] In one embodiment, such as Figure 4 As shown, the second pull-down module 31 includes a sixth transistor M6B and a seventh transistor M7B. The gate of the sixth transistor M6B is coupled to the pull-up node PU, and the first and second terminals of the sixth transistor M6B are coupled to the third power supply terminal VGL and the second pull-down node PD2, respectively. Exemplarily, the sixth transistor M6B can be turned on when the pull-up node PU is at an active level, providing the signal of the third power supply terminal VGL to the second pull-down node PD1. The gate of the seventh transistor M7B is coupled to the signal input terminal INPUT, and the first and second terminals of the seventh transistor M7B are coupled to the third power supply terminal VGL and the second pull-down node PD2, respectively. Exemplarily, the seventh transistor M7B can be turned on when the signal input terminal INPUT provides an active level, providing the signal of the third power supply terminal VGL to the second pull-down node PD1.

[0119] In one embodiment, such as Figure 4 As shown, the second pull-down control module 33 includes a fifth transistor M5B, the gate of which is coupled to both its second terminal and its second terminal. The second terminal of the fifth transistor M5B is coupled to a sixth node N6, and also to a second pull-down node PD2. Exemplarily, the fifth transistor M5B can be turned on when the second power supply terminal VDDB is at an active level, providing the signal of the second power supply terminal VDDB to the second pull-down node PD2. Exemplarily, when discharging the sixth node N6 through the second level adjustment module 34, the fifth transistor M5B can be turned on under the control of the second pull-down node PD2, providing the signal of the second pull-down node PD2 to the fourth node N4.

[0120] In one embodiment, such as Figure 4 As shown, the second level adjustment module 34 includes a fourteenth transistor M14B. The gate of the fourteenth transistor M14B is coupled to the third node N3, and the second terminal and the second terminal of the fourteenth transistor M14B are coupled to the sixth node N6 and the fifth node N5, respectively. Exemplarily, the fourteenth transistor M14B can be turned on when the third node N3 provides an effective level, providing a signal to the third power supply terminal VGL of the sixth node N6, thus discharging the sixth node N6.

[0121] In one embodiment, such as Figure 4 As shown, the second noise reduction module 32 includes an eighth transistor M8B. The gate of the eighth transistor M8B is coupled to the second pull-down node PD1, and the first and second terminals of the eighth transistor M8B are coupled to the third power supply terminal VGL and the pull-up node PU, respectively. For example, the eighth transistor M8B can be turned on when the second pull-down node PD2 is at an active level, providing the signal of the third power supply terminal VGL to the pull-up node PU.

[0122] In one embodiment, such as Figure 4 As shown, the first reset module 13 may include a second transistor M2. The gate of the second transistor M2 is coupled to the first reset signal terminal RST1, and the first and second terminals of the second transistor M2 are coupled to the pull-up node PU and the third power supply terminal VGL, respectively. For example, when the first reset signal terminal RST1 provides a valid level, the second transistor M2 is turned on, providing the signal for the third power supply terminal VGL to the pull-up node PU.

[0123] In one embodiment, such as Figure 4 As shown, the second reset module 16 may include a fourth transistor M4. The gate of the fourth transistor M4 is coupled to the second reset signal terminal RST2, and the first and second terminals of the fourth transistor M4 are coupled to the first signal output terminal Gout and the fourth power supply terminal LVGL, respectively. For example, when the second reset signal terminal RST2 provides a valid level, the fourth transistor M4 is turned on, providing the signal from the fourth power supply terminal LVGL to the first signal output terminal Gout.

[0124] In one implementation, such as Figure 4 As shown, the output module 14 includes a third transistor M3 and a bootstrap capacitor C1. The gate of the third transistor M3 is coupled to the pull-up node PU, the first terminal of the third transistor M3 is coupled to the clock signal terminal CLK, and the second terminal of the third transistor M3 is coupled to the first signal output terminal Gout. The first and second terminals of the bootstrap capacitor C1 are coupled to the pull-up node PU and the first signal output terminal Gout, respectively.

[0125] The third transistor M3 is turned on under the high-level signal of the pull-up node PU. When the clock signal terminal CLK is high, it provides a high-level signal of the clock signal terminal CLK to the first signal output terminal Gout, allowing Gout to output a high-level signal. Under the bootstrap effect of the bootstrap capacitor C1, the potential of the pull-up node PU is raised again, making the third transistor M3 turn on more fully, ensuring the stable output of the first signal output terminal Gout, and avoiding attenuation and distortion of the output signal of the first signal output terminal Gout.

[0126] For example, the output pull-down module 15 includes a thirteenth transistor M13A. The gate of the thirteenth transistor M13A is coupled to the first pull-down node PD1, and the first and second terminals of the thirteenth transistor M13A are coupled to the fourth power supply terminal LVGL and the first signal output terminal Gout, respectively. For example, when the corresponding row pixel does not need to be displayed, the thirteenth transistor M13A is turned on when the first pull-down node PD1 is at an active level, providing the signal of the fourth power supply terminal LVGL to the first signal output terminal Gout.

[0127] In one implementation, such as Figure 3 As shown, the output pull-down module 15 also includes a thirteenth transistor M13B. The gate of the thirteenth transistor M13B is coupled to the second pull-down node PD2. The first and second terminals of the thirteenth transistor M13B are coupled to the fourth power supply terminal LVGL and the first signal output terminal Gout, respectively.

[0128] When the first part is in operation, if the corresponding row of pixels does not need to be displayed, the first pull-down node PD1 returns to a high level, and the thirteenth transistor M13A is turned on under the control of the first pull-down node PD1, providing the fourth power supply terminal LVGL signal to the first signal output terminal Gout. When the second part is in operation, if the corresponding row of pixels does not need to be displayed, the second pull-down node PD2 returns to a high level, and the thirteenth transistor M13B is turned on under the control of the second pull-down node PD2, providing the fourth power supply terminal LVGL signal to the first signal output terminal Gout.

[0129] In one implementation, such as Figure 4 As shown, the output module 14 also includes an eleventh transistor M11 and a second signal output terminal OC out. The gate of the eleventh transistor M11 is coupled to the pull-up node PU, the first terminal of the eleventh transistor M11 is coupled to the clock signal terminal CLK, and the second terminal of the eleventh transistor M11 is coupled to the second signal output terminal OC out. Exemplarily, the eleventh transistor M11 is turned on under the control of the pull-up node PU, and can provide the clock signal terminal CLK to the second signal output terminal OC out.

[0130] In the GOA circuit, the first signal output terminal Gout can be coupled to the corresponding gate line, thereby providing a gate drive signal to the corresponding row pixel. The first signal output terminal Gout can also be coupled to the second reset signal terminal RST2 of the previous stage shift register, providing a reset signal to RST2 and resetting the first output signal terminal Gout of the previous stage shift register. The second signal output terminal OC out can be coupled to the signal input terminal INPUT of the next stage shift register to trigger the next stage shift register; the second signal output terminal OC out can also be coupled to the first reset signal terminal RST1 of the previous stage shift register, providing a reset signal to RST1 and resetting the pull-up node PU of the previous stage shift register.

[0131] Exemplarily, the output pull-down module 15 further includes a twelfth transistor M12A, the gate of which is coupled to the first pull-down node PD1, the first terminal of which is coupled to the third power supply terminal VGL, and the second terminal of which is coupled to the second signal output terminal OC out. Exemplarily, the output pull-down module 15 also includes a twelfth transistor M12B, the gate of which is coupled to the second pull-down node PD2, the first terminal of which is coupled to the third power supply terminal VGL, and the second terminal of which is coupled to the second signal output terminal OC out.

[0132] When the first part is in operation, the first power supply terminal VDDA provides a high-level signal, and the second power supply terminal VDDB provides a low-level signal. When the corresponding row of pixels does not need to be displayed, the first pull-down node PD1 returns to a high level, and the twelfth transistor M12A is turned on under the control of the first pull-down node PD1, providing the fourth power supply terminal LVGL signal to the second signal output terminal OC out. When the second part is in operation, the second power supply terminal VDDB provides a high-level signal, and the first power supply terminal VDDA provides a low-level signal. When the corresponding row of pixels does not need to be displayed, the second pull-down node PD2 returns to a high level, and the twelfth transistor M12B is turned on under the control of the second pull-down node PD2, providing the fourth power supply terminal LVGL signal to the second signal output terminal OC out.

[0133] The shift registers of the embodiments of this disclosure, such as Figure 4 As shown, extending the low-level time of either the first pull-down node PD1 or the second pull-down node PD2 extends the V of the eighth transistors M8A and M8B. gs The low-level time can suppress the characteristic left drift of the eighth transistors M8A and M8B.

[0134] For example, the thin-film transistors in the shift register are all oxide transistors, for instance, the active layer of the thin-film transistor is made of oxide.

[0135] For example, the thin-film transistors in the shift register are all NMOS transistors, such as... Figure 4 As shown. When the transistors in the shift register are NMOS transistors, the effective level of each transistor is a high-level signal.

[0136] In one embodiment, the width of the conductive channel of the first transistor M1 can be in the range of 120μm to 280μm, and the length can be in the range of 8μm to 12μm; for example, the width of the conductive channel of the first transistor M1 is 150μm and the length is 10μm.

[0137] The width of the conductive channel of the second transistor M2 can be in the range of 20μm to 30μm, and the length can be in the range of 8μm to 12μm; for example, the width of the conductive channel of the second transistor M2 is 25μm and the length is 10μm.

[0138] The width of the conductive channel of the third transistor M3 can be in the range of 800μm to 1200μm, and the length can be in the range of 4μm to 6μm; for example, the width of the conductive channel of the third transistor M3 is 1000μm and the length is 5μm.

[0139] The width of the conductive channel of the fourth transistor M4 can be in the range of 23μm to 27μm, and the length can be in the range of 4μm to 6μm; for example, the width of the conductive channel of the fourth transistor M4 is 25μm and the length is 5μm.

[0140] The width of the conductive channel of the fifth transistor M5 can be in the range of 4μm to 6μm, and the length can be in the range of 4μm to 6μm; for example, the width of the conductive channel of the fifth transistor M5 is 5μm and the length is 5μm.

[0141] The width of the conductive channel of the sixth transistor M6 (A, B) can be in the range of 35μm to 45μm, and the length can be in the range of 4μm to 6μm; for example, the width of the conductive channel of the sixth transistor M6 (A, B) is 40μm and the length is 5μm.

[0142] The width of the conductive channel of the seventh transistor M7 (A, B) can range from 15μm to 25μm, and the length can range from 4μm to 6μm; for example, the width of the conductive channel of the seventh transistor M7 (A, B) is 20μm and the length is 5μm.

[0143] The width of the conductive channel of the eighth transistor M8 (A, B) can be in the range of 120μm to 160μm, and the length can be in the range of 8μm to 12μm; for example, the width of the conductive channel of the eighth transistor M8 (A, B) is 140μm and the length is 10μm.

[0144] The width of the conductive channel of the eleventh transistor M11 can be in the range of 350μm to 450μm, and the length can be in the range of 4μm to 6μm; for example, the width of the conductive channel of the eleventh transistor M11 is 400μm and the length is 5μm.

[0145] The width of the conductive channel of the twelfth transistor M12 (A, B) can be in the range of 8μm to 12μm, and the length can be in the range of 4μm to 6μm; for example, the width of the conductive channel of the twelfth transistor M12 (A, B) is 10μm and the length is 5μm.

[0146] The width of the conductive channel of the thirteenth transistor M13 (A, B) can be in the range of 35μm to 45μm, and the length can be in the range of 4μm to 6μm; for example, the width of the conductive channel of the thirteenth transistor M13 (A, B) is 40μm and the length is 5μm.

[0147] The width of the conductive channel of the fourteenth transistor M14 (A, B) can range from 18μm to 22μm, and the length can range from 4μm to 6μm; for example, the width of the conductive channel of the fourteenth transistor M14 (A, B) is 20μm and the length is 5μm.

[0148] It should be noted that, in actual use, the type of each transistor in the shift register of this embodiment is not limited. Each transistor can be configured as an NMOS or PMOS transistor as needed, and the effective levels of the signal input terminal INPUT, the first reset signal terminal RST1, the second reset signal terminal RST2, the frame reset signal terminal, the first power supply terminal VDDA, the second power supply terminal VDDB, the third power supply terminal VGL, and the fourth power supply terminal LVGL can be configured accordingly. When the transistors in the shift register are PMOS transistors, the effective level of each transistor is a low-level signal.

[0149] For example, during the display phase of the display device, the signals of the third power terminal VGL and the fourth power terminal LVGL are the same. During the power-off phase of the display device, the signal of the fourth power terminal LVGL is the same as the signal of the first power terminal VDDA. That is, when the display device is powered off, the signal of the fourth power terminal LVGL is pulled high to a high level signal, and then changes with the high level signal to discharge the pixels in the display area. For example, when the device is powered off while the first part is in the working state, the signal of the fourth power terminal LVGL is pulled high to the potential of the first power terminal VDDA, and then changes with the potential of the first power terminal VDDA to discharge the pixels in the display area.

[0150] It should be noted that, Figure 4 The diagram illustrates exemplary structures of various modules or sub-modules. Those skilled in the art will understand that the various modules or sub-modules are not limited to... Figure 4 The structure shown is acceptable as long as it can fulfill its function.

[0151] Figure 5 This is a timing diagram of the shift register in one embodiment of this disclosure. The following is in conjunction with... Figure 4 and Figure 5 ,by Figure 5 Taking the first part in its working state as an example, the working process of the shift register is explained in detail. The shift register in this embodiment includes four working stages: the first stage is the first total reset stage, the second stage is the gate signal output stage, the third stage is the gate signal reset stage, and the fourth stage is the second total reset stage. It should be noted that the gate driving circuit includes multiple cascaded shift registers, and the stage in which multiple cascaded shift registers sequentially output gate signals can be called the frame display stage. The first total reset stage is located before the frame display is generated, and the second total reset stage is located after the frame display ends. Figure 5 The diagram shows the signals at the INPUT terminal of each of the n cascaded shift registers, where N3, PU, ​​and PD1 are the signals corresponding to INPUT1.

[0152] In the first stage, i.e., the first overall reset stage, the signal input terminal INPUT is a low-level signal, the pull-up node PU is a low-level signal, and the first pull-down node PD1 is a high-level signal. When the frame reset signal (high-level signal) is provided to the frame reset signal terminal TRST for the first time, the fifteenth transistor M15 is turned on under the control of the frame reset signal terminal TRST, and provides the third power supply terminal VGL signal to the pull-up node PU again, resetting the pull-up node PU. The first pull-down node PD1 is a high-level signal, and the first pull-down control module 23 provides the first pull-down node PD1 signal to the fourth node N4 under the control of the first pull-down node PD1. The frame reset signal terminal TRST charges the third node N3. When the voltage of the third node N3 is greater than the threshold voltage of the fourteenth transistor M14A, the fourteenth transistor M14A provides the third power supply terminal VGL signal to the fourth node N4 under the control of the third node N3, discharging the fourth node N4, thereby discharging the first power supply terminal VDDA and the first pull-down node PD1. This reduces the voltage of the first pull-down node PD1, thereby reducing the VA of the eighth transistor M8A. gs The high-level time of the eighth transistor M8A is extended. gs The low-level time can suppress the characteristic left drift of the eighth transistor M8A.

[0153] In the second stage, the gate signal output stage, the signal input terminal INPUT provides a high-level signal, the first power supply terminal VDDA provides a high-level signal, the frame reset signal terminal TRST is a low-level signal, and the fourteenth transistor M14A is turned off. The first transistor M1 is turned on under the control of the signal input terminal INPUT, providing the high-level signal from INPUT to the pull-up node PU, charging the pull-up node PU and raising its potential. The seventh transistor M7A is turned on under the control of the signal input terminal INPUT, providing the signal from the third power supply terminal VGL to the first pull-down node PD1, causing the first pull-down node PD1 to discharge through the seventh transistor M7A, thereby lowering its potential. When the potential of the pull-up node PU is greater than the threshold voltage of the sixth transistor M6A, the sixth transistor M6A is turned on under the control of the pull-up node PU, providing the signal from the third power supply terminal VGL to the first pull-down node PD1, causing the first pull-down node PD1 to discharge through the sixth transistor M6A, thereby further lowering its potential.

[0154] When the potential of the pull-up node PU is greater than the threshold voltage of the third transistor M3 and the eleventh transistor M11, the third transistor M3 and the eleventh transistor M11 are turned on under the control of the pull-up node PU, providing the clock signal CLK to the first signal output terminal Gout and the second signal output terminal OC out, respectively. In this embodiment of the present disclosure, the output signals of the first signal output terminal Gout and the second signal output terminal OC out are the same.

[0155] In the second stage, the gate signal output stage, Gout and the second signal output terminal OC out respectively output high-level signals. Under the action of the bootstrap capacitor C1, the potential of the pull-up node PU is raised again, causing the third transistor M3 and the eleventh transistor M11 to be fully turned on, so that the first signal output terminal Gout and the second signal output terminal OC out can output a stable clock signal CLK.

[0156] In the third stage, the gate signal reset stage, the frame reset signal terminal TRST provides a low-level signal. The reset signal of the first reset signal terminal RST controls the second transistor M2 to turn on, providing the third power supply terminal VGL signal to the pull-up node PU, causing the pull-up node PU to reset to a low-level signal. The sixth transistor M6A, the third transistor M3, and the eleventh transistor M11 are all turned off. The first power supply terminal VDDA controls the fifth transistor M5A to turn on, providing the first power supply terminal VDDA signal to the first pull-down node PD1.

[0157] The thirteenth transistor M13A is turned on under the control of the first pull-down node PD1, providing the signal of the fourth power supply terminal LVGL to the first signal output terminal Gout, and the first signal output terminal Gout outputs a low-level signal; the twelfth transistor M12A is turned on under the control of the first pull-down node PD1, providing the signal of the third power supply terminal VGL to the second signal output terminal OC out, and the second signal output terminal OC out outputs a low-level signal.

[0158] During the second overall reset phase, the frame reset signal terminal TRST provides a frame reset signal (high level signal) for the second time. When the frame reset signal terminal TRST provides a frame reset signal (high level signal) for the second time, the operating state of the shift register is the same as when the frame reset signal terminal TRST provides a frame reset signal (high level signal) for the first time.

[0159] In related technologies, during the second stage of the shift register, i.e., the gate signal output stage, the first pull-down node PD1 is low. Outside of the second stage, the first pull-down node PD1 is high, causing the V signal of the eighth transistor M8A to... gs The high level lasted for a relatively long time, causing the characteristics of the eighth transistor M8A to drift.

[0160] In this embodiment of the shift register, during the second stage (gate signal output stage), the first pull-down node PD1 is at a low level. During the first and fourth stages, the frame reset signal terminal TRST provides two frame reset signals, resulting in two low-level periods for the first pull-down node PD1. Compared to related technologies, this embodiment of the shift register reduces the VA of the eighth transistor M8A. gs The high-level time of the eighth transistor M8A is extended. gs The low-level time can suppress the characteristic left drift of the eighth transistor M8A.

[0161] This disclosure also provides a method for driving a shift register, wherein the shift register is the shift register in any embodiment of this disclosure. The method for driving the shift register includes:

[0162] The signal input terminal INPUT provides a low-level signal, and the frame reset signal terminal TRST provides a high-level signal. Under the control of the first pull-down node PD1, the first pull-down control module 23 provides the signal of the first pull-down node PD1 to the fourth node N4. Under the control of the third node N3, the first level adjustment module 24 provides the signal of the third power supply terminal LGV to the fourth node N4. The fourth node N4 is discharged through the third power supply terminal VGL, thereby discharging the first pull-down node PD1.

[0163] The frame reset signal terminal TRST provides a low-level signal, and the signal input terminal INPUT provides a high-level signal. Under the control of the signal input terminal INPUT, the input module 11 provides a high-level signal to the pull-up node PU. Under the control of the signal input terminal INPUT and / or the pull-up node PU, the first pull-down module 21 provides the third power supply terminal VGL signal to the first pull-down node PD1. Under the control of the pull-up node PU, the output module 14 provides the clock signal terminal CLK signal to the first signal output terminal Gout.

[0164] The frame reset signal terminal TRST provides a low-level signal, while the first reset signal terminal RST1 and the second reset signal terminal RST2 both provide high-level signals. Under the control of the first reset signal terminal RST1, the first reset module 13 provides the third power supply terminal VGL signal to the pull-up node PU, resetting the pull-up node PU. This resets the pull-up node PU to a low-level signal. Under the control of the first power supply terminal VDDA, the first pull-down control module 23 provides the first power supply terminal VDDA signal to the first pull-down node PD1, resetting the first pull-down node PD1. Under the control of the second reset signal terminal RST2, the second reset module 16 provides the fourth power supply terminal LVGL signal to the first signal output terminal Gout, resetting the first signal output terminal Gout.

[0165] In one embodiment, under the control of the pull-up node PPU, the output module 14 provides the clock signal CLK to the second signal output OC out. When the clock signal CLK provides a high-level signal, the second signal output OC out outputs a high-level signal. Under the control of the first pull-down node PD1, the output pull-down module 15 provides the third power supply signal VGL to the second signal output OC out, causing the second signal output OC out to output the third power supply signal VGL.

[0166] The specific process of driving the shift register can be described as above.

[0167] This disclosure also provides a gate driving circuit, such as... Figure 6 As shown, Figure 6 This is a structural block diagram of a gate driving circuit according to one embodiment of the present disclosure. The gate driving circuit may include multiple shift registers as in any embodiment of the present disclosure, and the multiple shift registers are cascaded and coupled.

[0168] For example, the gate drive circuit includes n cascaded shift registers. The output module includes a first signal output terminal Gout and a second signal output terminal OC out. The first signal output terminal Gout of the j-th stage shift register is coupled to the gate line and is also coupled to the second reset signal terminal RST2 of the (j-1)-th stage shift register. The second signal output terminal OC out of the j-th stage shift register is coupled to the signal input terminal INPUT of the (j+1)-th stage shift register, and the second signal output terminal of the j-th stage shift register is coupled to the first reset signal terminal RST1 of the (j-1)-th stage shift register. Here, j is greater than 1 and less than n. The signal input terminal INPUT of the first stage shift register is coupled to the trigger signal terminal STV.

[0169] The signal input terminal INPUT of the first-stage shift register is coupled to the trigger signal.

[0170] The frame reset signal terminal TRST of each shift register is coupled to the frame reset signal Total RST.

[0171] The frame reset signal provided to the frame reset signal terminal TRST precedes the trigger signal provided to the trigger signal terminal. In other words, the frame reset signal is provided to the frame reset signal terminal TRST before the trigger signal is provided. For example, both the frame reset signal and the trigger signal are high-level signals, and the falling edge of the frame reset signal precedes the rising edge of the trigger signal. This can also be understood as providing the frame reset signal to the frame reset signal terminal TRST before the start of a frame.

[0172] In one embodiment, after the last stage (nth stage) shift register is reset, a frame reset signal is provided to the frame reset signal terminal TRST. This can also be understood as providing a frame reset signal to the frame reset signal terminal TRST after the end of the current frame.

[0173] In the gate drive circuit of this disclosure embodiment, each shift register is at a low level when the frame reset signal terminal TRST is at an active level (high level) and the pull-up node is at a high level. Compared with the gate drive circuit in the related art, this extends the time when the pull-down node is at a low level and suppresses the characteristic drift of the noise reduction module.

[0174] This disclosure also provides a display device, including a shift register or a gate driving circuit as described in any embodiment of this disclosure.

[0175] Based on the inventive concept of the foregoing embodiments, this disclosure also provides a display device, which includes a display panel employing the foregoing embodiments. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0176] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0177] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0178] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0179] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0180] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0181] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A shift register, characterized in that, include: An input module, coupled to a signal input terminal and a pull-up node respectively, is configured to provide the signal from the signal input terminal to the pull-up node under the control of the signal input terminal; The frame reset module is coupled to the frame reset signal terminal, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the frame reset signal terminal; The first pull-down module is coupled to the signal input terminal, the first pull-down node, the pull-up node and the third power terminal respectively, and is configured to provide the signal of the third power terminal to the first pull-down node under the control of the signal input terminal and / or the pull-up node. A first pull-down control module is coupled to a fourth node and a first pull-down node, respectively. The fourth node is coupled to a first power supply terminal. The first pull-down control module is configured to provide the signal of the fourth node to the first pull-down node under the control of the fourth node. The first pull-down control module is also configured to provide the signal of the first pull-down node to the fourth node under the control of the first pull-down node. A first level adjustment module is coupled to a third node, a fourth node, and a fifth node, respectively. The fifth node is coupled to the third power supply terminal, and the third node is coupled to the frame reset signal terminal. The first level adjustment module is configured to provide the signal from the third power supply terminal to the fourth node under the control of the third node. The first noise reduction module is coupled to the first pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the first pull-down node; The output module is coupled to the pull-up node, the clock signal terminal and the first signal output terminal respectively, and is configured to provide the clock signal terminal to the first signal output terminal under the control of the pull-up node; The output pull-down module is coupled to the first pull-down node, the fourth power supply terminal, and the first signal output terminal, respectively, and is configured to provide the signal from the fourth power supply terminal to the first signal output terminal under the control of the first pull-down node or the second pull-down node.

2. The shift register according to claim 1, characterized in that, It also includes a first capacitor, which is coupled between the frame reset signal terminal and the third node, with the two plates of the first capacitor being coupled to the frame reset signal terminal and the third node, respectively.

3. The shift register according to claim 1, characterized in that, It also includes a resistor module, the two ends of which are coupled to the fifth node and the third power supply terminal, respectively.

4. The shift register according to claim 1, characterized in that, Also includes: The first reset module is coupled to the first reset signal terminal, the pull-up node and the third power supply terminal respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the first reset signal terminal; The second reset module is coupled to the second reset signal terminal, the first signal output terminal and the fourth power supply terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first signal output terminal under the control of the second reset signal terminal.

5. The shift register according to any one of claims 1-4, characterized in that, Also includes: The second pull-down module is coupled to the signal input terminal, the second pull-down node, the pull-up node and the third power terminal respectively, and is configured to provide the signal of the third power terminal to the second pull-down node under the control of the signal input terminal and / or the pull-up node. The second pull-down control module is coupled to the sixth node and the second pull-down node respectively. The sixth node is coupled to the second power supply terminal. The second pull-down control module is configured to provide the signal of the sixth node to the second pull-down node under the control of the sixth node. The second pull-down control module is also configured to provide the signal of the second pull-down node to the sixth node under the control of the second pull-down node. The second power supply terminal and the first power supply terminal are at opposite potentials at the same time. The second level adjustment module is coupled to the third node, the sixth node and the fifth node respectively. The second level adjustment module is configured to provide the signal of the third power supply terminal to the sixth node under the control of the third node. The second noise reduction module is coupled to the second pull-down node, the pull-up node, and the third power supply terminal, respectively, and is configured to provide the signal from the third power supply terminal to the pull-up node under the control of the second pull-down node.

6. The shift register according to claim 5, characterized in that, Includes at least one of the following: The input module includes a first transistor, the gate of which is coupled to the signal input terminal, and the first and second terminals of the first transistor are coupled to the signal input terminal and the pull-up node, respectively. The frame reset module includes a fifteenth transistor, the gate of which is coupled to the frame reset signal terminal, and the first and second terminals of which are coupled to the pull-up node and the third power supply terminal, respectively. The first pull-down module includes a sixth transistor A and a seventh transistor A. The gate of the sixth transistor A is coupled to the pull-up node, and the first and second terminals of the sixth transistor A are coupled to the third power supply terminal and the first pull-down node, respectively. The gate of the seventh transistor A is coupled to the signal input terminal, and the first and second terminals of the seventh transistor A are coupled to the third power supply terminal and the first pull-down node, respectively. The first pull-down control module includes a fifth transistor A, the gate of the fifth transistor A is coupled to both the first and second terminals of the fifth transistor A, the first terminal of the fifth transistor A is coupled to the fourth node, and the second terminal of the fifth transistor A is coupled to the first pull-down node; The first level adjustment module includes a fourteenth transistor A, the gate of which is coupled to the third node, and the first and second terminals of which are coupled to the fourth and fifth nodes, respectively. The first noise reduction module includes an eighth transistor A, the gate of which is coupled to the first pull-down node, and the first and second terminals of the eighth transistor A are coupled to the third power supply terminal and the pull-up node, respectively. The second pull-down module includes a sixth transistor B and a seventh transistor B. The gate of the sixth transistor B is coupled to the pull-up node, and the first and second terminals of the sixth transistor B are coupled to the third power supply terminal and the second pull-down node, respectively. The gate of the seventh transistor B is coupled to the signal input terminal, and the first and second terminals of the seventh transistor B are coupled to the third power supply terminal and the second pull-down node, respectively. The second pull-down control module includes a fifth transistor B, the gate of the fifth transistor B is coupled to both the first and second terminals of the fifth transistor B, the first terminal of the fifth transistor B is coupled to the sixth node, and the second terminal of the fifth transistor B is coupled to the second pull-down node; The second level adjustment module includes a fourteenth transistor B, the gate of which is coupled to the third node, and the first and second terminals of which are coupled to the sixth and fifth nodes, respectively. The second noise reduction module includes an eighth transistor B, the gate of which is coupled to the second pull-down node, and the first and second terminals of the eighth transistor B are coupled to the third power supply terminal and the pull-up node, respectively.

7. The shift register according to claim 1, characterized in that, The output module includes a third transistor and a bootstrap capacitor. The gate of the third transistor is coupled to the pull-up node, the first terminal of the third transistor is coupled to the clock signal terminal, and the second terminal of the third transistor is coupled to the first signal output terminal. The first and second terminals of the bootstrap capacitor are coupled to the pull-up node and the first signal output terminal, respectively. The output pull-down module includes a thirteenth transistor A, the gate of which is coupled to the first pull-down node, and the first and second terminals of which are coupled to the fourth power supply terminal and the first signal output terminal, respectively.

8. The shift register according to claim 7, characterized in that, The output pull-down module further includes a thirteenth transistor B, the gate of which is coupled to the second pull-down node, and the first and second terminals of which are coupled to the fourth power supply terminal and the first signal output terminal, respectively.

9. The shift register according to claim 8, characterized in that, The output module further includes an eleventh transistor and a second signal output terminal. The gate of the eleventh transistor is coupled to the pull-up node, the first terminal of the eleventh transistor is coupled to the clock signal terminal, and the second terminal of the eleventh transistor is coupled to the second signal output terminal. The output pull-down module further includes a twelfth transistor A, the gate of which is coupled to the first pull-down node, the first terminal of which is coupled to the third power supply terminal, and the second terminal of which is coupled to the second signal output terminal. The output pull-down module further includes a twelfth transistor B, the gate of which is coupled to the second pull-down node, the first terminal of which is coupled to the third power supply terminal, and the second terminal of which is coupled to the second signal output terminal.

10. The shift register according to claim 1, characterized in that, During the display phase of the display device, the signals of the third power terminal and the fourth power terminal are the same. During the power-off phase of the display device, the signal of the fourth power terminal is the same as the signal of the first power terminal.

11. A method for driving a shift register, characterized in that, Applied to the shift register of any one of claims 1-10, the method comprises: The signal input terminal provides a low-level signal, the frame reset signal terminal provides a high-level signal, the first pull-down control module provides the signal of the first pull-down node to the fourth node under the control of the first pull-down node, and the first level adjustment module provides the signal of the third power supply terminal to the fourth node under the control of the third node.

12. A gate driving circuit, characterized in that, Includes multiple cascaded shift registers as described in any one of claims 1-10.

13. The gate driving circuit according to claim 12, characterized in that, The signal input terminal of the first-stage shift register is coupled to the trigger signal, and the frame reset signal provided to the frame reset signal terminal is located before the trigger signal provided to the signal input terminal of the first-stage shift register.

14. A display device, characterized in that, It includes the shift register of any one of claims 1-10 or the gate drive circuit of claim 12 or 13.

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