Monitoring circuit, refresh method and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a monitoring circuit, a refreshing method and a memory. The monitoring circuit comprises: a sampling module, which samples an initial address to obtain a monitoring address; a counting module, which adjusts a counting value of a first counter corresponding to the monitoring address based on the obtained monitoring address; the counting module is further configured to configure a preset value for the monitoring address, and the size of the configured preset value is positively correlated with the length of time that the monitoring address exists in the counting module; and a processing module, which compares the counting value of the first counter corresponding to each monitoring address with the preset value based on an update signal; wherein, if the counting value of the first counter is greater than or equal to the preset value, the monitoring address is retained, and if the counting value of the first counter is less than the preset value, the monitoring address is released, and the first counter corresponding to the monitoring address and the preset value are reset. The present disclosure realizes the supplementary refreshing of the storage area with small power consumption, thereby ensuring the accuracy of the stored data in each storage area.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a monitoring circuit, a refresh method, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) stores data through a structure (1T1C) where a transistor is connected to a memory area. The transistor is controlled by a word line (WL). When the WL is turned on, the charge in the memory area is shared with the charge of the bit line (BL) to read data from or write data to the target memory area.

[0003] Frequent activation of word lines can lead to charge loss in adjacent memory areas, potentially causing errors in the stored data. To address this issue, current methods typically use a refresh cycle as the time unit, supplementing the memory areas adjacent to the word line address that is activated most frequently within a refresh cycle to prevent data errors. However, this method requires counting all activated word line addresses, necessitating the driving of a large number of counters, resulting in significant power consumption and making it impractical for real-world applications.

[0004] How to complete the supplementary refresh of the storage area with low power consumption to ensure the accuracy of the stored data in each storage area is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides a monitoring circuit, a refresh method, and a memory that achieves supplementary refresh of specific rows in the storage area with low power consumption. This ensures the accuracy of the stored data in each storage area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design.

[0006] One embodiment of this disclosure provides a monitoring circuit, including: a sampling module configured to sample an initial address to obtain a monitoring address, wherein the initial address is an enabled word line address in the memory where the monitoring circuit is located; a counting module connected to the sampling module, configured to adjust the count value of a first counter corresponding to the monitoring address based on the obtained monitoring address; the counting module is further configured to configure a preset value for the monitoring address, wherein the magnitude of the configured preset value is positively correlated with the duration of the monitoring address in the counting module; and a processing module connected to the counting module, configured to compare the count value of the first counter corresponding to each monitoring address with the preset value based on an update signal; wherein, if the count value of the first counter is greater than or equal to the preset value, the monitoring address is retained; if the count value of the first counter is less than the preset value, the monitoring address is released, and the first counter and the preset value corresponding to the monitoring address are reset.

[0007] In the monitoring circuit provided in this embodiment, the processing module continuously releases monitoring addresses whose count values ​​are less than a preset value in the counting module based on the update signal, that is, continuously releases noise addresses recorded in the counting module, so that the counting module can record new monitoring addresses. By avoiding the waste of counter resources caused by continuous recording of noise addresses, the number of first counters that the monitoring circuit needs to drive is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, the processing module retains monitoring addresses whose count values ​​are greater than or equal to the preset value, and the adjacent rows of monitoring addresses are used for supplementary refresh of the memory, that is, word line addresses that have been opened more than the preset value are retained to ensure the accuracy of the stored data in each memory area.

[0008] Additionally, the counting module includes: a judgment unit, connected to the sampling module, configured to determine whether the acquired monitoring address has been stored based on the acquired monitoring address and the stored monitoring address; if the monitoring address has been stored, a first control signal is generated; if the monitoring address has not been stored, a second control signal is generated; a counting unit, connected to the sampling module and the judgment unit, configured to increment the count value of the first counter corresponding to the monitoring address by 1 based on the first control signal, add a new first counter corresponding to the monitoring address based on the second control signal, and set the count value of the first counter to 1; and a reference unit, connected to the counting unit and the judgment unit, configured to configure a preset value for the monitoring address based on the second control signal, and the configured preset value is stored in the counting unit, and the preset value is adjusted based on the update signal.

[0009] In addition, the value of the preset configuration is positively correlated with the duration of the monitored address in the counting module. This includes: the value of the preset configuration is positively correlated with the number of update cycles in which the monitored address is retained in the counting module, where the update cycle is the interval between adjacent update signals. By setting the preset value as a variable related to the update cycle, i.e., increasing the retention standard for word line addresses that have been counted for a long time, the word line addresses that may cause errors in the data stored in the memory area are obtained more accurately, thereby further ensuring the accuracy of memory refresh.

[0010] Additionally, the reference unit includes: a setting subunit connected to the counting unit and the judgment unit, configured to, in response to a second control signal, set a preset value corresponding to the monitoring address based on a first initial value; and an adjustment subunit configured to, receive an update signal, and adjust the preset value corresponding to the monitoring address retained in the counting unit based on the update signal.

[0011] In addition, the preset value is the counting result of the second counter in the counting unit; adjusting the preset value corresponding to the monitoring address retained in the counting unit based on the update signal includes: based on the update signal, accumulating the second initial value to the second counter corresponding to the retained monitoring address.

[0012] In addition, the first initial value is set to 2. n The second initial value is set to 2. m m and n are positive integers greater than or equal to 1.

[0013] Additionally, the processing module includes: a first processing unit connected to the counting module, configured to receive the count value and preset value of the first counter corresponding to each monitoring address, and latch and transmit the count value and preset value of the first counter to the comparison unit based on the control of the update signal; the comparison unit connected to the first processing unit, configured to compare the count value of the first counter with the preset value, and generate and output a release control signal when the count value of the first counter is less than the preset value; and a second processing unit connected to the comparison unit and the counting module, configured to release the corresponding monitoring address in the counting module based on the release control signal, and reset the first counter and preset value corresponding to the monitoring address.

[0014] In addition, based on the control of the update signal, the count value and preset value of the first counter are latched and transmitted to the comparison unit, including: the update signal controls the input of the driving clock signal, wherein when the update signal is at an active level, the driving clock signal is input to the processing module, and when the update signal is at an inactive level, there is no driving clock signal input; when the driving clock signal is input, the processing module latches the count value and preset value of the first counter and transmits them to the comparison unit.

[0015] In addition, the sampling module obtains the monitoring address based on a preset interval. The preset interval is set to sample the monitoring address once every x initial addresses, where x is a positive integer. By setting the sampling probability for the sampling module, the number of word line addresses that the sampling module needs to obtain is reduced, that is, the power consumption of the monitoring circuit is further reduced by sampling detection.

[0016] Additionally, x is a positive integer less than or equal to 16.

[0017] In addition, the update signals include refresh signals and count adjustment signals. The refresh signal is used to instruct the memory to perform a refresh operation, and the count adjustment signal is provided in the interval between two adjacent refresh signals. By using refresh signals and count adjustment signals together as update signals, the frequency at which the processing module releases the monitored addresses in the counting module is increased, thereby further reducing the number of counters that the monitoring circuit needs to drive. In addition, by increasing the number of update signals, the monitoring frequency of the enabled word line addresses is increased, preventing the sudden multiple enabling of certain enabled word line addresses in a short period of time.

[0018] In addition, the memory refresh operation also includes: refreshing the adjacent rows of the monitoring addresses with the highest count value corresponding to the first counter in the monitoring addresses retained in the counting module, where y is a positive integer greater than or equal to 1; after refreshing, releasing the monitoring addresses with the highest count value in the counting module, and resetting the first counter and preset value corresponding to the monitoring addresses with the highest count value.

[0019] In addition, the counting unit is also configured to discard newly added monitoring addresses based on a second control signal when each of the first counters in the counting unit has a corresponding monitoring address.

[0020] Another embodiment of this disclosure provides a refresh method applied to the monitoring circuit provided in the above embodiments, including: Step S1: Obtaining a monitoring address and detecting whether the monitoring address is stored; if the monitoring address has been stored, then proceeding to step S2; if the monitoring address has not been stored, then proceeding to step S3; Step S2: Incrementing the count value of the first counter corresponding to the monitoring address by 1; Step S3: Using a new first counter to count the monitoring address, setting the count value of the first counter to 1, and setting a corresponding preset value for the monitoring address; Step S4: Adjusting the preset value corresponding to the retained monitoring address based on the update signal, and comparing the count value of the first counter corresponding to each monitoring address with the preset value; if the count value of the first counter is greater than or equal to the preset value, then proceeding to step S5; if the count value of the first counter is less than the preset value, then proceeding to step S6; Step S5: Retaining the monitoring address and continuing to execute step S1; Step S6: Releasing the monitoring address, resetting the first counter and preset value corresponding to the monitoring address, and continuing to execute step S1.

[0021] In addition, setting corresponding preset values ​​for monitoring addresses includes: acquiring newly added monitoring addresses and setting preset values ​​corresponding to the newly added monitoring addresses based on a first initial value; adjusting the preset values ​​corresponding to the retained monitoring addresses based on update signals, including: accumulating the preset values ​​corresponding to the retained monitoring addresses based on a second initial value.

[0022] Another embodiment of this disclosure also provides a memory that obtains the word line address to be refreshed based on the monitoring circuit provided in the above embodiments; it achieves supplementary refresh of specific rows in the memory area with less power consumption, ensuring the accuracy of the stored data in each memory area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a monitoring circuit provided in an embodiment of the present disclosure;

[0025] Figure 2 This is a schematic diagram of the structure of a counting module provided in an embodiment of the present disclosure;

[0026] Figure 3 This is a schematic diagram of the structure of a reference unit provided in an embodiment of the present disclosure;

[0027] Figure 4 and Figure 5 A schematic diagram illustrating the principle of a monitoring circuit for reserving and releasing monitoring addresses according to an embodiment of this disclosure;

[0028] Figure 6 This is a schematic diagram of the structure of a processing module provided in an embodiment of the present disclosure;

[0029] Figure 7 This is a schematic diagram of a driving clock signal input method provided in an embodiment of the present disclosure;

[0030] Figure 8 This is a flowchart illustrating each step in a refresh method provided in another embodiment of the present disclosure. Detailed Implementation

[0031] As the background technology shows, frequent activation of word lines can lead to charge loss in adjacent memory areas, potentially causing errors in the stored data. Currently, the common approach to this problem is to refresh the memory areas adjacent to the word line address that is most frequently activated within a refresh cycle, based on the refresh period as the time unit, thereby preventing data errors. However, this method requires counting all activated word line addresses, necessitating the driving of a large number of counters, resulting in significant power consumption and making it impractical for real-world applications.

[0032] One embodiment of this disclosure provides a monitoring circuit that achieves supplementary refresh of specific rows in the memory area with low power consumption, ensuring the accuracy of the stored data in each memory area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design.

[0033] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0034] Figure 1 This is a schematic diagram of the monitoring circuit provided in this embodiment. Figure 2 This is a schematic diagram of the counting module provided in this embodiment. Figure 3 This is a schematic diagram of the structure of the reference unit provided in this embodiment. Figure 4 and Figure 5 This is a schematic diagram illustrating the principle of the monitoring circuit in this embodiment for reserving and releasing monitoring addresses. Figure 6 This is a schematic diagram of the processing module provided in this embodiment. Figure 7 This is a schematic diagram of a driving clock signal input method provided in this embodiment. The monitoring circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0035] refer to Figure 1 Monitoring circuit, including:

[0036] The sampling module 101 is configured to sample the initial address to obtain the monitoring address, where the initial address is the word line address that is enabled in the memory where the monitoring circuit is located.

[0037] The counting module 102, connected to the sampling module 101, is configured to adjust the count value of the first counter corresponding to the acquired monitoring address based on the acquired monitoring address.

[0038] The counting module 102 is also configured to configure a preset value for the monitoring address, and the size of the configured preset value is positively correlated with the duration of the monitoring address in the counting module 102.

[0039] Specifically, the longer the monitoring address exists in the counting module 102, the larger the preset value corresponding to the monitoring address; the shorter the monitoring address exists in the counting module 102, the smaller the preset value corresponding to the monitoring address.

[0040] The processing module 103, connected to the counting module 102, is configured to compare the count value of the first counter corresponding to each monitoring address with a preset value based on the update signal; wherein, if the count value of the first counter is greater than or equal to the preset value, the monitoring address is retained; if the count value of the first counter is less than the preset value, the monitoring address is released, and the first counter and the preset value corresponding to the monitoring address are reset.

[0041] In the monitoring circuit provided in this embodiment, the processing module 103 continuously releases monitoring addresses whose count values ​​in the counting module 102 are less than a preset value based on the update signal, that is, continuously releases noise addresses recorded in the counting module 102, so that the counting module 102 can record new monitoring addresses. By avoiding the waste of counter resources caused by the continuous recording of noise addresses, the number of first counters that the monitoring circuit needs to drive is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, the processing module 103 retains monitoring addresses whose count values ​​are greater than or equal to the preset value. The adjacent rows of the monitoring addresses are used for supplementary refresh of the memory, that is, word line addresses that have been opened more than the preset value are retained to ensure the accuracy of the stored data in each memory area.

[0042] In some embodiments, the sampling module 101 provided in this embodiment obtains the monitoring address by sampling at a preset interval. The preset interval is set to sample the monitoring address once every x initial addresses, where x is a positive integer. That is, the sampling module 101 samples the monitoring address once every x word lines of memory are enabled. By setting the sampling probability for the sampling module 101, the number of word lines the sampling module 101 needs to obtain is reduced, thus further reducing the power consumption of the monitoring circuit through sampling detection. In some embodiments, x can be a positive integer less than or equal to 16; in a specific example, x can be a positive integer less than or equal to 8, for example, x can be a positive integer such as 8, 6, 4, or 2.

[0043] Regarding the counting module 102 provided in this embodiment, in some embodiments, refer to Figure 2The counting module 102 includes: a judgment unit 132, connected to the sampling module 101, configured to determine whether the acquired monitoring address has been stored based on the acquired monitoring address and the stored monitoring address; if the monitoring address has been stored, a first control signal is generated; if the monitoring address has not been stored, a second control signal is generated; a counting unit 112, connected to the sampling module 101 and the judgment unit 132, configured to increment the count value of the first counter corresponding to the monitoring address by 1 based on the first control signal, add a new first counter corresponding to the monitoring address based on the first control signal, and set the count value of the first counter to 1; and a reference unit 122, connected to the counting unit 112 and the judgment unit 132, configured to configure a preset value for the monitoring address based on the second control signal, and the configured preset value is stored in the counting unit 112, and the preset value is adjusted based on an update signal.

[0044] In other embodiments, the preset value can also be set to be stored in the reference unit. It should be noted that in the following description of this embodiment, the preset value is set in the counting unit 112 as an example for detailed explanation.

[0045] In some other embodiments, the reference unit 122 may also store the monitoring address. In this case, the reference unit 122 also needs to be connected to the sampling module 101 and is configured to add a monitoring address if there is no identical monitoring address in the reference unit 122, and configure a corresponding preset value for the monitoring address.

[0046] It should be noted that the capacity of the first counter is based on the refresh command reception interval, the preset sampling interval, and the word line enable interval in the memory. Specifically, in the DDR4 standard, under normal operating temperature, for a 16GB memory in 1X refresh mode, the word line enable interval tRC = 45ns, the preset sampling interval tREFC = 550ns, and the refresh command reception interval tREFI = 7.8us. At this time, in the burst transfer mode of the memory, the number of word line addresses that can be enabled by 9*tREFI is 9*(tREFI-tREFC) / tRC = 161. If the capacity of the first counter is b, it is necessary to ensure 2 b >161, meaning b is at least 8. In this example, the capacity of the first counter is set to 8 bits. It should be noted that the numerical examples in this example are only for those skilled in the art to understand how the capacity of the first counter is set, and do not constitute a limitation on this embodiment.

[0047] In practical applications, the number of first counters in the counting unit 122 is limited. The counting unit 122 is also configured such that when each first counter in the counting unit 122 has a corresponding monitoring address, that is, when all the first counters in the counting unit 122 have started counting and the monitoring addresses stored in the counting unit 122 are full, the counting unit 122 is configured to discard newly added monitoring addresses based on the second control signal.

[0048] In some embodiments, the preset value is positively correlated with the number of update cycles that the monitoring address retains in the counting module 102, where the update cycle is the interval between adjacent update signals.

[0049] Specifically, refer to Figure 3 The reference unit 122 includes: a setting subunit 202, connected to the counting unit 112 and the judgment unit 132, configured to, in response to a second control signal, set a preset value corresponding to the monitoring address based on a first initial value; and an adjustment subunit 203, configured to receive an update signal and adjust the preset value corresponding to the monitoring address stored in the counting unit 112 based on the update signal. When the judgment unit 132 determines that a new monitoring address has appeared, the reference unit 122 configures a preset value for the new monitoring address; when an update signal is received, the adjustment subunit 203 increases the preset value corresponding to the monitoring address stored in the counting unit 112, thereby achieving a positive correlation between the size of the set preset value and the number of update cycles in which the monitoring address is stored in the counting module 102.

[0050] In a specific example, the preset value is the counting result of the second counter in the counting unit 112, and the adjustment subunit 203 is configured to accumulate the second initial value to the second counter corresponding to the retained monitoring address based on the update signal.

[0051] refer to Figure 4The count value is the result of the first counter, used to represent the number of times the corresponding monitoring address is counted. The preset value is the result of the second counter, used to represent the recorded reference value of the corresponding monitoring address. Here, c represents the first initial value set by the setting subunit 201, y represents the step size of each adjustment by the adjustment subunit 203, and t1 to t5 represent the number of update cycles of the corresponding monitoring address. For monitoring addresses with a count value greater than or equal to the preset value, that is, word line addresses in the memory that have been opened a preset number of times, there is a risk of malicious attack, and the corresponding monitoring addresses need to be refreshed. For monitoring addresses with a count value less than the preset value, they are word line addresses that are accessed normally and do not need to be refreshed. In addition, word line addresses that are continuously opened are more likely to cause data errors in adjacent storage areas. In this embodiment, the preset value corresponding to the monitoring address is gradually increased as the retention time of the monitoring address increases. That is, only word line addresses that are continuously opened have a higher probability of causing errors in the stored data of adjacent storage areas, and are therefore more worthy of attention. They should be retained and their adjacent rows should be refreshed.

[0052] It should be noted that there are multiple ways to perform the supplementary refresh mentioned above. It can be based on each update signal to perform supplementary refresh on the adjacent rows of the monitoring address corresponding to the first counter with the maximum count value stored in the counting unit 122; it can also be set to perform supplementary refresh on the adjacent rows of the monitoring address with the maximum count value every n update signals; it can also be set to refresh the adjacent rows of multiple monitoring addresses in a single supplementary refresh; where the adjacent rows can be adjacent address rows such as +1 / -1, +1 / -2, etc. of the monitoring address.

[0053] More specifically, the first initial value is set to 2. n The second initial value is set to 2. m m and n are positive integers greater than or equal to 1; in a specific example, m and n can be set to 2, 3, 4 or 5; correspondingly, the values ​​of m and n can be set to the same value or different values.

[0054] For the counting module 102 provided above, the working principle is as follows: Figure 5 It should be noted that, Figure 5 The specific values ​​shown are only for those skilled in the art to understand the working principle of the counting module 102 provided in this embodiment, and do not constitute a limitation on this embodiment.

[0055] refer to Figure 5 and combined Figure 2 and Figure 3When the judgment unit 132 receives the monitoring address Address1 sampled by the sampling module 101, it generates a first control signal, and the counting unit 112 controls the count value of the first counter corresponding to the monitoring address Address1 to increment by 1 (from 10 to 11); when the judgment unit 132 receives the monitoring address Address3 sampled by the sampling module 101, it generates a first control signal, and the counting unit 112 controls the count value of the first counter corresponding to the monitoring address Address3 to increment by 1 (from 19 to 20); when the reference unit 122 receives the update signal, it indicates that the recorded... The monitored addresses have already existed for one update cycle. Reference unit 122 is adjusted to the preset values ​​corresponding to the monitored addresses in counting unit 112. Specifically, the preset value of monitored address Address1 changes from 4+4*1 to 4+4*2, the preset value of monitored address Address2 changes from 4+4*0 to 4+4*1, the preset value of monitored address Address3 changes from 4+4*5 to 4+4*6, the preset value of monitored address Address4 changes from 4+4*0 to 4+4*1, and the preset value of monitored address Address5 changes from 4+4*2 to 4+4*3, and so on. Enabling word line addresses are more likely to cause data errors in adjacent storage areas. By setting the preset value corresponding to the monitoring address to gradually increase as the retention time of the monitoring address increases, only continuously enabled word line addresses have a higher probability of causing data errors in adjacent storage areas and are therefore more worthy of attention. They should be retained and their adjacent rows refreshed. Then, the processing module 103 compares the count value of each monitoring address with the preset value, retains the monitoring addresses with count values ​​greater than or equal to the preset value, and releases the monitoring addresses with count values ​​less than the preset value. After the comparison, the monitoring address Address5 in the counting unit 112 is retained, other monitoring addresses are released, and the corresponding first counter and preset value are reset. When the judgment unit 132 receives the monitoring address Address6 sampled by the sampling module 101, since the monitoring address Address6 does not exist in the counting module 102, the judgment unit 132 generates a second control signal. At this time, the counting unit 112 adds the monitoring address Address6 and sets the count value of the first counter corresponding to the monitoring address Address6 to 1. The reference unit 122 sets the preset value 4+4*0 for the monitoring address Address6.

[0056] In the above implementation, the first initial value for the preset value of the monitoring address is 4, and the second initial value for accumulation based on the update signal is also set to 4. When the update signal is received, the preset value of the retained monitoring address is first accumulated, and then the count value is compared with the preset value. In other implementations, when the update signal is received, the count value can also be compared with the preset value first, and then the preset value of the retained monitoring address is accumulated, so as to reduce the number of second counters that the monitoring circuit needs to adjust, thereby reducing the power consumption of the monitoring circuit.

[0057] In addition, in some embodiments, the preset value also corresponds to a maximum value. After the value of the second counter accumulates to the maximum value, it will not continue to accumulate. When the count value of the first counter corresponding to the monitoring address is greater than or equal to the maximum value, it proves that the data in the storage area adjacent to the monitoring address is prone to errors and needs to be refreshed. At this time, there is no need to accumulate the preset value again, so as to avoid unnecessary value updates of the second counter.

[0058] For the processing module 103 provided in this embodiment, refer to... Figure 6 In some embodiments, the processing module 103 includes: a first processing unit 301, connected to the counting module 102, configured to receive the count value and preset value of a first counter corresponding to each monitoring address, and latch and transmit the count value and preset value of the first counter to the comparison unit 302 based on the control of an update signal. The comparison unit 302, connected to the first processing unit 301, is configured to compare the count value of the first counter with the preset value, and generate and output a release control signal when the count value of the first counter is less than the preset value. A second processing unit 303, connected to the comparison unit 302 and the counting module 102, is configured to release the corresponding monitoring address in the counting module 102 based on the release control signal, and reset the first counter and preset value (second counter) corresponding to the monitoring address.

[0059] Combination Figure 5 For example, for monitoring addresses Address1, Address2, Address3 and Address4, if the count value is less than the preset value, the comparison unit 302 generates a release control signal. Based on the release control signal, the second processing unit 303 releases the monitoring addresses Address1, Address2, Address3 and Address4 in the counting module 102, and resets the first counter and the preset value (second counter) corresponding to the monitoring addresses Address1, Address2, Address3 and Address4.

[0060] Specifically, in one example, the processing module 103 is driven by a driving clock signal, and the update signal controls the input of the driving clock signal. When the update signal is at an active level, the driving clock signal is input to the processing module 103; when the update signal is at an inactive level, no driving clock signal is input. When the driving clock signal is input, the processing module 103 latches the count value of the first counter and the preset value and transmits them to the comparison unit. (Reference) Figure 7 The drive clock signal and update signal are received through the input of AND gate 10, so that when the update signal is at an active level, the drive clock signal can be input to the processing module 103.

[0061] It should be noted that the input of the driving clock signal is implemented through AND gate 10, and the default effective level of the update signal is high. In some embodiments, if the effective level of the update signal is low, AND gate 10 can be replaced with an OR gate.

[0062] In another example, the processing module 103 can be directly driven by the update signal, that is, the update signal is directly used as the driving clock signal of the processing module 103, thereby realizing the updating of the monitoring address in the counting module 102 by the processing module 103 based on the update signal.

[0063] In the above example, the first processing unit 301 transmits the count value and preset value of the first counter based on the control of the update signal, while the comparison unit 302 and the second processing unit 303 operate directly based on the count value and preset value transmitted by the first counter without the control of the update signal. In some embodiments, the first processing unit 301 is configured to receive the count value and preset value of the first counter corresponding to each monitoring address, and continuously latch and transmit the count value and preset value of the first counter to the comparison unit 302. The comparison unit 302 is configured to compare the count value and preset value of the first counter, and generate and output a release control signal when the count value of the first counter is less than the preset value. The second processing unit 303, based on the release control signal, releases the corresponding monitoring address in the counting module 102 and resets the first counter and preset value (second counter) corresponding to the monitoring address. That is, the first processing unit 301, the comparison unit 302, and the second processing unit 303 do not need to operate based on the update signal and can continue to work. In other embodiments, it can also be set so that the first processing unit 301, the comparison unit 302, and the second processing unit 303 complete the corresponding operations based on the control of the update signal.

[0064] In some embodiments, the update signal mentioned above includes a refresh signal and a count adjustment signal. The refresh signal is used to instruct the memory to perform a refresh operation, i.e., the original signal of the memory. The count adjustment signal is provided between two adjacent refresh signals. The count adjustment signal is a newly defined signal within the refresh cycle and is used to update the monitoring address reserved in the counting module 102 based on the count value and a preset value. By using the refresh signal and the count adjustment signal together as update signals, the frequency at which the processing module 103 releases the monitoring address in the counting module 102 is increased, thereby further reducing the number of counters that the monitoring circuit needs to drive. In addition, by increasing the number of update signals, the monitoring frequency of the enabled word line address is increased, preventing the sudden multiple enabling of certain enabled word line addresses in a short period of time.

[0065] In addition, for the count adjustment signal within the same refresh cycle, the number of count adjustment signals can be appropriately adjusted according to the application scenario required by the memory, thereby adaptively adjusting the frequency of the monitoring address released by the processing module 103 in the count module 102.

[0066] For the memory to which the monitoring circuit provided in this embodiment belongs, the memory refresh operation further includes: refreshing the adjacent rows of the monitoring addresses with the highest count value corresponding to the first counter among the monitoring addresses retained in the counting module 102, where y is a positive integer greater than or equal to 1; after refreshing, releasing the monitoring addresses with the highest count value in the counting module 102, and resetting the first counter and the preset value (second counter) corresponding to the monitoring addresses with the highest count value.

[0067] In one example, if the first processing unit 301 latches and transmits the count value of the first counter and the preset value to the comparison unit 302 based on the control of the update signal, the comparison unit 302 compares the count value of the first counter with the preset value. Since the preset value also needs to be adjusted based on the update signal, the preset value latched and transmitted based on the update signal may be a preset value that has not yet been updated. Therefore, the comparison result cannot represent the real-time monitoring result. In a specific application, the update signal provided to the first processing unit 301 can be delayed compared to the update signal provided to the adjustment subunit 203 to ensure that the first processing unit 301 can latch the updated preset value based on the update signal.

[0068] In one example, if the first processing unit 301 latches and transmits the count value and preset value of the first counter to the comparison unit 302, the comparison unit 302 compares the count value and preset value of the first counter based on the control of the update signal, and combines... Figure 5For example, when the update signal is a refresh signal, the comparison unit 302 performs a comparison of the first counter and the count value with the preset value based on the update signal. Since the result of the comparison release will have a certain delay compared with the update signal, that is, the data (Address1-4) recorded in the first counting module will not be released when the refresh signal is valid, so it is impossible to confirm which address is the address that is retained after the update. Therefore, knowing the monitoring address Address5 that is retained after the update, it is necessary to perform a refresh based on the next refresh signal.

[0069] In a specific application, the timing of the update signal and refresh signal can be set to delay the refresh signal provided to the memory for refreshing operations. That is, after the data (Address1-4) recorded in the first counting module is released, the refresh signal can be provided to identify the monitoring address Address5 that is retained after the update, thereby synchronously updating the data in the counting module 102 and refreshing the monitoring address that is higher than the preset value.

[0070] In another example, if the first processing unit 301 continuously latches and transmits the count value of the first counter and the preset value to the comparison unit 302, the comparison unit 302 can compare the count value of the first counter and the preset value in real time. That is, after updating the preset value based on the update signal, it can promptly compare the updated preset value with the count value of the first counter and generate a release control signal based on the comparison result. Figure 5 For example, when the update signal is a refresh signal, the monitoring circuit releases monitoring addresses Address1, Address2, Address3 and Address4 based on the release control signal. At the same time, the memory refreshes the adjacent row of monitoring address Address5 based on the update signal, releases monitoring address Address5 in the counting module 102, and resets the first counter and the preset value (second counter) corresponding to monitoring address Address5.

[0071] In the monitoring circuit provided in this embodiment, the processing module 103 continuously releases monitoring addresses whose count values ​​in the counting module 102 are less than a preset value based on the update signal, that is, continuously releases noise addresses recorded in the counting module 102, so that the counting module 102 can record new monitoring addresses. By avoiding the waste of counter resources caused by the continuous recording of noise addresses, the number of first counters that the monitoring circuit needs to drive is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, the processing module 103 retains monitoring addresses whose count values ​​are greater than or equal to the preset value. The adjacent rows of the monitoring addresses are used for supplementary refresh of the memory, that is, word line addresses that have been opened more than the preset value are retained to ensure the accuracy of the stored data in each memory area.

[0072] It should be noted that the features disclosed in the monitoring circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new monitoring circuit embodiments.

[0073] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.

[0074] Another embodiment of this disclosure provides a refresh method applied to the monitoring circuit provided in the above embodiments. This method achieves supplementary refresh of specific rows in the storage area with lower power consumption, ensuring the accuracy of the stored data in each storage area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design.

[0075] Figure 8 This is a flowchart illustrating each step of the refresh method provided in this embodiment. The refresh method provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0076] refer to Figure 8 Refresh methods include:

[0077] Step S1: Obtain the monitoring address and check whether the monitoring address has been stored; if the monitoring address has been stored, proceed to step S2; if the monitoring address has not been stored, proceed to step S3.

[0078] The monitoring address is the address of the enabled word line in the memory. If the monitoring address has been stored, it proves that the currently enabled word line address has been counted, and counting needs to continue based on step S2. If the monitoring address has not been stored, it proves that the currently enabled word line address has not been counted, and the first counter needs to be configured to start counting based on step S3, and the corresponding preset value needs to be configured. It should be noted that the count value of the first counter and the preset value are both initially set to 0. After the count value of the first counter and the preset value are reset, they are also reset to 0. Therefore, after adding a monitoring address, the first counter, the count value, and the preset value need to be assigned values.

[0079] In some embodiments, step S1 obtains the monitoring address based on sampling at a preset interval. The preset interval is set to sample the monitoring address once every x initial addresses, where x is a positive integer. That is, the sampling module 101 samples the monitoring address once every x word lines of memory are enabled. By setting the sampling probability, the number of word lines to be obtained is reduced, thus further reducing the power consumption required for refresh through sampling detection. In some embodiments, x is a positive integer less than or equal to 16; in a specific example, x can be set to a positive integer such as 14, 12, 10, 8, 6, 4, or 2.

[0080] Step S2: Increment the count value of the first counter corresponding to the monitoring address by 1, and then execute step S4.

[0081] For the first counter, its capacity is set based on the refresh command reception interval, the preset sampling interval, and the word line enable interval in the memory. Specifically, in the DDR4 standard, under normal operating temperature, for a 16GB memory in 1X refresh mode, the word line enable interval tRC = 45ns, the preset sampling interval tREFC = 550ns, and the refresh command reception interval tREFI = 7.8us. At this time, in the memory's burst transfer mode, the number of word line addresses that can be enabled by 9*tREFI is 9*(tREFI-tREFC) / tRC = 161. If the capacity of the first counter is b, it is necessary to ensure 2... b >161, meaning b is at least 8. In this example, the capacity of the first counter is set to 8 bits. It should be noted that the numerical examples in this example are only for those skilled in the art to understand how the capacity of the first counter is set, and do not constitute a limitation on this embodiment.

[0082] Step S3: Use a new first counter to count the monitoring address, set the count value of the first counter to 1, and set the corresponding preset value for the monitoring address, then execute step S4.

[0083] Specifically, the newly added monitoring address is obtained, and the preset value corresponding to the monitoring address is set based on the first initial value.

[0084] For steps S1 to S3, in one example, refer to Figure 5 and combined Figure 2 and Figure 3When the judgment unit 132 receives the monitoring address Address1 sampled by the sampling module 101, it generates a first control signal, and the counting unit 112 controls the count value of the first counter corresponding to the monitoring address Address1 to increase by 1 (from 10 to 11); when the judgment unit 132 receives the monitoring address Address3 sampled by the sampling module 101, it generates a first control signal, and the counting unit 112 controls the count value of the first counter corresponding to the monitoring address Address3 to increase by 1 (from 19 to 20); when the judgment unit 132 receives the monitoring address Address6 sampled by the sampling module 101, since the monitoring address Address6 does not exist in the counting module 102, the judgment unit 132 generates a second control signal. At this time, the counting unit 112 adds the monitoring address Address6 and sets the count value of the first counter corresponding to the monitoring address Address6 to 1. The reference unit 122 sets a preset value of 4+4*0 for the monitoring address Address6.

[0085] Step S4: Adjust the preset value corresponding to the retained monitoring address based on the update signal, and compare the count value of the first counter corresponding to each monitoring address with the preset value. If the count value of the first counter is greater than or equal to the preset value, then proceed to step S5. If the count value of the first counter is less than the preset value, then proceed to step S6.

[0086] In a specific example, refer to Figure 4 The count value is the result of the first counter, used to represent the number of times the corresponding monitoring address is counted. The preset value is the result of the second counter, used to represent the recorded reference value of the corresponding monitoring address. Here, c represents the first initial value set by the setting subunit 201, y represents the step size of each adjustment by the adjustment subunit 203, and t1 to t5 represent the number of update cycles of the corresponding monitoring address. For monitoring addresses with a count value greater than or equal to the preset value, that is, word line addresses in the memory that have been opened a preset number of times, there is a risk of malicious attack, and the corresponding monitoring addresses need to be refreshed. For monitoring addresses with a count value less than the preset value, they are word line addresses that are accessed normally and do not need to be refreshed. In addition, word line addresses that are continuously opened are more likely to cause data errors in adjacent storage areas. In this embodiment, the preset value corresponding to the monitoring address is gradually increased as the retention time of the monitoring address increases. That is, only word line addresses that are continuously opened have a higher probability of causing errors in the stored data of adjacent storage areas, and are therefore more worthy of attention. They should be retained and their adjacent rows should be refreshed.

[0087] More specifically, the first initial value is set to 2. n The second initial value is set to 2. mm and n are positive integers greater than or equal to 1; in a specific example, m and n can be set to 2, 3, 4 or 5; correspondingly, the values ​​of m and n can be set to the same value or different values.

[0088] For step S4, in one example, refer to Figure 5 and combined Figure 2 and Figure 3 When the reference unit 122 receives the update signal, it indicates that the recorded monitoring address has been present for an additional update cycle. The reference unit 122 adjusts the preset value corresponding to the monitoring address in the counting unit 112. Specifically, the preset value of monitoring address Address1 changes from 4+4*1 to 4+4*2, the preset value of monitoring address Address2 changes from 4+4*0 to 4+4*1, the preset value of monitoring address Address3 changes from 4+4*5 to 4+4*6, the preset value of monitoring address Address4 changes from 4+4*0 to 4+4*1, and the preset value of monitoring address Address5 changes from 4+4*2 to 4+4*3. Word line addresses that are continuously enabled are more likely to cause data errors in adjacent storage areas. By setting the preset value corresponding to the monitoring address to gradually increase as the retention time of the monitoring address increases, it is determined that only word line addresses that are continuously enabled have a higher probability of causing errors in the stored data of adjacent storage areas. These are the addresses that deserve more attention and should be retained and their adjacent rows refreshed.

[0089] Step S5: Retain the monitoring address and continue with step S1.

[0090] Specifically, for the retained monitoring address, the second counter corresponding to the retained monitoring address is accumulated based on the second initial value, that is, the retained monitoring address after adjustment based on the update signal is obtained, and the second counter corresponding to the corresponding monitoring address is accumulated based on the second initial value.

[0091] Step S6: Release the monitoring address and reset the first counter and preset value corresponding to the monitoring address, then continue to execute step S1.

[0092] For steps S5 and S6, in one example, refer to Figure 5 and combined Figure 2 and Figure 3 The processing module 103 compares the count value of each monitoring address with the preset value, retains the monitoring addresses whose count value is greater than or equal to the preset value, and releases the monitoring addresses whose count value is less than the preset value. After the comparison, the monitoring address Address5 in the counting unit 112 is retained, the other monitoring addresses are released, and the corresponding first counter and preset value are reset.

[0093] In the above implementation, the first initial value for the preset value of the monitoring address is 4, and the second initial value for accumulation based on the update signal is also set to 4. When the update signal is received, the preset value of the retained monitoring address is first accumulated, and then the count value is compared with the preset value. In other implementations, when the update signal is received, the count value can also be compared with the preset value first, and then the preset value of the retained monitoring address is accumulated, so as to reduce the number of second counters that the monitoring circuit needs to adjust, thereby reducing the power consumption of the monitoring circuit.

[0094] In addition, in some embodiments, the preset value also corresponds to a maximum value. After the value of the second counter accumulates to the maximum value, it will not continue to accumulate. When the count value of the first counter corresponding to the monitoring address is greater than or equal to the maximum value, it proves that the data in the storage area adjacent to the monitoring address is prone to errors and needs to be refreshed. At this time, there is no need to accumulate the preset value again, so as to avoid unnecessary value updates of the second counter.

[0095] Regarding the update signal described above, in some embodiments, the update signal includes a refresh signal and a count adjustment signal. The refresh signal is used to instruct the memory to perform a refresh operation, i.e., the original signal of the memory. The count adjustment signal is provided within the interval between two adjacent refresh signals. The count adjustment signal is a newly defined signal within the refresh cycle, used to update the reserved monitoring address based on the count value and a preset value. By using the refresh signal and the count adjustment signal together as the update signal, the frequency of releasing the monitoring address is increased, thereby further reducing the number of counters that the monitoring circuit needs to drive. In addition, by increasing the number of update signals, the monitoring frequency of the enabled word line address is increased, preventing the sudden multiple enabling of certain enabled word line addresses in a short period of time.

[0096] In addition, for the count adjustment signal within the same refresh cycle, the number of count adjustment signals can be appropriately adjusted according to the application scenario required by the memory, thereby adaptively adjusting the frequency of releasing the monitoring address.

[0097] The refresh method provided in this embodiment continuously releases monitoring addresses with count values ​​less than a preset value based on the update signal, that is, continuously releases recorded noise addresses, so that the counting module can record new monitoring addresses. By avoiding the waste of counter resources caused by continuous recording of noise addresses, the number of first counters that the monitoring circuit needs to drive is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, monitoring addresses with count values ​​greater than or equal to the preset value are retained, and adjacent rows of monitoring addresses are used for supplementary refresh of the memory, that is, word line addresses that have been opened more than the preset value are retained to ensure the accuracy of the stored data in each memory area.

[0098] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments remain valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0099] It should be noted that the features disclosed in the refresh method provided in the above embodiments can be arbitrarily combined without conflict to obtain new refresh method embodiments.

[0100] Another embodiment of this disclosure provides a memory that obtains the word line address to be refreshed based on the monitoring circuit provided in the above embodiments, and achieves supplementary refresh of a specific row in the memory area with less power consumption. This ensures the accuracy of the stored data in each memory area while reducing the number of counters that the memory needs to drive, making it more suitable for actual memory design.

[0101] Specifically, for the monitoring circuit, the processing module continuously releases monitoring addresses whose count values ​​are less than a preset value in the counting module based on the update signal, that is, it continuously releases noise addresses recorded in the counting module, so that the counting module can record new monitoring addresses. By avoiding the waste of counter resources caused by the continuous recording of noise addresses, the number of first counters that the monitoring circuit needs to drive is reduced, thereby reducing the power consumption of the monitoring circuit. In addition, the processing module retains monitoring addresses whose count values ​​are greater than or equal to the preset value. The adjacent rows of monitoring addresses are used for supplementary refresh of the memory, that is, word line addresses that have been opened more than a preset value are retained to ensure the accuracy of the stored data in each memory area.

[0102] In some embodiments, the memory can be a storage cell or device based on a semiconductor device or component. For example, the memory device can be volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate type fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it can be non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0103] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A monitoring circuit, characterized in that, include: The sampling module is configured to sample an initial address to obtain a monitoring address, wherein the initial address is the word line address that is enabled in the memory where the monitoring circuit is located; The counting module, connected to the sampling module, is configured to adjust the count value of the first counter corresponding to the acquired monitoring address based on the acquired monitoring address. The counting module is further configured to configure a preset value for the monitoring address, and the magnitude of the preset value is positively correlated with the duration of the monitoring address in the counting module. The processing module, connected to the counting module, is configured to compare the count value of the first counter corresponding to each monitoring address with the preset value based on the update signal; wherein, if the count value of the first counter is greater than or equal to the preset value, the monitoring address is retained; if the count value of the first counter is less than the preset value, the monitoring address is released, and the first counter and the preset value corresponding to the monitoring address are reset.

2. The monitoring circuit according to claim 1, characterized in that, The counting module includes: The judgment unit, connected to the sampling module, is configured to determine whether the acquired monitoring address has been stored based on the acquired monitoring address and the stored monitoring address; if the monitoring address has been stored, a first control signal is generated; if the monitoring address has not been stored, a second control signal is generated. The counting unit, connected to the sampling module and the judgment unit, is configured to increment the count value of the first counter corresponding to the monitoring address by 1 based on the first control signal, add a new first counter corresponding to the monitoring address based on the second control signal, and set the count value of the first counter to 1. The reference unit, connected to the counting unit and the judgment unit, is configured to configure the preset value for the monitoring address based on the second control signal, and the configured preset value is stored in the counting unit, and the preset value is adjusted based on the update signal.

3. The monitoring circuit according to claim 2, characterized in that, The magnitude of the preset value configured is positively correlated with the duration of the monitoring address in the counting module, including: the magnitude of the preset value is positively correlated with the number of update cycles in which the monitoring address is retained in the counting module, wherein the update cycle is the interval between adjacent update signals.

4. The monitoring circuit according to claim 3, characterized in that, The reference unit includes: The sub-unit, which connects the counting unit and the judgment unit, is configured to, in response to the second control signal, set the preset value corresponding to the monitoring address based on the first initial value; The adjustment subunit is configured to receive the update signal and adjust the preset value corresponding to the monitoring address retained in the counting unit based on the update signal.

5. The monitoring circuit according to claim 4, characterized in that, include: The preset value is the counting result of the second counter in the counting unit; The step of adjusting the preset value corresponding to the monitoring address retained in the counting unit based on the update signal includes: based on the update signal, accumulating the second initial value to the second counter corresponding to the retained monitoring address.

6. The monitoring circuit according to claim 5, characterized in that, The first initial value is set to 2 n The second initial value is set to 2. m m and n are positive integers greater than or equal to 1.

7. The monitoring circuit according to claim 1, characterized in that, The processing module includes: The first processing unit, connected to the counting module, is configured to receive the count value of the first counter corresponding to each monitoring address and the preset value, and based on the control of the update signal, latch the count value of the first counter and the preset value and transmit them to the comparison unit. The comparison unit is connected to the first processing unit and is configured to compare the count value of the first counter with the preset value, and generate and output a release control signal when the count value of the first counter is less than the preset value. The second processing unit, connected to the comparison unit and the counting module, is configured to release the corresponding monitoring address in the counting module based on the release control signal, and reset the first counter and the preset value corresponding to the monitoring address.

8. The monitoring circuit according to claim 7, characterized in that, The control based on the update signal, which latches and transmits the count value of the first counter and the preset value to the comparison unit, includes: the update signal controlling the input of a driving clock signal, wherein when the update signal is at an active level, the driving clock signal is input to the processing module, and when the update signal is at an inactive level, no driving clock signal is input; when the driving clock signal is input, the processing module latches and transmits the count value of the first counter and the preset value to the comparison unit.

9. The monitoring circuit according to claim 1, characterized in that, The sampling module obtains the monitoring address based on a preset interval, wherein the preset interval is set to sample the monitoring address once every x initial addresses, where x is a positive integer.

10. The monitoring circuit according to claim 9, characterized in that, x is a positive integer less than or equal to 16.

11. The monitoring circuit according to claim 1, characterized in that, include: The update signal includes a refresh signal and a count adjustment signal. The refresh signal is used to instruct the memory to perform a refresh operation, and the count adjustment signal is provided within the interval between two adjacent refresh signals.

12. The monitoring circuit according to claim 1, characterized in that, include: The refresh operation of the memory further includes: refreshing the adjacent rows of the monitoring addresses with the highest count values ​​corresponding to the first counter among the monitoring addresses retained in the counting module, where y is a positive integer greater than or equal to 1; After refreshing, the y monitoring addresses with the highest count values ​​in the counting module are released, and the first counter and the preset value corresponding to the y monitoring addresses with the highest count values ​​are reset.

13. The monitoring circuit according to claim 2, characterized in that, The counting unit is further configured to discard newly added monitoring addresses based on the second control signal when each of the first counters in the counting unit has a corresponding monitoring address.

14. A refresh method, applied to the monitoring circuit according to any one of claims 1 to 13, characterized in that, include: Step S1: Obtain the monitoring address and check whether the monitoring address has been stored. If the monitoring address has been stored, proceed to step S2. If the monitoring address has not been stored, proceed to step S3. Step S2: Increment the count value of the first counter corresponding to the monitored address by 1; Step S3: Use a new first counter to count the monitored address, set the count value of the first counter to 1, and set a corresponding preset value for the monitored address; Step S4: Adjust the preset value corresponding to the retained monitoring address based on the update signal, and compare the count value of the first counter corresponding to each monitoring address with the preset value. If the count value of the first counter is greater than or equal to the preset value, then proceed to step S5; if the count value of the first counter is less than the preset value, then proceed to step S6. Step S5: Retain the monitoring address and continue to execute step S1; Step S6: Release the monitoring address, reset the first counter and the preset value corresponding to the monitoring address, and continue to execute step S1.

15. The refresh method according to claim 14, characterized in that, include: Setting a corresponding preset value for the monitoring address includes: obtaining a newly added monitoring address and setting a preset value corresponding to the newly added monitoring address based on a first initial value; The preset value corresponding to the monitoring address that is adjusted and retained based on the update signal includes: the preset value corresponding to the monitoring address that is accumulated and retained based on the second initial value.

16. A memory, characterized in that, The word line address to be refreshed is obtained based on the monitoring circuit described in any one of claims 1 to 13.

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