Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: forming a dummy gate structure across a device fin, including a sacrificial fin on top of the device fin, a blocking layer on top of the sacrificial fin, and a sacrificial gate covering top of the blocking layer, sidewalls of the sacrificial fin and the blocking layer, and part of sidewalls of the device fin; removing the sacrificial gate and the sacrificial fin to form a gate opening exposing the blocking layer and the device fin with a gap suspended between the blocking layer and the device fin; forming a gate dielectric layer on surfaces of the exposed top and sidewalls of the device fin, and the blocking layer; forming a first gate material layer in the gate opening in a first region, and a second gate material layer in the gate opening in a second region, the first gate material layer and the second gate material layer having different stack types and / or material types. Embodiments of the present application reduce the probability of damage to the top of the device fin, and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually transitioned from planar transistors to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate surrounds the fin-shaped channel on three sides. Compared to planar transistors, FinFETs offer stronger gate control over the channel and better suppress short-channel effects.

[0003] Furthermore, the gate structure typically includes a work function layer, and the work function value of the gate structure in different regions is usually adjusted by adjusting the material type and thickness of the metal in the work function layer, thereby adjusting the threshold voltage Vt of different devices.

[0004] However, the top of the fin is more likely to be damaged during the formation of the gate structure, which reduces the reliability of the device. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a first region and a second region; the substrate including a substrate and device fins disposed on the substrate; a stop layer located above the top of the device fins and suspended from the top of the device fins; a first gate structure located on the substrate of the first region and spanning the device fins of the first region, and the first gate structure filling the space between the device fins and the stop layer of the first region; a second gate structure located on the substrate of the second region and spanning the device fins of the second region, and the second gate structure filling the space between the device fins and the stop layer of the second region; wherein the first gate structure and the second gate structure have different stacking types and / or material types; a gate dielectric layer located between the first gate structure and the device fins, and between the second gate structure and the device fins; and source / drain doped regions located within the device fins on both sides of the first gate structure and the second gate structure.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; the substrate including a substrate and device fins discretely disposed on the substrate; forming a pseudo-gate structure across the device fins on the substrate, the pseudo-gate structure including a sacrificial fin located on top of the device fins, a barrier layer located on top of the sacrificial fins, and a sacrificial gate covering the top of the barrier layer, the sidewalls of the sacrificial fins and the barrier layer, and a portion of the sidewalls of the device fins; forming source / drain doped regions in the device fins on both sides of the pseudo-gate structure, the source / drain doped regions exposing the sacrificial fins and the barrier layer; removing the sacrificial gate and the sacrificial fins to form a gate opening exposing the barrier layer and the device fins, the barrier layer and the device fins being suspended at a distance; forming a gate dielectric layer on the top and sidewalls of the device fins exposed by the gate opening and on the surface of the barrier layer; forming a first gate material layer located within the gate opening in the first region and a second gate material layer located within the gate opening in the second region on the gate dielectric layer, the first gate material layer and the second gate material layer having different stacking types and / or material types.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this embodiment of the invention includes a stop layer suspended above the top of the device fins at intervals. This is because, during the formation of the semiconductor structure, a barrier layer is also suspended above the top of the device fins, and a gate dielectric layer is formed on the surface of the barrier layer. The gate dielectric layer located at the bottom of the barrier layer serves as a stop layer. The process of forming the first gate structure and the second gate structure includes forming a first gate material layer spanning the device fins of the first region and a second gate material layer spanning the device fins of the second region, and removing the first gate material layer and the second gate material layer above the top surface of the stop layer, as well as the barrier layer. Forming the first gate material layer and the second gate material layer typically includes forming a mask covering layer on the first or second region to cover the mask. The process involves etching the area exposed by the capping layer, thereby exposing a second or first region to form a first gate material layer and a second gate material layer with different stacking types and / or material types. The formation of the masking layer typically includes an anisotropic etching process to etch away the capping material layer located within the gate openings of the second or first region. During the anisotropic etching process, a barrier layer is suspended above the top of the device fin, which protects the top of the device fin and reduces the risk of damage to the film layer (e.g., gate dielectric layer) located on top of the device fin. This improves the performance of the first and second gate structures, thereby enhancing the performance of the semiconductor structure.

[0010] Furthermore, the top surface of the stop layer can also define the stop position for the removal of the first gate material layer and the second gate material layer, thereby defining the height of the first gate structure and the second gate structure. This is beneficial for accurately controlling the height of the first gate structure and the second gate structure, and improving the height consistency of the first gate structure and the second gate structure.

[0011] In the semiconductor structure formation method provided in this embodiment of the invention, the dummy gate structure includes a sacrificial fin located on top of a device fin, a barrier layer located on top of the sacrificial fin, and a sacrificial gate covering the top of the barrier layer, the sidewalls of the sacrificial fin and the barrier layer, and a portion of the sidewalls of the device fin. Forming a first gate material layer and a second gate material layer typically includes forming a mask cover layer on a first region or a second region to etch the region exposed by the mask cover layer. The mask cover layer correspondingly exposes the second region or the first region to form a first gate material layer and a second gate material layer with different stacking types and / or material types. The process of forming the mask cover layer typically includes an anisotropic etching process to etch and remove the cover material layer located in the gate opening of the second region or the first region. During the anisotropic etching process, the barrier layer is suspended above the top of the device fin, which can protect the top of the device fin and reduce the risk of damage to the film layer located on top of the device fin, thereby improving the performance of the first gate material layer or the second gate material layer and thus improving the performance of the semiconductor structure.

[0012] In an optional embodiment, the gate dielectric layer located on the bottom surface of the barrier layer is used as a stop layer; the method for forming the semiconductor structure further includes: after forming the first gate material layer and the second gate material layer, removing the first gate material layer and the second gate material layer that are higher than the top surface of the stop layer, as well as the barrier layer, the remaining first gate material layer is used as the first gate structure, and the remaining second gate material layer is used as the second gate structure, so that the stop layer can also play a role in defining the height of the first gate structure and the second gate structure, thereby facilitating precise control of the height of the first gate structure and the second gate structure, and improving the height consistency of the first gate structure and the height consistency of the second gate structure. Attached Figure Description

[0013] Figures 1 to 11 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] Figures 12 to 13 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0015] Figures 14 to 39 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0016] As is known from the background art, the top of the fin is currently more likely to be damaged during the formation of the gate structure.

[0017] This paper analyzes the reasons why the top of the fin has a high probability of being damaged during the formation of the gate structure, based on a semiconductor structure formation method. Figures 1 to 11 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0018] refer to Figure 1 and Figure 2 , Figure 1 This is a top view. Figure 2 (a) is Figure 1 Cross-sectional view along the XX direction. Figure 2 (b) is Figure 1 A cross-sectional view along the YY direction shows a substrate including a substrate 10 and fins 11 discretely disposed on the substrate 10. The substrate includes a first region 10a and a second region 10b. An isolation layer 12 is formed on the substrate 10 surrounding the fins 11, with the top of the isolation layer 12 lower than the top of the fins 11. A dummy gate structure 13 is formed on the isolation layer 12, spanning the fins 11 and covering a portion of the top and sidewalls of the fins 11. Source / drain doped regions 14 are formed in the fins 11 on both sides of the dummy gate structure 13. An interlayer dielectric layer 15 is formed on the isolation layer 12 on the side of the dummy gate structure 13, covering the source / drain doped regions 14.

[0019] refer to Figures 3 to 4 , Figure 3 This is a top view. Figure 4 (a) is Figure 3 Cross-sectional view along the XX direction. Figure 4 (b) is Figure 3 A cross-sectional view along the YY direction shows the removal of the pseudo-gate structure 13, forming the gate opening 16.

[0020] refer to Figures 5 to 6 , Figure 5 This is a top view. Figure 6 (a) is Figure 5 Cross-sectional view along the XX direction. Figure 6 (b) is Figure 5 A cross-sectional view along the YY direction shows that a gate dielectric layer 17 and a first work function layer 18 are formed at the bottom and sidewalls of the gate opening 16.

[0021] refer to Figures 7 to 9 , Figure 7 This is a top view. Figure 8 (a) is Figure 7 Cross-sectional view along the XX direction. Figure 8 (b) is Figure 7 Cross-sectional view along the YY direction. Figure 9 In order to be in Figure 8 (b) A partial magnified view at point C, with the first work function layer 18 of the first region 10a removed, exposing the gate dielectric layer 17 below the gate opening 16 of the first region 10a.

[0022] refer to Figures 10 to 11 , Figure 10 This is a top view. Figure 11 (a) is Figure 10 Cross-sectional view along the XX direction. Figure 11 (b) is Figure 10 In a cross-sectional view along the YY direction, a second work function layer 19 is formed on the gate dielectric layer 17 exposed at the gate opening 16 in the first region 10a. The thickness of the second work function layer 19 is less than the thickness of the first work function layer 18. A third work function layer 20 is formed within the gate opening 16. The thickness of the third work function layer 20 in the first region 10a is less than the thickness of the third work function layer 20 in the second region 10b. The third work function layer 20 in the second region 10b fills the gate opening 16 of the second region 10b. A metal electrode layer 21 is filled within the gate opening 16 of the first region 10a. The gate dielectric layer 17, the second work function layer 19, the third work function layer 20, and the metal electrode layer 21 in the first region 10a are used to form a first gate structure, and the gate dielectric layer 17, the first work function layer 18, and the third work function layer 20 in the second region 10b are used to form a second gate structure.

[0023] like Figures 7 to 9 As shown, in the above semiconductor structure formation method, the step of removing the first work function layer 18 of the first region 10a typically includes: forming a cover material layer (not shown) that fills the gate opening 16 on the substrate; using an anisotropic etching process to etch and remove the cover material layer located in the gate opening 16 of the first region 10a, and using the remaining cover material layer located in the gate opening 16 of the second region 10b as a cover layer 22; and removing the first work function layer 17 exposed by the cover layer 22.

[0024] In the process of etching away the cover material layer within the gate opening 16 of the first region 10a using an anisotropic etching process, the anisotropic etching process etches the cover material layer along a direction perpendicular to the substrate. This can easily cause over-etching of the film layer (e.g., gate dielectric layer 17) on top of the fin 11 below the gate opening 16 of the first region 10a, resulting in a higher probability of damage to the film layer (gate dielectric layer 17) on top of the fin 11 (e.g., Figure 9 (As shown by the dashed coil in the middle), this leads to a decrease in the performance of the device.

[0025] To address the technical problem, embodiments of the present invention provide a semiconductor structure in which a stop layer is suspended above the top of the device fin at intervals. This is because, during the formation of the semiconductor structure, a barrier layer is also suspended above the top of the device fin, and a gate dielectric layer is formed on the surface of the barrier layer. The gate dielectric layer located at the bottom of the barrier layer serves as the stop layer. The process of forming the first gate structure and the second gate structure includes forming a first gate material layer spanning the device fin across a first region and a second gate material layer spanning the device fin across a second region, and removing the first and second gate material layers above the top surface of the stop layer, as well as the barrier layer. The formation of the first and second gate material layers typically includes forming a mask covering layer on the first or second region. The process involves etching the area exposed by the mask cover layer, thereby exposing a second region or a first region to form a first gate material layer and a second gate material layer with different stacking types and / or material types. The formation of the mask cover layer typically includes an anisotropic etching process to etch away the cover material layer located within the gate opening in the second region or the first region. During the anisotropic etching process, a barrier layer is suspended above the top of the device fin, which can protect the top of the device fin and reduce the risk of damage to the film layer (e.g., gate dielectric layer) located on the top of the device fin. This improves the performance of the first gate structure and the second gate structure, thereby improving the performance of the semiconductor structure.

[0026] Furthermore, the top surface of the stop layer can also define the stop position for the removal of the first gate material layer and the second gate material layer, thereby defining the height of the first gate structure and the second gate structure. This is beneficial for accurately controlling the height of the first gate structure and the second gate structure, and improving the height consistency of the first gate structure and the second gate structure.

[0027] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 12 to 13 A schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 12 This is a top view. Figure 13 (a) is Figure 12 Cross-sectional view along the XX direction. Figure 13 (b) is Figure 12 Cross-sectional view along the YY direction.

[0028] like Figures 12 to 13As shown, in this embodiment, the semiconductor structure includes: a substrate, the substrate including a first region 100a and a second region 100b; the substrate including a substrate 100 and device fins 110 discretely disposed on the substrate 100; a stop layer 370, located above the top of the device fins 110 and suspended from the top of the device fins 110; a first gate structure 350, located on the substrate 100 of the first region 100a and spanning the device fins 110 of the first region 100a, and the first gate structure 350 filling the space between the device fins 110 of the first region 100a and the stop layer 370; and a second gate structure 360, located on the substrate 100 of the first region 100a and spanning the device fins 110 of the first region 100a. A device fin 110 is located on a substrate 100 in the second region 100b and spans the second region 100b, and a second gate structure 360 ​​is filled between the device fin 110 in the second region 100b and the stop layer 370; wherein the first gate structure 350 and the second gate structure 360 ​​have different stacking types and / or material types; a gate dielectric layer 250 is located between the first gate structure 350 and the device fin 110, and between the second gate structure 360 ​​and the device fin 110; source and drain doped regions 230 are located within the device fins 110 on both sides of the first gate structure 350 and the second gate structure 360.

[0029] The substrate is used to provide a process platform for the formation of semiconductor structures.

[0030] In this embodiment, the first region 100a is used to form a first device, and the second region 100b is used to form a second device.

[0031] As an example, the first region 100a is used to form a first type MOS transistor, and the second region 100b is used to form a second type MOS transistor. The first type MOS transistor and the second type MOS transistor have different channel conductivity types.

[0032] In one specific embodiment, the first type of MOS transistor is a PMOS transistor, and the second type of MOS transistor is an NMOS transistor. In other embodiments, the first type of MOS transistor may also be an NMOS transistor, and the second type of MOS transistor may be a PMOS transistor accordingly.

[0033] In some other embodiments, the first device and the second device may also be other different types of devices.

[0034] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0035] The device fin 110 provides a conductive channel for device operation. The device fin 110 is made of a semiconductor material. The material of the device fin 110 includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0036] In this embodiment, the device fin 110 and the substrate 100 are an integral structure. The material of the device fin 110 and the substrate 100 is the same, which is silicon. In other embodiments, the material of the device fin may be different from that of the substrate.

[0037] In this embodiment, the semiconductor structure further includes an isolation layer 105 located on the substrate 100 and surrounding the device fin 110, with the top of the isolation layer 105 being lower than the top of the device fin 110.

[0038] The isolation layer 105 is used to achieve isolation between adjacent device fins 110, and also to isolate the substrate 100 from the first gate structure 350 and the second gate structure 360, as well as to isolate the substrate 100 from the first gate structure 350 and the second gate structure 360.

[0039] In this embodiment, the isolation layer 105 is a shallow trench isolation (STI) structure. In this embodiment, the material of the isolation layer 105 is silicon oxide. In other embodiments, the material of the isolation layer can also be other insulating materials such as silicon nitride or silicon oxynitride.

[0040] The stop layer 370 is used to define the stop position during the planarization process of forming the first gate structure 350 and the second gate structure 360, thereby improving the height consistency of the first gate structure 350 and the height consistency of the second gate structure 360.

[0041] In this embodiment, the top surfaces of the first gate structure 350 and the second gate structure 360 ​​above the top of the device fin 110 have a recess D; the gate dielectric layer 250 is also located in the recess D, and the gate dielectric layer 250 located in the recess D is used as a stop layer 370.

[0042] The gate dielectric layer 250 is used to achieve electrical isolation between the first gate structure 350 and the device fin 110, and between the second gate structure 360 ​​and the device fin 110.

[0043] In this embodiment, the top surfaces of the first gate structure 350 and the second gate structure 360 ​​above the top of the device fin 110 have a recess D because during the formation of the semiconductor structure, a barrier layer is suspended above the top of the device fin 110, and the gate dielectric layer 250 is also formed on the surface of the barrier layer. The process of forming the first gate structure 350 and the second gate structure 360 ​​includes forming a first gate material layer of the device fin 110 spanning the first region 100a and a second gate material layer of the device fin 110 spanning the second region 100b, and removing the first gate material layer and the second gate material layer above the bottom surface of the gate dielectric layer 250, as well as the barrier layer.

[0044] The gate dielectric layer 250 is also located within the recess D. The top surface of the gate dielectric layer 250 within the recess D serves as a barrier layer 370, thereby defining the stop position for the removal of the first gate material layer and the second gate material layer, and further defining the height of the first gate structure 350 and the second gate structure 360. This facilitates precise control of the height of the first gate structure 350 and the second gate structure 360, and improves the height consistency of the first gate structure 350 and the second gate structure 360.

[0045] Accordingly, in this embodiment, the top surfaces of the first gate structure 350 and the second gate structure 360 ​​are flush with the top surface of the stop layer 370.

[0046] In the process of forming the semiconductor structure, the formation of the first gate material layer and the second gate material layer typically includes the step of forming a mask cover layer on the first region 100a or the second region 100b to etch the region exposed by the mask cover layer. The mask cover layer correspondingly exposes the second region 100b or the first region 100a to form the first gate material layer and the second gate material layer with different stacking types and / or material types. The process of forming the mask cover layer typically includes the step of using an anisotropic etching process to etch and remove the cover material layer located in the gate opening of the second region 100b or the first region 100a. During the anisotropic etching process, the barrier layer is suspended above the top of the device fin 110, which can protect the top of the device fin 110 and reduce the risk of damage to the film layer (e.g., the gate dielectric layer) located on the top of the device fin 110. This improves the performance of the first gate structure 350 and the second gate structure 360, thereby improving the performance of the semiconductor structure.

[0047] Accordingly, in this embodiment, the material of the stop layer 370 is the same as the material of the gate dielectric layer.

[0048] The first gate structure 350 is used to control the opening and closing of the conductive channel of the first device.

[0049] In this embodiment, the first gate structure 350 includes: a first work function layer 310 located on the gate dielectric layer 250 on the top and sidewalls of the device fin 110 in the first region 100a, and on the sidewalls and bottom of the stop layer 370; a first metal electrode 330 located on the first work function layer 310 on the sidewalls of the device fin 110 in the first region 100a, and between the first work function layers 310 located between the top of the device fin 110 and the stop layer 370; and a first metal electrode 340 spanning the device fin 110 in the first region 100a.

[0050] The first work function layer 310 is used to adjust the work function of the first gate structure 350, thereby adjusting the threshold voltage of the first device. The first work function layer 310 can be a single layer or a stacked structure, and the material of the first work function layer 310 includes one or more of titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, and silicon titanium nitride.

[0051] The first metal electrode 330 is used as an external electrode of the first gate structure 350.

[0052] In this embodiment, the material of the first metal electrode 330 is W. In other embodiments, the material of the electrode material layer can also be Al, Cu, Ag, Au, Pt, Ni, or Ti, etc. In specific implementations, the material of the first metal electrode 330 can also be a work function metal material. The work function metal material can be titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, or titanium silicon nitride.

[0053] The second gate structure 360 ​​is used to control the opening and closing of the conductive channel of the second device.

[0054] In this embodiment, the first gate structure 350 and the second gate structure 360 ​​are located on the isolation layer 105.

[0055] In this embodiment, the second gate structure 360 ​​includes: a second work function layer 320 located on the gate dielectric layer 250 on the top and sidewalls of the device fin 110 in the second region 100b, and on the sidewalls and bottom of the stop layer 370; and a second metal electrode 340 located on the second work function layer 320 on the sidewalls of the device fin 110 in the second region 100b, and between the second work function layers 320 located between the top of the device fin 110 and the stop layer 370, wherein the second metal electrode 340 spans the device fin 110 in the second region 100b.

[0056] The second work function layer 320 is used to adjust the work function of the second gate structure 360 ​​to adjust the threshold voltage of the second device. The second work function layer 320 can be a single layer or a stacked structure, and the material of the second work function layer 320 includes one or more of titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, and silicon titanium nitride.

[0057] The second metal electrode 340 is used as an external electrode of the second gate material layer.

[0058] In this embodiment, the material of the second metal electrode 340 is a work function metal material. The work function metal material can be titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, or silicon titanium nitride. In other embodiments, the material of the second metal electrode can also be W, Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0059] In this embodiment, the first gate structure 350 and the second gate structure 360 ​​have different stacking types and / or material types, thereby meeting the requirement of forming different types of gate structures in different regions to achieve different device functions.

[0060] In this embodiment, the first gate structure 350 and the second gate structure 360 ​​having different stacking types and / or material types means that the first gate structure 350 and the second gate structure 360 ​​have different types of stacking structures, or that the first gate structure 350 and the second gate structure 360 ​​have different material types, or that the first gate structure 350 and the second gate structure 360 ​​have both different types of stacking structures and different material types.

[0061] More specifically, in this embodiment, the first gate structure 350 and the second gate structure 360 ​​may include different types of work function layer materials, different numbers of work function layers, or both different types and different numbers of work function layers, or different thicknesses of the work function layers, etc., in order to achieve the purpose of adjusting the work function of the gate structure in different regions, thereby making the first device and the second device have different work functions, and thus making the first device and the second device have different threshold voltages, so as to adjust the threshold voltage of the device in different regions.

[0062] In this embodiment, the first work function layer 310 and the second work function layer 320 are made of different materials and / or have different numbers of layers, thereby adjusting the work function of the first gate structure 350 and the second gate structure 360, and thus adjusting the threshold voltage of the first device and the second device.

[0063] As an example, the first work function layer 310 includes a second work function membrane 270 and a third work function membrane 280 located on the second work function membrane 270.

[0064] As an example, the second work function layer 320 includes a first work function membrane 260 and a second work function membrane 270 located on the first work function membrane 260.

[0065] As an example, the material of the first work function membrane 260 includes titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, or silicon titanium nitride.

[0066] As an example, the material of the second work function film 270 includes titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, or titanium silicon nitride. In this embodiment, the material of the second work function film 270 is the same as the material of the first work function film 260. In other embodiments, the material of the second work function film may also be different from the material of the first work function film.

[0067] The material of the third work function membrane 280 can be titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon nitride, or titanium silicon nitride.

[0068] As an example, the material of the third work function film 280 is the same as the material of the second metal electrode 340. In other embodiments, the material of the third work function film may also be different from the material of the second metal electrode.

[0069] It should be noted that, in this embodiment, the materials and structures of the first gate structure 350 and the second gate structure 360 ​​are merely examples, and the number and material of the work function layers in the first gate structure 350 and the second gate structure 360 ​​are also merely examples. In specific embodiments, the structural type and material type of the first gate structure 350 and the second gate structure 360 ​​can be adjusted based on actual process requirements.

[0070] In this embodiment, the portion of the first gate structure 350 and the second gate structure 360 ​​located on the substrate 100 between adjacent device fins 110 is used as the first portion (not shown), and the portion located above the top of the device fin 110 and between the stop layer 370 is used as the second portion (not shown).

[0071] More specifically, the portion of the first gate structure 350 and the second gate structure 360 ​​located on the isolation layer 105 between the device fins 110 is used as the first portion (not shown), and the portion located above the top of the device fins 110 and between the stop layer 370 is used as the second portion (not shown).

[0072] In this embodiment, the semiconductor structure further includes a gate sidewall 400 located on the sidewalls of the first gate structure 350 and the second gate structure 360. The gate sidewall 400 is used to protect the sidewalls of the first gate structure 350 and the second gate structure 360, and also to define the formation location of the source / drain doped region 230 together with the first gate structure 350 and the second gate structure 360.

[0073] The material of the gate sidewall 400 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. The gate sidewall 400 can be a single-layer structure or a multilayer structure.

[0074] As an example, the gate sidewall 400 includes: a first sidewall 155 located on the sidewall of a first portion; and a second sidewall 210 located on the sidewall of a second portion.

[0075] In this embodiment, the material of the first sidewall 155 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. In this embodiment, the first sidewall 155 is a single-layer structure, and the material of the first sidewall 155 is silicon nitride.

[0076] In this embodiment, the material of the second sidewall 210 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. In this embodiment, the second sidewall 210 is a single-layer structure, and the material of the second sidewall 210 is silicon nitride.

[0077] In this embodiment, the gate dielectric layer 250 includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. As an example, the material of the high-k gate dielectric layer is hafnium oxide (HfO2).

[0078] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. In still other embodiments, the gate dielectric layer may consist only of a gate oxide layer. The material of the gate oxide layer includes one or both of silicon oxide and silicon oxynitride.

[0079] In this embodiment, the gate dielectric layer 250 is also located between the first gate structure 350 and the gate sidewall 400, and between the second gate structure 360 ​​and the gate sidewall 400.

[0080] The source / drain doped region 230 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped region 230 is used to provide a source of charge carriers.

[0081] In this embodiment, the source / drain doped region 230 includes a stress layer doped with ions. The source / drain doped region 230 is also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0082] Specifically, when forming an NMOS transistor, the material of the source and drain doped regions 230 is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, which is beneficial to improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0083] When forming a PMOS transistor, the source and drain doped regions 230 are made of a stress layer doped with P-type ions. The stress layer material includes Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions or In ions.

[0084] In one specific embodiment, the first type of MOS transistor is a PMOS transistor, and the second type of MOS transistor is an NMOS transistor. Accordingly, the material of the source / drain doped region 230 located in the first region 100a is a stress layer doped with N-type ions; the material of the source / drain doped region 230 located in the second region 100b is a stress layer doped with P-type ions.

[0085] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 180, which is located on the isolation layer 105 on the side of the first gate structure 350 and the second gate structure 360 ​​and covers the source and drain doped regions 230.

[0086] The interlayer dielectric layer 180 is used to isolate adjacent first gate structures 350 and adjacent second gate structures 360, thereby achieving electrical isolation between adjacent devices.

[0087] The interlayer dielectric layer 180 can be a single layer or a multilayer structure. The material of the interlayer dielectric layer 180 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the material of the interlayer dielectric layer 180 is silicon oxide.

[0088] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 14 to 39 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0089] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0090] refer to Figures 14 to 17A substrate is provided, the substrate including a first region 100a and a second region 100b; the substrate includes a substrate 100 and device fins 110 discrete on the substrate 100.

[0091] The substrate is used to provide a process platform for subsequent processes. In this embodiment, the first region 100a is used to form the first device, and the second region 100b is used to form the second device.

[0092] As an example, the first region 100a is used to form a first type MOS transistor, and the second region 100b is used to form a second type MOS transistor. The first type MOS transistor and the second type MOS transistor have different channel conductivity types.

[0093] In one specific embodiment, the first type of MOS transistor is a PMOS transistor, and the second type of MOS transistor is an NMOS transistor. In other embodiments, the first type of MOS transistor may also be an NMOS transistor, and the second type of MOS transistor may be a PMOS transistor accordingly.

[0094] In some other embodiments, the first device and the second device may also be other different types of devices.

[0095] In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0096] The device fin 110 provides a conductive channel for device operation. The device fin 110 is made of a semiconductor material. The material of the device fin 110 includes one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0097] In this embodiment, the device fin 110 and the substrate 100 are an integral structure. The material of the device fin 110 and the substrate 100 is the same, which is silicon. In other embodiments, the material of the device fin may be different from that of the substrate.

[0098] In this embodiment, during the step of providing the substrate, an initial sacrificial fin 120 and an initial barrier layer 130 are formed on the top of the device fin 110. The device fin 110, the initial sacrificial fin 120, and the initial barrier layer 130 are used to form a fin stack 140, and a plurality of fin stacks 140 are disposed on the substrate 100.

[0099] The initial sacrificial fin 120 is used for subsequent formation of sacrificial fins. The sacrificial fins define the heights of the subsequently formed first and second gate structures.

[0100] The sacrificial fin is subsequently removed. Therefore, the initial sacrificial fin 120 is made of a material that has etching selectivity with the device fin 110, in order to reduce the probability of accidental etching of the device fin 110 during the removal of the sacrificial fin.

[0101] As an example, the initial sacrificial fin 120 is made of silicon germanide. Silicon germanide is a commonly used semiconductor material and has an etch selectivity with silicon to achieve a high etch selectivity between the sacrificial fin and the device fin 110, while also improving process compatibility and reducing process costs.

[0102] In other embodiments, the material of the initial sacrificial fin may also be another material that has etching selectivity with respect to the material of the device fin, such as one or more of silicon phosphide, silicon carbide, and hafnium oxide.

[0103] The initial barrier layer 130 is used for subsequent barrier layer formation. The barrier layer serves to protect the top of the device fin 110 during the subsequent steps of forming the first gate structure located in the first region 100a and the second gate structure located in the second region 100b.

[0104] Therefore, the initial barrier layer 130 is made of a material that has etching selectivity with the material of the initial sacrificial fin 120, in order to reduce the probability of damage to the subsequent barrier layer during the removal of the sacrificial fin, so that the barrier layer can be retained, thereby protecting the top of the device fin 110 in the subsequent steps of forming the first gate structure and the second gate structure.

[0105] As an example, the initial barrier layer 130 may be made of one or more of silicon, silicon oxide, silicon nitride, and silicon oxynitride. In a specific embodiment, the initial barrier layer 130 may be made of silicon oxide. Silicon oxide is a commonly used insulating dielectric material, which is beneficial for improving process compatibility and reducing process costs, and also exhibits high etching selectivity between silicon oxide and silicon germanide.

[0106] In this embodiment, the steps of forming the substrate 100 and the fin stack 140 include:

[0107] like Figures 14 to 15 As shown, Figure 14 This is a top view. Figure 15 (a) is Figure 14 Cross-sectional view along the XX direction. Figure 15 (b) is Figure 14 A cross-sectional view along the YY direction provides an initial stacked structure, including: a substrate 100, a semiconductor layer 101 on the substrate 100, a sacrificial fin material layer 102 on the semiconductor layer 101, and a barrier material layer 103 on the sacrificial fin material layer 102; as shown Figures 16 to 17 As shown, Figure 16 This is a top view. Figure 17 (a) is Figure 16 Cross-sectional view along the XX direction. Figure 17 (b) is Figure 16 A cross-sectional view along the YY direction shows a barrier material layer 103, a sacrificial fin material layer 102, and a semiconductor layer 101. The remaining barrier material layer 103 is used as an initial barrier layer 130, the remaining sacrificial fin material layer 102 is used as an initial sacrificial fin portion 120, and the remaining semiconductor layer 101 is used as a device fin portion 110.

[0108] In this embodiment, the process of forming the semiconductor layer 101 and the sacrificial fin material layer 102 includes an epitaxial process.

[0109] In this embodiment, a deposition process (e.g., chemical vapor deposition) is used to form a barrier material layer 103 on the sacrificial fin material layer 102.

[0110] It should be noted that, in conjunction with references Figures 16 to 17 In this embodiment, the forming method further includes: after forming the device fin 110 and before forming the dummy gate structure, forming an isolation layer 105 surrounding the device fin 110 on the substrate 100, wherein the top of the isolation layer 105 is lower than the top of the device fin 110.

[0111] Specifically, after the fin stack 140 is formed and before the sacrificial gate across the fin stack 140 is formed, an isolation layer 105 is formed on the substrate 100 surrounding the device fin 110.

[0112] The isolation layer 105 is used to achieve isolation between adjacent device fins 110, and also to isolate the substrate 100 from the subsequently formed sacrificial gate, and to isolate the substrate 100 from the subsequently formed first gate structure and second gate structure.

[0113] In this embodiment, the isolation layer 105 is a shallow trench isolation (STI) structure. In this embodiment, the material of the isolation layer 105 is silicon oxide. In other embodiments, the material of the isolation layer can also be other insulating materials such as silicon nitride or silicon oxynitride.

[0114] refer to Figures 18 to 21 A dummy gate structure 200 is formed on the substrate 100 across the device fin 110. The dummy gate structure 200 includes a sacrificial fin 160 located on top of the device fin 110, a barrier layer 170 located on top of the sacrificial fin 160, and a sacrificial gate 150 covering the top of the barrier layer 170, the sidewalls of the sacrificial fin 160 and the barrier layer 170, and a portion of the sidewalls of the device fin 110.

[0115] The pseudo-gate structure 200 is used to define the formation location of the source and drain doped regions.

[0116] The sacrificial gate 150 and the sacrificial fin 160 occupy space for the subsequent formation of a first gate material layer in the first region 100a and a second gate material layer in the second region 100b.

[0117] For a description of the material of the sacrificial fin 160, please refer to the aforementioned detailed description of the initial sacrificial fin 120, which will not be repeated here.

[0118] In this embodiment, the sacrificial gate 150 spans the device fin 110, the sacrificial fin 160, and the barrier layer 170.

[0119] In this embodiment, the material of the sacrificial gate 150 includes polycrystalline silicon or amorphous silicon. As an example, the material of the sacrificial gate 150 is polycrystalline silicon.

[0120] The barrier layer 170 is used to protect the top of the device fin 110 during the subsequent formation of the first gate material layer and the second gate material layer, so as to reduce the probability of damage to the top of the device fin 110 and thus reduce the probability of damage to the film layer located on the top of the device fin 110.

[0121] Specifically, the subsequent formation of the first gate material layer and the second gate material layer typically includes forming a mask cover layer on the first region 100a or the second region 100b, and etching the region exposed by the mask cover layer. The mask cover layer correspondingly exposes the second region 100b or the first region 100a to form a first gate material layer and a second gate material layer with different stacking types and / or material types. The formation of the mask cover layer typically includes an anisotropic etching process to etch and remove the cover material layer located in the gate opening of the second region 100b or the first region 100a. During the anisotropic etching process, the barrier layer 170 is suspended above the top of the device fin 110 at intervals, which can protect the top of the device fin 110 and reduce the risk of damage to the film layer located on the top of the device fin 110, thereby improving the performance of the first gate material layer or the second gate material layer, and thus improving the performance of the semiconductor structure.

[0122] In this embodiment, the material of the barrier layer 170 includes one or more of silicon, silicon oxide, silicon nitride, and silicon oxynitride. For a detailed description of the material of the barrier layer 170, please refer to the foregoing description of the initial barrier layer 130, which will not be repeated here.

[0123] It should be noted that the thickness of the barrier layer 170 should not be too small or too large during the formation of the first gate material layer and the second gate material layer. If the thickness of the barrier layer 170 is too small, it is easily completely consumed during the subsequent formation of the first gate material layer and the second gate material layer, which reduces the barrier effect of the barrier layer 170 on the anisotropic etching process and correspondingly reduces the protective effect of the barrier layer 170 on the device fin 110. If the thickness of the barrier layer 170 is too large, it can lead to an excessively large height of the dummy gate structure 200. Moreover, after the formation of the first gate material layer and the second gate material layer, the first gate material layer and the second gate material layer above the bottom surface of the barrier layer 170, as well as the barrier layer 170, are usually removed. An excessively large thickness of the barrier layer 170 can lead to an excessively large amount of material removed, which can increase the process difficulty, process time, and reduce manufacturing efficiency. Therefore, in this embodiment, the thickness of the barrier layer 170 is 1 nm to 5 nm.

[0124] Accordingly, in this embodiment, in the aforementioned step of forming the initial barrier layer 130, the thickness of the initial barrier layer 130 is 1 nm to 5 nm.

[0125] In this embodiment, the steps for forming the pseudo-gate structure 200 include:

[0126] like Figures 18 to 19 As shown, Figure 18 This is a top view. Figure 19 (a) is Figure 18 Cross-sectional view along the XX direction. Figure 19 (b) is Figure 18 In a cross-sectional view along the YY direction, a sacrificial gate 150 is formed on the substrate 100 across the fin stack 140, and the sacrificial gate 150 covers part of the top and part of the sidewalls of the fin stack 140.

[0127] The sacrificial gate 150 is used to define the etching location for the initial barrier layer 130 and the initial sacrificial fin 120. In this embodiment, the sacrificial gate 150 is formed on the isolation layer 105 and spans the fin stack 140.

[0128] In this embodiment, the step of forming the sacrificial gate 150 includes: forming a sacrificial gate material layer (not shown) covering the isolation layer 105 and the fin stack 140; patterning the sacrificial gate material layer, and retaining the sacrificial gate material layer on a portion of the top and a portion of the sidewalls of the fin stack 140 for use as the sacrificial gate 150.

[0129] like Figures 20 to 21 As shown, Figure 20 This is a top view. Figure 21 (a) is Figure 20 Cross-sectional view along the XX direction. Figure 21 (b) is Figure 20In the cross-sectional view along the YY direction, the initial barrier layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150 are removed. The remaining initial barrier layer 130 is used as barrier layer 170, and the remaining initial sacrificial fin 120 is used as sacrificial fin 160.

[0130] In this embodiment, an anisotropic etching process is used to remove the initial barrier layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150, which helps to improve the accuracy of pattern transfer. As an example, the anisotropic etching process can be anisotropic dry etching process.

[0131] Reference Figures 18 to 19 In this embodiment, the method for forming the semiconductor structure further includes: after forming the sacrificial gate 150, and before removing the initial barrier layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150, forming a first sidewall 155 on the sidewall of the sacrificial gate 150.

[0132] The first sidewall 155 is used to protect the sidewall of the sacrificial gate 150, and is also used together with the sacrificial gate 150 to define the removal area of ​​the initial barrier layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150. The first sidewall 155 is also used to define the formation location of the source and drain doped regions.

[0133] The material of the first sidewall 155 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. The first sidewall 155 can be a single-layer structure or a multilayer structure. In this embodiment, the first sidewall 155 is a single-layer structure, and the material of the first sidewall 155 is silicon nitride.

[0134] refer to Figures 22 to 25 Source / drain doped regions 230 are formed in the device fins 110 on both sides of the pseudo-gate structure 200, and the source / drain doped regions 230 expose the sacrificial fins 160 and the barrier layer 170.

[0135] The source / drain doped region 230 is used as the source or drain of the field-effect transistor. When the field-effect transistor is working, the source / drain doped region 230 is used to provide a source of charge carriers.

[0136] In this embodiment, the source / drain doped region 230 includes a stress layer doped with ions. The source / drain doped region 230 is also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0137] Specifically, when forming an NMOS transistor, the material of the source and drain doped regions 230 is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, which is beneficial to improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0138] When forming a PMOS transistor, the source and drain doped regions 230 are made of a stress layer doped with P-type ions. The stress layer material includes Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions or In ions.

[0139] In one specific embodiment, the first type of MOS transistor is a PMOS transistor, and the second type of MOS transistor is an NMOS transistor. Accordingly, the material of the source / drain doped region 230 located in the first region 100a is a stress layer doped with N-type ions; the material of the source / drain doped region 230 located in the second region 100b is a stress layer doped with P-type ions.

[0140] As an example, in this embodiment, the step of forming the source / drain doped region 230 includes:

[0141] like Figures 22 to 23 As shown, Figure 22 This is a top view. Figure 23 (a) is Figure 22 Cross-sectional view along the XX direction. Figure 23 (b) is Figure 22 In the cross-sectional view along the YY direction, source-drain grooves 220 are formed in the device fins 110 on both sides of the pseudo-gate structure 200.

[0142] The source / drain groove 220 is used to provide space for the formation of source / drain doped regions.

[0143] Specifically, in this embodiment, after removing the initial barrier layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150, a source / drain groove 220 is formed in the device fin 110 exposed by the sacrificial gate 150. This allows the device fin 110 to be etched after the initial barrier layer 130 and the initial sacrificial fin 120 exposed by the sacrificial gate 150 are etched, which is beneficial to improving process integration.

[0144] Specifically, an anisotropic etching process is used to etch the exposed device fins 110 of the dummy gate structure 200 to form source / drain recesses 220, which helps to improve the cross-sectional morphology quality of the source / drain recesses 220. As an example, the anisotropic etching process is an anisotropic dry etching process.

[0145] like Figures 24 to 25 As shown, Figure 24 This is a top view. Figure 25 (a) is Figure 24 Cross-sectional view along the XX direction. Figure 25 (b) is Figure 24 A cross-sectional view along the YY direction shows that source / drain doped regions 230 are formed in the source / drain grooves 220.

[0146] Specifically, in this embodiment, an epitaxial process is used to form a stress layer, and during the formation of the stress layer, ions are self-doped in situ to form source / drain doped regions 230.

[0147] It should be noted that, in this embodiment, after forming the source / drain trench 220 and before forming the source / drain doped region 230 in the source / drain trench 220, the method for forming the semiconductor structure further includes: thinning the sidewalls of the sacrificial fin 160 and the barrier layer 170 along a direction perpendicular to the extension direction of the dummy gate structure 220 and parallel to the substrate 100, and forming sidewall trenches 225 (e.g., ...) on the sidewalls of the sacrificial fin 160 and the barrier layer 170. Figure 23 (as shown); a second sidewall 210 is formed within the sidewall groove 225 (as shown). Figure 25 (As shown).

[0148] The sidewall groove 225 is used to provide space for forming the second sidewall 210.

[0149] In this embodiment, an isotropic etching process is used to etch the sidewalls of the sacrificial fin 160 and the barrier layer 170 along a direction perpendicular to the extension direction of the dummy gate structure 200 and parallel to the substrate 100 to form sidewall grooves 225. The isotropic etching process can etch the sidewalls of the sacrificial fin 160 and the barrier layer 170 along a direction perpendicular to the extension direction of the dummy gate structure 200 and parallel to the substrate 100, thereby achieving thinning of the sidewalls of the sacrificial fin 160 and the barrier layer 170.

[0150] The second sidewall 210 is used to protect the sidewalls of the sacrificial fin 160 and the barrier layer 170. After the sacrificial fin 160 is removed to form the gate material layer, the second sidewall 210 can also protect the sidewalls of the gate material layer.

[0151] Furthermore, in this embodiment, forming the second sidewall 210 after forming the source / drain groove 220 and before forming the source / drain doped region 230 in the source / drain groove 220 is also beneficial to prevent the sidewalls of the sacrificial fin 160 and the barrier layer 170 from being exposed to the process environment in which the source / drain doped region 230 is formed, thereby preventing the source / drain doped region 230 from being formed on the sacrificial fin 160 and the barrier layer 170.

[0152] Specifically, in this embodiment, the material of the sacrificial fin 160 is a semiconductor material, and the process of forming the source / drain doped region 230 includes an epitaxial process. By forming a second sidewall 210 before forming the source / drain doped region 230, epitaxial growth on the sidewall of the sacrificial fin 160 is prevented during the formation of the source / drain doped region 230.

[0153] The material of the second sidewall 210 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate, silicon carbonitride, boron nitride, and boron carbonitride. The second sidewall 210 can be a single-layer structure or a multilayer structure. In this embodiment, the second sidewall 210 is a single-layer structure, and the material of the second sidewall 210 is silicon nitride.

[0154] In other embodiments, after removing the initial barrier layer and initial sacrificial fin exposed by the sacrificial gate, and before forming the source / drain trench, the sidewalls of the sacrificial fin and barrier layer are thinned in a direction perpendicular to the dummy gate structure and parallel to the substrate, forming sidewall trenches on the sidewalls of the sacrificial fin and barrier layer; a second sidewall is formed within the sidewall trench. Accordingly, the second sidewall can also protect the sidewalls of the sacrificial fin and barrier layer during the formation of the source / drain trench, preventing the sidewalls of the sacrificial fin and barrier layer from being exposed to the process environment in which the source / drain trench is formed.

[0155] The second sidewall and the first sidewall are used to form the gate sidewall.

[0156] It should be noted that, in this embodiment, the above process steps for forming the gate sidewall are merely an example. In other embodiments, the second sidewall may be formed on the sidewall of the dummy gate structure after removing the initial barrier layer and initial sacrificial fins exposed by the sacrificial gate, and before forming the source / drain recesses.

[0157] refer to Figures 26 to 27 , Figure 26 This is a top view. Figure 27 (a) is Figure 26 Cross-sectional view along the XX direction. Figure 27 (b) is Figure 26 In the cross-sectional view along the YY direction, in this embodiment, the method for forming the semiconductor structure further includes: after forming the source / drain doped region 230 and before removing the sacrificial gate 150 and the sacrificial fin 170, forming an interlayer dielectric layer 180 on the isolation layer 105 on the side of the dummy gate structure 200 to cover the source / drain doped region 230.

[0158] Interlayer dielectric layer 180 is used to isolate adjacent pseudo-gate structures 200, thereby achieving electrical isolation between adjacent devices. Interlayer dielectric layer 180 can be a single layer or a stacked structure. The material of interlayer dielectric layer 180 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the material of interlayer dielectric layer 180 is silicon oxide.

[0159] refer to Figures 28 to 29 , Figure 28 This is a top view. Figure 29 (a) is Figure 28 Cross-sectional view along the XX direction. Figure 29 (b) is Figure 28 In a cross-sectional view along the YY direction, the sacrificial gate 150 and the sacrificial fin 160 are removed to form a gate opening 240 that exposes the barrier layer 170 and the device fin 110. The barrier layer 170 and the device fin 110 are suspended at a distance.

[0160] The gate opening 240 is used to provide space for the subsequent formation of a first gate material layer in the first region 100a and a second gate material layer in the second region 100b.

[0161] The barrier layer 170 is suspended from the device fin 110 by a gap, so that the barrier layer 170 can block the anisotropic etching process during the subsequent formation of the first gate material layer and the second gate material layer, thereby protecting the top of the device fin 110, reducing the probability of damage to the top of the device fin 110, and correspondingly reducing the probability of damage to the film layer on the top of the device fin 110.

[0162] In this embodiment, the step of forming the gate opening 240 includes: removing the sacrificial gate 150 to form a top opening 41 that exposes the barrier layer 170 and the sacrificial fin 160; removing the exposed sacrificial fin 160 through the top opening 41 to form a bottom opening 42 located between the device fin 110 and the barrier layer 170, wherein the bottom opening 42 and the top opening 41 are used to constitute the gate opening 240.

[0163] The bottom opening 42 and the top opening 41 are connected.

[0164] As an example, one or both of anisotropic and isotropic etching processes are used to remove the sacrificial gate 150. For example, anisotropic etching is used to remove a portion of the sacrificial gate 150; isotropic etching is used to remove the remaining sacrificial gate 150.

[0165] As an example, an anisotropic dry etching process is used to remove a portion of the sacrificial gate 150; an isotropic etching process is used to remove the remaining sacrificial gate 150.

[0166] In this embodiment, an isotropic etching process is used to remove the exposed sacrificial fin 160 through the top opening 41. The isotropic etching process has the characteristics of isotropic etching, which can etch the sidewall of the sacrificial fin 160 exposed by the top opening 41, thereby removing the sacrificial fin 160 through the sidewall of the sacrificial fin 160 exposed by the top opening 41 and reducing the probability of sacrificial fin 160 residue.

[0167] As an example, a wet etching process is used to remove the exposed sacrificial fin 160 through the top opening 41. In this embodiment, the material of the sacrificial fin 160 is SiGe, and the sidewalls of the sacrificial fin 160 exposed by the top opening 41 are etched using an HCl solution.

[0168] refer to Figures 30 to 31 , Figure 30 This is a top view. Figure 31 (a) is Figure 30 Cross-sectional view along the XX direction. Figure 31 (b) is Figure 30 In the cross-sectional view along the YY direction, a gate dielectric layer 250 is formed on the top and sidewalls of the device fin 110 exposed by the gate opening 240 and on the surface of the barrier layer 170.

[0169] The gate dielectric layer 250 is used to achieve electrical isolation between the subsequently formed first gate material layer and the device fin 110, and between the second gate material layer and the device fin 110.

[0170] In this embodiment, during the step of forming the gate dielectric layer 250, the gate dielectric layer 250 located on the bottom surface of the barrier layer 170 serves as a stop layer 370. The stop layer 370 defines the stop position in the subsequent planarization process for forming the first gate structure and the second gate structure, thereby improving the high consistency between the first gate structure and the second gate structure and reducing the difficulty of the planarization process for forming the first gate structure and the second gate structure.

[0171] In this embodiment, the gate dielectric layer 250 includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. As an example, the material of the high-k gate dielectric layer is hafnium oxide (HfO2).

[0172] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. In still other embodiments, the gate dielectric layer may consist only of a gate oxide layer. The material of the gate oxide layer includes one or both of silicon oxide and silicon oxynitride.

[0173] In this embodiment, the process for forming the gate dielectric layer 250 includes atomic layer deposition (ALD). ALD has high step coverage capability, which is beneficial for improving the conformal coverage of the gate dielectric layer 250 on the top and sidewalls of the device fin 110 exposed by the gate opening 240 and the surface of the barrier layer 170. It also helps to improve the thickness uniformity of the gate dielectric layer 250 and form a thinner gate dielectric layer 250 to prevent the gate dielectric layer 250 located at the top of the device fin 110 and the bottom of the barrier layer 170 from contacting each other.

[0174] Reference Figures 30 to 35 A first gate material layer located within a gate opening 240 in a first region 100a and a second gate material layer located within a gate opening 240 in a second region 100b are formed on the gate dielectric layer 250. The first gate material layer and the second gate material layer have different stacking types and / or material types.

[0175] Forming the first gate material layer and the second gate material layer typically includes forming a mask cover layer on the first region 100a or the second region 100b, and etching the region exposed by the mask cover layer. The mask cover layer correspondingly exposes the second region 100b or the first region 100a to form the first gate material layer and the second gate material layer with different stacking types and / or material types. The process of forming the mask cover layer typically includes using an anisotropic etching process to etch away the cover material layer located within the gate opening 240 of the second region 100b or the first region 100a. During the anisotropic etching process, the barrier layer 170 is suspended above the top of the device fin 110 at intervals, which can protect the top of the device fin 110 and reduce the risk of damage to the film layer located on the top of the device fin 110, thereby improving the performance of the first gate material layer or the second gate material layer, and thus improving the performance of the semiconductor structure.

[0176] The first gate material layer is used to subsequently form the first gate structure; the second gate material layer is used to subsequently form the second gate structure.

[0177] In this embodiment, the first gate material layer and the second gate material layer have different stacking types and / or material types, thereby meeting the requirement of forming different types of gate structures in different regions to achieve different device functions.

[0178] In this embodiment, the first gate material layer and the second gate material layer having different stacking types and / or material types means that the first gate material layer and the second gate material layer have different types of stacking structures, or that the first gate material layer and the second gate material layer have different material types, or that the first gate material layer and the second gate material layer have both different types of stacking structures and different material types.

[0179] More specifically, in this embodiment, the first gate material layer and the second gate material layer may include different work function layer material types, different numbers of work function layers, or both different work function layer types and different numbers of work function layers, or different thicknesses of the work function layers, etc., in order to achieve the purpose of adjusting the work function of the gate structure in different regions, thereby making the first device and the second device have different threshold voltages, so as to adjust the threshold voltage of the device in different regions.

[0180] In this embodiment, the steps of forming the first gate material layer and the second gate material layer include:

[0181] like Figures 30 to 31 As shown, a first work function film 260 is formed on the gate dielectric layer 250.

[0182] The first work function film 260 located in the second region 100b is used to subsequently form the second work function layer to adjust the work function of the second gate structure.

[0183] As an example, the material of the first work function membrane 260 includes titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, or silicon titanium nitride.

[0184] like Figures 32 to 33 As shown, Figure 32 This is a top view. Figure 33 (a) is Figure 32 Cross-sectional view along the XX direction. Figure 33 (b) is Figure 32 A cross-sectional view along the YY direction shows the removal of the first work function film 260 located in the first region 100a, exposing the gate dielectric layer 250 of the first region 100a.

[0185] The first work function film 260 located in the first region 100a is removed to allow for the subsequent formation of a second work function film in the gate dielectric layer 260 of the first region 100b. The second work function film may have a different material and / or thickness than the first work function film.

[0186] In this embodiment, the step of removing the first work function film 260 located in the first region 100a includes: forming a mask cover layer 30 that fills the gate opening 240 of the second region 100b, exposing the gate opening 240 of the first region 100a; and removing the first work function film 260 exposed by the mask cover layer 30.

[0187] The masking layer 30 is used as a mask for etching the first work function film 260.

[0188] As an example, the material of the mask covering layer 30 is SOC (spin on carbon).

[0189] In this embodiment, the step of forming the mask cover layer 30 includes: forming a cover material layer (not shown) that fills the gate opening 240; using an anisotropic etching process to remove the cover material layer located in the first region 100a, exposing the gate opening 240 of the first region 100a, and using the remaining cover material layer as the mask cover layer 30.

[0190] In the step of removing the cover material layer located in the first region 100a using an anisotropic etching process, the barrier layer 170 is suspended above the device fin 110 at intervals. It can block the anisotropic etching process, thereby preventing the anisotropic etching process from etching the top of the device fin 110, thereby reducing the probability of damage to the top of the device fin 110. This is beneficial to reducing the probability of damage to the film layer (e.g., gate dielectric layer 250) located on the top of the device fin 110.

[0191] In this embodiment, the process for removing the first work function film 260 exposed by the mask cover layer 30 includes an isotropic etching process. The isotropic etching process has the characteristics of isotropic etching, enabling the etching of film materials located on uneven structural surfaces, thereby facilitating the complete removal of the first work function film 260 exposed by the mask cover layer 30.

[0192] After removing the mask cover layer 30 to expose the first work function film 260, the mask cover layer 30 is removed to expose the gate opening 240 of the second region 100b.

[0193] like Figures 34 to 35 As shown, Figure 34 This is a top view. Figure 35 (a) is Figure 34 Cross-sectional view along the XX direction. Figure 35 (b) is Figure 34In the cross-sectional view along the YY direction, a second work function film 270 is formed on the gate dielectric layer 250 exposed by the gate opening 240 in the first region 100a and on the first work function film 260 exposed by the gate opening 240 in the second region 100b. The second work function film 270 located in the first region 100a is used to form the first work function layer 310, and the first work function film 260 and the second work function film 270 located in the second region 100b are used to form the second work function layer 320.

[0194] In this embodiment, the thickness of the first work function layer 310 is different from that of the second work function layer 320, and the first work function layer 310 and the second work function layer 320 contain different types of materials and have different stacking structures, thereby adjusting the work function of the first gate material layer and the second gate material layer.

[0195] As an example, the material of the second work function film 270 includes titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, or titanium silicon nitride. In this embodiment, the material of the second work function film 270 is the same as the material of the first work function film 260. In other embodiments, the material of the second work function film may also be different from the material of the first work function film.

[0196] like Figures 34 to 35 As shown, a first metal electrode 330 is formed on the first work function layer 310 to fill the gate opening 240 of the first region 100a, for forming a first gate material layer (not shown) with the first work function layer 310 of the first region 100a; a second metal electrode 340 is filled in the gate opening 240 of the second region 100a, for forming a second gate material layer (not shown) with the second work function layer 320.

[0197] The first metal electrode 330 is used as an external electrode of the first gate material layer.

[0198] In this embodiment, the material of the first metal electrode 330 is W. In other embodiments, the material of the electrode material layer can also be Al, Cu, Ag, Au, Pt, Ni, or Ti, etc. In specific implementations, the material of the first metal electrode 330 can also be a work function metal material. The work function metal material can be titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, or titanium silicon nitride.

[0199] The second metal electrode 340 is used as an external electrode of the second gate material layer.

[0200] In this embodiment, the material of the second metal electrode 340 is a work function metal material. The work function metal material can be titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon tantalum nitride, or silicon titanium nitride. In other embodiments, the material of the second metal electrode can also be W, Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0201] It should be noted that, in this embodiment, before forming the first metal electrode 330 that fills the gate opening 240 of the first region 100a on the first work function layer 310, the method further includes: forming a third work function film 280 on the second work function film 270 exposed by the gate opening 240 of the first region 100a, wherein the second work function film 270 and the third work function film 280 located in the first region 100a are used to constitute the first work function layer 310.

[0202] A third work function film 280 is formed to further adjust the work function of the first gate material layer, thereby adjusting the threshold voltage of the device in the first region 100a. In other embodiments, the step of forming the third work function film may be omitted based on actual process requirements.

[0203] The material of the third work function membrane 280 can be titanium aluminide, tantalum carbide, aluminum, titanium carbide, titanium nitride, tantalum nitride, silicon nitride, or titanium silicon nitride.

[0204] As an example, the material of the third work function film 280 is the same as the material of the second metal electrode 340. In other embodiments, the material of the third work function film may also be different from the material of the second metal electrode.

[0205] It should be noted that the steps for forming the first gate material layer and the second gate material layer described above are merely examples, and the number and material of the work function layer in the first and second gate material layers are also just examples. In specific embodiments, the structure and material types of the first and second gate material layers can be adjusted based on actual process requirements.

[0206] refer to Figures 36 to 39 In this embodiment, the forming method further includes: after forming the first gate material layer and the second gate material layer, removing the first gate material layer and the second gate material layer above the top surface of the stop layer 370 and the barrier layer 170, the remaining first gate material layer is used as the first gate structure 350, and the remaining second gate material layer is used as the second gate structure 360.

[0207] The first gate structure 350 is used to control the opening and closing of the conductive channel of the device in the first region 100a. The second gate structure 360 ​​is used to control the opening and closing of the conductive channel of the device in the second region 100b.

[0208] In this embodiment, during the formation of the first gate material layer and the second gate material layer, the barrier layer 170 is suspended above the top of the device fin 110 at intervals, which can protect the top of the device fin 110, reduce the risk of damage to the film layer on the top of the device fin 110, and correspondingly improve the performance of the first gate material layer or the second gate material layer, thereby improving the formation quality of the first gate structure 350 and the second gate structure 360, and thus improving the performance of the semiconductor structure.

[0209] In this embodiment, the stop layer 370 can also define the height of the first gate structure 350 and the second gate structure 360, which is conducive to accurately controlling the height of the first gate structure 350 and the second gate structure 360, and improving the height consistency of the first gate structure 350 and the height consistency of the second gate structure 360.

[0210] In this embodiment, the process of removing the first gate material layer and the second gate material layer of the gate dielectric layer 250 above the top surface of the stop layer 370, as well as the barrier layer 170, includes a planarization process. Accordingly, after forming the first gate structure 350 and the second gate structure 360, the top surfaces of the first gate structure 350 and the second gate structure 360 ​​above the top of the device fin 110 have a recess D (e.g., ...). Figure 39 (As shown by the middle arrow D). The gate dielectric layer 250 is located within the recess D, and the gate dielectric layer 250 located within the recess D is used as the stop layer 370.

[0211] Specifically, along the extending direction of the first gate structure 350 and the second gate structure 360, the top surfaces of the first gate structure 350 and the second gate structure 360 ​​located above the top of the device fin 110 have a recess D.

[0212] Accordingly, in this embodiment, the first gate structure 350 includes: a first work function layer 310 located on the gate dielectric layer 250 on the top and sidewalls of the device fin 110 in the first region 100a, and on the sidewalls and bottom of the stop layer 370; a first metal electrode 330 located on the first work function layer 310 on the sidewalls of the device fin 110 in the first region 100a, and between the first work function layers 310 located between the top of the device fin 110 and the stop layer 370; and a first metal electrode 340 spanning the device fin 110 in the first region 100a.

[0213] Accordingly, in this embodiment, the second gate structure 360 ​​includes: a second work function layer 320 located on the gate dielectric layer 250 on the top and sidewalls of the device fin 110 in the second region 100b, and on the sidewalls and bottom of the stop layer 370; and a second metal electrode 340 located on the second work function layer 320 on the sidewalls of the device fin 110 in the second region 100b, and between the second work function layers 320 located between the top of the device fin 110 and the stop layer 370, wherein the second metal electrode 340 spans the device fin 110 in the second region 100b.

[0214] The first work function layer 310 and the second work function layer 320 are made of different materials and / or have different numbers of layers, thereby adjusting the work function of the first gate structure 350 and the second gate structure 360, and thus adjusting the threshold voltage of the first device and the second device.

[0215] In this embodiment, the step of removing the first gate material layer and the second gate material layer above the top surface of the stop layer 370, as well as the barrier layer 170, includes:

[0216] like Figures 36 to 37 As shown, Figure 36 This is a top view. Figure 37 (a) is Figure 36 Cross-sectional view along the XX direction. Figure 37 (b) is Figure 36 A cross-sectional view along the YY direction, with the top surface of the barrier layer 170 as the stopping position, shows the first and second gate material layers undergoing a first planarization process.

[0217] In this embodiment, the barrier layer 170 is made of an insulating dielectric material, while the first gate material layer and the second gate material layer are made of metallic materials. The barrier layer 170 has a significant material difference from the first gate material layer and the second gate material layer, which makes it easier for the first planarization process to stop on the top surface of the barrier layer 170. This helps to reduce the process difficulty of the first planarization process and makes it easier to define the stop position of the first planarization process.

[0218] As an example, the first planarization process is a chemical mechanical planarization process.

[0219] like Figures 38 to 39 As shown, Figure 38 This is a top view. Figure 39 (a) is Figure 38 Cross-sectional view along the XX direction. Figure 39 (b) is Figure 38 A cross-sectional view along the YY direction shows that, with the top surface of the stop layer 370 as the stop position, the first gate material layer, the second gate material layer, and the barrier layer 170 are subjected to a second planarization process.

[0220] The material of the stop layer 370 is significantly different from that of the first gate material layer and the second gate material layer, which makes it easier for the second planarization process to stop on the top surface of the stop layer 370, thus reducing the difficulty of the second planarization process.

[0221] Specifically, in this embodiment, the gate dielectric layer 250 located on the bottom surface of the barrier layer 170 is used as the stop layer 370. The material of the gate dielectric layer 250 is a dielectric material, and the materials of the first gate material layer and the second gate material layer are metal materials. Thus, the second planarization process can be easily stopped on the top surface of the stop layer 370, which helps to reduce the process difficulty of the second planarization process and makes it easier to define the stop position of the second planarization process.

[0222] As an example, the second planarization process is a chemical mechanical planarization process.

[0223] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first region and a second region; the substrate includes a substrate and device fins discrete on the substrate; A stop layer is located above the top of the device fin and suspended at a distance from the top of the device fin. A first gate structure is located on the substrate of the first region and spans the device fin of the first region, and the first gate structure fills the space between the device fin and the stop layer in the first region. A second gate structure is located on the substrate of the second region and spans the device fin of the second region, and the second gate structure fills the space between the device fin and the stop layer in the second region. The first gate structure and the second gate structure have different stacking types and / or material types. A gate dielectric layer is located between the first gate structure and the device fin, and between the second gate structure and the device fin; The source and drain doped regions are located within the device fins on both sides of the first and second gate structures.

2. The semiconductor structure as described in claim 1, characterized in that, The top surfaces of the first gate structure and the second gate structure above the top of the device fin have recesses; the gate dielectric layer is also located within the recesses, and the gate dielectric layer located within the recesses serves as the stop layer.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, The top surfaces of the first gate structure and the second gate structure are flush with the top surface of the stop layer.

4. The semiconductor structure as described in claim 1, characterized in that, The portion of the first gate structure and the second gate structure located on the substrate between adjacent device fins serves as the first portion, and the portion located above the top of the device fins and between the stop layer serves as the second portion. The semiconductor structure further includes: a gate sidewall located on the sidewalls of the first gate structure and the second gate structure; the gate sidewall includes: a first sidewall located on the sidewall of the first portion; and a second sidewall located on the sidewall of the second portion.

5. The semiconductor structure as described in claim 1, characterized in that, The first gate structure includes: a first work function layer located on the gate dielectric layer at the top and sidewalls of the device fin in the first region, and on the sidewalls and bottom of the stop layer; a first metal electrode located on the first work function layer at the sidewalls of the device fin in the first region, and between the first work function layers located at the top of the device fin and the stop layer, the first metal electrode spanning the device fin in the first region; The second gate structure includes: a second work function layer located on the gate dielectric layer at the top and sidewalls of the device fin in the second region, and on the sidewalls and bottom of the stop layer; and a second metal electrode located on the second work function layer at the sidewalls of the device fin in the second region, and between the second work function layers located between the top of the device fin and the stop layer, the second metal electrode spanning the device fin in the second region. The first work function layer and the second work function layer have different materials and / or different numbers of layers.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an isolation layer located on the substrate and surrounding the device fins, the top of the isolation layer being lower than the top of the device fins; and an interlayer dielectric layer located on the isolation layer on the sides of the first gate structure and the second gate structure and covering the source and drain doped regions. The first gate structure and the second gate structure are located on the isolation layer.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region; the substrate includes a substrate and device fins discrete on the substrate; A pseudo-gate structure is formed on the substrate, spanning the device fin. The pseudo-gate structure includes a sacrificial fin located on top of the device fin, a barrier layer located on top of the sacrificial fin, and a sacrificial gate covering the top of the barrier layer, the sidewalls of the sacrificial fin and the barrier layer, and a portion of the sidewalls of the device fin. Source / drain doped regions are formed in the device fins on both sides of the pseudo-gate structure, and the source / drain doped regions expose the sacrificial fins and the barrier layer; The sacrificial gate and sacrificial fin are removed to form a gate opening that exposes the barrier layer and the device fin, with the barrier layer and the device fin suspended at a distance; A gate dielectric layer is formed on the top and sidewalls of the device fin exposed at the gate opening and on the surface of the barrier layer; A first gate material layer located within a gate opening in the first region and a second gate material layer located within a gate opening in the second region are formed on the gate dielectric layer, wherein the first gate material layer and the second gate material layer have different stacking types and / or material types.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of providing the substrate, an initial sacrificial fin and an initial barrier layer are formed on the top of the device fin, and the device fin, the initial sacrificial fin and the initial barrier layer are used to form a fin stack. The step of forming the pseudo-gate structure includes: forming a sacrificial gate on the substrate that spans the fin stack, the sacrificial gate covering a portion of the top and a portion of the sidewalls of the fin stack; Remove the initial barrier layer and initial sacrificial fin exposed by the sacrificial gate, and use the remaining initial barrier layer as the barrier layer and the remaining initial sacrificial fin as the sacrificial fin.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The steps of forming the source / drain doped region include: after removing the initial barrier layer and initial sacrificial fin exposed by the sacrificial gate, forming a source / drain trench in the device fin exposed by the sacrificial gate; and forming the source / drain doped region in the source / drain trench.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method of forming the semiconductor structure further includes, after forming the source / drain trench and before forming the source / drain doped region in the source / drain trench; or, after removing the initial barrier layer and initial sacrificial fin exposed by the sacrificial gate and before forming the source / drain trench: The sidewalls of the sacrificial fin and the barrier layer are thinned along a direction perpendicular to the extension direction of the pseudo-gate structure and parallel to the substrate, and a sidewall groove is formed on the sidewalls of the sacrificial fin and the barrier layer; a second sidewall is formed in the sidewall groove.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the semiconductor structure further includes: after forming the sacrificial gate, and before removing the initial barrier layer and initial sacrificial fins exposed by the sacrificial gate, forming a first sidewall on the sidewall of the sacrificial gate.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, After removing the initial barrier layer and initial sacrificial fin exposed by the sacrificial gate, and before forming the source-drain trench, the method of forming the semiconductor structure further includes forming a gate sidewall on the sidewall of the dummy gate structure.

13. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of forming a gate opening includes: removing the sacrificial gate to form a top opening that exposes the barrier layer and the sacrificial fin; and removing the exposed sacrificial fin through the top opening to form a bottom opening located between the device fin and the barrier layer, the bottom opening and the top opening constituting the gate opening.

14. The method for forming a semiconductor structure as described in claim 7, characterized in that, The steps of forming the first gate material layer and the second gate material layer include: forming a first work function film on the gate dielectric layer; Remove the first work function film located in the first region to expose the gate dielectric layer in the first region; A second work function film is formed on the gate dielectric layer exposed by the gate opening in the first region and on the first work function film exposed by the gate opening in the second region. The second work function film located in the first region is used to form the first work function layer, and the first work function film and the second work function film located in the second region are used to form the second work function layer. A first metal electrode is formed on the first work function layer to fill the gate opening of the first region, and is used to form a first gate material layer with the first work function layer of the first region. A second metal electrode is filled within the gate opening in the second region to form a second gate material layer together with the second work function layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The step of removing the first work function film located in the first region includes: forming a mask covering layer that fills the gate opening in the second region, thereby exposing the gate opening in the first region; Remove the first work function membrane exposed by the mask covering layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The step of forming the mask cover layer includes: forming a cover material layer that fills the gate opening; using an anisotropic etching process to remove the cover material layer located in the first region, exposing the gate opening in the first region, and using the remaining cover material layer as the mask cover layer.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process of removing the first work function film exposed by the mask cover layer includes an isotropic etching process.

18. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of forming the gate dielectric layer, the gate dielectric layer located at the bottom surface of the barrier layer is used as a stop layer; the method of forming the semiconductor structure further includes: after forming the first gate material layer and the second gate material layer, removing the first gate material layer and the second gate material layer above the top surface of the stop layer, as well as the barrier layer, the remaining first gate material layer is used as a first gate structure, and the remaining second gate material layer is used as a second gate structure.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The step of removing the first gate material layer and the second gate material layer above the top surface of the stop layer, as well as the barrier layer, includes: performing a first planarization process on the first gate material layer and the second gate material layer with the top surface of the barrier layer as the stop position; and performing a second planarization process on the first gate material layer, the second gate material layer, and the barrier layer with the top surface of the stop layer as the stop position.

20. The method for forming a semiconductor structure according to any one of claims 7 to 19, characterized in that, The material of the sacrificial fin includes one or more of silicon germanide, silicon phosphide, silicon carbide, and hafnium oxide.

21. The method for forming a semiconductor structure according to any one of claims 7 to 19, characterized in that, The barrier layer is made of one or more of silicon, silicon oxide, silicon nitride, and silicon oxynitride.

22. The method for forming a semiconductor structure according to any one of claims 7 to 19, characterized in that, In the step of forming the barrier layer, the thickness of the barrier layer is 1 nm to 5 nm.

23. The method for forming a semiconductor structure according to any one of claims 7 to 19, characterized in that, The method for forming the semiconductor structure further includes: after forming the device fin and before forming the dummy gate structure, forming an isolation layer surrounding the device fin on the substrate, wherein the top of the isolation layer is lower than the top of the device fin; After the source / drain doped regions are formed, and before the sacrificial gate and sacrificial fins are removed, an interlayer dielectric layer is formed on the isolation layer on the side of the dummy gate structure to cover the source / drain doped regions.

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