A method for reducing dielectric loss during io silicon oxide removal

Abstract

The application provides a method for reducing dielectric layer loss in an IO silicon oxide removal process, a plurality of mutually spaced gate structures on a silicon substrate; an IO silicon oxide layer between the bottom of the gate structure and the silicon substrate; a deposition etching stop layer; the gate structure is composed of a polysilicon structure, a first hard mask layer and a second hard mask layer; a first dielectric layer is deposited to fill the space between the gate structures; the first dielectric layer is back etched; a silicon nitride layer is deposited to continuously cover the first dielectric layer and the exposed etching stop layer; a second dielectric layer is deposited on the silicon nitride layer; a non-selective back etching is performed to remove the second dielectric layer and the gate structure, the side wall, the etching stop layer and the silicon nitride layer covered by the second dielectric layer; the remaining polysilicon structure is removed; and the IO silicon oxide layer is removed. The application forms a silicon nitride hard mask on the first dielectric layer to prevent the first dielectric layer from being damaged in the process of removing the IO silicon oxide layer, so that the loss of the gate height can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and particularly to a method for reducing dielectric layer loss in IO silicon oxide removal process. BACKGROUND

[0002] Before depositing a high dielectric value film, the original silicon oxide on the components in the non-IO (input / output) area is removed. Since the dielectric layer (silicon oxide) is exposed during the process, loss occurs. Especially when the silicon oxide on the components in the IO area is subjected to over etching to ensure complete removal, the loss of dielectric layer results in overall gate height loss. SUMMARY

[0003] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a method for reducing dielectric layer loss in IO silicon oxide removal process, which solves the problem of dielectric layer loss during the removal of silicon oxide in the IO area in the prior art, and makes the gate height loss.

[0004] To achieve the above-mentioned objects and other related objects, the present application provides a method for reducing dielectric layer loss in IO silicon oxide removal process, which at least comprises:

[0005] Step one, providing a semiconductor structure; the semiconductor structure comprises: a silicon substrate; a plurality of mutually spaced gate structures arranged on the silicon substrate; an IO silicon oxide layer between the bottom of the gate structure and the upper surface of the silicon substrate; a side wall attached to the side wall of the gate structure;

[0006] Depositing an etching stop layer; the etching stop layer is continuously distributed on the side wall of the gate structure, the top of the gate structure, and the upper surface of the silicon substrate between the gate structures; the gate structure is composed of a polysilicon structure, a first hard mask layer, and a second hard mask layer stacked from bottom to top;

[0007] Step two, depositing a first dielectric layer to fill the space between the gate structures, and then planarizing and exposing the etching stop layer on the top of the gate structure;

[0008] Step three, back etching the first dielectric layer, and back etching to a height of two-thirds of the polysilicon structure height of the remaining first dielectric layer;

[0009] Step four, depositing a silicon nitride layer to continuously cover the upper surface of the first dielectric layer and the upper surface of the exposed etching stop layer;

[0010] Step five, depositing a second dielectric layer on the silicon nitride layer to fill the space between the gate structures, and then planarizing to expose the silicon nitride layer on the top of the gate structure;

[0011] Step six, non-selective etching to remove the second dielectric layer and the gate structure, sidewall, etching stop layer and silicon nitride layer covered by the second dielectric layer; the first dielectric layer, the silicon nitride layer on the upper surface of the first dielectric layer and the polysilicon structure, sidewall and etching stop layer between the first dielectric layers are reserved;

[0012] Step seven, removing the remaining polysilicon structure to form a recess, the bottom of the recess exposes the IO silicon oxide layer;

[0013] Step eight, removing the IO silicon oxide layer, the silicon nitride layer on the upper surface of the first dielectric layer as a hard mask makes the first dielectric layer not be damaged in the process of removing the IO silicon oxide layer.

[0014] Preferably, the first hard mask layer in step one is silicon nitride; the second hard mask layer is silicon oxide.

[0015] Preferably, the sidewall attached to the gate structure sidewall in step one is composed of a first sidewall and a second sidewall attached to the first sidewall.

[0016] Preferably, the first sidewall and the second sidewall in step one are both silicon nitride.

[0017] Preferably, the sidewall of the first hard mask layer in step one is completely covered by the first sidewall and the second sidewall; the upper end part of the sidewall of the second hard mask layer is not covered by the first sidewall and the second sidewall.

[0018] Preferably, the part of the etching stop layer covering the top of the gate structure in step one includes that the etching stop layer covers the upper surface of the gate structure and the sidewall of the top end part of the gate structure, and connects with the etching stop layer covering the second sidewall.

[0019] Preferably, the etching stop layer in step one is silicon nitride.

[0020] Preferably, the first dielectric layer in step two is silicon oxide; the planarization method is chemical mechanical polishing.

[0021] Preferably, the second dielectric layer in step five is silicon oxide.

[0022] Preferably, after the non-selective etching to remove the second dielectric layer in step six, the reserved silicon nitride layer on the upper surface of the first dielectric layer forms a concave structure, and the second dielectric layer in the concave structure is reserved.

[0023] Preferably, the second dielectric layer located in the concave structure is removed at the same time when the IO silicon oxide layer is removed in step eight.

[0024] As mentioned above, the method for reducing dielectric layer loss in the process of removing IO silicon oxide of the present application has the following beneficial effects: the present application forms a silicon nitride hard mask on the first dielectric layer, preventing the first dielectric layer from being damaged in the process of removing the IO silicon oxide layer, thus avoiding the loss of the gate height. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figures 1 to 8 The structural schematic diagram of each step of the method for reducing dielectric layer loss in the process of removing IO silicon oxide of the present application is shown in

[0026] Figure 9 The flow chart of the method for reducing dielectric layer loss in the process of removing IO silicon oxide of the present application is shown in DETAILED DESCRIPTION

[0027] The embodiments of the present application will be described in detail hereinafter with specific reference to the drawings. Other advantages and effects of the present application will be easily understood by those skilled in the art from the description of the present application. The present application can also be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0028] Please refer to Figures 1 to 9 It should be noted that the diagrams provided in the present embodiment only schematically illustrate the basic concept of the present application, and the diagrams only show the components related to the present application rather than the number, shape and size of the components in actual implementation. The shape, number and proportion of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complicated.

[0029] The present application provides a method for reducing dielectric layer loss in the process of removing IO silicon oxide, as shown in Figure 9 Figure 9 The flow chart of the method for reducing dielectric layer loss in the process of removing IO silicon oxide of the present application is shown in

[0030] Step one, providing a semiconductor structure; the semiconductor structure includes: a silicon substrate; a plurality of mutually spaced gate structures located on the silicon substrate; an IO silicon oxide layer between the bottom of the gate structure and the upper surface of the silicon substrate; a side wall adhered to the side wall of the gate structure;

[0031] ​An etch stop layer is deposited; the etch stop layer covers the sidewalls of the gate structure, the top of the gate structure, and the upper surface of the silicon substrate between the gate structures in a continuously distributed manner; the gate structure consists of a polysilicon structure, a first hard mask layer, and a second hard mask layer stacked from bottom to top; as shown Figure 1 As shown, step one provides the semiconductor structure; the semiconductor structure includes: a silicon substrate (silicon bulk) 01; a plurality of gate structures arranged at intervals on the silicon substrate 01; a 10-layer silicon oxide layer 02 between the bottom of the gate structure and the upper surface of the silicon substrate 01; and sidewalls attached to the sidewalls of the gate structures.

[0032] like Figure 1 As shown, in step one, an etch stop layer 08 is deposited on the semiconductor structure. The etch stop layer 08 continuously covers the sidewalls of the gate structure, the top of the gate structure, and the upper surface of the silicon substrate 01 between the gate structures. The gate structure consists of a polysilicon structure 03, a first hard mask layer 04, and a second hard mask layer 05 stacked from bottom to top. Further, in step one of this embodiment, the sidewalls attached to the gate structure sidewalls consist of a first sidewall 06 and a second sidewall 07 attached to the first sidewall 06. That is, the etch stop layer 08 continuously covers the second sidewall 07, the top of the second hard mask layer 05, and the upper surface of the silicon substrate 01 between the gate structures.

[0033] Further, in step one of this embodiment, the first hard mask layer 04 is silicon nitride; the second hard mask layer 05 is silicon oxide. Even further, in step one of this embodiment, both the first sidewall 06 and the second sidewall 07 are silicon nitride. In step one of this embodiment, the sidewalls of the first hard mask layer 04 are completely covered by the first sidewall 06 and the second sidewall 07; the upper portion of the sidewalls of the second hard mask layer 05 is not covered by the first sidewall 06 and the second sidewall 07.

[0034] Further, in step one of this embodiment, the portion of the gate structure covered by the etch stop layer 08 includes: the etch stop layer 08 covering the upper surface of the gate structure and the sidewall of the top portion of the gate structure (i.e., the etch stop layer 08 covering the upper surface of the second hard mask layer 05 and its upper end sidewall), and connecting with the etch stop layer covering the second sidewall 07. In step one of this embodiment, the etch stop layer 08 is silicon nitride.

[0035] Step 2: Deposit a first dielectric layer to fill the space between the gate structures, then planarize and expose the etch stop layer on top of the gate structures;

[0036] The first dielectric layer in step two of the embodiment is silicon oxide, and the planarization method is chemical mechanical polishing.

[0037] As shown in FIG. 2, a first dielectric layer 09 is deposited to fill the space between the gate structures, and then the first dielectric layer is planarized to expose the etch stop layer on the top of the gate structures (i.e. the upper surface of the second hard mask layer 05). Figure 2

[0038] As shown in FIG. 3, the first dielectric layer 09 is etched back until the remaining height of the first dielectric layer 09 is two-thirds of the height of the polysilicon structure 03. That is, the distance from the bottom of the first dielectric layer 09 (the upper surface of the etch stop layer) to the top of the first dielectric layer 09 is two-thirds of the distance from the bottom of the polysilicon structure 03 (the upper surface of the IO silicon oxide layer 02) to the top of the polysilicon structure 03. Figure 3

[0039] As shown in FIG. 4, a silicon nitride layer 10 is deposited to continuously cover the upper surface of the first dielectric layer 09 and the exposed upper surface of the etch stop layer 08. Figure 4

[0040] As shown in FIG. 5, a second dielectric layer 11 is deposited on the silicon nitride layer 10 to fill the space between the gate structures, and then the second dielectric layer 11 is planarized to expose the silicon nitride layer 10 on the top of the gate structures. The second dielectric layer 11 in step five of the embodiment is silicon oxide. Figure 5

[0041] As shown in FIG. 6, a non-selective etch back is performed to remove the second dielectric layer and the gate structures, sidewalls, etch stop layers and silicon nitride layers covered by the second dielectric layer. The first dielectric layer, the silicon nitride layer on the upper surface of the first dielectric layer, and the polysilicon structures, sidewalls and etch stop layers between the first dielectric layers are retained. Figure 6 ​​​​As shown, step six involves non-selective etch-back (i.e., removing layers of different materials from top to bottom at the same etching rate) to remove the second dielectric layer 11 and the gate structure, sidewalls, etch stop layer 08, and silicon nitride layer 10 covered by the second dielectric layer 11 (that is, all other material layers at the same height as the removed second dielectric layer are removed, see reference). Figure 6 The first dielectric layer 09, the silicon nitride layer 10 located on the upper surface of the first dielectric layer 09, and the polysilicon structure 03, sidewalls (including the first sidewall and the second sidewall) and etch stop layer 08 located between the first dielectric layers 09 (between two adjacent first dielectric layers 09 in the horizontal direction) are retained.

[0042] like Figure 6 As shown, in further embodiment of the present invention, after the non-selective etch-back to remove the second dielectric layer 11 in step six, the silicon nitride layer 10 located on the upper surface of the first dielectric layer 09 forms a concave structure, and the second dielectric layer 11 located in the concave structure is retained.

[0043] Step 7: Remove the remaining polysilicon structure to form a groove, the bottom of which exposes the IO silicon oxide layer; as shown Figure 7 As shown, step seven removes the remaining polysilicon structure to form a groove 12, the bottom of which exposes the IO silicon oxide layer 02.

[0044] Step 8: Remove the IO silicon oxide layer. The silicon nitride layer covering the upper surface of the first dielectric layer acts as a hard mask to prevent the first dielectric layer from being damaged during the removal of the IO silicon oxide layer. Figure 8 As shown, in step eight, the silicon oxide layer 02 is removed. The silicon nitride layer 10 covering the upper surface of the first dielectric layer 09 acts as a hard mask to prevent the first dielectric layer 09 from being damaged during the removal of the silicon oxide layer 02. If the silicon nitride layer 10 is not formed on the upper surface of the first dielectric layer, the first dielectric layer 09 will also be etched during the etching process of removing the silicon oxide layer 02, and thus will be damaged.

[0045] In a further embodiment of the present invention, in step eight, while removing the IO silicon oxide layer 02, the second dielectric layer located within the concave structure is also removed.

[0046] In summary, this invention forms a silicon nitride hard mask on the first dielectric layer, preventing damage to the first dielectric layer during the removal of the IO silicon oxide layer, thus avoiding loss of gate height. Therefore, this invention effectively overcomes various shortcomings of the prior art and has high industrial applicability.

[0047] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A method of reducing dielectric loss during an IO silicon oxide removal process, comprising: At least comprising: Step one, providing a semiconductor structure; the semiconductor structure comprises: a silicon substrate; a plurality of mutually spaced gate structures on the silicon substrate; an IO silicon oxide layer between the bottom of the gate structure and the upper surface of the silicon substrate; a side wall adhering to the side wall of the gate structure; Depositing an etching stop layer; the etching stop layer covers the side wall of the gate structure, the side wall of the gate structure, and the upper surface of the silicon substrate between the gate structures in a continuous distribution; the gate structure is composed of a polysilicon structure, a first hard mask layer and a second hard mask layer from bottom to top; Step two, depositing a first dielectric layer to fill the space between the gate structures, and then planarizing and exposing the etching stop layer on the top of the gate structure; Step three, etching back the first dielectric layer, and etching back to the height of the remaining first dielectric layer is two-thirds of the height of the polysilicon structure; Step four, depositing a silicon nitride layer to continuously cover the upper surface of the first dielectric layer and the exposed upper surface of the etching stop layer; Step five, depositing a second dielectric layer on the silicon nitride layer to fill the space between the gate structures, and then planarizing to expose the silicon nitride layer on the top of the gate structure; Step six, non-selective etching back to remove the second dielectric layer and the gate structure, side wall, etching stop layer and silicon nitride layer covered by the second dielectric layer; the first dielectric layer, the silicon nitride layer on the upper surface of the first dielectric layer, and the polysilicon structure, side wall and etching stop layer between the first dielectric layer are retained; Step seven, removing the remaining polysilicon structure to form a recess, the bottom of the recess exposes the IO silicon oxide layer; Step eight, removing the IO silicon oxide layer, the silicon nitride layer on the upper surface of the first dielectric layer as a hard mask makes the first dielectric layer not lost in the process of removing the IO silicon oxide layer.

2. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 1, wherein: The first hard mask layer in step one is silicon nitride; the second hard mask layer is silicon oxide.

3. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 2, wherein: The side wall adhering to the gate structure in step one is composed of a first side wall and a second side wall adhering to the first side wall.

4. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 3, wherein: The first side wall and the second side wall in step one are both silicon nitride.

5. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 4, wherein: The side wall of the first hard mask layer in step one is completely covered by the first side wall and the second side wall; the upper part of the side wall of the second hard mask layer is not covered by the first side wall and the second side wall.

6. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 5, wherein: The part of the etching stop layer covering the top of the gate structure in step one includes: the etching stop layer covers the upper surface of the gate structure and the side wall of the top part of the gate structure, and connects with the etching stop layer covering the second side wall.

7. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 1, wherein: The etching stop layer in step one is silicon nitride.

8. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 1, wherein: The first dielectric layer in step two is silicon oxide; the planarization method is chemical mechanical polishing.

9. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 1, wherein: The second dielectric layer in step five is silicon oxide.

10. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 1, wherein: After the non-selective etching back in step six to remove the second dielectric layer, the retained silicon nitride layer on the upper surface of the first dielectric layer forms a concave structure, and the second dielectric layer located in the concave structure is retained.

11. The method of reducing dielectric loss during an IO silicon oxide removal process of claim 10, wherein: In step eight, the second dielectric layer located within the recessed structure is removed while the IO silicon oxide layer is removed.

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