Data access, multi-chip cascade method, system, device and storage medium

Abstract

A data access and multi-chip cascading method, system, device, and storage medium, the method comprising: receiving a first data access instruction from a previous-level chip; determining a new access address based on the access address in the first data access instruction and the address space information of the current chip; updating the access address in the first data access instruction to the new access address, and then sending the updated first data access instruction to the next-level chip to access target data. The access address planning and updating method proposed in the disclosed embodiments enables cross-chip data access in a multi-chip cascade mode, and can flexibly construct a cascade chipset with a larger addressable range on demand to meet the needs of different products or applications.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of computer chip technology, and in particular to a data access, multi-chip cascade method, system, electronic device, and storage medium. Background Art

[0002] As chip systems grow larger and more complex, the amount of data that various SoCs (System on Chips) must process in specific application scenarios continues to climb. A single chip is increasingly unable to meet the demands of increasingly complex applications. Therefore, connecting multiple chips to form multi-chip systems has become a solution.

[0003] The design of a reasonable chip topology and inter-chip data access schemes directly determines the implementation complexity and applicable scenarios of a multi-chip system. How to effectively connect multiple chips to form a multi-chip cascade system that meets different application requirements while maintaining low implementation complexity has become a topic of constant exploration for those skilled in the art. Summary of the Invention

[0004] The embodiments of the present disclosure provide a data access, multi-chip cascading method, system, device and storage medium. Based on the proposed access address planning and update method, cross-chip data access in a multi-chip cascade mode can be achieved, and a cascade chipset with a larger addressable range can be flexibly constructed on demand to meet the needs of different products or applications.

[0005] This application provides a data access method, including:

[0006] receiving a first data access instruction from an upper-level chip;

[0007] Determining a new access address according to the access address in the first data access instruction and address space information of the current chip;

[0008] After the access address in the first data access instruction is updated to the new access address, the updated first data access instruction is sent to the next-level chip to access the target data.

[0009] The present application also provides a multi-chip cascading method, comprising:

[0010] At least two chips are cascaded in a linear manner;

[0011] The at least two chips include: a head chip and a tail chip; except for the tail chip, each of the at least two chips corresponds to a next-level chip;

[0012] Each of the at least two chips performs data access according to the data access method described in any embodiment of the present disclosure.

[0013] The present application also provides a multi-chip cascading method, comprising:

[0014] At least two chips are cascaded in a ring manner;

[0015] The at least two chips include: a head chip and a tail chip; each of the at least two chips corresponds to a next-level chip;

[0016] Each of the at least two chips performs data access according to the data access method described in any embodiment of the present disclosure.

[0017] The present application also provides a multi-chip cascading method, comprising:

[0018] At least two chipsets are connected to the central processing unit in a star-shaped manner;

[0019] Each chipset includes at least two chips, and the at least two chips in each chipset are cascaded using the multi-chip cascading method described in any embodiment of the present disclosure.

[0020] The present application also provides a multi-chip cascade system, comprising:

[0021] At least two chips cascaded in a linear manner;

[0022] The at least two chips include: a head chip and a tail chip; except for the tail chip, each of the at least two chips corresponds to a next-level chip;

[0023] Each of the at least two chips performs data access according to the data access method described in any embodiment of the present disclosure.

[0024] The present application also provides a multi-chip cascade system, comprising:

[0025] At least two chips cascaded in a ring manner;

[0026] The at least two chips include: a head chip and a tail chip; each of the at least two chips corresponds to a next-level chip;

[0027] Each of the at least two chips performs data access according to the data access method described in any embodiment of the present disclosure.

[0028] The present application also provides a multi-chip cascade system, comprising:

[0029] a central processing unit and at least two chipsets;

[0030] The at least two chipsets are connected to the central processing unit in a star-shaped manner;

[0031] Each chipset includes at least two chips, and the at least two chips in each chipset are cascaded using the multi-chip cascading method described in any embodiment of the present disclosure.

[0032] The present application also provides an electronic device, comprising:

[0033] one or more processors;

[0034] a storage device for storing one or more programs,

[0035] When the one or more programs are executed by the one or more processors, the one or more processors implement the data access method as described in any embodiment of the present disclosure.

[0036] The present application also provides an electronic device, comprising:

[0037] one or more processors;

[0038] a storage device for storing one or more programs,

[0039] When the one or more programs are executed by the one or more processors, the one or more processors implement the multi-chip cascading method as described in any embodiment of the present disclosure.

[0040] The present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data access method as described in any embodiment of the present disclosure.

[0041] The present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the multi-chip cascading method as described in any embodiment of the present disclosure.

[0042] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0044] Figure 1A flowchart of a data access method provided in an embodiment of the present application;

[0045] Figure 2 A flowchart of another data access method provided in an embodiment of the present application;

[0046] Figure 3 A flowchart of another data access method provided in an embodiment of the present application;

[0047] Figure 4 A flowchart of another data access method provided in an embodiment of the present application;

[0048] Figure 5 A schematic diagram of a linear topology cascade chip structure provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of another linear topology cascade chip structure provided in an embodiment of the present application;

[0050] Figure 7 A schematic diagram of a cascaded chip structure with a ring topology provided in an embodiment of the present application;

[0051] Figure 8 A schematic diagram of another ring topology cascade chip structure provided in an embodiment of the present application;

[0052] Figure 9 A schematic diagram of communication signals between cascaded chips provided in an embodiment of the present application;

[0053] Figure 10 A schematic diagram of a cascade chip structure with a linear and star composite topology provided in an embodiment of the present application;

[0054] Figure 11 A schematic diagram of a cascaded chip structure of a ring and star composite topology provided in an embodiment of the present application;

[0055] Figure 12 A schematic diagram of a cascade chip structure with a linear expansion topology provided in an embodiment of the present application;

[0056] Figure 13 A schematic diagram of a cascade chip structure of a ring expansion topology provided in an embodiment of the present application;

[0057] Figure 14 A schematic diagram of a cascade chip structure with a linear and star composite expansion topology provided in an embodiment of the present application;

[0058] Figure 15 A schematic diagram of a cascade chip structure of a ring and star composite expansion topology provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] This application describes multiple embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0060] This application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0061] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0062] It should be noted that the descriptions of "first", "second", etc. in the embodiments of the present disclosure are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0063] In chip design, the basic positioning is a scenario where a single chip works. As the complexity of applications increases, the requirements for chip processing power, chip capacity, and addressable range are increasing, and the chip configuration needs to be continuously expanded. However, different products or applications have different requirements for chip processing power and capacity. The continuous pursuit of expanded high-configuration single-chip solutions is not friendly to effectively control chip costs, product size, and product costs. The disclosed embodiment provides a data access method that implements cross-chip addressing and data access based on the chip cascade topology. It can flexibly and simply implement a cascade combination from a single chip to multiple chips, and use a basic single chip to build a cascade chipset that meets different configuration requirements to meet a variety of product specifications or application needs.

[0064] The present disclosure provides a data access method. Figure 1 Shown, including:

[0065] Step 110, receiving a first data access instruction from an upper-level chip;

[0066] Step 120: determining a new access address based on the access address in the first data access instruction and the address space information of the current chip;

[0067] Step 130 : After updating the access address in the first data access instruction to the new access address, the updated first data access instruction is sent to the next-level chip to access the target data.

[0068] It should be noted that in the embodiments of the present disclosure, the first data access instruction and the second data access instruction are different types of data access instructions for the current chip. The first and second are relative concepts, belonging to two types of data access instructions from different perspectives. The first data access instruction comes from other external chips and is a data access instruction sent to the current chip by other external chips. The second data access instruction is a data access instruction initiated by the current chip itself. For the current chip, the second data access instruction can also be sent to the cascaded external chip. After it is issued, for the external chip that receives the instruction, the instruction is the first data access instruction.

[0069] In some exemplary embodiments, the address space information includes: a maximum addressable range within a chip and an address range accessible to external cascade chips.

[0070] In some exemplary embodiments, the maximum addressable range within the chip includes an address range accessible to an external cascade chip.

[0071] The maximum addressable range on a chip indicates that if the address is within this range, it will be addressed on the chip. If it exceeds this range, an error will be reported or the address will be addressed to another chip. It should be noted that the specific division of the address space within the maximum addressable range on a chip is determined by the current chip design requirements. All addresses can be allocated for use, or some addresses can be reserved for use. It is not limited to a specific aspect.

[0072] The address range accessible to the external cascade chip indicates that the addresses within this range are allowed to be accessed by the external chip, and its address range is included in the maximum addressable range within the chip.

[0073] It should be noted that in order to achieve the cascading of multiple chips, the data access method described in the present disclosure is proposed. The cascading of multiple chips can expand the address space. The address space accessible to the current chip is partly its own on-chip address space, and partly the sum of the accessible address spaces of the cascaded external chips. For example, the current chip is N0, and its maximum on-chip addressable range is 0x0000_0000~0x7FFF_FFFF. There are 8 chips N1-N8 cascaded externally, and the accessible address range of each provided external chip is 0x0000_0000~0x0FFF_FFFF. Then, the maximum address range that N0 can access is: 0x0000_0000~0xFFFF_FFFF, of which 0x0000_0000~0x7FFF_FFFF is addressed within its own chip, and 0x8000_0000~0xFFFF_FFFF is addressed within the accessible address range provided by N1-N8 to the outside. At this time, the access address width is 32 bits. The highest 4 bits are used to determine whether data is accessed on-chip or off-chip. If the highest 4 bits are less than 0x8, on-chip addressing is performed. If they are greater than or equal to 0x8, off-chip addressing is performed.

[0074] The maximum addressable range within the chip can be defined as an upper threshold, for example, 0x8000_0000, indicating that access addresses less than the upper threshold 0x8000_0000 are addressed within the chip. Alternatively, the maximum addressable range within the chip can be defined as a start address and an end address, for example, 0x0000_0000 to 0x7FFF_FFFF, indicating that access addresses within this start address and end address are all addressed within the chip. The specific definition is not limited to the aspects of the examples disclosed herein.

[0075] The address range accessible to external cascade chips can be defined as an upper threshold, for example: 0x1000_0000, indicating that the access address less than the upper threshold 0x1000_0000 is the address space within the current chip that can be accessed by external chips. Alternatively, the address range accessible to external cascade chips can be defined as a start address and an end address, for example, 0x0000_0000 to 0x0FFF_FFFF, indicating that the access address within this start address and end address is the address space within the current chip that can be accessed by external chips.

[0076] In some exemplary embodiments, the address range accessible to the external cascade chip is at most equal to the maximum addressable range within the chip.

[0077] In some exemplary embodiments, the address range accessible to the external cascade chip is within the lower address range of the maximum addressable range on the chip. A low address refers to an address with a smaller address value; for example, the maximum addressable range on the chip is 0x0000_0000 to 0x7FFF_FFFF, where 0x0000_0000 to 0x0FFF_FFFF is the address range accessible to the external cascade chip. The address range accessible to the external cascade chip corresponds to an address offset. For example, the address range accessible to the external cascade chip is 0x0000_0000 to 0x0FFF_FFFF, and its corresponding address offset is 0x1000_0000.

[0078] It should be noted that the address range of 0x1000_0000 to 0x7FFF_FFFF included in the maximum addressable range on the chip can be accessed by other instructions generated by the current chip, or it can be reserved and unallocated addresses. Among them, low addresses refer to addresses with smaller address values.

[0079] In some exemplary embodiments, based on specific address space planning, within the total accessible address range, the maximum addressable range within the chip corresponds to a lower address range within the total accessible address range. The maximum addressable range within the chip corresponds to an address offset. For example, the maximum addressable range within the chip is 0x0000_0000 to 0x7FFF_FFFF, and its corresponding address offset is 0x80000000.

[0080] It should be noted that, in the embodiment of the present disclosure, accessing target data according to data access instructions is not limited to accessing specific on-chip components, but can access on-chip memories, registers, and peripheral devices, etc.

[0081] In some exemplary embodiments, determining a new access address according to the access address in the first data access instruction and address space information of the current chip includes:

[0082] According to the access address in the first data access instruction, the maximum addressable range on the chip of the current chip and the accessible address range of the external cascade chip, it is determined that the access address exceeds the accessible range on the chip of the current chip, and the new access address is determined.

[0083] In some exemplary embodiments, whether the access address exceeds the on-chip accessible range of the current chip is determined according to the following method:

[0084] Subtract the offset corresponding to the maximum addressable range of the current chip from the access address in the first data access instruction to obtain an address difference;

[0085] If the address difference falls within the address range accessible to the external cascade chip of the current chip, determining that the address does not exceed the on-chip accessible range of the current chip;

[0086] When the address difference does not fall within the address range accessible to the external cascade chip of the current chip, it is determined that the address exceeds the on-chip accessible range of the current chip.

[0087] For example, the maximum addressable range of the current chip is 0x0000_0000~0x7FFF_FFFF, corresponding to an offset of 0x8000_0000; the external cascade chip can access the address range of 0x0000_0000~0x0FFF_FFF, corresponding to an offset of 0x1000_0000. The access address in the first data access instruction is 0x9100_0000, 0x9100_0000-0x8000_0000=0x1100_0000, which does not fall within the range of 0x0000_0000~0x0FFF_FFF, then it is judged that the access address 0x9100_0000 exceeds the on-chip accessible range of the current chip, and the new access address is determined; the access address in the first data access instruction is 0x8100_0000, 0x8100_0000-0x8000_0000=0x0100_0000, which falls within the range of 0x0000_0000~0x0FFF_FFF, then it is judged that the access address 0x8100_0000 does not exceed the on-chip accessible range of the current chip, that is, it is within the on-chip accessible range of the current chip.

[0088] In some exemplary embodiments, Figure 2 As shown, the method further includes:

[0089] Step 140: Based on the access address in the first data access instruction, the maximum addressable range on the chip of the current chip, and the accessible address range of the external cascade chip, determine whether the access address in the first data access instruction is within the accessible range on the chip of the current chip, and then access the target data in the current chip based on the access address and the maximum addressable range on the chip of the current chip.

[0090] In some exemplary embodiments, accessing target data in the current chip according to the access address and the maximum addressable range of the current chip includes:

[0091] The address offset corresponding to the maximum addressable range within the current chip is subtracted from the access address in the first data access instruction to obtain an on-chip access address, and the target data in the current chip is accessed.

[0092] For example, the access address in the first data access instruction is 0x8100_0000, 0x8100_0000-0x8000_0000=0x0100_0000, which falls between 0x0000_0000~0x0FFF_FFF. It is judged that the access address 0x8100_0000 does not exceed the on-chip accessible range of the current chip, that is, within the on-chip accessible range of the current chip, and the target data in the current chip is accessed; 0x8100_0000-0x8000_0000=0x0100_0000, and the on-chip access address 0x0100_0000 is obtained. According to the on-chip access address 0x0100_0000, the on-chip addressing of the current chip is performed to access the target data.

[0093] In some exemplary embodiments, Figure 3 As shown, the method further includes:

[0094] Step 150: Based on the access address in the first data access instruction, the maximum addressable range on the chip of the current chip, and the accessible address range of the external cascade chip, it is determined that the access address in the first data access instruction exceeds the accessible range on the chip of the current chip, but the current chip is not cascaded to the next level chip, then the first data access instruction is discarded or exception handling is performed.

[0095] For example, the access address in the first data access instruction is 0x9100_0000, 0x9100_0000-0x8000_0000=0x1100_0000, which does not fall within the range of 0x0000_0000~0x0FFF_FFF. It is then determined that the access address 0x9100_0000 exceeds the on-chip accessible range of the current chip, but the current chip is not cascaded to the next-level chip, so the data access instruction is discarded or exception handling is performed.

[0096] In some exemplary embodiments, the new access address in step 130 is determined according to the following method:

[0097] The address offset corresponding to the address range accessible to the external cascade chip of the current chip is subtracted from the access address in the received first data access instruction to obtain the new access address.

[0098] For example, the access address in the first data access instruction is 0x9100_0000, 0x9100_0000-0x8000_0000=0x1100_0000, which does not fall within the range of 0x0000_0000~0x0FFF_FFF. It is then determined that the access address 0x9100_0000 exceeds the on-chip accessible range of the current chip, and the new access address is calculated: 0x9100_0000-0x1000_0000=0x8100_0000. After the access address in the first data access instruction is changed to the new access address 0x8100_0000, it is sent to the next-level chip.

[0099] In some exemplary embodiments, sending the updated first data access instruction to the next-level chip to access the target data includes:

[0100] Method 1: the current chip sends the updated first data access instruction to the next-level chip to access the target data;

[0101] or,

[0102] Method 2: After the current chip completes handshake with the next-level chip, the current chip sends the updated first data access instruction to the next-level chip to access the target data;

[0103] or,

[0104] Mode three: the current chip sends a corresponding data block transfer instruction to the next-level chip according to the updated first data access instruction to access the target data.

[0105] Mode 1 is also called direct forwarding transmission, mode 2 is called handshake transmission, and mode 3 is called block transmission. In other words, data between chips can be transmitted using any of these three modes. As you can understand, direct forwarding transmission has a relatively high bit error rate, while handshake transmission has a relatively low bit error rate. Block transmission is more suitable for transmitting large amounts of data. You can choose the desired transmission mode based on your data transmission needs, and you are not limited to a specific mode.

[0106] In some exemplary embodiments, Figure 4 As shown, the method further includes:

[0107] Step 160 , access the target data in the current chip or send the second data access instruction to the next-level chip to access the target data according to the access address in the second data access instruction initiated by the current chip and the maximum addressable range of the current chip.

[0108] In some exemplary embodiments, step 160 includes:

[0109] According to the access address in the second data access instruction initiated by the current chip and the maximum addressable range of the current chip, it is determined that the access address in the second data access instruction exceeds the maximum addressable range of the current chip, and then the second data access instruction is sent to the next-level chip to access the target data;

[0110] or,

[0111] According to the access address in the second data access instruction initiated by the current chip and the maximum addressable range within the chip of the current chip, it is determined that the access address in the second data access instruction is within the maximum addressable range within the chip of the current chip, and then the target data in the current chip is accessed according to the access address in the second data access instruction.

[0112] For example, if the access address in the second data access instruction is 0x7100_0000, and the maximum addressable range of the current chip N0 is 0x0000_0000 to 0x7FFF_FFFF, the access address 0x7100_0000 is within the maximum addressable range of the current chip. Therefore, the target data in the current chip is accessed according to the access address 0x7100_0000. For another example, if the access address in the second data access instruction is 0x8100_0000, and the maximum addressable range of the current chip is 0x0000_0000 to 0x7FFF_FFFF, the access address 0x8100_0000 exceeds the maximum addressable range of the current chip. Therefore, the second data access instruction is sent to the next cascade chip N1. It can be understood that for N0, the data access instruction is a data access instruction initiated by N0 itself, which is the second data access instruction; for N1, the data access instruction is an instruction from the upper-level chip N0, which is the first data access instruction.

[0113] It can be understood that after the current chip completes the corresponding local access for the received first data access instruction or receives a response from the next-level chip, it returns a response to the previous-level chip. After the current chip completes the corresponding local access for the second data access instruction or receives a response from the next-level chip, it performs subsequent processing accordingly. Based on this, according to the solution provided by the embodiment of the present disclosure, each chip can achieve intra-chip or cross-chip data access after multiple chips are cascaded.

[0114] It can be understood that according to the data access method provided by the embodiments of the present disclosure, for multiple cascaded chips, based on the planned address space, each chip at each level implements target data access according to the corresponding data access instruction processing rules for both the second data access instruction initiated by itself and the first data access instruction from other external chips. This allows for flexible and on-demand configuration of the cascade structure, achieving simple and unified logic.

[0115] The present disclosure also provides a multi-chip cascading method, including:

[0116] At least two chips are cascaded in a linear manner;

[0117] The at least two chips include: a head chip and a tail chip; except for the tail chip, each of the at least two chips corresponds to a next-level chip;

[0118] Each of the at least two chips accesses data according to the method according to any embodiment of the present disclosure.

[0119] In some exemplary embodiments, the cascaded chips are chips of the same specification; and each chip has the same address space information.

[0120] In some exemplary embodiments, the cascaded chips are chips of different specifications; chips of different specifications have different address space information.

[0121] In some exemplary embodiments, Figure 5 As shown, nine identical chips, N0-N8, are cascaded in a linear fashion. For chip N0, the maximum addressable range is 0x0000_0000 to 0x7FFF_FFFF, but the actual allocated address range is 0x0000_0000 to 0x0FFF_FFFF, leaving the remaining addresses unallocated. For chips N1-N8, the maximum addressable range is 0x0000_0000 to 0x7FFF_FFFF, but the actual allocated address range is 0x0000_0000 to 0x0FFF_FFFF, leaving the remaining addresses unallocated. Externally cascaded chips can access addresses in the range 0x0000_0000 to 0x0FFF_FFFF.

[0122] For N0, the data in the chip can be accessed through the address space 0x0000_0000~0x0FFF_FFFF, the first-level chip N1 can be accessed through the address space 0x8000_0000~0x8FFF_FFFF, the second-level chip N2 can be accessed through the address space 0x9000_0000~0x9FFF_FFFF, the third-level chip N3 can be accessed through the address space 0xA000_0000~0xAFFF_FFFF, and the third-level chip N4 can be accessed through the address space 0xB000_0000~0x BFFF_FFFF can access the off-chip fourth-level chip N4, the off-chip fifth-level chip N5 can be accessed through the address space 0xC000_0000~0xCFFF_FFFF, the off-chip sixth-level chip N6 can be accessed through the address space 0xD000_0000~0xDFFF_FFFF, the off-chip seventh-level chip N7 can be accessed through the address space 0xE000_0000~0xEFFF_FFFF, and the off-chip eighth-level chip N8 can be accessed through the address space 0xF000_0000~0xFFFF_FFFF.

[0123] For N0, the chip address space division of N0-N8 is shown in Table 1:

[0124] Table 1 Division of chip address space

[0125] chip Address Space Chip N0 0x0000_0000~0x0FFF_FFFF Chip N1 0x8000_0000~0x8FFF_FFFF Chip N2 0x9000_0000~0x9FFF_FFFF Chip N3 0xA000_0000~0xAFFF_FFFF Chip N4 0xB000_0000~0xBFFF_FFFF Chip N5 0xC000_0000~0xCFFF_FFFF Chip N6 0xD000_0000~0xDFFF_FFFF Chip N7 0xE000_0000~0xEFFF_FFFF Chip N8 0xF000_0000~0xFFFF_FFFF

[0126] Each chip N1-N8 receives the first data access instruction sent by the previous level chip, and subtracts the address offset 0x8000_0000 corresponding to the maximum addressable range within the chip from its access address. If the result is within the address range 0x0000_0000 to 0x0FFF_FFFF accessible to the external cascade chip, the chip is accessed according to the result. If the result exceeds the address range 0x0000_0000 to 0x0FFF_FFFF accessible to the external cascade chip, the new access address is calculated as the received access address minus the address offset 0x1000_0000 corresponding to the address range accessible to the external cascade chip, and the first data access instruction with the updated access address is sent to the next level chip.

[0127] For example, N0 initiates a second data access instruction with an access address of 0x9100_0000, executes step 160 to send the second data access instruction to the next-level chip N1; N1 executes step 110 to receive the first data access instruction with an access address of 0x9100_0000, executes step 120 to determine that the new access address is 0x8100_0000, and continues to execute step 130 to update the access address of the first data access instruction to 0x8100_0000. 0, and sends it to the next-level chip N2; N2 executes step 110 and receives the first data access instruction with the access address 0x8100_0000. Then, it executes step 140 and determines that the access address 0x8100_0000 is within the on-chip accessible range of the current chip N2. It then calculates the on-chip access address 0x8100_0000-0x8000_0000=0x0100_0000 and accesses the target data in N2 based on 0x0100_0000. That is, the second data access instruction with the access address 0x9100_0000 initiated by N0 ultimately obtains the target data from N2.

[0128] In a linear connection, only the previous chip can access the next chip, and the next chip cannot access the previous chip. The chip access relationship is shown in Table 2. Chip N0 can access all subsequent chips from N1 to N8; chip N1 can access all subsequent chips from N2 to N8; chip N2 can access all subsequent chips from N3 to N8; chip N3 can access all subsequent chips from N4 to N8; chip N4 can access all subsequent chips from N5 to N8; chip N5 can access all subsequent chips from N6 to N8; chip N6 can access subsequent chips N7 and N8; chip N7 can access subsequent chip N8; and chip N8 can only access itself.

[0129] Table 2 Linear connection chip access relationship

[0130] chip Accessible off-chip Chip N0 N1,N2,N3,N4,N5,N6,N7,N8 Chip N1 N2,N3,N4,N5,N6,N7,N8 Chip N2 N3,N4,N5,N6,N7,N8 Chip N3 N4,N5,N6,N7,N8 Chip N4 N5,N6,N7,N8 Chip N5 N6,N7,N8 Chip N6 N7,N8 Chip N7 N8 Chip N8 none

[0131] In some exemplary embodiments, the linear topology, N0-N8, is different according to the number of connected chips. There are 8 linear topologies, such as Figure 7 As shown, these structures are Figure 5 In the same way, the front-end chip can access the back-end chip.

[0132] In some exemplary embodiments, the access address bit width is 32 bits. The highest 2 bits are used to determine whether data is accessed on-chip or off-chip. If the highest 2 bits are less than 01, on-chip addressing is performed. If they are greater than or equal to 01, off-chip addressing is performed. The maximum addressable range on-chip is 0x0000_0000~0x3FFF_FFFF, and its corresponding address offset is 0x4000_0000. The actual allocation uses 0x0000_0000~0x3FFF_FFFF. The external cascade chip can access the address range of 0x0000_0000~0x3FFF_FFFF, and its corresponding address offset is 0x4000_0000. The four chips N0-N3 are cascaded. For N0, the chip address space of N0-N3 is divided as shown in Table 3:

[0133] Table 3 Division of chip address space

[0134] chip Address Space Chip N0 0x0000_0000~0x3FFF_FFFF Chip N1 0x4000_0000~0x7FFF_FFFF Chip N2 0x8000_0000~0xBFFF_FFFF Chip N3 0xC000_0000~0xFFFF_FFFF

[0135] It can be understood that the specific addressing address is addressed on-chip or off-chip based on the highest few bits, which can be flexibly determined according to design requirements. More examples will not be discussed in detail here.

[0136] The present disclosure also provides a multi-chip cascading method, including:

[0137] At least two chips are cascaded in a ring manner;

[0138] The at least two chips include: a head chip and a tail chip; each of the at least two chips corresponds to a next-level chip;

[0139] Each chip performs data access according to the data access method described in any embodiment of the present disclosure.

[0140] In some exemplary embodiments, the cascaded chips are chips of the same specification; and each chip has the same address space information.

[0141] In some exemplary embodiments, the cascaded chips are chips of different specifications; chips of different specifications have different address space information.

[0142] In some exemplary embodiments, Figure 7 As shown, nine identical chips, N0 through N8, are cascaded in a ring configuration. Each chip, N0 through N8, has a maximum internal addressable range of 0x0000_0000 to 0x7FFF_FFFF. However, addresses from 0x0000_0000 to 0x0FFF_FFFF are actually allocated for use, leaving the remaining addresses reserved for external cascaded chips. The address range from 0x0000_0000 to 0x0FFF_FFFF is accessible to all external cascaded chips.

[0143] exist Figure 7 In the ring connection shown, all chips are connected in a ring. In this case, all chips are equal in terms of connection, with no hierarchy. Each chip can initiate a call to any other chip outside the chip. The chip access relationship is shown in Table 4.

[0144] Table 4 Ring connection chip access relationship

[0145]

[0146]

[0147] For chip N0, you can Figure 7 The arrows shown in the figure access chips N1, N2, N3, N4, N5, N6, N7, and N8; chip N1 can be Figure 7 The arrows shown in the figure access chips N2, N3, N4, N5, N6, N7, N8, and N0; chip N2 can be Figure 7 The arrows shown in the figure access chips N3, N4, N5, N6, N7, N8, N0, and N1; chip N3 can be Figure 7 The arrows shown in the figure access chips N4, N5, N6, N7, N8, N0, N1, and N2; chip N4 can be accessed according to Figure 7 The arrows shown in the figure access chips N5, N6, N7, N8, N0, N1, N2, and N3; chip N5 can be Figure 7 The arrows shown in the figure access chips N6, N7, N8, N0, N1, N2, N3, and N4; chip N6 can be accessed according to Figure 7 The arrows shown in the figure access chips N7, N8, N0, N1, N2, N3, N4, and N5; chip N7 can be Figure 7 The arrows shown in the figure access chips N8, N0, N1, N2, N3, N4, N5, and N6; chip N8 can be Figure 7 The arrows shown in the figure access chips N0, N1, N2, N3, N4, N5, N6, and N7.

[0148] In some exemplary embodiments, the ring topology, N0-N8, has eight ring topologies, depending on the number of connected chips. Figure 8 As shown, these structures are Figure 7 Similarly, each chip can initiate an access to any off-chip chip.

[0149] In some exemplary embodiments, Figure 9As shown in the figure, inter-chip cascade signal types include synchronization signals, data signals, and low-speed management signals. Synchronization signals coordinate the synchronous operation of each chip. Data signals provide inter-chip data transmission and have a relatively high data rate, also known as high-speed data signals. Management signals manage high-speed links and the operation of each chip and have a relatively low data rate, also known as low-speed management signals.

[0150] As you can see, each chip is connected to the next-level chip via interconnect signals. Synchronous signals are forwarded to the next-level chip via a forwarding mechanism. Pulse-level synchronous signals are output to the next-level chip via an additional amplifier, and RF synchronous signals are also output to the next-level chip via an amplifier. Data signals are forwarded to the next-level chip via the next-level on-chip bus. Management signals are connected via adapters to signal lines. When using the I2C (Inter-Integrated Circuit) protocol, simply connect the I2C slave within the chip to the bus via an open-drain transmission transistor, and connect a pull-up resistor to the bus. This signal connection method only requires two chips to be connected to form a system.

[0151] Figure 9 Management signals can enhance the functional safety of chip topology systems. Before data transmission, the data signal path is trained using management signals to achieve the optimal configuration before data transmission begins. A cyclic redundancy check (CRC) is added during data transmission. During data transmission, the receiver verifies the received data. If an error is detected, the sender is notified via management signals to retransmit the data.

[0152] The present disclosure also provides a multi-chip cascading method, including:

[0153] At least two chipsets are connected to the central processing unit in a star-shaped manner;

[0154] Each chipset includes at least two chips, and the at least two chips in each chipset are cascaded in a linear manner as described in the embodiment of the present disclosure or in a ring manner as described in the embodiment of the present disclosure.

[0155] The present disclosure also provides a multi-chip cascade system, including:

[0156] At least two chips cascaded in a linear manner;

[0157] The at least two chips include: a head chip and a tail chip; except for the tail chip, each of the at least two chips corresponds to a next-level chip;

[0158] Each of the at least two chips performs data access according to the data access method described in any embodiment of the present disclosure.

[0159] The present disclosure also provides a multi-chip cascade system, including:

[0160] At least two chips cascaded in a ring manner;

[0161] The at least two chips include: a head chip and a tail chip; each of the at least two chips corresponds to a next-level chip;

[0162] Each of the at least two chips performs data access according to the data access method described in any embodiment of the present disclosure.

[0163] The present disclosure also provides a multi-chip cascade system, including:

[0164] a central processing unit and at least two chipsets;

[0165] The at least two chipsets are connected to the central processing unit in a star-shaped manner;

[0166] Each chipset includes at least two chips, and the at least two chips in each chipset are cascaded in a linear manner as described in the embodiment of the present disclosure or in a ring manner as described in the embodiment of the present disclosure.

[0167] In some exemplary embodiments, Figure 10 The composite topology shown in Figure 1 is a combination of linear and star topologies. This structure is formed by connecting a linear topology with a central processing unit, which is connected to the central processing unit through other means, such as Ethernet, CAN bus, etc. Figure 10 The figure below shows an example of a four-chip linear and star topology. Each chipset can be composed of multiple chips of the same or varying numbers in a linear topology. The number of linear topologies, and therefore the number of chipsets, can be flexibly configured as needed.

[0168] In some exemplary embodiments, Figure 11 The figure shows a composite topology structure that is a combination of ring and star. This structure is formed by connecting the ring topology structure to the central processing unit, which is connected to the central processing unit through other means, such as Ethernet, CAN bus, etc. Figure 11 The figure below shows an example of a four-chip ring and star topology. Each chipset can be a linear topology consisting of multiple chips of equal or varying numbers. The number of ring topologies, and therefore the number of chipsets, can be flexibly configured as needed.

[0169] It's understood that different chip connection topologies can be applied to different systems. Linear and ring topologies can be applied to package-level and PCB-level system connections. Composite star topologies can be applied to domain system connections, such as indoor system connections and in-vehicle system connections.

[0170] The embodiment of the present disclosure also provides a multi-chip cascade system, which is based on a limited address bit width and can be expanded to connect more chips through upper-layer software.

[0171] In some exemplary embodiments, Figure 12 As shown, the chips are connected in a linear extension topology. In the case of a 32-bit address width, chips N9 to Nk are extended chips. N0 can access chip N8 at most based on address addressing. Chips N9 to Nk can be accessed via software. This is true for every chip. The data access method provided by the embodiment of the present disclosure can access up to 8 off-chip chips via access addresses. Subsequent chips can be accessed via software.

[0172] In some exemplary embodiments, Figure 13 As shown, the chips are connected in a ring-shaped extended topology. With a 32-bit address width, chips N9 to Nk are extended chips. N0 can access chip N8 at the most by addressing, and chips N9 to Nk can be accessed via software. This is true for every chip. The data access method provided by the embodiments of the present disclosure can access up to eight off-chip chips via the access address, and subsequent chips can be accessed via software.

[0173] In some exemplary embodiments, Figure 14 and Figure 15 As shown, they are Figure 12 and Figure 13 The linear topology, ring topology and star composite extended topology in the. Each local topology and Figure 12 and Figure 13 These structures are connected to the central processing unit in a linear or ring topology, and are connected to the central processing unit through other means, such as Ethernet, CAN bus, etc. Figure 14 and Figure 15 The number of linear or ring topologies can also be arbitrary depending on the scenario.

[0174] The present disclosure also provides an electronic device, including:

[0175] one or more processors;

[0176] a storage device for storing one or more programs,

[0177] When the one or more programs are executed by the one or more processors, the one or more processors implement the data access method as described in any embodiment of the present disclosure.

[0178] The present disclosure also provides an electronic device, including:

[0179] one or more processors;

[0180] a storage device for storing one or more programs,

[0181] When the one or more programs are executed by the one or more processors, the one or more processors implement the multi-chip cascading method as described in any embodiment of the present disclosure.

[0182] An embodiment of the present disclosure further provides a computer storage medium, wherein the storage medium stores a computer program, wherein the computer program is configured to execute the data access method as described in any embodiment of the present disclosure when running.

[0183] An embodiment of the present disclosure further provides a computer storage medium, wherein the storage medium stores a computer program, wherein the computer program is configured to execute the multi-chip cascading method as described in any embodiment of the present disclosure when running.

[0184] It can be seen that based on the access address planning and update method proposed in the present disclosure, the data access method can realize cross-chip data access in a multi-chip cascade mode, and can flexibly construct a cascade chipset with a larger addressable range on demand to meet the needs of different products or applications.

[0185] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A data access method, characterized in that: The invention relates to a method for transmitting data between cascaded chips; wherein the cascaded chips coordinate synchronous operation through synchronization signals; the cascaded chips transmit data through data signals, and the data signals forward data to the next-level chip through the on-chip bus of the next-level chip; the cascaded chips perform operation management and data transmission management through management signals; under the management of the management signals, the data access method includes: receiving a first data access instruction from an upper-level chip; Determining a new access address according to the access address in the first data access instruction and address space information of the current chip; After the access address in the first data access instruction is updated to the new access address, the updated first data access instruction is sent to the next-level chip to access the target data.

2. The data access method according to claim 1, wherein: The address space information includes: the maximum addressable range within the chip and the address range accessible to external cascade chips; The determining of a new access address according to the access address in the first data access instruction and the address space information of the current chip includes: According to the access address in the first data access instruction, the maximum addressable range on the chip of the current chip and the accessible address range of the external cascade chip, it is determined that the access address exceeds the accessible range on the chip of the current chip, and the new access address is determined.

3. The data access method according to claim 2, wherein: The new access address is determined in the following manner: The address offset corresponding to the address range accessible to the external cascade chip of the current chip is subtracted from the access address in the received first data access instruction to obtain the new access address.

4. The data access method according to claim 2, wherein: The method further comprises: According to the access address in the first data access instruction, the maximum addressable range on the chip of the current chip and the accessible address range of the external cascade chip, it is determined that the access address in the first data access instruction is within the accessible range on the chip of the current chip, and then the target data in the current chip is accessed according to the access address and the maximum addressable range on the chip of the current chip.

5. The data access method according to claim 4, wherein: The step of accessing target data in the current chip according to the access address and the maximum addressable range of the current chip includes: The address offset corresponding to the maximum addressable range within the current chip is subtracted from the access address in the first data access instruction to obtain an on-chip access address, and the target data in the current chip is accessed.

6. The data access method according to claim 2, wherein: The method further comprises: According to the access address in the first data access instruction, the maximum addressable range on the chip of the current chip and the accessible address range of the external cascade chip, it is determined that the access address in the first data access instruction exceeds the accessible range on the chip of the current chip, but the current chip is not cascaded to the next level chip, then the first data access instruction is discarded or exception handling is performed.

7. The data access method according to any one of claims 1 to 6, wherein: The sending of the updated first data access instruction to the next-level chip to access the target data includes: The current chip sends the updated first data access instruction to the next-level chip to access the target data; Alternatively, after the current chip completes handshake with the next-level chip, the current chip sends the updated first data access instruction to the next-level chip to access the target data; Alternatively, the current chip sends a corresponding data block transfer instruction to the next-level chip according to the updated first data access instruction to access the target data.

8. The data access method according to claim 2, wherein: The method further comprises: According to the access address in the second data access instruction initiated by the current chip and the maximum addressable range within the current chip, the target data in the current chip is accessed or the second data access instruction is sent to the next level chip to access the target data.

9. A multi-chip cascading method, characterized in that: include: At least two chips are cascaded in a linear manner; The at least two chips include: a head chip and a tail chip; except for the tail chip, each of the at least two chips corresponds to a next-level chip; Each of the at least two chips performs data access according to the data access method according to any one of claims 1 to 8; The cascaded chips coordinate synchronous work through synchronization signals; the cascaded chips transmit data through data signals, and the data signals forward data to the next-level chip through the on-chip bus of the next-level chip; the cascaded chips perform operation management and data transmission management through management signals.

10. A multi-chip cascading method, characterized in that: include: At least two chips are cascaded in a ring manner; The at least two chips include: a head chip and a tail chip; each of the at least two chips corresponds to a next-level chip; Each chip performs data access according to the data access method according to any one of claims 1 to 8; The cascaded chips coordinate synchronous work through synchronization signals; the cascaded chips transmit data through data signals, and the data signals forward data to the next-level chip through the on-chip bus of the next-level chip; the cascaded chips perform operation management and data transmission management through management signals.

11. A multi-chip cascading method, characterized in that: include: At least two chipsets are connected to the central processing unit in a star-shaped manner; Each chipset includes at least two chips, and the at least two chips in each chipset are cascaded using the multi-chip cascading method according to claim 9 or 10.

12. A multi-chip cascade system, characterized in that: include: At least two chips cascaded in a linear manner; The at least two chips include: a head chip and a tail chip; except for the tail chip, each of the at least two chips corresponds to a next-level chip; Each of the at least two chips performs data access according to the data access method according to any one of claims 1 to 8; The cascaded chips coordinate synchronous work through synchronization signals; the cascaded chips transmit data through data signals, and the data signals forward data to the next-level chip through the on-chip bus of the next-level chip; the cascaded chips perform operation management and data transmission management through management signals.

13. A multi-chip cascade system, characterized in that: include: At least two chips cascaded in a ring manner; The at least two chips include: a head chip and a tail chip; each of the at least two chips corresponds to a next-level chip; Each chip performs data access according to the data access method according to any one of claims 1 to 8; The cascaded chips coordinate synchronous work through synchronization signals; the cascaded chips transmit data through data signals, and the data signals forward data to the next-level chip through the on-chip bus of the next-level chip; the cascaded chips perform operation management and data transmission management through management signals.

14. A multi-chip cascade system, characterized in that: include: a central processing unit and at least two chipsets; The at least two chipsets are connected to the central processing unit in a star-shaped manner; Each chipset includes at least two chips, and the at least two chips in each chipset are cascaded using the multi-chip cascading method according to claim 9 or 10.

15. An electronic device, characterized in that: include: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the data access method according to any one of claims 1 to 8, or implement the multi-chip cascading method according to any one of claims 9 to 11.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the data access method according to any one of claims 1 to 8 is implemented, or the multi-chip cascading method according to any one of claims 9 to 11 is implemented.

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