LDMOS device and preparation method thereof

Abstract

The present application provides an LDMOS device and a preparation method thereof, wherein a substrate has a drift region and a channel region arranged at intervals, wherein the drift region has a drain region; a field oxide layer is located on the drift region between the drain region and the channel region; a gate polysilicon is connected to a gate field plate, the gate polysilicon is located on the substrate, and the gate field plate is located on the field oxide layer; the polysilicon field plate is located in the drift region, is spaced apart from the gate field plate, and is located on a side of the gate field plate away from the channel region; an interlayer dielectric layer covers the substrate, the field oxide layer, the gate polysilicon, the gate field plate, and the polysilicon field plate, the interlayer dielectric layer has a contact hole located between the polysilicon field plate and the drain region, and is spaced apart from the polysilicon field plate and the drain region; a contact hole field plate is filled in the contact hole and is connected to the polysilicon field plate and the channel region, and the polysilicon field plate and the contact hole field plate overlap or are spaced apart from the field oxide layer to increase the breakdown voltage.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an LDMOS device and a method for manufacturing the same. Background Art

[0002] The BCD process is a process for fabricating bipolar junction transistors (BJTs), complementary metal oxide semiconductors (CMOSs), and diffused metal oxide semiconductors (DMOSs) on the same chip. When using the BCD process to fabricate laterally diffused metal oxide semiconductor (LDMOS) transistors, a field plate is typically used to reduce the electric field and increase the voltage. The field plate is formed by extending the gate polysilicon across the field oxide (FOX) layer. However, this structure easily causes the peak electric field to concentrate below the gate polysilicon. This concentrated electric field can lead to premature breakdown, which in turn reduces the breakdown voltage. Summary of the Invention

[0003] In view of this, the present application provides an LDMOS device and a method for manufacturing the same to improve the breakdown voltage.

[0004] The present application provides an LDMOS device, comprising:

[0005] A substrate having a drift region and a channel region spaced apart from each other, wherein the drift region has a drain region;

[0006] a field oxide layer, disposed on the drift region and located between the drain region and the channel region;

[0007] A gate polysilicon and a gate field plate, wherein the gate polysilicon is connected to the gate field plate, the gate polysilicon is disposed on the substrate, and the gate field plate is disposed on the field oxide layer;

[0008] a polysilicon field plate, located in the drift region, the polysilicon field plate being spaced apart from the gate field plate and located on a side of the gate field plate away from the channel region;

[0009] an interlayer dielectric layer covering the substrate, the field oxide layer, the gate polysilicon, the gate field plate, and the polysilicon field plate, the interlayer dielectric layer having a contact hole penetrating the interlayer dielectric layer to expose the substrate, the contact hole being located between the polysilicon field plate and the drain region, and the contact holes being spaced apart from the polysilicon field plate and the drain region;

[0010] A contact hole field plate is filled in the contact hole, and the contact hole field plate is connected to the polysilicon field plate and the channel region; in the direction from the interlayer dielectric layer toward the substrate, the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are located within the orthographic projection of the field oxide layer, or the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are spaced apart from the orthographic projection of the field oxide layer.

[0011] In some embodiments, a side of the field oxide layer away from the channel region is arranged in contact with or spaced apart from the drain region.

[0012] In some embodiments, the contact hole field plate has a width of 0.1-1 μm.

[0013] In some embodiments, the polysilicon field plate has a thickness of 0.1-5 μm.

[0014] In some embodiments, the channel region has a body region and a source region connected to the body region, and the contact hole field plates are both connected to the polysilicon field plate and the source region.

[0015] In some embodiments, the LDMOS device further includes a barrier layer disposed between the contact hole field plate and the substrate.

[0016] In some embodiments, the LDMOS device further includes a metal layer, which is disposed on the interlayer dielectric layer and the contact hole field plate, and the contact hole field plate is connected to the polysilicon field plate and the channel region through the metal layer.

[0017] The present application also provides a method for preparing an LDMOS device, which is used to prepare the LDMOS device described above, comprising:

[0018] Providing a substrate, wherein the substrate has a drift region and a channel region that are spaced apart, and the drift region has a drain region;

[0019] forming a field oxide layer on the drift region, wherein the field oxide layer is located between the drain region and the channel region;

[0020] forming a gate polysilicon and a gate field plate connected to the gate polysilicon on the substrate and the field oxide layer, wherein the gate polysilicon is disposed on the substrate and the gate field plate is disposed on the field oxide layer;

[0021] forming a polysilicon field plate on the drift region, wherein the polysilicon field plate is spaced apart from the gate field plate and is located on a side of the gate field plate away from the channel region;

[0022] forming an interlayer dielectric layer on the substrate, the field oxide layer, the gate polysilicon, the gate field plate, and the polysilicon field plate, wherein the interlayer dielectric layer has a contact hole penetrating the interlayer dielectric layer to expose the substrate, the contact hole being located between the polysilicon field plate and the drain region, and the contact holes being spaced apart from the polysilicon field plate and the drain region;

[0023] A contact hole field plate is formed in the contact hole, and the contact hole field plate is connected to the polysilicon field plate and the channel region; in the direction from the interlayer dielectric layer toward the substrate, the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are located within the orthographic projection of the field oxide layer, or the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are spaced apart from the orthographic projection of the field oxide layer.

[0024] In some embodiments, after forming a gate polysilicon and a gate field plate connected to the gate polysilicon on the substrate and the field oxide layer, and before forming a polysilicon field plate on the drift region, the method further includes:

[0025] A barrier layer is formed on the substrate and a portion of the polysilicon field plate located between the polysilicon field plate and the drain region.

[0026] The present application provides an LDMOS device and a preparation method thereof. The LDMOS device includes a substrate, a field oxide layer, a gate polysilicon, a gate field plate, a polysilicon field plate, an interlayer dielectric layer, and a contact hole field plate. The substrate has a drift region and a channel region that are spaced apart, and the drift region has a drain region; the field oxide layer is disposed on the drift region and is located between the drain region and the channel region; the gate polysilicon and the gate field plate are connected to the gate field plate, the gate polysilicon is disposed on the substrate, and the gate field plate is disposed on the field oxide layer; the polysilicon field plate is located in the drift region, the polysilicon field plate is spaced apart from the gate field plate, and is located on the side of the gate field plate away from the channel region; the interlayer dielectric layer is provided. The interlayer dielectric layer covers a substrate, a field oxide layer, a gate polysilicon, a gate field plate and a polysilicon field plate. The interlayer dielectric layer has a contact hole that penetrates the interlayer dielectric layer to expose the substrate. The contact hole is located between the polysilicon field plate and the drain region, and the contact holes are spaced apart from the polysilicon field plate and the drain region. The contact hole field plate is filled in the contact hole, and the contact hole field plate is connected to the polysilicon field plate and the channel region. In the direction from the interlayer dielectric layer toward the substrate, the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are located within the orthographic projection of the field oxide layer, or the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are spaced apart from the orthographic projection of the field oxide layer to increase the breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 This is a schematic diagram of the first structure of the LDMOS device provided by this application;

[0029] Figure 2 This is a schematic diagram of the physical structure of the simulation experiment (TCAD) of the LDMOS device provided by this application;

[0030] Figure 3 Schematic diagram of the electric field intensity distribution effect of an existing LDMOS device;

[0031] Figure 4 yes Figure 3 The electric field intensity data diagram along the tangential direction at point a in the figure;

[0032] Figure 5 This is a schematic diagram of the electric field intensity distribution effect of the LDMOS device provided by this application;

[0033] Figure 6 yes Figure 5 The electric field intensity data diagram along the tangential direction at point b in the figure;

[0034] Figure 7 It is a schematic diagram of the current density distribution effect of the existing LDMOS device;

[0035] Figure 8 This is a schematic diagram of the current density distribution effect of the LDMOS device provided by this application;

[0036] Figure 9 yes Figure 7 The c in the figure is consistent with the Figure 8 The current density data along the tangential direction at point d in the figure;

[0037] Figure 10 yes Figure 7 The e in the figure is consistent with the Figure 8 The current density data along the tangential direction at point f in FIG;

[0038] Figure 11 This is a second structural diagram of the LDMOS device provided by this application;

[0039] Figure 12 This is a schematic flow chart of a method for preparing an LDMOS device provided in this application;

[0040] Figure 13-16It is a schematic diagram of the process structure of the method for preparing the LDMOS device provided in this application.

[0041] Reference numerals:

[0042] 10. LDMOS device; 100. substrate; 110. channel region; 111. source region; 120. drift region; 121. drain region; 200. field oxide layer; 300. gate polysilicon; 400. gate field plate; 500. polysilicon field plate; 600. barrier layer; 700. interlayer dielectric layer; 701. contact hole; 800. contact hole field plate; 900. metal layer. DETAILED DESCRIPTION

[0043] The following, in conjunction with the accompanying drawings, clearly and completely describes the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0044] The present application provides an LDMOS device, which includes a substrate, a field oxide layer, a gate polysilicon, a gate field plate, a polysilicon field plate, an interlayer dielectric layer, and a contact hole field plate. The substrate has a drift region and a channel region that are spaced apart, and the drift region has a drain region; the field oxide layer is arranged on the drift region and is located between the drain region and the channel region; the gate polysilicon and the gate field plate are connected to the gate field plate, the gate polysilicon is arranged on the substrate, and the gate field plate is arranged on the field oxide layer; the polysilicon field plate is located in the drift region, the polysilicon field plate is spaced apart from the gate field plate, and is located on the side of the gate field plate away from the channel region; the interlayer dielectric layer is provided. The dielectric layer covers the substrate, the field oxide layer, the gate polysilicon, the gate field plate and the polysilicon field plate; the interlayer dielectric layer has a contact hole that penetrates the interlayer dielectric layer to expose the substrate; the contact hole is located between the polysilicon field plate and the drain region, and the contact holes are spaced apart from the polysilicon field plate and the drain region; the contact hole field plate is filled in the contact hole, and the contact hole field plate is connected to the polysilicon field plate and the channel region; in the direction from the interlayer dielectric layer toward the substrate, the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are located within the orthographic projection of the field oxide layer, or the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are spaced apart from the orthographic projection of the field oxide layer.

[0045] In the present application, a gate field plate connected to the gate polysilicon is arranged on the field oxide layer, a polysilicon field plate is arranged on the side of the gate field plate away from the gate polysilicon and is spaced apart from the gate field plate, and a contact hole field plate is arranged between the polysilicon field plate and the drain region and is spaced apart from the drain region and the polysilicon field plate. In addition, in the direction from the interlayer dielectric layer toward the substrate, the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are arranged to be located within the orthographic projection of the field oxide layer, or the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are arranged to be spaced apart from the orthographic projection of the field oxide layer, and at the same time, the contact hole field plates are short-circuited with the polysilicon field plate and the channel region to zero potential to form multiple independent field plates, so that the gate field plate can reduce the peak value below the gate polysilicon. The electric field is formed by flattening the peak electric field between the gate field plate and the drain region through the polysilicon field plate and the contact hole field plate, so that the electric field distribution at the front end, middle end and rear end of the drift region is more uniform, which can effectively improve the electric field distribution in the drift region, so that the peak electric field is close to the rectangular distribution required by the theoretical maximum breakdown voltage, so as to have a higher breakdown voltage. That is, multiple independent field plates are used to regulate the electric field and current density respectively to flatten the peak electric field between the drain region and the source region on the substrate surface, so that the peak electric field is close to the rectangular distribution required by the theoretical maximum breakdown voltage, so as to improve the withstand voltage of the LDMOS device, and at the same time increase the current path width between the drain region and the source region. The current density at the same position is higher, resulting in a lower specific on-resistance, thereby improving the performance of the LDMOS device.

[0046] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the first structure of an LDMOS device provided in the present application. The present application provides an LDMOS device 10, comprising a substrate 100, a field oxide layer 200, a gate polysilicon layer 300, a gate field plate 400, a first spacer, a second spacer, a polysilicon field plate 500, a third spacer, a barrier layer 600, an interlayer dielectric layer 700, a contact hole field plate 800, a conductive connection portion, a conductive portion, a metal layer 900, and a connection layer.

[0047] The substrate 100 is formed of polycrystalline silicon. The substrate 100 has a drift region 120 and a channel region 110 that are spaced apart. The drift region 120 has a drain region 121. The channel region 110 has a body region and a source region 111 connected to the body region. The source region 111 is located on the side of the body region close to the drift region 120. The drift region 120, the channel region 110, the drain region 121, the body region and the source region 111 are formed by doping ions into the substrate 100.

[0048] The field oxide layer 200 is disposed on the drift region 120 and is located between the drain region 121 and the channel region 110. Specifically, the material of the field oxide layer 200 includes an insulating material such as silicon dioxide, silicon nitride or silicon oxynitride. In this embodiment, the field oxide layer 200 is formed of silicon dioxide as an example. The field oxide layer 200 is located between the drain region 121 and the source region 111. The area on the side of the field oxide layer 200 away from the source region where the gate polysilicon 300 is not disposed is an extension region of the field oxide layer 200. In the direction from the source region 111 toward the drain region 121, the length of the extension region of the field oxide layer 200 is 0-5 μm. The length of the extension region of the field oxide layer 200 is the distance between the gate field plate 800 and the drain region 121. Specifically, in the direction from the source region 111 to the drain region 121, the length of the extension region of the field oxide layer 200 can be 0 μm, 0.7 μm, 1.6 μm, 2.8 μm, 3.9 μm, 4.4 μm or 5 μm, etc. The thickness s of the field oxide layer 200 is 300-1500 Å. Specifically, the thickness s of the field oxide layer 200 can be 300 Å, 500 Å, 820 Å, 1280 Å, 1340 Å, 1480 Å or 1500 Å, etc. The gate insulating layer is disposed on the substrate 100 between the source region 111 and the field oxide layer 200, and the gate insulating layer is spaced apart from the source region 111.

[0049] The gate polysilicon 300 and the gate field plate 400 are connected to each other. The gate polysilicon 300 is disposed on the substrate 100, and the gate field plate 400 is disposed on the field oxide layer 200. Specifically, the gate polysilicon 300 is disposed on the gate insulating layer, the gate field plate 400 is located on a side of the gate polysilicon 300 away from the source region 111, and the gate field plate 400 is disposed on the field oxide layer 200. The gate polysilicon 300 is connected to the gate field plate 400. A first spacer is disposed on the channel region 110, and the first spacer covers the sidewall of the gate polysilicon 300 away from the gate field plate 400. The second spacer is disposed on the field oxide layer 200, and the second spacer covers the sidewall of the gate field plate 400 away from the gate polysilicon 300.

[0050] The polysilicon field plate 500 is located in the drift region 120. The polysilicon field plate 500 is spaced apart from the gate field plate 400 and is located on the side of the gate field plate 400 away from the channel region 110. Specifically, a gate insulating layer is provided between the polysilicon field plate 500 and the drift region 120, that is, the side of the polysilicon field plate 500 close to the substrate 100 is provided in contact with the gate insulating layer. Optionally, the thickness of the gate insulating layer located below the gate polysilicon 300 is less than the thickness of the gate insulating layer located below the polysilicon field plate 500 to reduce the resistance between the source region and the external voltage input. The polysilicon field plate 500 is composed of polysilicon; the distance between the polysilicon field plate 500 and the gate field plate 400 is 0.05-2μm. Specifically, the distance between the polysilicon field plate 500 and the gate field plate 400 can be 0.05, 0.84 μm, 1.23 μm, 1.84 μm or 2 μm, etc.; in the direction from the interlayer dielectric layer 700 toward the substrate 100, the orthographic projection of the polysilicon field plate 500 and the orthographic projection of the field oxide layer 200 are spaced apart or completely overlapped. In this embodiment, the orthographic projection of the polysilicon field plate 500 and the orthographic projection of the field oxide layer 200 are spaced apart from each other in the direction from the interlayer dielectric layer 700 toward the substrate 100. That is, in the direction from the interlayer dielectric layer 700 toward the substrate 100, the orthographic projection of the polysilicon field plate 500 and the orthographic projection of the field oxide layer 200 do not overlap, and the side of the field oxide layer 200 away from the channel region 110 is not in contact with the drain region 121. The polysilicon field plate 500 is located on the side of the gate field plate 400 away from the gate polysilicon 300, and the polysilicon field plate 500 is spaced apart from the gate field plate 400. The length of the polysilicon field plate 500 in the direction from the source region 111 toward the drain region 121 is 0.1-5 μm. Specifically, the length of the polysilicon field plate 500 can be 0.1 μm, 0.8 μm, 1.6 μm, 2.4 μm, 3.7 μm, 4.5 μm, or 5 μm. The third sidewall spacer is located on the field oxide layer 200 and covers the sidewalls on opposite sides of the polysilicon field plate 500. The third sidewall spacer is spaced apart from the second sidewall spacer.

[0051] The blocking layer 600 is arranged on a portion of the polysilicon field plate 500 and the drift region 120 between the field oxide layer 200 and the drain region 121, that is, the blocking layer 600 is arranged between the contact hole field plate 800 and the substrate 100. The blocking layer 600 is composed of an oxide layer and a silicon nitride layer arranged alternately. The thickness of the oxide layer in the blocking layer near the drift region 120 is 100-800Å. Specifically, the thickness of the oxide layer in the blocking layer near the drift region 120 can be 100Å, 200Å, 320Å, 480Å, 540Å, 780Å or 800Å, etc. The blocking layer 600 is an etching stop layer for the contact hole 701, and the contact hole 701 stops on the nitride layer in the blocking layer 600.

[0052] A metal silicide layer is provided on the substrate 100 which is not provided with a gate insulating layer, a field oxide layer 200 and a blocking layer 600. A metal silicide layer is also provided on the side of the gate polysilicon 300 and the gate field plate 400 away from the substrate 100. A metal silicide layer is also provided on the side of the polysilicon field plate 500 away from the substrate 100.

[0053] The interlayer dielectric layer 700 covers the substrate 100, the field oxide layer 200, the gate polysilicon 300, the gate field plate 400, and the polysilicon field plate 500. The interlayer dielectric layer 700 has a contact hole 701 that penetrates the interlayer dielectric layer 700 to expose the substrate 100. The contact hole 701 is located between the polysilicon field plate 500 and the drain region 121, and the contact hole 701 is spaced apart from the polysilicon field plate 500 and the drain region 121. Specifically, the material of the interlayer dielectric layer 700 includes an insulating material such as silicon dioxide, silicon nitride, or silicon oxynitride. The interlayer dielectric layer 700 covers the metal silicide layer, the first sidewall, the gate polysilicon 300, the gate field plate 400, the second sidewall, the third sidewall, the polysilicon field plate 500 and the barrier layer 600; the interlayer dielectric layer 700 has a contact hole 701, a first via hole, a second via hole, a third via hole and a fourth via hole penetrating the interlayer dielectric layer 700, the first via hole and the third via hole are respectively located on opposite sides of the second via hole, the fourth via hole is located on the side of the third via hole away from the second via hole, the contact hole 701 is located between the third via hole and the fourth via hole, and the contact hole 701 is located between the polysilicon field plate 500 and the drain region 12 1, and the contact holes 701 are spaced apart from the polysilicon field plate 500 and the drain region 121; the first via hole exposes the metal silicide layer on the body region, the second via hole exposes the metal silicide layer on the source region 111; the third via hole exposes the metal silicide layer on the polysilicon field plate 500; the contact hole 701 exposes the barrier layer 600 between the field oxide layer 200 and the drain region 121, and the diameter of the contact hole 701 is 0.1-1 μm. Specifically, the diameter of the contact hole 701 can be 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.86 μm, or 1 μm. The fourth via hole exposes the metal silicide layer on the drain region 121.

[0054] The contact hole field plate 800 is filled in the contact hole 701, and the contact hole field plate 800 is connected to the polysilicon field plate 500 and the channel region 110. Specifically, the conductive connection portion is filled in the first via hole, the second via hole, and the third via hole, the conductive portion is filled in the fourth via hole, and the contact hole field plate 800 is filled in the contact hole 701. The material of the conductive connection portion, the conductive portion, and the contact hole field plate 800 includes at least one of Ti, TiN, and W. In this embodiment, the conductive connection portion, the conductive portion, and the contact hole field plate 800 are composed of W as an example. The width w of the contact hole field plate 800 is 0.1-1μm. Specifically, the width w of the contact hole field plate 800 can be 0.1μm, 0.3μm, 0.5μm, 0.7μm, 0.86μm, or 1μm, etc. In the direction from the interlayer dielectric layer 700 toward the substrate 100, the contact hole field plate 800 is spaced apart from the field oxide layer 200, that is, the orthographic projection of the polysilicon field plate 500 and the orthographic projection of the contact hole field plate 800 are spaced apart from the orthographic projection of the field oxide layer 200, so as to reduce the capacitance thickness of the contact hole field plate 800, thereby increasing the capacitance of the contact hole field plate 800, and thus improving the performance of the device.

[0055] The metal layer 900 is disposed on the interlayer dielectric layer and the contact hole field plate 800. The contact hole field plate 800 is connected to the polysilicon field plate 500 and the channel region 110 through the metal layer 900. Specifically, the material of the metal layer 900 includes at least one of Ti, TiN, and Al. The metal layer 900 is disposed on the interlayer dielectric layer, the contact hole field plate 800, and the conductive connection portion. The contact hole field plate 800 is connected to the polysilicon field plate 500, the body region, and the source region 111 through the metal layer 900. The connection layer is co-layered with the metal layer 900 and spaced apart from the metal layer 900. The connection layer is connected to the conductive portion.

[0056] In the prior art, field plates are typically formed by extending gate polysilicon across the field oxide (FOX) layer, and are typically single field plates. However, this structure has only one electric field peak, which is typically concentrated below the gate polysilicon. This results in a reduced avalanche breakdown voltage on the substrate surface, reaching a maximum of only 32.2V, and an increase in the specific on-resistance, which can even reach 14.5mΩ.mm. 2 and above, which results in poor performance of existing LDMOS devices.

[0057] See also Figure 3 and Figure 4 , Figure 3 Schematic diagram of the electric field intensity distribution effect of an existing LDMOS device; Figure 4 yes Figure 3 The electric field intensity data diagram along the tangential direction at a in Figure 3 and Figure 4It can be seen that the existing LDMOS device has only one electric field peak and is relatively concentrated below the gate polysilicon, that is, the electric field is concentrated in one place, resulting in a lower avalanche breakdown voltage on the substrate surface.

[0058] See also Figure 2 、 Figure 5 and Figure 6 , Figure 2 This is a schematic diagram of the physical structure of the simulation experiment (TCAD) of the LDMOS device provided by this application; Figure 5 This is a schematic diagram of the electric field intensity distribution effect of the LDMOS device provided by this application; Figure 6 yes Figure 4 The electric field intensity data diagram along the tangential direction at point b in the figure. The LDMOS device 10 provided in the present application has a gate field plate 400 connected to the gate polysilicon 300 disposed on the field oxide layer 200, a polysilicon field plate 500 spaced apart from the gate field plate 400 disposed on the side of the gate field plate 400 away from the gate polysilicon 300, and a contact hole field plate 800 spaced apart from the drain region 121 and the polysilicon field plate 500 disposed between the polysilicon field plate 500 and the drain region 121, and the contact hole field plate 800 is spaced apart from the polysilicon field plate 500. The source region 111 is short-circuited to zero potential to form multiple independent field plates, so that the surface electric field strength of the substrate 100 has three peaks, which are respectively distributed at the front end, middle end and rear end of the substrate 100, flattening the peak electric field between the drain region 121 and the source region 111, so that the peak electric field is close to the rectangular distribution required for the theoretical maximum breakdown voltage, and the electric field peak is not concentrated in only one place, that is, the electric field distribution will not be uneven. Through this design, its breakdown voltage is increased by 18.3% or more.

[0059] See also Figure 7-10 , Figure 7 It is a schematic diagram of the current density distribution effect of the existing LDMOS device; Figure 8 This is a schematic diagram of the current density distribution effect of the LDMOS device provided by this application; Figure 9 yes Figure 7 The c in the figure is consistent with the Figure 8 The current density data along the tangential direction at point d in the figure; Figure 10 yes Figure 7 The e in the figure is consistent with the Figure 8 The current density data plotted along the tangent line at point f in the figure. In existing LDMOS devices, the current path between the drain and source regions is too narrow, and the current density at the same location is low, resulting in an increase in specific on-resistance.

[0060] Please continue reading Figures 8-10The LDMOS device 10 provided in the present application comprises a gate field plate 400 connected to the gate polysilicon 300 disposed on the field oxide layer 200, a polysilicon field plate 500 spaced apart from the gate field plate 400 on a side of the gate field plate 400 away from the gate polysilicon 300, and a contact hole field plate 800 spaced apart from the drain region 121 and the polysilicon field plate 500 between the polysilicon field plate 500 and the drain region 121. The contact hole field plates 800 are all short-circuited to the polysilicon field plate 500 and the source region 111 at zero potential to form multiple independent field plates. This significantly increases the width of the current path from the drain region to the source region, and increases the current density at the same position, thereby reducing the specific on-resistance. Using the LDMOS device 10 provided in the present application, the specific on-resistance is reduced by 38.6%.

[0061] Therefore, in the present application, a gate field plate 400 connected to the gate polysilicon 300 is provided on the field oxide layer 200, a polysilicon field plate 500 is provided on the side of the gate field plate 400 away from the gate polysilicon 300 and spaced apart from the gate field plate 400, and a contact hole field plate 800 is provided between the polysilicon field plate 500 and the drain region 121 and spaced apart from the drain region 121 and the polysilicon field plate 500, and the contact hole field plates 800 are all short-circuited with the polysilicon field plate 500 and the source region 111 to zero potential to form multiple independent field plates, so that the gate field plate 800 can reduce the peak electric field under the gate polysilicon 300, and at the same time, the polysilicon field plate 500 is used to reduce the peak electric field under the gate polysilicon 300. The contact hole field plate 800 and the contact hole field plate 800 flatten the peak electric field between the gate field plate 800 and the drain region 121, making the electric field distribution at the front end, middle end and rear end of the drift region 120 more uniform, thereby effectively improving the electric field distribution of the drift region 120, so that the peak electric field is close to the rectangular distribution required for the theoretical maximum breakdown voltage, so as to have a higher breakdown voltage, that is, multiple independent field plates are used to regulate the electric field and current density respectively, so as to flatten the peak electric field between the drain region 121 and the source region 111 on the surface of the substrate 100, so that the peak electric field is close to the rectangular distribution required for the theoretical maximum breakdown voltage, so as to improve the withstand voltage of the LDMOS device 10, so that the withstand voltage value can reach 38.1V and above, and at the same time increase the current path width between the drain region and the source region, and the current density at the same position is higher, resulting in a reduction in the specific on-resistance, so that the specific on-resistance is reduced to 8.9 mΩ.mm 2 and below, thereby improving the performance of the LDMOS device 10.

[0062] In the present application, the thickness s of the field oxide layer 200 is set between 300-1500 Å so that the gate field plate 400 has a good ability to adjust the capacitance size, thereby achieving the purpose of modulating the electric field, thereby improving the voltage resistance of the LDMOS device 10 while reducing the on-resistance, thereby ensuring the performance of the LDMOS device 10.

[0063] In the present application, the length of the polysilicon field plate 500 is set between 0.1-5 μm in the direction from the source region 111 toward the drain region 121, so that the polysilicon field plate 500 has a good ability to adjust the capacitance size, thereby achieving the purpose of modulating the electric field, thereby improving the voltage resistance of the LDMOS device 10 while reducing the on-resistance, thereby ensuring the performance of the LDMOS device 10.

[0064] In the present application, the distance between the polysilicon field plate 500 and the gate field plate 400 is set to 0.05-2 μm, so that the polysilicon field plate 500 and the gate field plate 400 can adjust their respective sizes while avoiding connection between the two, thereby ensuring the performance of the device.

[0065] In the present application, the thickness of the oxide layer in the barrier layer near the drift region 120 is set between 100-800 Å, so that the contact hole field plate 800 has a good ability to adjust the capacitance size, thereby achieving the purpose of modulating the electric field, thereby improving the voltage resistance of the LDMOS device 10 while reducing the on-resistance, thereby ensuring the performance of the LDMOS device 10.

[0066] In the present application, the width w of the contact hole field plate 800 is set between 0.1-1 μm so that the contact hole field plate 800 has a good ability to adjust the capacitance size, thereby achieving the purpose of modulating the electric field, thereby improving the voltage resistance of the LDMOS device 10 while reducing the on-resistance, thereby ensuring the performance of the LDMOS device 10.

[0067] In the present application, the length of the extension region of the field oxide layer 200 in the direction from the source region 111 toward the drain region 121 is set to 0-5 μm, so that the contact hole field plate 800 and the polysilicon field plate 500 have a good ability to adjust the capacitance size, thereby achieving the purpose of modulating the electric field, thereby improving the withstand voltage performance of the LDMOS device 10 while reducing the specific on-resistance, thereby ensuring the performance of the LDMOS device 10.

[0068] In the present application, the gate field plate 400 , the polysilicon field plate 500 and the contact hole field plate 800 are adjacently arranged, so as to improve the breakdown voltage and reduce the specific on-resistance while saving the device area.

[0069] In the present application, multiple independent field plates are provided in the LDMOS device 10 of the present application, so that the breakdown voltage can be increased and the specific on-resistance can be reduced without adding an additional photomask process, and the manufacturing process is simple.

[0070] See also Figure 11 , Figure 11This is a schematic diagram of the second structure of the LDMOS device provided in this application. It should be noted that the difference between the second structure and the first structure lies in that the field oxide layer 200 is disposed in contact with the drain region 121 on the side away from the channel region 110. In the direction from the interlayer dielectric layer 700 toward the substrate 100, the orthographic projection of the contact hole field plate 800 and the orthographic projection of the barrier layer are located within the orthographic projection of the field oxide layer 200, thereby further enhancing the electric field regulation effect of the contact hole field plate 800 and thus further ensuring device performance. The rest of the structure is the same as the first structure and will not be repeated here.

[0071] In one embodiment, the thickness of the field oxide layer 200 located below the portion of the polysilicon field plate 500 varies, decreasing gradually as it approaches the drain region 121. The polysilicon field plate 500 is continuously distributed above the portion of the field oxide layer 200. The portion of the field oxide layer 200 adjacent to the drain region 121 has two stepped layers. The difference between the thickness of the portion of the field oxide layer 200 adjacent to the drain region 121 and the thickness of the portion of the field oxide layer 200 adjacent to the gate field plate 400 is equal to the thickness of the gate insulation layer located below the gate polysilicon layer 300. Due to the stepped shape of the field oxide layer 200 below the polysilicon field plate 500, the polysilicon field plate 500 attracts free electrons on the surface of the drift region 120 in a gradually varying distribution, further pulling the electric field toward the drain region 121. This results in a more uniform electric field distribution on the surface of the drift region 120 and a higher breakdown voltage for the LDMOS.

[0072] The present application also provides a method for preparing an LDMOS device, which is used to prepare the LDMOS device provided in the present application, comprising:

[0073] S11. Provide a substrate, wherein the substrate has a drift region and a channel region that are spaced apart, and a drain region is provided in the drift region.

[0074] S12. Form a field oxide layer on the drift region, wherein the field oxide layer is located between the drain region and the channel region.

[0075] S13. Forming gate polysilicon and a gate field plate connected to the gate polysilicon on the substrate and the field oxide layer, wherein the gate polysilicon is disposed on the substrate, and the gate field plate is disposed on the field oxide layer.

[0076] S14. Form a polysilicon field plate on the drift region. The polysilicon field plate is spaced apart from the gate field plate and is located on a side of the gate field plate away from the channel region.

[0077] S15. An interlayer dielectric layer is formed on the substrate, the field oxide layer, the gate polysilicon, the gate field plate and the polysilicon field plate. The interlayer dielectric layer has a contact hole that penetrates the interlayer dielectric layer to expose the substrate. The contact hole is located between the polysilicon field plate and the drain region, and the contact holes are spaced apart from the polysilicon field plate and the drain region.

[0078] S16. A contact hole field plate is formed in the contact hole, and the contact hole field plate is connected to the polysilicon field plate and the channel region. In the direction from the interlayer dielectric layer toward the substrate, the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are located within the orthographic projection of the field oxide layer, or the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are spaced apart from the orthographic projection of the field oxide layer.

[0079] In the present application, the LDMOS device prepared by the preparation method of the present application can be prepared into an LDMOS device having multiple independent field plates without adding additional masks and other process steps, so that it has a higher breakdown voltage and lower specific on-resistance, thereby improving the performance of the LDMOS device and reducing the production cost and production cycle of the device.

[0080] See also Figure 12-16 , Figure 12 This is a schematic flow chart of a method for preparing an LDMOS device provided in this application; Figure 13-16 This is a schematic diagram of the process structure of the method for preparing the LDMOS device provided in this application. This application also provides a method for preparing the LDMOS device provided in this application, which is used to prepare the LDMOS device provided in this application, and the method includes:

[0081] S11. Provide a substrate, wherein the substrate has a drift region and a channel region that are spaced apart, and a drain region is provided in the drift region.

[0082] See also Figure 13 Specifically, the substrate 100 has a drift region 120 and a channel region 110 that are spaced apart. The drift region 120 has a drain region 121. The channel region 110 has a body region and a source region 111 connected to the body region. The source region 111 is located on a side of the body region close to the drift region 120. The drift region 120, the channel region 110, the drain region 121, the body region, and the source region 111 are formed by doping ions into the substrate 100.

[0083] S12. Form a field oxide layer on the drift region, wherein the field oxide layer is located between the drain region and the channel region.

[0084] Please continue reading Figure 13 Specifically, a field oxide layer 200 is formed on the drift region 120 between the drain region 121 and the source region 111 .

[0085] See also Figure 14 In one embodiment, after step S12, the method further includes:

[0086] An insulating layer is disposed on the substrate 100 and the field oxide layer 200 , and is etched to form a gate insulating layer. The gate insulating layer is located on the substrate 100 between the source region 111 and the field oxide layer 200 , and the source region 111 is spaced apart from the gate insulating layer.

[0087] S13. Forming gate polysilicon and a gate field plate connected to the gate polysilicon on the substrate and the field oxide layer, wherein the gate polysilicon is disposed on the substrate, and the gate field plate is disposed on the field oxide layer.

[0088] S14. Form a polysilicon field plate on the drift region. The polysilicon field plate is spaced apart from the gate field plate and is located on a side of the gate field plate away from the channel region.

[0089] See also Figure 14 Specifically, polysilicon is disposed on the substrate 100, the field oxide layer 200, and the gate insulating layer, and is etched to form a gate polysilicon 300, a gate field plate 400, and a polysilicon field plate 500. The gate polysilicon 300 is disposed on the gate insulating layer, the gate field plate 400 is located on a side of the gate polysilicon 300 away from the source region 111, and the gate field plate 400 is disposed on the field oxide layer 200. The gate polysilicon 300 is connected to the gate field plate 400. In the direction from the interlayer dielectric layer 700 toward the substrate 100, the orthographic projection of the polysilicon field plate 500 is spaced apart from the orthographic projection of the field oxide layer 200, that is, the side of the field oxide layer 200 away from the channel region 110 is not in contact with the drain region 121.

[0090] In one embodiment, after step S11, the method further includes: forming a blocking wall on the substrate 100, the field oxide layer 200, the gate polysilicon 300, the gate field plate 400 and the polysilicon field plate 500, and etching to form a first sidewall, a second sidewall and a third sidewall, wherein the first sidewall is arranged on the channel region 110, and the first sidewall covers the sidewall of the gate polysilicon 300 away from the gate field plate 400, the second sidewall is arranged on the field oxide layer 200, and the second sidewall covers the sidewall of the gate field plate 400 away from the gate polysilicon 300; the third sidewall is located on the field oxide layer 200, and the third sidewall covers the sidewalls on opposite sides of the polysilicon field plate 500, and the third sidewall is spaced apart from the second sidewall.

[0091] See also Figure 15In one embodiment, after step S11, the method further includes: forming a barrier layer 600 on the substrate 100 and a portion of the polysilicon field plate 500 located between the polysilicon field plate 500 and the drain region 121. Furthermore, forming a barrier layer 600 on the drift region 120 between the third sidewall spacer and the drain region 121 on the side of the polysilicon field plate 500 away from the gate field plate 400; then, forming a metal silicide on the substrate 100, the field oxide layer 200, the gate polysilicon 300, the gate field plate 400, the polysilicon field plate 500, and the barrier layer 600, and etching to form a metal silicide layer, the metal silicide layer being located on the substrate 100 where the gate insulating layer, the field oxide layer 200, and the barrier layer 600 are not provided, and the metal silicide layer being located on the side of the gate polysilicon 300 and the gate field plate 400 away from the substrate 100, and the metal silicide layer being located on the side of the polysilicon field plate 500 away from the substrate 100.

[0092] S15. An interlayer dielectric layer is formed on the substrate, the field oxide layer, the gate polysilicon, the gate field plate and the polysilicon field plate. The interlayer dielectric layer has a contact hole that penetrates the interlayer dielectric layer to expose the substrate. The contact hole is located between the polysilicon field plate and the drain region, and the contact holes are spaced apart from the polysilicon field plate and the drain region.

[0093] See also Figure 16 Specifically, an insulating material is provided on the substrate, the field oxide layer, the gate polysilicon, the gate field plate, and the polysilicon field plate, and then etched to form an interlayer dielectric layer. The interlayer dielectric layer 700 has a contact hole 701, a first via, a second via, a third via and a fourth via that penetrate the interlayer dielectric layer 700. The first via and the third via are respectively located on opposite sides of the second via, and the fourth via is located on a side of the third via away from the second via. The contact hole 701 is located between the third via and the fourth via. The contact hole 701 is located between the polysilicon field plate 500 and the drain region 121, and the contact holes 701 are spaced apart from the polysilicon field plate 500 and the drain region 121, and the orthographic projection of the contact hole 701 is spaced apart from the orthographic projection of the field oxide layer 200. The first via exposes the metal silicide layer on the body region, the second via exposes the metal silicide layer on the source region 111, the third via exposes the metal silicide layer on the polysilicon field plate 500, and the contact hole 701 exposes the barrier layer 600 between the field oxide layer 200 and the drain region 121.

[0094] S16. A contact hole field plate is formed in the contact hole, and the contact hole field plate is connected to the polysilicon field plate and the channel region. In the direction from the interlayer dielectric layer toward the substrate, the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are located within the orthographic projection of the field oxide layer, or the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are spaced apart from the orthographic projection of the field oxide layer.

[0095] Please continue reading Figure 16 A metal material is disposed in the contact hole 701, the first via hole, the second via hole, the third via hole, and the fourth via hole to form a contact hole field plate 800 in the contact hole 701. The formed contact hole field plate 800 is spaced apart from the field oxide layer 200, and the orthographic projection of the contact hole 701 is spaced apart from the orthographic projection of the field oxide layer 200. That is, in a direction from the interlayer dielectric layer 700 toward the substrate 100, the orthographic projection of the polysilicon field plate 500 and the orthographic projection of the contact hole field plate 800 are spaced apart from the orthographic projection of the field oxide layer 200. Conductive connecting portions are formed in the first via hole, the second via hole, and the third via hole, and a conductive portion is formed in the fourth via hole. Then, a metal layer 900 is formed on the interlayer dielectric layer, the contact hole field plate 800, and the conductive connecting portions.

[0096] In another embodiment, in the direction from the interlayer dielectric layer 700 toward the substrate 100 , the orthographic projection of the polysilicon field plate 500 and the orthographic projection of the contact field plate 800 are located within the orthographic projection of the field oxide layer 200 .

[0097] In the present application, the LDMOS device 10 prepared by the preparation method of the present application can be prepared to obtain an LDMOS device 10 with multiple independent field plates without adding additional masks and other process steps. That is, the prepared device can be provided with a gate field plate 400 connected to the gate polysilicon 300 on the field oxide layer 200, a polysilicon field plate 500 spaced apart from the gate field plate 400 on the side of the gate field plate 400 away from the gate polysilicon 300, and a contact hole field plate 800 spaced apart from the drain region 121 and the polysilicon field plate 500 between the polysilicon field plate 500 and the drain region 121, and the contact hole field plate 800 is short-circuited with the polysilicon field plate 500 and the source region 111 to zero potential to form multiple independent field plates, so that the gate The field plate 800 can reduce the peak electric field below the gate polysilicon 300. At the same time, the polysilicon field plate 500 and the contact hole field plate 800 can flatten the peak electric field between the gate field plate 800 and the drain region 121, making the electric field distribution at the front, middle, and rear ends of the drift region 120 more uniform. This can effectively improve the electric field distribution in the drift region 120, so that the peak electric field is close to the rectangular distribution required for the theoretical maximum breakdown voltage, thereby having a higher breakdown voltage. That is, multiple independent field plates are used to separately regulate the electric field and current density to flatten the peak electric field between the drain region 121 and the source region 111 on the surface of the substrate 100, so that the peak electric field is close to the rectangular distribution required for the theoretical maximum breakdown voltage, thereby improving the withstand voltage of the LDMOS device 10, so that the withstand voltage value can reach 38.1V or above. At the same time, the current path width between the drain region and the source region is increased, and the current density at the same position is higher, resulting in a lower specific on-resistance, so that the specific on-resistance is reduced to 8.9 mΩ.mm. 2And below, thereby improving the performance of the LDMOS device 10, that is, the device prepared by the preparation method provided by the present application has a higher breakdown voltage and a lower specific on-resistance, improving the performance of the LDMOS device 10 and reducing the production cost and production cycle of the device,

[0098] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An LDMOS device, characterized in that: include: A substrate having a drift region and a channel region spaced apart from each other, wherein the drift region has a drain region; a field oxide layer, disposed on the drift region and located between the drain region and the channel region; A gate polysilicon and a gate field plate, wherein the gate polysilicon is connected to the gate field plate, the gate polysilicon is disposed on the substrate, and the gate field plate is disposed on the field oxide layer; a polysilicon field plate, located above the drift region, the polysilicon field plate being spaced apart from the gate field plate and located on a side of the gate field plate away from the channel region, the polysilicon field plate having a thickness of 0.1-5 μm; an interlayer dielectric layer covering the substrate, the field oxide layer, the gate polysilicon, the gate field plate, and the polysilicon field plate, the interlayer dielectric layer having a contact hole penetrating the interlayer dielectric layer to expose the substrate, the contact hole being located between the polysilicon field plate and the drain region, and the contact holes being spaced apart from the polysilicon field plate and the drain region; a contact hole field plate filled in the contact hole, the contact hole field plate being connected to the polysilicon field plate and the channel region; the channel region having a body region and a source region connected to the body region, the contact hole field plate being connected to the polysilicon field plate and the source region; in a direction from the interlayer dielectric layer toward the substrate, an orthographic projection of the polysilicon field plate and an orthographic projection of the contact hole field plate are located within an orthographic projection of the field oxide layer, or an orthographic projection of the polysilicon field plate and an orthographic projection of the contact hole field plate are spaced apart from an orthographic projection of the field oxide layer; A barrier layer is provided between the contact hole field plate and the substrate. The barrier layer is composed of an oxide layer and a silicon nitride layer that are alternately provided. The thickness of the oxide layer in the barrier layer close to the drift region is 100-800Å.

2. The LDMOS device according to claim 1, wherein: The field oxide layer is arranged in contact with or spaced apart from the drain region at a side away from the channel region.

3. The LDMOS device according to claim 1, wherein: The width of the contact hole field plate is 0.1-1 μm.

4. The LDMOS device according to claim 1, wherein: The LDMOS device further includes a metal layer, which is disposed on the interlayer dielectric layer and the contact hole field plate. The contact hole field plate is connected to the polysilicon field plate and the channel region through the metal layer.

5. A method for preparing an LDMOS device, characterized in that: Used to prepare the LDMOS device according to any one of claims 1 to 4, comprising: Providing a substrate, wherein the substrate has a drift region and a channel region that are spaced apart, and the drift region has a drain region; forming a field oxide layer on the drift region, wherein the field oxide layer is located between the drain region and the channel region; forming a gate polysilicon and a gate field plate connected to the gate polysilicon on the substrate and the field oxide layer, wherein the gate polysilicon is disposed on the substrate and the gate field plate is disposed on the field oxide layer; forming a polysilicon field plate on the drift region, wherein the polysilicon field plate is spaced apart from the gate field plate and is located on a side of the gate field plate away from the channel region; forming an interlayer dielectric layer on the substrate, the field oxide layer, the gate polysilicon, the gate field plate, and the polysilicon field plate, wherein the interlayer dielectric layer has a contact hole penetrating the interlayer dielectric layer to expose the substrate, the contact hole being located between the polysilicon field plate and the drain region, and the contact holes being spaced apart from the polysilicon field plate and the drain region; A contact hole field plate is formed in the contact hole, and the contact hole field plate is connected to the polysilicon field plate and the channel region; in the direction from the interlayer dielectric layer toward the substrate, the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are located within the orthographic projection of the field oxide layer, or the orthographic projection of the polysilicon field plate and the orthographic projection of the contact hole field plate are spaced apart from the orthographic projection of the field oxide layer.

6. The method for preparing an LDMOS device according to claim 5, wherein: After forming gate polysilicon and a gate field plate connected to the gate polysilicon on the substrate and the field oxide layer, and before forming a polysilicon field plate on the drift region, the method further includes: A barrier layer is formed on the substrate and a portion of the polysilicon field plate located between the polysilicon field plate and the drain region.

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