An engineered modified device and method

Abstract

The embodiment of the application provides an engineering modified device and method, relates to the chip design field, and the device comprises: the device comprises: a searching unit and a first operation unit, the searching unit performs first search processing to search for a similar register based on the lowest level of a second register in a second SYN netlist instantiation hierarchy; when the first search processing result is that the similar register searched is chained in the first scan chain, the first operation unit connects the port for DFT of the second register with the port for DFT of the similar register in the first scan chain. Based on the scheme, the second register is inserted into the scan chain through the device, and the DFT controllable signal point with consistent function logic is selected for the second register, the time sequence impact on the original circuit is small, the device is strong in universality, high in efficiency, and suitable for the chip under different design templates and the scene with a large number of newly added registers.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, and more particularly, to an engineering modification device and method. BACKGROUND

[0002] In the process of chip design, in order to be able to test the final produced physical chip, the design engineer needs to insert a testability (design for test, DFT) circuit in the designed electrical gate level synthesis (synphysize, SYN) netlist to obtain a DFT netlist, and perform a layout and routing operation based on the DFT netlist to obtain a place and route (PR) netlist. However, in the later stage of chip design, if it is found that there is an error in the original circuit design or new functions need to be added, the PR netlist needs to be directly modified, that is, engineering modification. The current way to complete engineering modification is to manually write a script to insert a new register into the scan chain of the original netlist. However, in the case of a large netlist, manually writing a script to add a register is a huge workload, low in efficiency, poor in generality, and difficult to implement.

[0003] Therefore, how to solve the problem of low modification efficiency and poor generality of the current engineering modification method is a technical problem that needs to be solved at the present stage. SUMMARY

[0004] The embodiments of the present application provide an engineering modification device and method to solve the problem of low modification efficiency and poor generality of the current engineering modification method.

[0005] In a first aspect, an engineering modification device is provided, which includes a searching unit and a first operation unit.

[0006] The searching unit performs a first search process to search for a similar register based on the lowest level in the instantiation hierarchy in which a second register is located in a second SYN netlist, wherein the second register is a register that needs to be added to a first scan chain, the first scan chain is a scan chain inserted in a design for testability (DFT) circuit included in a first SYN netlist, the second SYN netlist is a modified first SYN netlist, and the similar register is a register with consistent functional logic as the second register; when the first search process result is that a similar register already chained in the first scan chain is searched, the first operation unit connects the port for DFT of the second register with the port for DFT of the similar register in the first scan chain.

[0007] It should be understood that the second register is added in the first scan chain because the first PR netlist in which the first scan chain is located has some errors or needs to add some functions. The first PR netlist can be the original PR netlist before the engineering modification, and the first PR netlist can be a netlist obtained based on the first DFT netlist after layout and wiring; the first DFT netlist can be the original DFT netlist before the engineering modification, and the first DFT netlist is a netlist obtained after inserting the DFT circuit in the first SYN netlist; and the first SYN netlist is a netlist obtained after synthesizing the original register transfer level (RTL) code.

[0008] For example, the instantiation hierarchy of the second register can be represented by the instantiation hierarchy name of the second register. The instantiation hierarchy name is composed of letters and numbers. Since the instantiation hierarchy name is named according to the specified naming rule, the registers with similar instantiation hierarchy names are close in physical position.

[0009] For example, the instantiation hierarchy name of the second register can be in the following form:

[0010] A1.1.1.1; A1.1.1.2; A1.1.2.1; A1.1.2.2; A1.2.1.1; A1.2.1.2; and so on. The combination of letters and numbers can represent the specific physical position of the specified register in the DFT circuit, or can be understood as the position of the register in the specific level in the DFT circuit, or can be understood as the specific path that can track the specified register in the DFT circuit. Of course, in order to distinguish different registers under the same hierarchy name, the register id that can uniquely identify the register can also be carried after the instantiation hierarchy name, for example: A1.1.1.1- register id (001), A1.1.2.1- register id (002), and so on. For these two register instantiation hierarchies, only the second last level is different, therefore, the physical positions of the two registers should be close. Further, the digital circuit also includes a register: A1.1.1.2- register id (003), compared with register 002, the instantiation hierarchy of register 003 and register 001 only differs in the last level, therefore, it can be known that the physical position of register 003 and register 001 is closer.

[0011] It should be understood that the above instantiation hierarchy name is only an example of illustration, and the instantiation hierarchy name can also be named by other naming rules, but the naming rules need to meet the following conditions, that is, the instantiation hierarchy names of the registers with close physical positions are similar, and vice versa.

[0012] For example, the first operation unit or the searching unit can determine that the similar register has been chained on the first scan chain by the following manner: firstly, judging whether the similar register exists in the first PR netlist; then, judging whether the similar register has been on the scan chain; when both of the two judgment conditions are "yes", it can be considered that the similar register has been chained on the first scan chain.

[0013] Based on the above technical solution, the second register can be inserted into the scan chain without manually writing code scripts, and the DFT controllable signal point with consistent function logic is selected for the second register, which has less impact on the timing of the original circuit. Moreover, the method has strong universality and high efficiency, and is suitable for scenarios with a large number of newly added registers and is also suitable for engineering modification of chips under different design templates.

[0014] In combination with the first aspect, in some implementations of the first aspect, the searching unit filters out the candidate register based on the lowest instantiation level of the second register in the second SYN netlist; in the second SYN netlist, the searching unit determines that the candidate register is the similar register when the candidate register satisfies at least one of the following conditions:

[0015] the candidate register is directly connected with the newly added register, or

[0016] a buffer is arranged between the candidate register and the newly added register, or

[0017] a pair of inverters is arranged between the candidate register and the newly added register.

[0018] Based on the above technical solution, it can be ensured that the searched similar register has consistent function logic with the second register, so as to ensure that the second register newly added to the first scan chain still satisfies the DFT controllability.

[0019] In combination with the first aspect, in some implementations of the first aspect, the apparatus further comprises a first processing unit, when the searching unit searches a plurality of similar registers in the second SYN netlist, the first processing unit matches the instantiation level names of the plurality of similar registers with the instantiation level name of the second register respectively, the instantiation level name is composed of letters and numbers; the first operation unit corresponds and connects the port for DFT of the second register with the port for DFT of the similar register which has been chained on the first scan chain and has the highest matching degree.

[0020] For example, the first processing unit can further match the instantiation hierarchy names of the plurality of similar registers respectively with the instantiation hierarchy name of the second register, and sort the plurality of similar registers in descending order according to the matching degrees.

[0021] For example, the first processing unit can further sort the instantiation hierarchy names of the similar registers and the second register according to texts, and the closer the similar register is to the second register in the queue, the higher the matching degree of the similar register and the second register is. It should be understood that the higher the matching degree is, the more consistent the similar register is with the second register in the control logic, and the more the digital circuit measurability after the insertion of the second register is guaranteed, that is, the port for DFT of the second register after the insertion is still controllable by the original DFT circuit.

[0022] Based on the above technical solutions, the most suitable similar register for being connected with the second register can be selected from the plurality of similar registers, which guarantees that the port for DFT of the second register can be controlled by the logic function signal source of the original circuit, and the change to the original circuit is small, and the original function logic of the original circuit is not affected.

[0023] In combination with the first aspect, in some implementations of the first aspect, when the first search processing result is that no similar register that has been chained to the first scan chain is searched, the searching unit expands the search range of the first search processing, and continues to search for the similar register until the similar register that has been chained to the first scan chain is searched.

[0024] Based on the above technical solutions, the second register can find the DFT controllable point, so as to guarantee that the second register can be inserted into the first scan chain, and the logic function port of the second register is DFT controllable in the digital circuit.

[0025] In combination with the first aspect, in some implementations of the first aspect, the searching unit searches for the similar register based on the last level of the second register in the second SYN netlist.

[0026] For example, the last level of the second register in the second SYN netlist can be considered as the second last level of the second register in the instantiation hierarchy. However, if no similar register that has been chained to the first scan chain is searched in the above operation, the searching unit can continue to search for the similar register based on the third last level of the second register in the instantiation hierarchy in the second SYN netlist, and so on.

[0027] Based on the technical solution, the search range is expanded layer by layer, the most similar register that matches the second register is searched as finely as possible, and the second register can find the DFT controllable point, so that the second register can be inserted into the first scan chain, the logic function port of the second register can be controlled in the digital circuit, and the impact on the original circuit is minimized.

[0028] With reference to the first aspect, in some implementations of the first aspect, the port for DFT includes a clock CLK port, a scan enable SE port, and a reset RST port.

[0029] With reference to the first aspect, in some implementations of the first aspect, the apparatus further includes a second processing unit and a second operation unit.

[0030] Before the search unit determines the instantiation level of the second register, the second processing unit determines at least one second register, groups the at least one second register according to the CLK source information to which the second register belongs, and sorts the second registers in the same group according to the instantiation level of the second register.

[0031] For example, the CLK source information can be identification information of the CLK source, such as CLK1, CLK2, etc., and the CLK source information to which the second register belongs indicates which CLK source the CLK control signal port of the second register receives. Therefore, the grouping of the at least one second register can be to divide the at least one second register into at least one group of second registers, and the CLK source information of the second registers in each group is the same, for example, CLK1 or CLK2, etc.

[0032] Based on the technical solution, in the case where the number of registers in each group is relatively large, it can be basically guaranteed that the two adjacent second registers inserted into the first scan chain have the same CLK source, and the case where the CLK sources of the two adjacent second registers are different is basically avoided, so that the problem of disorder of the overall layout and wiring of the circuit after the second register is inserted can be avoided.

[0033] With reference to the first aspect, in some implementations of the first aspect, the second processing unit sorts the second registers in the same group according to the instantiation level name of the second registers in the same group, and the instantiation level name is composed of letters and numbers, and the text sorting is a sorting method based on the alphabetical order and the increasing or decreasing order of numbers.

[0034] Based on the above technical solution, by performing text sorting on the second registers in the same group, the entire second register queue is guaranteed to have adjacent two second registers as close as possible in physical position. By inserting the sorted second registers into the first scan chain, the original circuit layout and routing disorder caused by inserting the second registers can be effectively avoided.

[0035] In combination with the first aspect, in some implementations of the first aspect, the second operation unit determines at least one first scan chain, and determines a third number of each first scan chain, the third number being a number of registers that can be inserted into the first scan chain; and the second operation unit inserts the second registers after grouping and sorting into the first scan chain with the largest third number in sequence first.

[0036] For example, after determining the third number of the at least one first scan chain, the at least one first scan chain can be sorted in descending order according to the third number, and the first scan chain with the largest third number is arranged in the first place, the first scan chain with the second largest third number is arranged in the second place, and so on. Based on this, the second registers after grouping and sorting can be inserted into the specified first scan chain in the order of the first scan chain.

[0037] For example, the second registers after grouping and sorting can also be stored in a list of registers to be chained, and then the third number of each first scan chain is determined in the order of the first scan chain obtained by the above sorting method, and then the third number of second registers is cut from the list of registers to be chained and inserted into the corresponding first scan chain, until the number of second registers in the list of registers to be chained is 0.

[0038] Based on the above technical solution, it can be basically guaranteed that adjacent two second registers inserted into the first scan chain have the same CLK source, and the situation that multiple pairs of adjacent two second registers have different CLK sources basically does not occur, thereby avoiding the problem of overall circuit layout and routing disorder caused by inserting the second registers.

[0039] In combination with the first aspect, in some implementations of the first aspect, the second operation unit determines a first number of each first scan chain, the first number being a number of first registers included in the first scan chain, the first register being a register originally in the first scan chain; the second operation unit determines a maximum first number in the at least one first scan chain as a second number; and the second operation unit determines a third number according to a difference between the second number and the first number.

[0040] In some implementations of the first aspect, the second operation unit determines a first number of each first scan chain, the first number being a number of first registers included in the first scan chain; the second operation unit determines a fourth number, the fourth number being a maximum scan chain length declared by a user; and the second operation unit determines a third number according to a difference between the fourth number and the first number.

[0041] For example, when the user does not declare the maximum scan chain length in advance, the maximum value in the first numbers of the first scan chains can be taken as the maximum scan chain length declared by the user. For example, the first numbers of the first scan chains are 100, 120, 150, and 180 respectively, and the second number can be determined as 180. Then, the second number is subtracted from the first numbers respectively to obtain the following third numbers: 80, 60, 30, and 0 respectively. When the second registers are inserted, the second registers are first inserted into the first scan chain with the third number of 80, and then the remaining second registers are inserted into the first scan chain with the third number of 60, and so on. It can be seen that the first scan chain with the largest third number is the scan chain with the shortest length in all the first scan chains, and the first scan chain with the smallest third number is the scan chain with the longest length in all the first scan chains, and the third number of the first scan chain is 0.

[0042] In some implementations of the first aspect, the second operation unit inserts the second registers after grouping and sorting from the tail of the first scan chain.

[0043] Based on the above technical solution, the second registers are inserted at the tail of the first scan chain, which can effectively avoid the influence of the second registers on the original test function logic of the first scan chain.

[0044] In the second aspect, a method for engineering modification is provided. The method includes: performing first search processing to search for a similar register in a lowest level of instantiation hierarchy in which a second register is located based on a second synthesized SYN netlist, wherein the second register is a register that needs to be newly added to a first scan chain, the first scan chain is a scan chain inserted in a design for testability (DFT) circuit included in a first SYN netlist, the second SYN netlist is a modified first SYN netlist, and the similar register is a register with consistent function logic as the second register; and when the first search processing result is that the similar register is searched and chained in the first scan chain, connecting a port for DFT of the second register with a port for DFT of the similar register in the first scan chain.

[0045] Based on the above technical scheme, the second register can be inserted into the scan chain, and a DFT controllable signal point with consistent function logic is selected for the second register, which has less impact on the timing of the original circuit. Moreover, the method has strong universality, high efficiency, and is suitable for scenarios with a large number of newly added registers, and is also suitable for engineering modification of chips under different design templates.

[0046] In combination with the second aspect, in some implementations of the second aspect, the candidate register is filtered out based on the lowest level in the instantiation hierarchy in which the second register is located in the second synthesized SYN netlist; and in the second SYN netlist, the candidate register is determined as the similar register when the candidate register satisfies at least one of the following conditions:

[0047] the candidate register is directly connected with the newly added register, or

[0048] a buffer is arranged between the candidate register and the newly added register, or

[0049] a pair of inverters is arranged between the candidate register and the newly added register.

[0050] Based on the above technical scheme, it can be ensured that the searched similar register has consistent function logic with the second register, so as to ensure that the second register newly added to the first scan chain still meets the DFT controllability.

[0051] In combination with the second aspect, in some implementations of the second aspect, when a plurality of similar registers are searched in the second SYN netlist, the instantiation hierarchy names of the plurality of similar registers are respectively matched with the instantiation hierarchy name of the second register, the instantiation hierarchy name being composed of letters and numbers; and the port for DFT of the second register is correspondingly connected with the port for DFT of the similar register with the highest matching degree which has been chained in the first scan chain.

[0052] For example, the instantiation hierarchy names of the plurality of similar registers can also be respectively matched with the instantiation hierarchy name of the second register, and the plurality of similar registers can be sorted in descending order according to the matching degrees; and then it is confirmed in sequence whether the sorted similar registers have been chained in the first scan chain, and the port for DFT of the second register is correspondingly connected with the port for DFT of the similar register which is first confirmed to have been chained in the first scan chain.

[0053] Based on the above technical scheme, the most suitable similar register for being connected with the second register can be selected from the plurality of similar registers, which ensures that the port for DFT of the second register can be controlled by the logic function signal source of the original circuit, and has less impact on the original circuit and does not affect the original function logic of the original circuit.

[0054] With reference to the second aspect, in some implementations of the second aspect, when the first search processing result is that the similar register chained to the first scan chain is not found, the search range of the first search processing is expanded, and the search for the similar register is continued until the similar register chained to the first scan chain is found.

[0055] Based on the above technical solution, the second register can find the DFT controllable point, so as to ensure that the second register can be inserted into the first scan chain and realize that the logical function port of the second register is DFT controllable in the digital circuit.

[0056] With reference to the second aspect, in some implementations of the second aspect, the similar register is searched based on the last level of the instantiation hierarchy of the second register in the second SYN netlist.

[0057] Based on the above technical solution, the similar register most matched with the second register is searched as finely as possible by expanding the search range layer by layer, so as to ensure that the second register can find the DFT controllable point, so as to ensure that the second register can be inserted into the first scan chain and realize that the logical function port of the second register is DFT controllable in the digital circuit, and the impact on the original circuit is reduced as much as possible.

[0058] With reference to the second aspect, in some implementations of the second aspect, the port for DFT includes: a clock CLK port, a scan enable SE port, and a reset RST port.

[0059] With reference to the second aspect, in some implementations of the second aspect, before the instantiation hierarchy of the second register is determined, at least one second register is determined; the at least one second register is grouped according to the CLK source information to which the second register belongs, and the second registers in the same group are sorted according to the instantiation hierarchy of the second register; and the second registers after grouping and sorting are inserted into the first scan chain in sequence.

[0060] Based on the above technical solution, in the case that the number of registers in each group is relatively large, it can be basically ensured that the two adjacent second registers inserted into the first scan chain have the same CLK source, and the case that the CLK sources of the two adjacent second registers in each pair are different basically does not occur, so that the problem of disorder of the overall layout and wiring of the circuit after the second register is inserted can be avoided.

[0061] With reference to the second aspect, in some implementations of the second aspect, the second registers in the same group are textually sorted according to the instantiation hierarchy name of the second registers in the same group, the instantiation hierarchy name is composed of letters and numbers, and the textual sorting is a sorting manner based on the alphabetical order and the increasing or decreasing order of numbers.

[0062] Based on the above technical scheme, by performing text sorting on the second registers in the same group, the entire second register queue is guaranteed to have adjacent two second registers as close as possible in physical position, so that the sorted second registers are inserted into the first scan chain, which can effectively avoid the situation of circuit layout and wiring disorder caused by inserting the second registers.

[0063] In combination with the second aspect, in some implementations of the second aspect, at least one first scan chain is determined, and a third number of each first scan chain is determined, the third number being the number of registers that can be inserted into the first scan chain; and the second registers after grouping and sorting are inserted into the current first scan chain with the largest third number in sequence first.

[0064] Based on the above technical scheme, it can be basically guaranteed that adjacent two second registers inserted into the first scan chain have the same CLK source, and the situation that multiple pairs of adjacent two second registers have different CLK sources basically does not occur, thereby avoiding the problem of circuit overall layout and wiring disorder caused by inserting the second registers.

[0065] In combination with the second aspect, in some implementations of the second aspect, a first number of each first scan chain is determined, the first number being the number of first registers included in the first scan chain, the first register being a register originally in the first scan chain; a largest first number in at least one first scan chain is determined as a second number; and a third number is determined according to the difference between the second number and the first number.

[0066] In combination with the second aspect, in some implementations of the second aspect, a first number of each first scan chain is determined, the first number being the number of first registers included in the first scan chain; a fourth number is determined, the fourth number being a maximum scan chain length declared by a user; and a third number is determined according to the difference between the fourth number and the first number.

[0067] In combination with the second aspect, in some implementations of the second aspect, the second registers after grouping and sorting are inserted in sequence from the tail of the first scan chain.

[0068] Based on the above technical scheme, inserting the second registers at the tail of the first scan chain can effectively avoid the influence of the second registers on the original test function logic of the first scan chain.

[0069] The third aspect provides an apparatus for engineering modification, including a memory for storing computer instructions; and a processor for executing the computer instructions stored in the memory to enable the apparatus to perform the method in any one of the possible implementation manners of the method design of the second aspect.

[0070] In a fourth aspect, a computer storage medium is provided, and the computer storage medium stores computer instructions, and the computer instructions, when executed on a computer, cause the computer to execute the method in any possible implementation manner of the method design in the second aspect.

[0071] In a fifth aspect, a chip is provided, and the chip comprises a processor configured to execute the method in any possible implementation manner of the method design in the second aspect.

[0072] In a sixth aspect, a computer program product is provided, and the computer program code or instructions, when executed on a computer, cause the computer to execute the method in any possible implementation manner of the method design in the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0073] Figure 1 FIG. 1 is a flow diagram of a chip design provided by an embodiment of the present application.

[0074] Figure 2 FIG. 2 is a flow diagram of a method of modifying a PR netlist provided by an embodiment of the present application.

[0075] Figure 3 FIG. 3 is a flow diagram of a method of engineering modification provided by an embodiment of the present application.

[0076] Figure 4 FIG. 4 is a schematic block diagram of an engineering modification device 400 provided by an embodiment of the present application.

[0077] Figure 5 FIG. 5 is a DFT controllable point connection diagram of a second register RST port provided by an embodiment of the present application.

[0078] Figure 6 FIG. 6 is a schematic block diagram of an engineering modification device 600 provided by an embodiment of the present application.

[0079] Figure 7 FIG. 7 is a schematic block diagram of an engineering modification device 700 provided by an embodiment of the present application.

[0080] Figure 8 FIG. 8 is a flow diagram of a method of engineering modification provided by an embodiment of the present application.

[0081] Figure 9 FIG. 9 is a flow diagram of a method of engineering modification provided by an embodiment of the present application.

[0082] Figure 10 FIG. 10 is a schematic diagram of engineering modification device internal signaling interaction provided by an embodiment of the present application. DETAILED DESCRIPTION

[0083] The technical solutions in the embodiments of the present application will be described below with reference to the drawings.

[0084] Figure 1 A flowchart of a chip design provided by an embodiment of the present application is shown.

[0085] In the process of chip design, a chip engineer first needs to program the product function logic through code, and write RTL code.

[0086] Then, the chip engineer uses electronic design automation (EDA) software to convert the RTL code into a SYN netlist.

[0087] In order to test and screen the final produced physical chip, the chip engineer needs to insert a testability circuit into the synthesized netlist to obtain a DFT netlist.

[0088] Finally, the chip engineer performs layout and routing on the DFT netlist to obtain a PR netlist.

[0089] Among them, the scan chain circuit accounts for a large proportion in the entire testability circuit. The scan chain is formed by connecting the register scan channel head to tail by the chip engineer through the above-mentioned electronic design automation software, and is connected to the input or output port of the chip. Among them, the above-mentioned register can be a register including a D flip-flop.

[0090] In the above-mentioned test and screening process, the test excitation signal needs to be input to the chip inside through the scan chain, and the chip response is triggered, and then the register state information representing the chip response signal at this time is transmitted to the test machine through the scan chain. The test machine completes the test and screening based on the register state information and the screening standard.

[0091] However, for example, in the later stage of chip design, the chip engineer finds that the original chip design is wrong, or needs to add new functions to the chip. In this case, the PR netlist usually needs to be modified directly, and the modification process is as follows:

[0092] Figure 2 A flowchart of modifying the PR netlist provided by an embodiment of the present application is shown.

[0093] Firstly, the chip engineer needs to modify the original RTL code to determine the newly added functional elements or modify the errors of the original chip design, and obtains a new RTL code.

[0094] Then, similar to the above-mentioned chip design process, the chip engineer needs to use electronic design automation software to synthesize based on the new RTL code to obtain a new SYN netlist.

[0095] Since there are some elements between the original PR netlist and the new PR netlist expected to be designed, in order to ensure that the new PR netlist still has testability, a corresponding register needs to be added in the scan chain corresponding to the original PR netlist. Since the scan chain is part of the original DFT netlist, in this way, the testability of the new PR netlist can be ensured. The process is the key step of modifying the PR netlist, and the process can also be referred to as engineering change order (ECO).

[0096] Finally, the new SYN netlist and the new PR netlist are compared for consistency. If the consistency judgment condition is met, the ECO is completed; if the consistency judgment condition is not met, further fine-tuning test needs to be performed on the circuit. The consistency refers to that the circuit function of the new PR netlist is consistent with the expected function of the corresponding circuit of the new SYN netlist.

[0097] However, at the present stage, when the ECO work is carried out in the chip design delivery process, the operation of inserting the new register into the original scan chain still depends on the manual code script written by engineers. However, due to the great difference between different chip designs, the script written does not have universality, and the efficiency of manually writing the script is low. When the number of newly added registers reaches thousands, it is basically difficult to achieve the method of manually writing code script to complete the insertion of the scan chain.

[0098] In view of this, the embodiment of the application provides an engineering modification device and method. Through a corresponding logic function unit, the insertion position, insertion order and functionally consistent DFT controllable signal point of the newly added register are determined according to the instantiation level of the register and the correlation of the register in the chip physical position. Thus, the problem of low efficiency and poor universality of manually writing code script to complete the engineering modification can be solved.

[0099] Figure 3 A method design idea schematic diagram of engineering modification is shown. The embodiment of the application is based on the basic idea in Figure 3 and proposes a method of engineering modification.

[0100] In some possible embodiments, the instantiation level of the register can be represented by an instantiation level name. The registers with similar instantiation level names should be in similar instantiation levels, and the physical positions of the registers in the digital circuit should also be similar.

[0101] In some possible embodiments, the instantiation hierarchy name of the above-mentioned register can be understood as the physical location identification information of the register in the DFT circuit. For example, for a functional module A, the functional module A is divided into a first sub-module at level 1, a first sub-module at level 2, and the like, wherein the first sub-module at level 1 further includes a second sub-module 1 at the next level, a second sub-module 2, and the like, and the first sub-modules at the same level as the first sub-module at level 2 are the same. The instantiation hierarchy can be understood as information capable of representing the level of the register. Based on this, the instantiation hierarchy name of the register can be in the following form:

[0102] A1.1.1.1; A1.1.1.2; A1.1.2.1; A1.1.2.2; A1.2.1.1; A1.2.1.2; and the like. The combination of letters and numbers can represent the specific physical location of the specified register in the DFT circuit, or can be understood as the specific level of the register in the DFT circuit, or can be understood as the specific path capable of tracking the specified register in the DFT circuit. Of course, in order to distinguish different registers under the same hierarchy name, the register id capable of uniquely identifying the register can also be carried after the instantiation hierarchy name, for example: A1.1.1.1-register id(001), A1.1.2.1-register id(002), and the like. For the instantiation hierarchies of these two registers, only the second last level is different, therefore, the physical locations of the two registers should be close to each other. Further, the digital circuit further includes a register: A1.1.1.2-register id(003), compared with the register 002, the instantiation hierarchy of the register 003 and the register 001 only differs in the last level, therefore, it can be known that the physical location of the register 003 and the register 001 is closer.

[0103] Then, the registers with close physical locations basically have the same clock / scan enable / reset (CLK / SE / RST) source, and have almost consistent path transmission delay. Moreover, the CLK / SE / RST sources in the original PR netlist are controllable by the DFT circuit. When the registers with close physical locations are connected in series on the same scan chain, the path delay of the scan chain is small, thereby facilitating the timing convergence of the scan chain.

[0104] It should be understood that the above-mentioned instantiation hierarchy name is only an exemplary description, and the instantiation hierarchy name can also be named by other naming rules, but the naming rules need to meet the following conditions, that is, the instantiation hierarchy names of the registers with close physical locations are similar, and vice versa.

[0105] In some possible embodiments, in the process of digital circuit design, in order to avoid the layout and routing after adding the new register from conflicting with the layout and routing of the original scan chain, the newly added registers can be as concentrated as possible in one or more scan chains, so as to prevent the layout and routing from being disordered and even causing line conflicts due to the dispersed deployment of the newly added registers in too many scan chains.

[0106] In some possible embodiments, in the process of digital circuit design, the newly added register is usually added at the end of the scan chain. If the register is added at a certain position in the middle of the scan chain, the newly added register can affect the functional logic of the original scan chain, for example, breaking the timing of the original scan chain register. However, the newly added register at the end of the chain does not have this problem.

[0107] Based on the above description, it can be known that inserting the newly added register into the specified scan chain and ensuring that the newly added register is controllable by the signal source such as CLK / SE / RST at the position of the original scan chain after the newly added register is inserted into the scan chain is crucial for engineering modification.

[0108] Figure 4 An apparatus 400 for engineering modification is shown in the embodiment of the application.

[0109] The apparatus 400 includes a searching unit 410 and a first operation unit 420. The searching unit 410 performs a first search process to search for a similar register based on the lowest level in which a second register is located in a second instantiation hierarchy in a second SYN netlist. The second register is a register that needs to be added to a first scan chain, the first scan chain is a scan chain included in a design for test (DFT) circuit inserted in a first SYN netlist, the second SYN netlist is a modified first SYN netlist, and the similar register is a register with consistent functional logic as the second register.

[0110] When the first search process result is that the similar register is searched and chained in the first scan chain, the first operation unit 420 connects the port for DFT of the second register to the port for DFT of the similar register in the first scan chain.

[0111] In some possible embodiments, the first scan chain described above can be the original scan chain proposed in the above embodiment, that is, the scan chain included in the original PR netlist.

[0112] It should be understood that the second register is added in the first scan chain because the first PR netlist in which the first scan chain is located has some errors or needs to add some functions. The first PR netlist can be the original PR netlist proposed in the above embodiments, and the first PR netlist can be a netlist obtained based on the first DFT netlist after layout and routing; the first DFT netlist can be the original DFT netlist proposed in the above embodiments, and the first DFT netlist is a netlist obtained after inserting the DFT circuit in the first SYN netlist; and the first SYN netlist is a netlist obtained after synthesizing the original RTL code.

[0113] In some possible embodiments, the instantiation level of the second register can be represented by the instantiation level name of the second register. The instantiation level name is composed of letters and numbers, and since the instantiation level name is named according to the specified naming rule, the instantiation level names of the two registers are similar, and the two registers are close in physical position.

[0114] In some possible embodiments, since the second SYN netlist is the modified first SYN netlist, that is, the corresponding function logic is added or modified on the basis of the functions to be implemented by the first SYN netlist. Therefore, the second register needs to be added to the first scan chain of the first PR netlist corresponding to the first SYN netlist, and it is ensured that the added second register still satisfies the DFT controllability.

[0115] It should be understood that when the similar register searched is already chained in the first scan chain, that is, the similar register originally exists in the first scan chain, the second register can be connected with the similar register at this time to implement the existing first scan chain circuit based on the second register. This is a prerequisite for the second register to satisfy the DFT controllability. In some possible embodiments, whether the similar register is already chained in the first scan chain can be judged by the first operation unit 420 or the search unit 410, and the specific operation is as follows:

[0116] First, it is judged whether the similar register exists in the first PR netlist;

[0117] Then, it is judged whether the similar register is already on the scan chain;

[0118] When both of the two judgment conditions are "yes", it can be considered that the similar register is already chained in the first scan chain.

[0119] Based on the above technical solution, the second register can be inserted into the scan chain without manually writing a code script, and the DFT controllable signal point with consistent function logic is selected for the second register, which has less impact on the timing of the original circuit. Moreover, the method has strong universality and high efficiency, and is suitable for scenarios where a large number of registers are added, and is also suitable for engineering modification of chips under different design templates.

[0120] In order to ensure that the newly added second register still satisfies the DFT controllability, it is necessary to ensure that the searched similar register is consistent with the functional logic of the second register. In some possible embodiments, the functional logic consistency between the screened similar register and the second register can be ensured in the following manner:

[0121] The searching unit 410 screens the candidate register based on the lowest level in the instantiation hierarchy of the second register in the second SYN netlist. In the second SYN netlist, the searching unit 410 determines that the candidate register is a similar register when the candidate register satisfies at least one of the following conditions:

[0122] The candidate register is directly connected to the newly added register, or

[0123] A buffer is arranged between the candidate register and the newly added register, or

[0124] A pair of inverters is arranged between the candidate register and the newly added register.

[0125] For example, if the candidate register is directly connected to the newly added register, it indicates that the functional logic of the two is consistent. Otherwise, if the two are directly connected, it will cause the DFT uncontrollability of the functional logic of at least one register. If a buffer is arranged between the candidate register and the newly added register, it indicates that the functional logic of the two is consistent. Because the buffer does not modify the excitation signal, the arrangement of the buffer between the two is equivalent to that the two are directly connected. Similarly, if a pair of inverters is arranged between the candidate register and the newly added register, it indicates that the functional logic of the two is consistent. Because the pair of inverters does not modify the excitation signal, the arrangement of the pair of inverters between the two is equivalent to that the two are directly connected.

[0126] In some possible embodiments, if a buffer and a pair of inverters are arranged between the candidate register and the newly added register, it is known from the above description that the two are also equivalent to being directly connected.

[0127] Based on the above technical solution, it can be ensured that the searched similar register is consistent with the functional logic of the second register, so that the second register newly added to the first scan chain still satisfies the DFT controllability.

[0128] In some possible embodiments, when the searching unit 410 searches for the similar register, the first indication information is generated and sent to the first operation unit 420. The first indication information is used to instruct the first operation unit 410 to perform subsequent judgment on whether the similar register is serially connected to the first scan chain and the corresponding subsequent operation.

[0129] In some possible implementations, since the similar registers searched by the searching unit in the second SYN netlist can be multiple, and there can also be multiple similar registers that have been chained in the first scan chain, these similar registers can all be registers connected with the second register, but not necessarily all the most suitable.

[0130] In view of this, the device 400 described above can further include a first processing unit 430 cooperating with the first operation unit 420 described above, which can select the similar registers in the following manner to achieve that the layout of the overall digital circuit after connecting the second register is not disordered and the DFT is controllable:

[0131] The first processing unit 430 described above matches the instantiation hierarchy names of the multiple similar registers respectively with the instantiation hierarchy name of the second register, which is composed of letters and numbers;

[0132] The first operation unit 420 described above corresponds and connects the port for DFT of the second register with the port for DFT of the similar register that has the highest matching degree and has been chained in the first scan chain.

[0133] In some possible embodiments, the first processing unit 430 described above can further match the instantiation hierarchy names of the multiple similar registers respectively with the instantiation hierarchy name of the second register, and sort the multiple similar registers in descending order according to the matching degrees. The first operation unit 420 can then confirm in sequence whether the similar registers sorted have been chained in the first scan chain, and correspond and connect the port for DFT of the second register with the port for DFT of the similar register that is first confirmed to have been chained in the first scan chain.

[0134] In some possible implementations, the first processing unit 420 described above can sort the instantiation hierarchy names of the similar registers and the second register according to the text, and the closer the similar register is to the second register in the queue, the higher the matching degree of the two. It should be understood that the higher the matching degree, the more consistent the similar register and the second register are in the control logic, and the more it can guarantee the digital circuit testability after inserting the second register, that is, guarantee that the port for DFT of the second register can still be controlled by the original DFT circuit after being inserted.

[0135] In some possible embodiments, the first operation unit 420 generates second indication information after searching for the multiple similar registers, and sends the second indication information to the first processing unit 430, where the second indication information is used to instruct the first processing unit 430 to match the multiple similar registers searched for with the instantiation hierarchy name of the second register. When the first processing unit 430 completes the matching for the multiple similar registers, the first processing unit 430 generates third indication information and sends the third indication information to the first operation unit 420, where the third indication information is used to instruct the first operation unit 420 to correspondingly connect the port for DFT of the second register with the port for DFT of the similar register with the highest matching degree that has been serially chained to the first scan chain.

[0136] The following is a detailed description of connecting the RST port of the second register with the RST port of the similar register as an example.

[0137] Figure 5 A DFT controllable point connection diagram of the RST port of the second register is shown.

[0138] The search unit 410 determines the multiple similar registers based on the search range as follows, where the instantiation hierarchy name of each similar register is as follows:

[0139] A1.1.1.2-Register 001;

[0140] A1.1.2.2-Register 002;

[0141] A1.1.1.4-Register 003;

[0142] A1.1.1.3-Register 004;

[0143] The instantiation hierarchy name of the second register is A1.1.1.1-Register 005.

[0144] After the text sorting, the following queue can be obtained:

[0145] A1.1.1.1-Register 005; A1.1.1.2-Register 001; A1.1.1.3-Register 004; A1.1.1.4-Register 003; A1.1.2.2-Register 002;

[0146] As can be seen, the matching degree of Register 001 with Register 005 is the highest, so Register 001 is arranged at the first position in the queue except for Register 005.

[0147] Then, the similar registers are sequentially determined whether they have been serially chained to the first scan chain according to the above order.

[0148] After judging that the register 001 is not chained in the first scan chain, the register 005 cannot be connected with the register 001, and then the register 004 is judged. After judging that the register 004 is not chained in the first scan chain, the register 005 cannot be connected with the register 004, and then the register 003 is judged. After judging that the register 003 is chained in the first scan chain, the RST port of the register 005 needs to be connected with the RST port of the register 003 in the connection mode as shown in the following figure, and then the RST port DFT of the register 005 is controlled. Figure 5

[0149] Similarly, the SE port and the CLK port of the second register can also be connected with the corresponding ports of the similar register determined by the above method.

[0150] Based on the above technical solution, the most suitable similar register for being connected with the second register can be selected from the multiple similar registers, so that the port of the second register for DFT can be controlled by the logic function signal source of the original circuit, and the change of the original circuit is small, and the original function logic of the original circuit is not affected.

[0151] In some possible embodiments, when the first search processing result is that no similar register chained in the first scan chain is searched, the search unit 410 can expand the search range of the first search processing, and continue to search for the similar register until the similar register chained in the first scan chain is searched. The search unit 410 can expand the search range in the following manner.

[0152] Based on the last level of the lowest level of the instantiation hierarchy in which the second register is located in the second SYN netlist, the similar register is searched.

[0153] In some possible embodiments, the last level of the lowest level of the instantiation hierarchy in which the second register is located in the second SYN netlist can be considered as the second last level of the instantiation hierarchy in which the second register is located. However, if the similar register chained in the first scan chain is not searched in the above operation, the similar register can be further searched based on the third last level of the instantiation hierarchy in which the second register is located in the second SYN netlist, and so on.

[0154] Based on the above technical solution, the second register can find the DFT controllable point, so that the second register can be inserted into the first scan chain, and the logic function port of the second register is DFT controllable in the digital circuit.

[0155] ​Through the above embodiment, the control signal link between the second register and the first scan chain can be connected, and the DFT controllability of CLK / SE / RST of the second register inserted into the first scan chain is guaranteed. However, in addition, the data link between the second register and the first scan chain needs to be connected, so as to realize the data transmission function between the second register and the first scan chain.

[0156] Figure 6 A schematic block diagram of another engineering modified device 600 is shown.

[0157] The device 600 includes a second processing unit 610 and a second operation unit 620. Before the search unit 410 determines the instantiation level of the second register, the second processing unit 610 determines at least one second register, groups the at least one second register according to the CLK source information to which the second register belongs, and sorts the second registers in the same group according to the instantiation level of the second register.

[0158] In some possible embodiments, the CLK source information can be identification information of the CLK source, such as CLK1, CLK2, etc., and the CLK source information to which the second register belongs indicates which CLK source the CLK control signal port of the second register is used to receive. Therefore, the grouping of the at least one second register can be to divide the at least one second register into at least one group of second registers, and the CLK source information of the second registers in each group is the same, for example, CLK1 or CLK2, etc.

[0159] Based on the above technical solution, in the case that the number of registers in each group is relatively large, it can be basically guaranteed that the two adjacent second registers inserted into the first scan chain have the same CLK source, effectively reducing the case that the CLK sources of the two adjacent second registers are different, thereby avoiding the problem of disorder of the overall circuit layout after the second register is inserted.

[0160] In some possible embodiments, the second processing unit 610 can perform text sorting on the second registers in the same group according to the instantiation level name of the second registers in the same group. The instantiation level name is composed of letters and numbers, and the text sorting is a sorting method based on the order of the alphabet and the increasing or decreasing order of the numbers. Since the instantiation level name is named according to the specified naming rule, the two adjacent second registers after the text sorting are close in physical position.

[0161] For example, the instantiation level names of the second registers in a group are as follows:

[0162] A1.1.3.1; B1.1.3.1; A1.1.2.2; A1.1.2.1; B1.1.1.1; A2.1.1.1;

[0163] The arrangement order of the second registers after the above sorting operation is as follows:

[0164] A1.1.2.1; A1.1.2.2; A1.1.3.1; A2.1.1.1; B1.1.1.1; B1.1.3.1;

[0165] The second registers after the above sorting have the following characteristics:

[0166] The physical positions of the adjacent two second registers in the queue in the digital circuit are close.

[0167] For example, the instantiation level name of the second register to be inserted is A1.2.3.4.5.6, and it can be seen that the lowest level in the instantiation level name is the level where "6" is located.

[0168] In addition, the second operation unit 620 inserts the second registers after grouping and sorting into the first scan chain in sequence.

[0169] In some possible embodiments, after the second processing unit 610 completes grouping and sorting of the plurality of second registers, fourth indication information can be generated and sent to the second operation unit 620, the fourth indication information being used to instruct the second operation unit 620 to insert the second registers after grouping and sorting into the first scan chain in sequence.

[0170] In some possible embodiments, since the second registers are divided into groups, the second operation unit 620 can insert the second registers into the first scan chain by grouping insertion.

[0171] For example, the process of inserting the second registers into the first scan chain by grouping can be as follows:

[0172] First, a group of second registers with clock source information CLK1 are inserted into the first scan chain;

[0173] Then, a group of second registers with clock source information CLK2 are inserted into the first scan chain;

[0174] Then, a group of second registers with clock source information CLK3 are inserted into the first scan chain;

[0175] And so on, which will not be described again.

[0176] Based on the above technical solution, the process of inserting the second register into the first scan chain can be realized. Then the data link between the newly added second register and the first scan chain of the first PR netlist is opened, thereby realizing the function of data transmission.

[0177] In some possible embodiments, a plurality of first scan chains as described above can be included in the first PR netlist, and the user can declare the head and tail of the first scan chains. Before the second processing unit 610 determines the at least one second register, the plurality of first scan chains can be determined according to the user's declaration of the head and tail of the at least one first scan chain, and the chain tail can be tracked to the chain head, and then a scan chain database can be established to store the information of the first scan chains.

[0178] However, the first scan chain into which the second operation unit 620 inserts the second register is not randomly inserted. In some possible embodiments, the second register is also inserted into the first scan chain according to a specified method. If the positions of the second registers inserted into the first scan chain are relatively dispersed, this will inevitably cause the problem of disordered layout and wiring of the entire circuit, and even affect the original test function logic of the first scan chain. Therefore, it is necessary to select appropriate first scan chains for the insertion of the second registers.

[0179] In some possible embodiments, the second operation unit 620 can determine at least one first scan chain, and determine a third number of each first scan chain, the third number being the number of registers that can be inserted into the first scan chain. The second register after grouping and sorting is first inserted into the first scan chain with the largest current third number.

[0180] It should be understood that the DFT circuit included in the first PR netlist usually includes at least one first scan chain, and the at least one second register can be inserted into the first scan chain. However, before the second register is inserted into the first scan chain, the third number of each first scan chain needs to be determined to determine how many idle insertion spaces each first scan chain has, i.e., how many second registers can be inserted into each first scan chain. The second register after classification and sorting is first inserted into the first scan chain with the largest third number, so as to as much as possible insert the second registers with the same clock source and close physical positions into one scan chain.

[0181] For example, the number of the second registers of the group of CLK1 is 20, the number of the second registers of the group of CLK2 is 15, and the maximum of the third number of the at least one first scan chain is 40. Therefore, the second registers of CLK1 can be inserted into the first scan chain with the third number of 40 in the order of the sorted second registers. After the second registers of CLK1 are inserted, the second registers of CLK2 can be inserted into the first scan chain with the third number of 40 in the order of the sorted second registers, after the last inserted second register of CLK1.

[0182] For example, the number of the second registers of the group of CLK1 is 20, the number of the second registers of the group of CLK2 is 15, and the maximum of the third number of the at least one first scan chain is 30. Therefore, the second registers of CLK1 can be inserted into the first scan chain with the third number of 30 in the order of the sorted second registers. After the second registers of CLK1 are inserted, the second registers of CLK2 can be inserted into the first scan chain with the third number of 30 in the order of the sorted second registers, after the last inserted second register of CLK1. However, when the tenth second register is inserted, the first scan chain with the maximum third number has no space left, and therefore the remaining five second registers of CLK2 can be inserted into the first scan chain with the second maximum third number. The same method can be applied to the other first scan chains.

[0183] In some possible embodiments, after the third number of the at least one first scan chain is determined, the at least one first scan chain can be sorted in descending order according to the third number, and the first scan chain with the maximum third number is sorted first, the first scan chain with the second maximum third number is sorted second, and so on. Based on this, the second registers after grouping and sorting can be inserted into the specified first scan chain in the order of the first scan chain.

[0184] In addition, the second registers after grouping and sorting can be stored in a list of registers to be chained, and then the third number of each first scan chain can be determined in the order of the first scan chain obtained by the sorting method, and then the second registers with the third number can be cut from the list of registers to be chained and inserted into the corresponding first scan chain, until the number of the second registers in the list of registers to be chained is 0.

[0185] Based on the above technical solution, it can be ensured that the two adjacent second registers inserted into the first scan chain have the same CLK source, and the situation that the CLK sources of the two adjacent second registers are different is basically avoided, thereby avoiding the problem of disorder of the overall layout and wiring of the circuit after the second registers are inserted.

[0186] In some possible embodiments, the second operation unit 620 can determine the third number of the first scan chain in the following manner:

[0187] The first number of each first scan chain is determined, the first number being the number of first registers included in the first scan chain, the first register being a register originally in the first scan chain; the maximum first number in at least one first scan chain is determined as the second number; and the third number is determined according to the difference between the second number and the first number. Alternatively,

[0188] The first number of each first scan chain is determined; the fourth number is determined, the fourth number being the maximum scan chain length declared by the user; and the third number is determined according to the difference between the fourth number and the first number.

[0189] For example, when the user declares the maximum scan chain length in advance, i.e., the fourth number, the third number can be determined directly based on the fourth number. For example, the fourth number is 200, and the first numbers of the first scan chains are 100, 120, 150, and 180 respectively. Then, the third numbers are obtained by performing difference operations between the fourth number and the first numbers respectively, i.e., 100, 80, 50, and 20. Then, when the second registers are inserted, the first scan chain with the third number of 100 is inserted first, and when the idle insertion space of 100 is full, the remaining second registers need to be inserted into the first scan chain with the third number of 80, and so on.

[0190] For example, when the user does not declare the maximum scan chain length in advance, the maximum value in the first numbers of the first scan chains can be taken as the maximum scan chain length declared by the user. For example, the first numbers of the first scan chains are 100, 120, 150, and 180 respectively, and the second number is determined as 180. Then, the third numbers are obtained by performing difference operations between the second number and the first numbers respectively, i.e., 80, 60, 30, and 0. Then, when the second registers are inserted, the first scan chain with the third number of 80 is inserted first, and when the idle insertion space of 80 is full, the remaining second registers need to be inserted into the first scan chain with the third number of 60, and so on. It can be known that the first scan chain with the largest third number is the scan chain with the shortest length among all the first scan chains, and the first scan chain with the smallest third number is the scan chain with the longest length among all the first scan chains, and the third number of the first scan chain is 0.

[0191] In some possible embodiments, whether the maximum value in the second quantity is determined or the fourth quantity is determined, the purpose is to determine a reference value which can be used as a basis for determining the slack space of the first scan chain. The determination of the reference value is not limited to the above two schemes, and can also be determined by other reasonable schemes. For example, the maximum value in the first quantity of the first scan chain is weighted as the reference value, or the maximum value in the first quantity of the first scan chain is directly taken as the reference value, and the embodiments of the present application are not limited thereto.

[0192] The method modified through the above process can realize the insertion of the second register into the first scan chain. Through the process, the data link between the newly added second register and the first scan chain of the first PR netlist can be connected, so that the function of data transmission is realized.

[0193] After the second operation unit 620 determines the first scan chain with the maximum current third quantity, the second register grouped and sorted can be inserted into the tail of the first scan chain in sequence.

[0194] Based on the above technical scheme, the second register is inserted into the tail of the first scan chain, which can effectively avoid the influence of the second register on the original test function logic of the first scan chain.

[0195] In some possible embodiments, the device 400 and the device 600 can be two independent devices, or can be a device in which the logical function units included in the device 400 and the device 600 are integrated, as shown in the schematic block diagram of the device 700 modified through the engineering provided by the embodiments of the present application. Figure 7

[0196] In some possible embodiments, after the second operation unit 620 connects the data link between the plurality of second registers and the first scan chain, fifth indication information can be generated and sent to the searching unit 410 of the device 400, and the fifth indication information is used to instruct the searching unit 410 to search for the similar register, so that the inserted second register realizes DFT controllability.

[0197] In addition, based on the device 400, the device 600 and the device 700 provided by the above embodiments, the embodiments of the present application further provide an engineering modification method. The method aims to insert the newly added second register into the first scan chain and connect the data link between the two.

[0198] Figure 8 A flowchart of the method modified through the engineering provided by the embodiments of the present application is shown.

[0199] ​S810: determining at least one second register.

[0200] S820: grouping the at least one second register according to CLK source information to which the second register belongs.

[0201] S830: sorting the second registers in the same group according to instantiation levels of the second registers.

[0202] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the process of grouping and sorting the at least one second register can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0203] S840: sequentially inserting the second registers after grouping and sorting into the first scan chain.

[0204] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific process of inserting the second registers into the first scan chain can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0205] Based on the foregoing technical solution, the process of inserting the second registers into the first scan chain can be realized. Then the data link between the newly added second registers and the first scan chain of the first PR netlist is opened, so as to realize the function of data transmission.

[0206] In addition, the present application embodiment proposes another engineering modification method, which aims to open the logical function link between the second registers inserted into the first scan chain and the existing first scan chain circuit.

[0207] Figure 9 A flowchart of another engineering modification method proposed by the present application embodiment is shown.

[0208] S910: performing first search processing to search for a similar register based on the lowest level in the instantiation level of the second register in the second synthesized SYN netlist.

[0209] Wherein, the second register is a register that needs to be newly added to the first scan chain, the first scan chain is a scan chain inserted in the design for testability (DFT) circuit included in the first SYN netlist, the second SYN netlist is the modified first SYN netlist, and the similar register is a register with the same function logic as the second register.

[0210] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the process of searching for a similar register can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0211] S920: When the first search processing result is that a similar register chained in the first scan chain is searched, the port for DFT of the second register is connected to the port for DFT of the similar register in the first scan chain.

[0212] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the process of how to determine that the similar register is chained in the first scan chain can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0213] Based on the above technical solutions, the second register can be inserted into the scan chain without manually writing code scripts, and the DFT controllable signal point with consistent function logic is selected for the second register. The method has strong universality, high efficiency, and is suitable for scenarios with a large number of newly added registers, and is also suitable for chips under different design templates.

[0214] In some possible embodiments, the above engineering modification method proposed by the embodiments of the present application can be applied to the engineering modification device proposed by the embodiments of the present application. The above method steps S810 to S840 can be applied to the above device 400 or device 700, and the above method steps S910 and S920 can be applied to the above device 600 or device 700. Moreover, after each functional logic unit in the device completes the corresponding step, it can instruct other designated functional logic units to execute the corresponding step through the indication information.

[0215] Figure 10 A schematic diagram of internal signaling interaction of an engineering modification device proposed by the embodiments of the present application is shown.

[0216] In some possible embodiments, after the above second processing unit 610 completes steps S810 to S830, fourth indication information can be generated and sent to the above second operation unit 620. The fourth indication information is used to instruct the second operation unit 620 to insert the second register after grouping and sorting into the first scan chain in sequence.

[0217] After the above second operation unit 620 receives the fourth indication information and executes S840, fifth indication information can be generated and sent to the search unit 410 of the above device 400 after execution. The fifth indication information is used to instruct the search unit 410 to search for the similar register, so that the inserted second register can be controlled by DFT.

[0218] After the fifth indication information is received by the searching unit 410 and S910 is performed, the first indication information is generated and sent to the first operation unit 420, which is used to instruct the first operation unit 410 to make a subsequent judgment on whether the similar register has been connected in series in the first scan chain and the corresponding subsequent operation.

[0219] After the first indication information is received by the first operation unit 410, S920 can be directly performed.

[0220] Alternatively, the second indication information is generated and sent to the first processing unit 430, which is used to instruct the first processing unit 430 to match the instantiation hierarchy name of the second register with the searched similar registers. When the first processing unit 430 completes the matching for the similar registers, the third indication information is generated and sent to the first operation unit 420, which is used to instruct the first operation unit 420 to correspondingly connect the port for DFT of the second register with the port for DFT of the similar register with the highest matching degree which has been connected in series in the first scan chain.

[0221] Alternatively, after S910 is performed by the searching unit 410, the sixth indication information is directly generated and sent to the first processing unit 430, which is used to instruct the first processing unit 430 to match the instantiation hierarchy name of the second register with the searched similar registers. When the first processing unit 430 completes the matching for the similar registers, the third indication information is generated and sent to the first operation unit 420, which is used to instruct the first operation unit 420 to correspondingly connect the port for DFT of the second register with the port for DFT of the similar register with the highest matching degree which has been connected in series in the first scan chain.

[0222] Those skilled in the art can understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0223] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0224] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. The division of the units is merely logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0225] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0226] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can be a physically separate unit, or two or more units can be integrated into one unit.

[0227] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0228] The above is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An engineering modified device, characterized by, The device comprises: a searching unit and a first operating unit; the searching unit performs a first search process to search for a similar register in a lowest instantiation level of a second register in a second SYN netlist, the second register being a register needed to be added to a first scan chain, the first scan chain being a scan chain inserted in a design-for-test (DFT) circuit included in a first SYN netlist, the second SYN netlist being the first SYN netlist after modification, the similar register being a register having consistent function logic with the second register; when the first search process result is that the similar register is searched in the first scan chain, the first operating unit connects a port for DFT of the second register and a port for DFT of the similar register in the first scan chain.

2. The apparatus of claim 1, wherein, the searching unit performing the first search process comprises: the searching unit filters out a candidate register based on the lowest instantiation level of the second register in the second SYN netlist; the searching unit determines the candidate register as the similar register when the candidate register satisfies at least one of the following conditions in the second SYN netlist: the candidate register is directly connected with the added register, or a buffer is arranged between the candidate register and the added register, or a pair of inverters is arranged between the candidate register and the added register.

3. The apparatus of claim 1 or 2, wherein, the device further comprises a first processing unit when the searching unit searches for a plurality of similar registers in the second SYN netlist, the first processing unit matches instantiation level names of the plurality of similar registers with an instantiation level name of the second register respectively, the instantiation level name being composed of letters and numbers; the first operating unit connects the port for DFT of the second register and the port for DFT of the similar register having the highest matching degree and being chained in the first scan chain.

4. The apparatus of claim 1 or 2, wherein, when the first search process result is that the similar register is not searched in the first scan chain, the searching unit expands a search range of the first search process to continue searching for the similar register until the similar register is searched in the first scan chain.

5. The apparatus of claim 4, wherein, the searching unit expanding the search range of the first search process comprises: the searching unit searches for the similar register based on a previous level of the lowest instantiation level of the second register in the second SYN netlist.

6. The apparatus of claim 1 or 2, wherein, the port for DFT comprises a clock (CLK) port, a scan enable (SE) port and a reset (RST) port.

7. The apparatus of claim 1 or 2, wherein, the device further comprises a second processing unit and a second operating unit; the second processing unit determines at least one of the second registers before the searching unit determines the instantiation level of the second register; the second processing unit groups the at least one of the second registers according to CLK source information to which the second registers belong, and sorts the second registers in the same group according to the instantiation level of the second registers. The second operation unit inserts the second register, after being grouped and sorted, into the first scan chain in sequence.

8. The apparatus of claim 7, wherein, The step of sorting the second registers in the same group according to the instantiation level of the second register includes: The second processing unit performs text sorting on the second registers in the same group according to the instantiation hierarchy name of the second register in the same group. The instantiation hierarchy name consists of letters and numbers, and the text sorting is based on alphabetical order and ascending or descending numerical order.

9. The apparatus of claim 7, wherein, The second operation unit inserts the second register, after being grouped and sorted, into the first scan chain sequentially, including: The second operation unit determines at least one of the first scan chains and determines a third quantity for each of the first scan chains, the third quantity being the number of registers into which the first scan chain can be inserted; The second operation unit inserts the second register, after being grouped and sorted, into the first scan chain with the largest current third quantity.

10. The apparatus of claim 9, wherein, The determination of the third number for each of the first scan chains includes: The second operation unit determines a first quantity for each of the first scan chains, the first quantity being the number of first registers included in the first scan chain, and the first registers being the original registers in the first scan chain; The second operation unit determines the largest of the first quantities in at least one of the first scan chains as the second quantity; The second operation unit determines the third quantity based on the difference between the second quantity and the first quantity.

11. The apparatus of claim 9, wherein, The determination of the third number for each of the first scan chains includes: The second operation unit determines a first number for each of the first scan chains, the first number being the number of first registers included in the first scan chain; The second operation unit determines a fourth quantity, which is the maximum scan chain length declared by the user; The second operation unit determines the third quantity based on the difference between the fourth quantity and the first quantity.

12. The apparatus of claim 7, wherein, The second operation unit further includes inserting the second register, after being grouped and sorted, into the first scan chain in sequence: The second operation unit is inserted sequentially into the second register after the grouping and sorting from the end of the first scan chain.

13. A method of engineering modification, characterized by, include: A first search process is performed to search for similar registers based on the lowest level of the instantiation level of the second register in the second SYN netlist. The second register is a register that needs to be added to the first scan chain. The first scan chain is the scan chain included in the design for testability (DFT) circuit inserted into the first SYN netlist. The second SYN netlist is the modified first SYN netlist. The similar register is a register whose functional logic is consistent with that of the second register. When the first search result is that a similar register already linked in the first scan chain is found, the port of the second register used for DFT is connected to the port of the similar register used for DFT in the first scan chain.

14. The method of claim 13, wherein, The first search process includes: filtering out a candidate register based on a lowest instantiation level of a second register in the second SYN netlist; determining the candidate register as the similar register when the candidate register meets at least one of the following conditions in the second SYN netlist: the candidate register is directly connected with the new register, or a buffer is arranged between the candidate register and the new register, or a pair of inverters is arranged between the candidate register and the new register.

15. The method according to claim 13 or 14, characterized in that, when a plurality of similar registers are searched in the second SYN netlist, the method further comprises: matching instantiation level names of the plurality of similar registers with an instantiation level name of the second register respectively, the instantiation level name being composed of letters and numbers; correspondingly connecting a port for DFT of the second register with a port for DFT of the similar register which is highest in matching degree and has been concatenated in the first scan chain.

16. The method according to claim 13 or 14, characterized in that when the first search processing result is that the similar register which has been concatenated in the first scan chain is not searched, enlarging a search range of the first search processing and continuing to search the similar register until the similar register which has been concatenated in the first scan chain is searched.

17. The method of claim 16, wherein, the enlarging of the search range of the first search processing comprises: searching the similar register based on a previous level of the lowest instantiation level of the second register in the second SYN netlist.

18. The method of claim 13 or 14, wherein, the port for DFT comprises a clock CLK port, a scan enable SE port and a reset RST port.

19. An engineered modified device, characterized in that, comprises: a memory for storing computer instructions; a processor for executing the computer instructions stored in the memory, so that the apparatus executes the method in any one of claims 13 to 18.

20. A computer storage medium, comprising, the computer storage medium stores computer instructions, and the instructions, when executed on a computer, cause the computer to execute the method in any one of claims 13 to 18.

21. A chip, characterized by comprises a processor for executing the method in any one of claims 13 to 18.

22. A computer program product, characterised in that, the computer program code or instructions, when executed on a computer, cause the computer to execute the method in any one of claims 13 to 18.

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