A method and system for calibrating the safe operation domain of power semiconductor devices during their life cycle

Abstract

The present invention discloses a method and system for calibrating the life cycle safe operation domain of a power semiconductor device. The method includes: S1: constructing an initial safe operation domain; S2: constructing a quantitative assessment model for the aging degree of the power semiconductor device to obtain the cumulative damage growth based on actual operation data; S3: establishing a relationship between the thermal resistance between the chip and the housing and the cumulative damage; S4: establishing a quantitative relationship between aging-sensitive parameters and the safe operation boundary of the power semiconductor device based on the quantitative assessment model for the aging degree of the power semiconductor device, obtaining a safe operation boundary degradation model, and solving to obtain a degraded safety boundary; S5: constructing the life cycle safe operation domain of the power semiconductor device based on the degraded safety boundary and the non-degraded safety boundary obtained from the initial safe operation domain. The present invention solves the problem of the lack of a quantitative method for the life cycle safe operation domain in the prior art, and has the advantages of accurate model results, efficient modeling steps, and a wide range of application scenarios.

Description

Technical Field

[0001] The present invention belongs to the field of reliability analysis of power semiconductor devices, and in particular relates to a method and system for calibrating the safe operation domain of a power semiconductor device during its life cycle. Background Art

[0002] Power semiconductor devices, core components of modern power electronic equipment, are widely used in renewable energy power generation, transmission and distribution grids, and motor drive systems. A survey of electronic component manufacturers and practitioners in the power industry, including aerospace, automation, motor drive, and State Grid, revealed that failures related to power semiconductors account for over half of all failures in power electronic equipment. As core components in large-capacity power electronic equipment, power semiconductors are also the most vulnerable. Therefore, their long-term operational capability must be a key consideration in equipment design to enhance reliability.

[0003] Existing research on the reliability of power semiconductor devices primarily focuses on failure mechanism analysis, lifespan assessment, and health status monitoring. Commonly used empirical models and recognized reliability assessment procedures have been established. Research has shown that aging failures in power semiconductor devices can include various types, including bond wire detachment, solder fatigue, gate oxide degradation, bond wire root fracture, and aluminum metallization reconstruction. The first two types are the most prevalent, with the root cause being thermomechanical strain between materials caused by load fluctuations. Both bond wire detachment and solder fatigue can significantly alter the electrothermal parameters of power semiconductor devices, such as the collector-emitter on-state voltage and chip-case thermal resistance. Based on actual failure data, researchers have defined aging failure criteria for power semiconductor devices, using a 10% increase in collector-emitter on-state voltage and a 20% increase in chip-case thermal resistance as indicators of bond wire detachment and solder fatigue, respectively. With the continuous improvement of packaging technology, studies have shown that the fatigue failure standard of the solder layer often occurs earlier than the collector-emitter conduction voltage, and the chip-case thermal resistance has gradually been recognized as a sensitive parameter for measuring the degree of aging.

[0004] In industrial applications, it is found that in addition to long-term aging failures, short-term sudden failures also account for a large proportion, including transient overvoltage, transient overcurrent, and transient over-junction temperature. In order to make the selection process of power semiconductor devices more convenient and the results more reliable, it is necessary to characterize the electrothermal stress of power semiconductor devices as a basis. A commonly used method is to characterize the safe operating range of power semiconductor devices from the two dimensions of voltage and current. Operating conditions outside this range will cause sudden failure. However, changes in the electrothermal parameters of power semiconductor devices after long-term operation will change the safe operating conditions, which in turn makes it more likely to cause sudden failure of power semiconductor devices. The existing safe operating domain describes the safe operating conditions of power semiconductor devices before use, and lacks a quantitative description of the contraction of the safe operating domain after long-term operation. It is impossible to ensure that the operating state is within the safe operating range during long-term operation. Summary of the Invention

[0005] In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a method and system for calibrating the safe operating domain of a power semiconductor device during its life cycle, which solves the problems existing in the prior art, such as the lack of a quantitative description of the impact of device aging on the safe operating domain, the failure to consider changes in the safe operating boundary during long-term service when selecting devices, and the lack of a scientific method for selecting the selection margin corresponding to device aging.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a method for calibrating the safe operation domain of a power semiconductor device during its life cycle, comprising:

[0008] S1: Construct the initial safe operation domain based on the initial parameters of the power semiconductor devices;

[0009] S2: Based on the actual operating conditions of power semiconductor devices, a quantitative assessment model for the aging degree of power semiconductor devices is constructed. When the cumulative damage reaches the aging failure standard, the cumulative damage growth based on actual operating data is obtained;

[0010] S3: Describe the degradation process of aging-sensitive parameters with aging based on initial parameters and actual operating conditions, and establish the relationship between chip-case thermal resistance and cumulative damage;

[0011] S4: Based on the cumulative damage growth of actual operating data, the relationship between the chip-case thermal resistance and the cumulative damage, and on the basis of the quantitative assessment model of the aging degree of power semiconductor devices, a quantitative relationship between aging-sensitive parameters and the safe operating boundary of power semiconductor devices is established. The safe operating boundary degradation model is obtained and the degradation safety boundary is solved.

[0012] S5: Constructing a life cycle safety operation domain according to the degraded safety boundary and the non-degraded safety boundary obtained from the initial safety operation domain.

[0013] As a further improvement of the present invention, the initial safe operating domain is represented as a closed area consisting of four boundaries in a three-dimensional space characterized by three parameters: collector-emitter voltage, collector current and casing temperature, wherein the two dimensions of voltage and current are represented by logarithmic coordinates; the four boundaries of the initial safe operating domain are the maximum voltage boundary, the maximum current boundary, the maximum power loss boundary and the casing temperature range boundary, which are represented as corresponding planes of the three-dimensional space; in the initial safe operating domain, the operating state corresponding to the points within all boundaries is a safe operating state, and the operating state corresponding to the points outside any boundary is an operating state that causes sudden failure of the power semiconductor device.

[0014] As a further improvement of the present invention, the life cycle safe operation domain is represented as a closed area consisting of four boundaries in a three-dimensional space characterized by three parameters: collector-emitter voltage, collector current, and case temperature. Its mathematical expression is:

[0015]

[0016] Among them, the first row of expressions corresponds to the maximum voltage boundary, V CES(BR) is the breakdown voltage; the second row of expressions corresponds to the maximum current boundary, I chip(max) is the maximum on-state current constrained by the chip and bonding wires, T j(max) is the maximum junction temperature, T c is the case temperature, V CE(sat) With junction temperature T j The associated collector-emitter conduction saturation voltage, R th(jc) is the thermal resistance between junction and case; the third row of expressions corresponds to the maximum power loss boundary, Z th(jc) is the transient thermal impedance between junction and case, D is the cumulative damage of power semiconductor devices, F (D) is the growth rate of thermal resistance between junction and shell, and D There is a mapping relationship; the fourth line expression corresponds to the shell temperature range boundary, T a is the ambient temperature.

[0017] As a further improvement of the present invention, the process of describing the degradation of aging-sensitive parameters with aging degree is to use cumulative damage to quantify the aging degree of the device, and use the thermal resistance growth rate between the junction and the shell as the aging-sensitive parameter to establish the relationship between the safe operating domain and the aging degree.

[0018] As a further improvement of the present invention, the mapping relationship between the thermal resistance growth rate and the cumulative damage between the junctions and crusts satisfies the following formula:

[0019]

[0020] Where, F (D) is the growth rate of thermal resistance between junctions and shells, D For cumulative damage, η is the growth rate of thermal resistance between junctions and shells when the preset aging failure standard is reached, A 0 and β is the coefficient to be fitted in the formula.

[0021] As a further improvement of the present invention, a quantitative evaluation model for the aging degree of power semiconductor devices is constructed, including:

[0022] S21, input the actual operating condition data of the power semiconductor device, including the on-state current, blocking voltage and case temperature within a mission cycle;

[0023] S22, constructing a power loss and junction temperature coupled iterative model of power semiconductor devices to calculate the power loss and junction temperature of the power semiconductor devices during a task cycle;

[0024] S23, extract the thermal stress statistical information of the power semiconductor device, and use the rain flow counting method to count the number of junction temperature cycles of the power semiconductor device within the task cycle n , and each junction temperature cycle condition, including the amplitude of the junction temperature cycle ΔT j and average T jm ;

[0025] S24, build the life model of power semiconductor devices through accelerated aging experiments, establish the number of junction temperature cycles before failure and the ΔT j 、 T jm The relationship between the defined fixed junction temperature cycling conditions;

[0026] S25, constructing a cumulative damage calculation model for power semiconductor devices, calculating the cumulative damage of the power semiconductor devices within a task cycle, which is the linear superposition of the damage caused by each junction temperature cycle within the task cycle;

[0027] S26, repeating the above S21 to S25 until the cumulative damage of the power semiconductor device reaches a preset value; constructing a quantitative evaluation model for the aging degree of the power semiconductor device.

[0028] As a further improvement of the present invention, the life model of the power semiconductor device is:

[0029]

[0030] Where, N f is the number of cycles before failure under this thermal stress condition, A and b is the coefficient fitted according to the accelerated aging test results, E a is the aging activation energy, k b is the Boltzmann constant;

[0031] The cumulative damage calculation model is:

[0032]

[0033] in, D Represents the cumulative damage of power semiconductor devices, N f,i For the i The number of cycles before failure under the thermal stress condition of a junction temperature cycle is represented by the reciprocal of the number of cycles before failure. i damage caused by a junction temperature cycle.

[0034] As a further improvement of the present invention, the relationship between the thermal resistance between the chip and the housing and the cumulative damage is established, including:

[0035] S31, discretize the expected service conditions and construct a set of discrete expected service conditions M ;

[0036] S32, construct a finite element analysis model of power semiconductor devices considering the coupling of solid heat transfer and solid mechanics;

[0037] S33, input working condition set M In one of the working conditions, the finite element analysis model is used to calculate the number of junction temperature cycles that each part of the solder layer can withstand before failure;

[0038] S34, discretize the number of junction temperature cycles that each location can withstand before failure, and determine the discretization accuracy of the number of cycles N Δ , obtain several solder layer failure cycle isosurfaces;

[0039] S35, dividing the aging stages according to the isosurfaces of the number of failure cycles of the solder layer, sequentially treating the areas enclosed by each isosurface as fatigue failures and removing the solder in the areas, thereby obtaining solder layer models at different aging stages;

[0040] S36, based on the solder layer model at different aging stages, uses the finite element analysis model to calculate the chip-to-case thermal resistance at different aging stages;

[0041] S37, based on the calculation results, obtain the mapping relationship between the thermal resistance growth rate between the chip and the housing and the cumulative damage:

[0042]

[0043] Where, F (D) is the growth rate of thermal resistance between junctions and shells, D For cumulative damage, η is the growth rate of thermal resistance between junctions and shells when the preset aging failure standard is reached, A 0 and β is the coefficient to be fitted in the formula, N f is the number of cycles when the thermal resistance between chip and housing reaches the failure standard, N is the actual number of cycles;

[0044] S38, repeat the above S33 to S37 until M The formula fitting coefficients are obtained for all working conditions.

[0045] As a further improvement of the present invention, the expected service conditions are discretized to construct a discrete expected service condition set. M ,include:

[0046] S311: From the amplitude of the junction temperature cycle ( ΔT j ) and the mean value ( T jm ) two dimensions to determine the expected service range of power semiconductor devices, and extract the maximum and minimum values of the junction temperature cycle amplitude and average value respectively ( ΔT j(max) , ΔT j(min) , T jm(max) , T jm(min) );

[0047] S312: Determine the discretization accuracy of the expected service conditions, including the discretization interval of the junction temperature cycle amplitude m ΔT and the discretization interval of the average value of the junction temperature cycle mTm ;

[0048] S313: Constructing a Discrete Set of Expected Service Conditions M ;

[0049]

[0050] Where, ΔT j(max) , ΔT j(min) Extract the maximum and minimum values of the junction temperature cycle amplitude respectively, T jm(max) , T jm(min) Extract the maximum and minimum values of the junction temperature cycle amplitude and average value respectively.

[0051] A second aspect of the present invention provides a system for calibrating a safe operating domain of a power semiconductor device during its life cycle, comprising:

[0052] An initial model building module is used to build an initial safe operation domain based on the initial parameters of the power semiconductor device;

[0053] An evaluation model construction module is used to construct a quantitative evaluation model for the aging degree of power semiconductor devices based on the actual operating conditions of power semiconductor devices. When the cumulative damage reaches the aging failure standard, the cumulative damage growth based on actual operating data is obtained;

[0054] The aging relationship establishment module is used to describe the degradation process of aging-sensitive parameters with aging degree based on initial parameters and actual operating conditions, and establish the relationship between the thermal resistance between chip and housing and the cumulative damage;

[0055] The degradation model construction module is used to establish a quantitative relationship between aging-sensitive parameters and the safe operating boundary of power semiconductor devices based on the cumulative damage growth of actual operating data, the relationship between the thermal resistance between the chip and the housing, and the cumulative damage. This is based on the quantitative assessment model of the aging degree of power semiconductor devices, and the safe operating boundary degradation model is obtained. The degradation safety boundary is solved.

[0056] The safe operation domain construction module is used to construct a life cycle safe operation domain based on the degraded safety boundary and the non-degraded safety boundary obtained from the initial safe operation domain.

[0057] Compared with the prior art, the present invention has the following beneficial effects:

[0058] The life cycle safe operation domain calibration method of the present invention first establishes an initial three-dimensional safe operation domain based on the initial parameters of the device; then, through precise electrothermal analysis and life assessment based on accelerated aging experiments, a quantitative assessment model for the aging degree of power semiconductor devices is constructed to obtain the cumulative damage growth based on actual operation data; then, through finite element analysis considering solid heat transfer and solid mechanics, the relationship between the thermal resistance between the chip and the housing and the cumulative damage is established; finally, by establishing a quantitative relationship between aging sensitive parameters and the safe operation boundary of the power semiconductor device, the device life cycle safe operation domain is constructed. The method disclosed by the present invention takes into account the actual operating conditions and thermal resistance degradation process, conducts a quantitative assessment of the aging degree of the power semiconductor device and obtains the shrinkage characteristics of the safe operation domain, providing a reference for the selection of margins considering the long-term service of the device.

[0059] The life cycle safe operation domain of the present invention quantitatively describes the characteristics of power semiconductor devices, such as the reduction of safe operating state and shrinkage of safe operating domain after long-term operation. It also depicts the mutual coupling between the safe operating boundaries of voltage, current and temperature of the device throughout its life cycle, as well as the process of change with package aging. This makes it easier to judge whether the electrical and thermal stresses of the device are within the safe operating range during long-term service, and proposes a more scientific method to guide its selection. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings, in which:

[0061] Figure 1 A flow chart of a method for calibrating the safe operation domain of a power semiconductor device during its life cycle provided by the present invention;

[0062] Figure 2 The safe operation domain of the IGBT module life cycle calibrated by the present invention;

[0063] Figure 3 This is a flow chart of the calibration method for the safe operation domain of the life cycle of the IGBT module of the present invention;

[0064] Figure 4 The initial safe operation domain of the IGBT module calibrated by the present invention;

[0065] Figure 5 The actual operating conditions of the IGBT module of the present invention during a duty cycle, where (a) is the transmission power and (b) is the ambient temperature;

[0066] Figure 6 Calculation results of power loss and junction temperature of the IGBT module of the present invention, where (a) is power loss and (b) is junction temperature;

[0067] Figure 7 The junction temperature rain flow counting statistical result of the IGBT module of the present invention;

[0068] Figure 8 The solder layer model of the IGBT module at different aging stages of the present invention;

[0069] Figure 9 The relationship between the thermal resistance growth rate and the cumulative damage between the chip and the housing of the IGBT module of the present invention;

[0070] Figure 10 This is a schematic diagram of a power semiconductor device life cycle safe operation domain calibration system provided by the present invention. DETAILED DESCRIPTION

[0071] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0072] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0073] The present invention relates to the field of describing the long-time-scale safe operating conditions of power semiconductor devices, and proposes a life cycle safe operating domain and calibration method for power semiconductor devices to determine the maximum stress that power semiconductor devices can withstand during long-term service, thereby providing more scientific guidance for their selection.

[0074] like Figure 1 As shown, the first object of the present invention is to provide a method for calibrating the safe operation domain of a power semiconductor device during its life cycle, comprising:

[0075] S1: Construct the initial safe operation domain based on the initial parameters of the power semiconductor devices;

[0076] S2: Based on the actual operating conditions of power semiconductor devices, a quantitative assessment model for the aging degree of power semiconductor devices is constructed. When the cumulative damage reaches the aging failure standard, the cumulative damage growth based on actual operating data is obtained;

[0077] S3: Describe the degradation process of aging-sensitive parameters with aging based on initial parameters and actual operating conditions, and establish the relationship between chip-case thermal resistance and cumulative damage;

[0078] S4: Based on the cumulative damage growth of actual operating data, the relationship between the chip-case thermal resistance and the cumulative damage, and on the basis of the quantitative assessment model of the aging degree of power semiconductor devices, a quantitative relationship between aging-sensitive parameters and the safe operating boundary of power semiconductor devices is established. The safe operating boundary degradation model is obtained and the degradation safety boundary is solved.

[0079] S5: Constructing a life cycle safety operation domain according to the degraded safety boundary and the non-degraded safety boundary obtained from the initial safety operation domain.

[0080] The present invention provides a method for calibrating the safe operating domain of a power semiconductor device over its life cycle. The model includes four boundaries: maximum voltage, maximum current, maximum power loss, and shell temperature range, taking into account the impact of device aging. The calibration method constructs an initial safe operating domain, obtains cumulative damage based on actual operating data, establishes a relationship between the thermal resistance between the chip and the shell and the cumulative damage, and establishes a quantitative relationship between aging-sensitive parameters and safe operating boundaries, ultimately constructing a safe operating domain over the life cycle. The model and calibration method disclosed in the present invention have the advantages of accurate model results, efficient modeling steps, and a wide range of application scenarios. It quantifies the characteristics of the device's safe operating domain shrinking after long-term operation, facilitates judgment on whether the device's electrical and thermal stresses are within the safe operating range during long-term service, and proposes a more scientific method to guide its selection.

[0081] The life cycle safe operation domain provided by the present invention is represented as a closed area in a three-dimensional space characterized by three parameters: collector-emitter voltage, collector current, and case temperature, where the voltage and current dimensions are represented using logarithmic coordinates.

[0082] The life cycle safe operation domain consists of four boundaries, namely the maximum voltage boundary, the maximum current boundary, the maximum power loss boundary and the shell temperature range boundary, which are represented by the corresponding planes of the three-dimensional space. The mathematical expression is:

[0083]

[0084] Among them, the first row of expressions corresponds to the maximum voltage boundary, where V CES(BR)is the breakdown voltage, which represents the maximum voltage that the device can withstand and is almost unaffected by temperature; the second row of expressions corresponds to the maximum current boundary, where I chip(max) is the maximum on-state current constrained by the chip and bonding wires, T j(max) is the maximum junction temperature, T c is the case temperature, V CE(sat) With junction temperature T j The associated collector-emitter conduction saturation voltage, R th(jc) is the thermal resistance between junction and case; the third row of expressions corresponds to the maximum power loss boundary, where Z th(jc) is the transient thermal impedance between junction and case, D is the cumulative damage of power semiconductor devices, F (D) is the growth rate of thermal resistance between junction and shell, and D There is a mapping relationship; the fourth line expression corresponds to the shell temperature range boundary, where T a is the ambient temperature;

[0085] Specifically, the cumulative damage is used to quantify the aging degree of the device in the life cycle safe operation domain, and the growth rate of the thermal resistance between the junction and the shell is used as the aging sensitive parameter to establish the relationship between the safe operation domain and the aging degree;

[0086] Specifically, the mapping relationship between the thermal resistance growth rate between the junctions and the cumulative damage satisfies the following formula:

[0087]

[0088] Where, F (D) is the growth rate of thermal resistance between junctions and shells, D For cumulative damage, η is the growth rate of thermal resistance between junctions and shells when the preset aging failure standard is reached, A 0 and β is the coefficient to be fitted in the formula.

[0089] Specifically, in the life cycle safe operation domain, the operating state of the power semiconductor device corresponding to all points within the boundaries is a safe operating state, and the operating state of the power semiconductor device corresponding to any point outside the boundaries is an operating state that causes sudden failure of the device.

[0090] The following is combined with Figure 1 The content of each step of the present invention is described in detail:

[0091] S1: Construct the initial safe operation domain based on the initial parameters of the power semiconductor devices;

[0092] As a specific embodiment, the initial safe operation domain described in step S1 is represented as a closed area consisting of four boundaries in a three-dimensional space characterized by three parameters: collector-emitter voltage, collector current, and case temperature, wherein the voltage and current dimensions are represented by logarithmic coordinates; the four boundaries of the initial safe operation domain are the maximum voltage boundary, the maximum current boundary, the maximum power loss boundary, and the case temperature range boundary, which are represented as corresponding planes of the three-dimensional space; in the initial safe operation domain, the operating state corresponding to the points within all boundaries is a safe operating state, and the operating state corresponding to any point outside any boundary is an operating state that causes sudden failure of the power semiconductor device; the mathematical expression of the initial safe operation domain is:

[0093]

[0094] Among them, the first row of expressions corresponds to the maximum voltage boundary, where V CES(BR) is the breakdown voltage, which represents the maximum voltage that the device can withstand and is almost unaffected by temperature; the second row of expressions corresponds to the maximum current boundary, where I chip(max) is the maximum on-state current constrained by the chip and bonding wires, T j(max) is the maximum junction temperature, T c is the case temperature, V CE(sat) With junction temperature T j The associated collector-emitter conduction saturation voltage, R th(jc) is the thermal resistance between junction and case; the third row of expressions corresponds to the maximum power loss boundary, where Z th(jc) is the transient thermal impedance between junction and shell; the fourth row of expressions corresponds to the shell temperature range boundary, where T a is the ambient temperature;

[0095] S2: Build a quantitative assessment model for the aging degree of power semiconductor devices to obtain the cumulative damage growth based on actual operating data until the cumulative damage reaches the aging failure standard;

[0096] As a specific embodiment, the modeling steps of the power semiconductor device aging degree quantitative evaluation model described in step S2 include:

[0097] (1) Input the actual operating data of the power semiconductor device, including the transmission power and ambient temperature during a mission cycle;

[0098] (2) Construct a coupled iterative model of power loss and junction temperature of power semiconductor devices, as shown in the following formula, where P cond 、 P on and P off They are the conduction loss, turn-on loss and turn-off loss of power semiconductor devices respectively. f s is the switching frequency, E on and E off are the turn-on energy and turn-off energy of the device in the data sheet, V on and V off are the actual turn-on voltage and turn-off voltage of the device, V ref The reference values for the turn-on voltage and turn-off voltage of the device in the data sheet; k is the number of iteration steps;

[0099]

[0100] The power loss and junction temperature coupled iterative model of the power semiconductor device is used to calculate the power loss and junction temperature of the power semiconductor device during a duty cycle. The calculation steps are as follows:

[0101] Step 1: Input the case temperature as the initial junction temperature value and set a reasonable junction temperature iterative calculation error;

[0102] Step 2: Calculate the conduction loss, turn-on loss, and turn-off loss according to the formulas in the first three rows.

[0103] Step 3: Update the calculated junction temperature value according to the formula in the fourth row and compare it with the calculated junction temperature value in the previous step;

[0104] Step 4: Repeat steps 2 and 3 until the difference between the two junction temperature calculations is less than the set junction temperature iterative calculation error.

[0105] (3) Extract the thermal stress statistical information of power semiconductor devices and use the rain flow counting method to count the number of junction temperature cycles of power semiconductor devices during the task cycle n , and the amplitude of each junction temperature cycle ( ΔT j ) and the mean value ( T jm );

[0106] (4) The life model of power semiconductor devices is constructed through accelerated aging experiments, as shown in the following formula:

[0107]

[0108] Where, N f is the number of cycles before failure under this thermal stress condition, A and b is the coefficient fitted according to the accelerated aging test results, E a is the aging activation energy, k b is the Boltzmann constant;

[0109] (5) Construct a cumulative damage calculation model for power semiconductor devices, as shown in the following formula:

[0110]

[0111] Where, D Represents the cumulative damage of power semiconductor devices, N f,i For the i The number of cycles before failure under the thermal stress condition of a junction temperature cycle is represented by the reciprocal of the number of cycles before failure. i Damage caused by a junction temperature cycle;

[0112] The cumulative damage calculation model of the power semiconductor device is used to calculate the cumulative damage of the power semiconductor device within a task cycle, which is the linear superposition of the damage caused by each junction temperature cycle within the task cycle;

[0113] (6) Repeat (1) to (5) above until the cumulative damage of the power semiconductor device reaches 100%;

[0114] S3: Describe the degradation process of aging-sensitive parameters with aging degree, and establish the relationship between chip-case thermal resistance and cumulative damage;

[0115] As a specific embodiment, the modeling step of the relationship between the chip-housing thermal resistance and the cumulative damage described in S3 includes:

[0116] (1) Discretization is performed based on the expected service conditions. The specific steps include:

[0117] Step 1: Cycle the amplitude from the junction temperature ( ΔT j ) and the mean value ( T jm ) two dimensions to determine the expected service range of power semiconductor devices, and extract the maximum and minimum values of the junction temperature cycle amplitude and average value respectively ( ΔTj(max) , ΔT j(min) , T jm(max) , T jm(min) );

[0118] Step 2: Determine the discretization accuracy of the expected service conditions, including the discretization interval of the junction temperature cycle amplitude m ΔT and the discretization interval of the average value of the junction temperature cycle m Tm ;

[0119] Step 3: Construct a discretized set of expected service conditions M ;

[0120]

[0121] (2) Construct a finite element analysis model for power semiconductor devices that considers the coupling of solid heat transfer and solid mechanics;

[0122] (3) Input working condition set M In one of the working conditions, the finite element analysis model is used to calculate the number of junction temperature cycles that each part of the solder layer can withstand before failure;

[0123] (4) Discretize the result of step (3) and determine the discretization accuracy of the number of cycles N Δ , obtain several solder layer failure cycle isosurfaces;

[0124] (5) The aging stages are divided according to the isosurfaces of the number of failure cycles of the solder layer. The areas wrapped by each isosurface are regarded as fatigue failures and the solder in the areas is removed to obtain the solder layer models at different aging stages.

[0125] (6) The finite element analysis model is used to calculate the thermal resistance between the chip and the housing at different aging stages;

[0126] (7) According to the calculation results, fit the coefficients in the following formula A 0 and β , the mapping relationship between the thermal resistance growth rate between the chip and the housing and the cumulative damage is obtained:

[0127]

[0128] Where, F (D) is the growth rate of thermal resistance between junctions and shells, D For cumulative damage, η is the growth rate of thermal resistance between junctions and shells when the preset aging failure standard is reached, A 0 andβ is the coefficient to be fitted in the formula, N f is the number of cycles when the thermal resistance between chip and housing reaches the failure standard, N is the actual number of cycles;

[0129] (8) Repeat (3) to (7) until the M The formula fitting coefficients are obtained for all working conditions.

[0130] S4: Establish a quantitative relationship between aging-sensitive parameters and the safe operating boundaries of power semiconductor devices;

[0131] S5: Build a life cycle safe operation domain.

[0132] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the preferred embodiments are only for illustrating the present invention, and are not intended to limit the scope of protection of the present invention.

[0133] like Figure 2 As shown in the figure, the safe operation domain of the life cycle is calibrated using the Insulated Gate Bipolar Transistor (IGBT) module as an example. It is represented as a three-dimensional space characterized by three parameters: collector-emitter voltage, collector current, and case temperature. The voltage and current dimensions are represented using logarithmic coordinates.

[0134] Furthermore, the IGBT module life cycle safe operation domain consists of four boundaries, namely the maximum voltage boundary, the maximum current boundary, the maximum power loss boundary and the case temperature range boundary, which are represented as corresponding planes in the three-dimensional space, and the mathematical expression thereof is:

[0135]

[0136] Among them, the first row of expressions corresponds to the maximum voltage boundary, where V CES(BR) is the breakdown voltage, which represents the maximum voltage that the device can withstand and is almost unaffected by temperature; the second row of expressions corresponds to the maximum current boundary, where I chip(max) is the maximum on-state current constrained by the chip and bonding wires, T j(max) is the maximum junction temperature, T c is the case temperature, V CE(sat) With junction temperature T j The associated collector-emitter conduction saturation voltage, R th(jc)is the thermal resistance between junction and case; the third row of expressions corresponds to the maximum power loss boundary, where Z th(jc) is the transient thermal impedance between junction and case, D is the cumulative damage of the IGBT module, F (D) is the growth rate of thermal resistance between junction and shell, and D There is a mapping relationship; the fourth line expression corresponds to the shell temperature range boundary, where T a is the ambient temperature;

[0137] Furthermore, the IGBT module life cycle safe operation domain uses cumulative damage to quantify the aging degree of the device, and the thermal resistance growth rate between the junction and the shell is used as an aging sensitive parameter to establish the relationship between the safe operation domain and the aging degree.

[0138] Furthermore, the mapping relationship between the thermal resistance growth rate and the cumulative damage between the shells satisfies the following formula, where η is the growth rate of thermal resistance between junctions and shells when the preset aging failure standard is reached, A 0 and β is the coefficient to be fitted in the formula; in this embodiment, η Take 50%, A 0 takes 0.91, β Take 1.45;

[0139]

[0140] Furthermore, in the IGBT module life cycle safe operation domain, the operating states corresponding to points within all boundaries are safe operating states, and the operating states corresponding to points outside any boundary are operating states that may cause sudden failure of the device.

[0141] The flow chart of the calibration method of the life cycle safe operation domain of the IGBT module embodiment is as follows: Figure 3 As shown, the following steps are included:

[0142] (1) Construct the initial safe operation domain based on the initial parameters of the IGBT module;

[0143] like Figure 4As shown, the initial safe operating domain of the IGBT module is represented as a closed area consisting of four boundaries in a three-dimensional space characterized by three parameters: collector-emitter voltage, collector current, and case temperature, where the voltage and current dimensions are represented in logarithmic coordinates. The four boundaries of the initial safe operating domain of the IGBT module are the maximum voltage boundary, the maximum current boundary, the maximum power loss boundary, and the case temperature range boundary, and are represented as corresponding planes in the three-dimensional space. In the initial safe operating domain of the IGBT module, the operating state corresponding to the points within all boundaries is the safe operating state, and the operating state corresponding to any point outside any boundary is the operating state that causes sudden failure of the IGBT module. The mathematical expression of the initial safe operating domain of the IGBT module is:

[0144]

[0145] Among them, the first row of expressions corresponds to the maximum voltage boundary, where V CES(BR) is the breakdown voltage, which represents the maximum voltage that the device can withstand and is almost unaffected by temperature; the second row of expressions corresponds to the maximum current boundary, where I chip(max) is the maximum on-state current constrained by the chip and bonding wires, T j(max) is the maximum junction temperature, T c is the case temperature, V CE(sat) With junction temperature T j The associated collector-emitter conduction saturation voltage, R th(jc) is the thermal resistance between junction and case; the third row of expressions corresponds to the maximum power loss boundary, where Z th(jc) is the transient thermal impedance between junction and shell; the fourth row of expressions corresponds to the shell temperature range boundary, where T a is the ambient temperature;

[0146] (2) Construct a quantitative assessment model for the aging degree of IGBT modules to obtain the cumulative damage growth based on actual operating data until the cumulative damage reaches the aging failure standard;

[0147] 1) Input the actual operating condition data of the IGBT module, including the transmission power and ambient temperature during a task cycle, such as Figure 5 As shown;

[0148] 2) Construct an iterative model of power loss and junction temperature coupling of the IGBT module, as shown in the following equation, where P cond 、P on and P off They are the conduction loss, turn-on loss and turn-off loss of the IGBT module respectively. f s =1kHz is the switching frequency, E on and E off are the turn-on energy and turn-off energy of the device in the data sheet, V on and V off are the actual turn-on voltage and turn-off voltage of the device, V ref The reference values for the turn-on voltage and turn-off voltage of the device in the data sheet; k is the number of iteration steps;

[0149]

[0150] The power loss and junction temperature coupled iterative model of the IGBT module is used to calculate the power loss and junction temperature of the IGBT module during a duty cycle. The calculation steps are as follows:

[0151] Step 1: Input the case temperature as the initial junction temperature value and set a reasonable junction temperature iterative calculation error;

[0152] Step 2: Calculate the conduction loss, turn-on loss, and turn-off loss according to the formulas in the first three rows.

[0153] Step 3: Update the calculated junction temperature value according to the formula in the fourth row and compare it with the calculated junction temperature value in the previous step;

[0154] Step 4: Repeat steps 2 and 3 until the difference between the two junction temperature calculations is less than the set junction temperature iterative calculation error.

[0155] In this embodiment, the power loss and junction temperature calculation results of the IGBT module are as follows: Figure 6 As shown;

[0156] 3) Extract the thermal stress statistics of the IGBT module and use the rain flow counting method to count the number of junction temperature cycles of the IGBT module during the task cycle n , and the amplitude of each junction temperature cycle ( ΔT j ) and the mean value ( T jm ),like Figure 7 As shown;

[0157] 4) Construct the life model of the IGBT module as shown below, where Nf is the number of cycles before failure under this thermal stress condition, A and b is the coefficient fitted according to the accelerated aging test results, E a is the aging activation energy, k b is the Boltzmann constant; in this embodiment, the specific parameters are shown in Table 1;

[0158]

[0159] Table 1 IGBT module life model parameters

[0160]

[0161] 5) Construct the cumulative damage calculation model of the IGBT module as shown below, where D Represents the cumulative damage of the IGBT module, N f,i For the i The number of cycles before failure under the thermal stress condition of a junction temperature cycle is represented by the reciprocal of the number of cycles before failure. i Damage caused by a junction temperature cycle;

[0162]

[0163] The cumulative damage calculation model of the IGBT module is used to calculate the cumulative damage of the IGBT module within a duty cycle, which is the linear superposition of the damage caused by each junction temperature cycle within the duty cycle;

[0164] 6) Repeat 1) to 5) above until the cumulative damage of the IGBT module reaches 100%. The calculation result is as follows: Figure 8 As shown;

[0165] (3) Describe the degradation process of aging-sensitive parameters with aging degree and establish the relationship between chip-case thermal resistance and cumulative damage;

[0166] 1) Discretize the expected service conditions. The specific steps include:

[0167] Step 1: Cycle the amplitude from the junction temperature ( ΔT j ) and the mean value ( T jm ) two dimensions to determine the expected service range of the IGBT module, and extract the maximum and minimum values of the junction temperature cycle amplitude and average value respectively ( ΔT j(max) =60℃, ΔT j(min) =17℃, Tjm(max) =27℃, T jm(min) =84℃);

[0168] Step 2: Determine the discretization accuracy of the expected service conditions, including the discretization interval of the junction temperature cycle amplitude m ΔT = 5℃ and the discretization interval of the average value of the junction temperature cycle m Tm =5℃;

[0169] Step 3: Construct a discretized set of expected service conditions M ;

[0170]

[0171] 2) Construct a finite element analysis model of the IGBT module that considers the coupling of solid heat transfer and solid physics;

[0172] 3) Input working condition set M In one of the working conditions, the finite element analysis model is used to calculate the number of junction temperature cycles that each part of the solder layer can withstand before failure;

[0173] 4) Discretize the result of step 3) to determine the discretization accuracy of the number of cycles N Δ =2000, obtain the isosurfaces of the number of failure cycles of several solder layers;

[0174] 5) The aging stages are divided according to the isosurface of the solder layer failure cycles. The areas wrapped by each isosurface are regarded as fatigue failure and the solder in the area is removed to obtain the solder layer models at different aging stages, such as Figure 8 As shown;

[0175] 6) Use the finite element analysis model to calculate the chip-case thermal resistance at different aging stages;

[0176] 7) According to the calculation results, fit the coefficients in the following formula A 0 and β , the mapping relationship between the thermal resistance growth rate between the chip and the housing and the cumulative damage is obtained, where N f The number of cycles when the thermal resistance between chip and housing reaches the failure standard;

[0177]

[0178] 8) Repeat 3) to 7) until the target M The formula fitting coefficients are obtained for all working conditions.

[0179] In this embodiment, the formula fitting coefficients under all working conditions areA 0=0.91, β =1.45, the relationship between the thermal resistance growth rate between the chip and the housing and the cumulative damage is as follows Figure 9 As shown;

[0180] (4) Establish a quantitative relationship between aging-sensitive parameters and the safe operating boundary of the IGBT module, as shown in the following formula;

[0181]

[0182] (5) Construct the safe operation domain of the IGBT module life cycle, such as Figure 2 shown.

[0183] In summary, the present invention proposes a set of life cycle safe operation domains and calibration methods for power semiconductor devices, which fully considers the characteristics of device aging causing degradation of their safe operation boundaries during long-term service, solves the problems of insufficient existing models, and provides a reference for the selection of margins considering long-term service of devices.

[0184] like Figure 10 As shown, in a second aspect, the present invention provides a method system for calibrating the safe operation domain of a power semiconductor device during its life cycle, comprising:

[0185] An initial model building module is used to build an initial safe operation domain based on the initial parameters of the power semiconductor device;

[0186] An evaluation model construction module is used to construct a quantitative evaluation model for the aging degree of power semiconductor devices based on the actual operating conditions of power semiconductor devices. When the cumulative damage reaches the aging failure standard, the cumulative damage growth based on actual operating data is obtained;

[0187] The aging relationship establishment module is used to describe the degradation process of aging-sensitive parameters with aging degree based on initial parameters and actual operating conditions, and establish the relationship between the thermal resistance between chip and housing and the cumulative damage;

[0188] The degradation model construction module is used to establish a quantitative relationship between aging-sensitive parameters and the safe operating boundary of power semiconductor devices based on the cumulative damage growth of actual operating data, the relationship between the thermal resistance between the chip and the housing, and the cumulative damage. This is based on the quantitative assessment model of the aging degree of power semiconductor devices, and the safe operating boundary degradation model is obtained. The degradation safety boundary is solved.

[0189] The safe operation domain construction module is used to construct a life cycle safe operation domain based on the degraded safety boundary and the non-degraded safety boundary obtained from the initial safe operation domain.

[0190] The third object of an embodiment of the present invention is to provide an electronic device, comprising a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein the processor implements the method for calibrating the life cycle safe operation domain of the power semiconductor device when executing the computer program.

[0191] The fourth object of an embodiment of the present invention is to provide a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for calibrating the life cycle safe operation domain of the power semiconductor device is implemented.

[0192] This invention is applicable to the lifecycle safe operation domain and calibration method of power semiconductor devices of any existing packaging form under any operating conditions, including but not limited to IGBTs and power MOSFETs. Furthermore, the technical concept of this invention can be further extended to the lifecycle safe operation domain and calibration method of other key components in power electronic systems, such as electrolytic capacitors and magnetic components.

[0193] In summary, the present invention has the following advantages:

[0194] 1) Accurate model results: The failure mechanism of power semiconductor devices is fully considered, appropriate aging-sensitive parameters are selected, precise electrothermal analysis and life assessment based on accelerated aging experiments are used, and changes in internal parameters and internal stresses caused by aging are continuously updated to accurately quantify the impact of the aging process on the safe operating range of the device.

[0195] 2) Efficient modeling: By constructing a cumulative damage model, the impact of external stress changes under actual operating conditions is continuously updated, allowing for convenient quantification of the aging process of power semiconductor devices under actual operating conditions. By discretizing the gradual finite element model, the computational efficiency of the relationship between thermal resistance and cumulative damage is greatly improved while ensuring accuracy, allowing for rapid analysis of the evolution of the safe operating domain at different aging stages.

[0196] 3) Wide range of application scenarios: It is suitable for calibrating the life cycle safe operation domain of power semiconductor devices under different operating conditions (on-state current, ambient temperature, heat dissipation conditions, switching frequency, duty cycle, etc.), and is also suitable for power semiconductor devices of different power levels in any existing packaging form, including but not limited to IGBTs, power MOSFETs, etc.

[0197] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0198] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0199] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0200] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0201] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the scope of protection of the claims of the present invention.

Claims

1. A method for calibrating the safe operation domain of a power semiconductor device during its life cycle, characterized in that: include: S1: Construct the initial safe operation domain based on the initial parameters of the power semiconductor devices; S2: Based on the actual operating conditions of power semiconductor devices, a quantitative assessment model for the aging degree of power semiconductor devices is constructed. When the cumulative damage reaches the aging failure standard, the cumulative damage growth based on actual operating data is obtained; S3: Describe the degradation process of aging-sensitive parameters with aging based on initial parameters and actual operating conditions, and establish the relationship between chip-case thermal resistance and cumulative damage; S4: Based on the cumulative damage growth of actual operating data, the relationship between the chip-case thermal resistance and the cumulative damage, and on the basis of the quantitative assessment model of the aging degree of power semiconductor devices, a quantitative relationship between aging-sensitive parameters and the safe operating boundary of power semiconductor devices is established. The safe operating boundary degradation model is obtained and the degradation safety boundary is solved. S5: Constructing a life cycle safety operation domain according to the degraded safety boundary and the non-degraded safety boundary obtained from the initial safety operation domain; The initial safe operating domain is represented as a closed area consisting of four boundaries in a three-dimensional space characterized by three parameters: collector-emitter voltage, collector current, and case temperature, where the voltage and current dimensions are represented using logarithmic coordinates. The four boundaries of the initial safe operating domain are the maximum voltage boundary, the maximum current boundary, the maximum power loss boundary, and the case temperature range boundary, and are represented as corresponding planes in the three-dimensional space. In the initial safe operating domain, the operating state corresponding to points within all boundaries is a safe operating state, and the operating state corresponding to any point outside any boundary is an operating state that causes sudden failure of the power semiconductor device. Construct a quantitative assessment model for the aging degree of power semiconductor devices, including: S21, input the actual operating condition data of the power semiconductor device, including the on-state current, blocking voltage and case temperature within a mission cycle; S22, constructing a power loss and junction temperature coupled iterative model of power semiconductor devices to calculate the power loss and junction temperature of the power semiconductor devices during a task cycle; S23, extract the thermal stress statistical information of the power semiconductor device, and use the rain flow counting method to count the number of junction temperature cycles of the power semiconductor device within the task cycle n , and each junction temperature cycle condition, including the amplitude of the junction temperature cycle ΔT j and average T jm ; S24, build the life model of power semiconductor devices through accelerated aging experiments, establish the number of junction temperature cycles before failure and the ΔT j 、 T jm The relationship between the defined fixed junction temperature cycling conditions; S25, constructing a cumulative damage calculation model for power semiconductor devices, calculating the cumulative damage of the power semiconductor devices within a task cycle, which is the linear superposition of the damage caused by each junction temperature cycle within the task cycle; S26, repeating the above S21 to S25 until the cumulative damage of the power semiconductor device reaches a preset value; constructing a quantitative evaluation model for the aging degree of the power semiconductor device.

2. The method for calibrating the safe operation domain of a power semiconductor device during its life cycle according to claim 1, characterized in that: The life cycle safe operation domain is represented as a closed area consisting of four boundaries in a three-dimensional space characterized by three parameters: collector-emitter voltage, collector current, and case temperature. Its mathematical expression is: Among them, the first row of expressions corresponds to the maximum voltage boundary, V CES(BR) is the breakdown voltage; the second row of expressions corresponds to the maximum current boundary, I chip(max) is the maximum on-state current constrained by the chip and bonding wires, T j(max) is the maximum junction temperature, T c is the case temperature, V CE(sat) With junction temperature T j The associated collector-emitter conduction saturation voltage, R th(jc) is the thermal resistance between junction and case; the third row of expressions corresponds to the maximum power loss boundary, Z th(jc) is the transient thermal impedance between junction and case, D is the cumulative damage of power semiconductor devices, F (D) is the growth rate of thermal resistance between junction and shell, and D There is a mapping relationship; the fourth line expression corresponds to the shell temperature range boundary, T a is the ambient temperature.

3. The method for calibrating the safe operation domain of a power semiconductor device during its life cycle according to claim 1, characterized in that: The process of describing the degradation of aging-sensitive parameters with aging degree is to quantify the aging degree of the device by using cumulative damage, and to use the growth rate of thermal resistance between junctions and shells as the aging-sensitive parameter for establishing the relationship between the safe operating domain and the aging degree.

4. The method for calibrating the safe operation domain of a power semiconductor device during its life cycle according to claim 2, characterized in that: The mapping relationship between the thermal resistance growth rate and the cumulative damage between the junctions and shells satisfies the following formula: Where, F (D) is the growth rate of thermal resistance between junctions and shells, D For cumulative damage, η is the growth rate of thermal resistance between junctions and shells when the preset aging failure standard is reached, A 0 and β is the coefficient to be fitted in the formula.

5. The method for calibrating the safe operation domain of a power semiconductor device during its life cycle according to claim 1, characterized in that: The life model of the power semiconductor device is: Where, N f is the number of cycles before failure under this thermal stress condition, A and b is the coefficient fitted according to the accelerated aging test results, E a is the aging activation energy, k b is the Boltzmann constant; The cumulative damage calculation model is: in, D Represents the cumulative damage of power semiconductor devices, N f,i For the i The number of cycles before failure under the thermal stress condition of a junction temperature cycle is represented by the reciprocal of the number of cycles before failure. i damage caused by a junction temperature cycle.

6. The method for calibrating the safe operation domain of a power semiconductor device during its life cycle according to claim 1, characterized in that: Establish the relationship between chip-to-case thermal resistance and cumulative damage, including: S31, discretize the expected service conditions and construct a set of discrete expected service conditions M ; S32, construct a finite element analysis model of power semiconductor devices considering the coupling of solid heat transfer and solid mechanics; S33, input working condition set M In one of the working conditions, the finite element analysis model is used to calculate the number of junction temperature cycles that each part of the solder layer can withstand before failure; S34, discretize the number of junction temperature cycles that each location can withstand before failure, and determine the discretization accuracy of the number of cycles N Δ , obtain several solder layer failure cycle isosurfaces; S35, dividing the aging stages according to the isosurfaces of the number of failure cycles of the solder layer, sequentially treating the areas enclosed by each isosurface as fatigue failures and removing the solder in the areas, thereby obtaining solder layer models at different aging stages; S36, based on the solder layer model at different aging stages, uses the finite element analysis model to calculate the chip-to-case thermal resistance at different aging stages; S37, based on the calculation results, obtain the mapping relationship between the thermal resistance growth rate between the chip and the housing and the cumulative damage: Where, F (D) is the growth rate of thermal resistance between junctions and shells, D For cumulative damage, η is the growth rate of thermal resistance between junctions and shells when the preset aging failure standard is reached, A 0 and β is the coefficient to be fitted in the formula, N f is the number of cycles when the thermal resistance between chip and housing reaches the failure standard, N is the actual number of cycles; S38, repeat the above S33 to S37 until M The formula fitting coefficients are obtained for all working conditions.

7. The method for calibrating the safe operation domain of a power semiconductor device during its life cycle according to claim 6, characterized in that: Discretize the expected service conditions and construct a set of discrete expected service conditions M ,include: S311: Amplitude of the junction temperature cycle ΔT j and average T jm Two dimensions are used to determine the expected service operating range of power semiconductor devices, extracting the maximum and minimum values of the junction temperature cycle amplitude and average value respectively; S312: Determine the discretization accuracy of the expected service conditions, including the discretization interval of the junction temperature cycle amplitude m ΔT and the discretization interval of the average value of the junction temperature cycle m Tm ; S313: Constructing a Discrete Set of Expected Service Conditions M ; Where, ΔT j(max) , ΔT j(min) Extract the maximum and minimum values of the junction temperature cycle amplitude respectively, T jm(max) , T jm(min) Extract the maximum and minimum values of the junction temperature cycle amplitude and average value respectively.

8. A power semiconductor device life cycle safety operation domain calibration system, characterized by: include: An initial model building module is used to build an initial safe operation domain based on the initial parameters of the power semiconductor device; An evaluation model construction module is used to construct a quantitative evaluation model for the aging degree of power semiconductor devices based on the actual operating conditions of power semiconductor devices. When the cumulative damage reaches the aging failure standard, the cumulative damage growth based on actual operating data is obtained; The aging relationship establishment module is used to describe the degradation process of aging-sensitive parameters with aging degree based on initial parameters and actual operating conditions, and establish the relationship between the thermal resistance between chip and housing and the cumulative damage; The degradation model construction module is used to establish a quantitative relationship between aging-sensitive parameters and the safe operating boundary of power semiconductor devices based on the cumulative damage growth of actual operating data, the relationship between the thermal resistance between the chip and the housing, and the cumulative damage. This is based on the quantitative assessment model of the aging degree of power semiconductor devices, and the safe operating boundary degradation model is obtained. The degradation safety boundary is solved. The safe operation domain construction module is used to construct a life cycle safe operation domain based on the degraded safety boundary and the non-degraded safety boundary obtained from the initial safe operation domain.

Images