A packaging method for a test chip

Abstract

The present application relates to a packaging method for a test chip, and relates to the field of semiconductor packaging technology. The method includes extracting a first integrated circuit wafer and covering one side of the first integrated circuit wafer with a first dielectric layer; sputtering a first metal TiCu layer on one side of the first dielectric layer; photolithography of an image on a first mask to form a first photolithography layer on the first metal TiCu layer; electroplating a first UBM metal layer on the first photolithography layer; sequentially removing the first photolithography layer and the first metal TiCu layer to expose a first electroplated metal layer formed into a first design chip image and a first test chip image; forming a first bump on the first electroplated metal layer; and cutting the first integrated circuit wafer into individual first chips. The present application has a test chip with a special image in the design center during the packaging process, so that each test is at the same level, the test results are relatively accurate, and the judgment basis is standardized, thereby improving the efficiency of the test.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a packaging method for a test chip. Background Art

[0002] Wafer Level Packaging (WLP) is a "wafer packaging followed by cutting" method, which adopts the wafer operation mode in the integrated circuit chip manufacturing plant, that is, packaging is completed on the entire wafer and then cutting is completed to obtain a large number of finished chips at one time.

[0003] In wafer-level packaging, the quality of the first bump is primarily characterized by electrical performance, appearance, and bonding strength. Various tests are incorporated into the packaging process to verify quality. Leakage current testing, also known as leakage testing, is crucial for detecting chip open-short conditions after bump formation, effectively preventing widespread electrical failures during chip electrical performance testing.

[0004] The existing technology has the following problems: each chip has a different detection position due to different designs, but the difference in detection position will affect the detection results, resulting in test results not being reflected at the same level, and there is still room for improvement. Summary of the Invention

[0005] In order to improve the problem that different detection positions of chips may be different due to different designs, but the differences in detection positions may affect the detection results, resulting in the test results not being reflected at the same level, the present application provides a packaging method for a test chip.

[0006] In a first aspect, the present application provides a packaging method for a test chip, which adopts the following technical solution:

[0007] A packaging method for a test chip, applied to a chip without a rewiring structure, comprising:

[0008] Taking out a first integrated circuit wafer and covering a side of the first integrated circuit wafer where the first electrode is exposed with a first dielectric layer, the first integrated circuit wafer being provided with a first chip to be formed, the first chip to be formed being provided with a first electrode and a first circuit module, the first integrated circuit wafer being covered with a first passivation layer, the first passivation layer being provided with a first opening on a side away from the first integrated circuit wafer where the first electrode is exposed;

[0009] sputtering a first metal TiCu layer on a side of the first dielectric layer away from the first integrated circuit wafer;

[0010] Performing photolithography on the image on the preset first mask to form a first photolithography layer on the first metal TiCu layer, wherein the first photolithography layer includes a preset first design chip image and a first test chip image;

[0011] electroplating a first UBM metal layer on the first photoresist layer;

[0012] Sequentially removing the first photoresist layer and the first metal TiCu layer to expose the first electroplated metal layer formed into the first design chip image and the first test chip image;

[0013] forming a first bump on the first electroplated metal layer by a ball planting process or a reflow process;

[0014] After being inspected, the first integrated circuit wafer is cut into individual first chips, wherein the first chips include a design chip having a first design chip image and a first test chip having a first test chip image.

[0015] By adopting the above technical solution, a test chip with a special image in the center is designed during the packaging process, so that leakage detection can be performed on the test chip without being restricted by the chip surface graphic design. This ensures that each test is at the same level, the test results are more accurate, and the judgment basis is standardized, thereby improving the efficiency of detection.

[0016] Optionally, the first test chip image includes a first leakage test image and a first shear force test image set on different first test chips, the first shear force test image is set at the edge of the first photolithography layer, and the first test chip containing the first leakage test image is provided with contacts connected to the outside world for circuit testing and intermediate traces with the same line width and line spacing connecting the two contacts.

[0017] By adopting the above technical solution, since the leakage detection process does not interfere with the shear force detection process, leakage test images and shear force test images can be designed simultaneously in the same packaging process, thereby improving the efficiency of packaging detection.

[0018] Optionally, the first test chip image includes a first leakage test image and a first shear force test image set on the same test chip, the first shear force test image is set at the edge of the first photolithography layer, and the first test chip including the first leakage test image is provided with a first contact connected to the outside world for circuit testing and a first intermediate trace with the same line width and line spacing connecting the two first contacts.

[0019] By adopting the above technical solution, since the leakage test chip is generally not a required chip, two different detection patterns can be designed on the same chip, thereby reducing the required number of test chips as much as possible and improving the chip packaging yield.

[0020] Optionally, the first test chip provided with the first shear force test image is located on an edge line of a preset first effective range and partially exceeds the first effective range.

[0021] By adopting the above technical solution, since these chips are on the edge line of the effective range, they will generally be cut off and scrapped in the later stage. The test chip is designed at the invalid edge position to avoid the loss of effective chip yield and improve the packaging yield.

[0022] In a second aspect, the present application provides a packaging method for a test chip, which adopts the following technical solution:

[0023] A packaging method for a test chip, applied to a chip with a rewiring structure, comprising:

[0024] Taking out a second integrated circuit wafer and covering a side of the second integrated circuit wafer where the second electrode is exposed with a second dielectric layer, the second integrated circuit wafer being provided with a second chip to be formed, the second chip to be formed being provided with a second electrode and a second circuit module, the second integrated circuit wafer being covered with a second passivation layer, and a side of the second passivation layer being provided with a second opening exposing the second electrode;

[0025] sputtering a second metal TiCu layer on a side of the second dielectric layer away from the second integrated circuit wafer;

[0026] Performing photolithography on the image on the preset second mask to form a second photolithography layer on the second metal TiCu layer, wherein the second photolithography layer includes a preset second design chip image and a second test chip image, and the second test chip image includes a second leakage test image;

[0027] electroplating a redistribution layer on the second photoresist layer;

[0028] Electroplating a second UBM metal layer on the redistribution layer;

[0029] removing the second photoresist layer and the second metal TiCu layer in sequence to expose the second electroplated metal layer formed into the second design chip image and the second test chip image;

[0030] forming a second bump on the second electroplated metal layer by a ball planting process or a reflow process;

[0031] After testing, the second integrated circuit wafer is cut into single second chips, wherein the second chips include a design chip having a second design chip image and a first test chip having a second test chip image. The second test chip is provided with contacts for connecting to the outside world for circuit testing and an intermediate trace with the same line width and line spacing connecting the two contacts.

[0032] By adopting the above technical solution, a test chip with a special image in the center is designed during the packaging process, so that leakage detection can be performed on the test chip without being restricted by the chip surface graphic design. This ensures that each test is at the same level, the test results are more accurate, and the judgment basis is standardized, thereby improving the efficiency of detection.

[0033] Optionally, the following steps are further included between the step of electroplating a redistribution layer on the second photoresist layer and the step of electroplating a second UBM metal layer on the redistribution layer:

[0034] Continue coating a third dielectric layer on the redistribution layer and sputtering a third metal TiCu layer;

[0035] covering the side of the second integrated circuit wafer where the second electrode is exposed with a third dielectric layer;

[0036] sputtering a third metal TiCu layer on a side of the third dielectric layer away from the second integrated circuit wafer;

[0037] The image on the preset third mask is photolithographically processed to form a third photolithographic layer on the third metal TiCu layer, wherein the third photolithographic layer includes a preset third test chip image, and the third test chip image includes a second shear force test image.

[0038] By adopting the above technical solution, since the leakage detection process does not interfere with the shear force detection process, leakage test images and shear force test images can be designed simultaneously in the same packaging process, thereby improving the efficiency of packaging detection.

[0039] Optionally, the second leakage test image and the second shear force test image are located on the same second test chip after the step of cutting the second integrated circuit wafer into single second chips.

[0040] By adopting the above technical solution, since the leakage test chip is generally not a required chip, two different detection patterns can be designed on the same chip, thereby reducing the required number of test chips as much as possible and improving the chip packaging yield.

[0041] Optionally, a method for determining whether to continue the steps of coating a third dielectric layer and sputtering a third metal TiCu layer on the redistribution layer is further included, the method comprising:

[0042] Executing a preset leakage current detection method and obtaining a leakage current detection result;

[0043] Analyze possible causes of abnormalities based on leakage current detection results;

[0044] Find the corresponding detection plan from the preset detection database based on the possible cause of the abnormality;

[0045] Determine the exact cause of the abnormality after executing the detection plan;

[0046] Find the corresponding treatment plan from the preset treatment database based on the accurate abnormal cause;

[0047] When the processing type corresponding to the processing scheme is a preset continuous etching category, executing the processing scheme and re-obtaining the leakage current detection result;

[0048] When the leakage current detection result is a preset normal result, the steps of coating a third dielectric layer on the redistribution layer and sputtering a third metal TiCu layer are performed;

[0049] When the processing type corresponding to the processing scheme is the machine adjustment category, the processing scheme is output and the steps of coating a third dielectric layer on the redistribution layer and sputtering a third metal TiCu layer are no longer performed.

[0050] By adopting the above technical solution, when leakage detection is already possible during the packaging process, the leakage detection is started directly. If the detection result is not a problem or can be solved, the shear test step can be performed. If the detection result is a problem and cannot be solved, it means that the wafer itself has been scrapped or it takes a long time to solve. At this time, the wafer does not need to proceed to the next step and is set aside, thereby reducing the defective rate of wafer packaging.

[0051] Optionally, the method further includes a method for arranging a second test chip image on a second mask, the method comprising:

[0052] Determining optional chip positions and optional quantities, wherein the optional chip positions are positions on the second mask corresponding to the second chip to be formed that falls on an edge line of a preset second effective range and partially exceeds the second effective range;

[0053] When the selectable number is greater than the preset detection requirement number, the selectable chip position is output as a second test chip image;

[0054] When the selectable number is less than the detection required number, analyzing the second design chip image to obtain a design image number;

[0055] Find the corresponding design requirement quantity from the preset requirement database based on the design image number;

[0056] Counting the number of design image numbers, and defining the number as the actual number of designs;

[0057] When the actual design quantity is greater than the design requirement quantity, the required quantity difference is calculated based on the optional quantity and the inspection requirement quantity;

[0058] Determine the actual quantity difference based on the actual design quantity and the design requirement quantity;

[0059] When the required quantity difference is less than the actual quantity difference, the image numbers are analyzed and counted to determine the outermost image numbers and the positions of the peripheral chips;

[0060] The peripheral chip positions corresponding to the required quantity difference and the optional chip positions corresponding to the optional quantity are arbitrarily selected as the positions of the second test chip image for output.

[0061] By adopting the above technical solution, when the number of test chips on the edge line is insufficient, if there are excess design chips, testing is performed on the excess design chips to ensure the test quantity of the test chips.

[0062] Optionally, a further arrangement method of the second test chip image on the second mask is further included, the method comprising:

[0063] analyzing the second test chip image to obtain a test image number when the selectable number is less than the detection required number;

[0064] Finding corresponding equivalent replacement possibilities from a preset comparison database based on the outermost image number and the test image number;

[0065] When there is an equivalent replacement possibility greater than a preset non-influence probability, the outermost image number corresponding to the equivalent replacement possibility is defined as the equivalent design image number, and the test image number corresponding to the equivalent replacement possibility is defined as the equivalent test image number;

[0066] Performing a partial update based on a second test chip image corresponding to an identical test image number and a second design chip image corresponding to an identical design image number to obtain an updated leakage test image;

[0067] Count the number of chips corresponding to the same design image number;

[0068] Calculate the sum of the chip quantity and the optional quantity, and define the sum as the total optional quantity;

[0069] When the total number of options is less than the number required for testing, continue to search for equivalent test image numbers and update the total number of options;

[0070] When the total optional quantity is greater than the preset minimum leakage detection requirement quantity and the sum of the required quantity difference and the optional quantity is greater than the preset minimum shear force requirement quantity, the optional chip position is output as the second leakage test image, and the position on the second mask corresponding to the second design chip image corresponding to the equivalent design image number is output as the position corresponding to the updated leakage test image.

[0071] By adopting the above technical solution, when some design chips similar to the test image are updated and test chips are obtained, if the leakage test results meet the requirements without affecting the shear force test requirements, they can still be used as normal chips, saving chip costs and improving chip utilization.

[0072] In summary, this application includes at least the following beneficial technical effects:

[0073] 1. By designing a test chip with a special image in the center during the packaging process, each test is at the same level, the test results are more accurate and the judgment basis is standardized, which improves the efficiency of the test;

[0074] 2. Design leakage test images and shear force test images simultaneously in the same packaging process, improving the efficiency of packaging inspection;

[0075] 3. Design two different detection patterns on the same chip, thereby minimizing the number of test chips required and improving the chip packaging yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 This is a flow chart of a packaging method for a test chip in Example 1 of the present application.

[0077] Figure 2 This is a surface schematic diagram of the test chip in Example 1 of the present application.

[0078] Figure 3 This is a schematic diagram of the distribution of the test chips in Example 1 of the present application in the wafer.

[0079] Figure 4 This is a partially enlarged schematic diagram of the distribution of the test chips in Example 1 of the present application in the wafer.

[0080] Figure 5 This is a flow chart of a packaging method for a test chip in Example 2 of the present application.

[0081] Figure 6 This is a flow chart of a method for determining whether to continue coating a third dielectric layer and sputtering a third metal TiCu layer on the redistribution layer in Example 2 of the present application.

[0082] Figure 7 This is a flowchart of a method for arranging a second test chip image on a second mask in Example 2 of the present application.

[0083] Figure 8 This is a flowchart of a method for further arranging the second test chip image on the second mask in Example 2 of the present application. DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solutions and advantages of this application more clear, the following Figure 1-8 It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0085] Example 1

[0086] The present application embodiment discloses a packaging method for a test chip. Figure 1 , a packaging method for a test chip includes:

[0087] Step 100: Take out the first integrated circuit wafer and cover the side of the first integrated circuit wafer where the first electrode is exposed with a first dielectric layer.

[0088] A first integrated circuit wafer has a first chip to be formed, which has a first electrode and a first circuit module. The first integrated circuit wafer is covered with a first passivation layer. The purpose of passivation is to transform the metal surface into a state that is less susceptible to oxidation, thereby slowing the corrosion rate of the metal. The first passivation layer has a first opening on the side facing away from the first integrated circuit wafer, exposing the first electrode. A first dielectric layer is also covered on the side with the first opening. A dielectric layer is a material layer acting between two electrodes under equipotential conditions, primarily to prevent electrical breakdown between the electrodes.

[0089] Step 101 : sputtering a first metal TiCu layer on a side of a first dielectric layer away from a first integrated circuit wafer.

[0090] The first metal TiCu layer is an electroplating seed layer, generally composed of 1000A Ti+4000A Cu, which facilitates subsequent electroplating on the first metal TiCu layer.

[0091] Step 102: Photolithography is performed on the image on the preset first mask to form a first photolithography layer on the first metal TiCu layer.

[0092] A reticle, also known as a mask, photomask, or photolithography mask, is a graphic master used in the photolithography process in microelectronics and integrated optoelectronics manufacturing. It forms a mask pattern on a transparent substrate using an opaque light-blocking film, and the pattern is transferred to the wafer through exposure. The first photoresist layer is created by applying a glue layer to the first metal TiCu layer, then exposing and developing it through a mask. This creates an opening in the photoresist coated on the first metal TiCu layer that corresponds to the design pattern on the mask. The image on the first photoresist layer includes a first design chip image and a first test chip image. The first design chip image corresponds to the first design chip for use. The first test chip image, on the other hand, is an image of a chip used only for testing.

[0093] The first test chip image here includes a first leakage test image and a first shear force test image, and the first leakage test image and the first shear force test image are set on different first test chips. The first test chip containing the first leakage test image is provided with contacts for connecting to the outside world for circuit testing and an intermediate trace with the same line width and line spacing that connects the two contacts. In the rewiring design, each chip has a minimum line spacing and minimum line width. The minimum line width and line spacing of each chip design varies, but the process technology capability is fixed, that is, 20X20um. The size of the four contacts is not restricted and can be adjusted according to the space. The minimum line width and line spacing of the test pattern affects the leakage current test results. If they are all designed to be 20X20um, each chip will be tested at the same level. The leakage current is tested on the four contacts. The purpose of the leakage current detection is to verify whether the surface metal TiCu layer has been etched cleanly. If it is not etched cleanly, the non-conductive metal wires will conduct electricity, causing the chip to fail.

[0094] Because the chip is still intact when the leakage current test is completed, in order to reduce the number of test chips, you can also Figure 2 The illustrated setting sets the first leakage test pattern and the first shear force test pattern on the same first test chip, so as to detect different functions on the same first test chip.

[0095] Step 103 : Electroplating a first UBM metal layer on the first photoresist layer.

[0096] The first UBM metal layer is a bonding layer for interconnecting the upper and lower layers.

[0097] Step 104 : sequentially removing the first photoresist layer and the first metal TiCu layer to expose the first electroplated metal layer formed into the first design chip image and the first test chip image.

[0098] The purpose of the removal is to expose the corresponding image and the corresponding first UBM metal layer. The first electroplated metal layer is the first UBM metal layer remaining after removing the first photoresist layer and the first metal TiCu layer.

[0099] Step 105: forming a first bump on the first electroplated metal layer, wherein the forming process is a ball planting process or a reflow process.

[0100] The first bump is a contact point for connecting the electrode to the outside world.

[0101] Step 106 : After inspection, the first integrated circuit wafer is cut into individual first chips, wherein the first chips include a design chip having a first design chip image and a first test chip having a first test chip image.

[0102] The tests are leakage current test and shear force test.

[0103] The first test chip provided with the first shear force test image is located on the edge line of the first effective range and partially exceeds the first effective range. Figure 3 and Figure 4 As shown, the purpose is that the chips in this part are invalid chips themselves, and the shear force test is a destructive test. If it is performed on a valid chip, it will affect the yield of the chip. However, if the chip itself is invalid, it can ensure the chip yield and the normal shear force test.

[0104] Example 2

[0105] The present application embodiment discloses a packaging method for a test chip. Figure 5 , a packaging method for a test chip includes:

[0106] Step 200 : Taking out the second integrated circuit wafer and covering the side of the second integrated circuit wafer where the second electrode is exposed with a second dielectric layer.

[0107] The second integrated circuit wafer here is the same as the first integrated circuit wafer, except that the internal chip design has a rewiring structure.

[0108] The second integrated circuit wafer also has a second chip to be formed, which has a second electrode and a second circuit module. The second integrated circuit wafer is covered with a second passivation layer. One side of the second passivation layer has a second opening that exposes the second electrode. The method for covering the second dielectric layer is similar to step 100 and is not further described here.

[0109] Step 201 : sputtering a second metal TiCu layer on a side of the second dielectric layer away from the second integrated circuit wafer.

[0110] The method of sputtering the second metal TiCu layer is similar to step 101 and will not be described in detail here.

[0111] Step 202: Photolithography is performed on the preset image on the second mask to form a second photolithography layer on the second metal TiCu layer, wherein the second photolithography layer includes a preset second design chip image and a second test chip image, and the second test chip image includes a second leakage test image.

[0112] If only the shear force test and the leakage current test are performed here, then the second test chip image here only has the second leakage current test image. The operation of the second photolithography layer is similar to step 102 and will not be described in detail here.

[0113] Step 203: Electroplating a redistribution layer on the second photoresist layer.

[0114] The rewiring layer is used to change the position of internal circuit contacts to meet the requirements of electrical connection with external electrical devices.

[0115] Step 204: Cover the side of the second integrated circuit wafer where the second electrode is exposed with a third dielectric layer.

[0116] The purpose here is to form an image for shear force detection at the outermost end of the chip, so it is necessary to continue laying a metal TiCu layer and a third dielectric layer.

[0117] Step 205 : sputtering a third metal TiCu layer on a side of the third dielectric layer away from the second integrated circuit wafer.

[0118] The method of sputtering the third metal TiCu layer is similar to step 201 and will not be described in detail here.

[0119] Step 206: Photolithography is performed on the predetermined image on the third mask to form a third photolithography layer on the third metal TiCu layer. The third photolithography layer includes a predetermined third test chip image, and the third test chip image includes the second shear force test image.

[0120] The method for forming the third photoresist layer here is similar to step 202 and will not be repeated here. The difference is that only the second shear force test image is included here. If the etching degree of the third metal TiCu layer needs to be tested here, the second leakage test image needs to be included as well.

[0121] Step 207 : Electroplating a second UBM metal layer on the redistribution layer.

[0122] The electroplating method of the second UBM metal layer here is similar to step 103 and will not be described in detail here.

[0123] Step 208 : sequentially removing the second photoresist layer and the second metal TiCu layer to expose the second electroplated metal layer formed into the second design chip image and the second test chip image.

[0124] Step 209: forming a second bump on the second electroplated metal layer, wherein the forming process is a ball planting process or a reflow process.

[0125] Step 210: After testing, the second integrated circuit wafer is diced into individual second chips. The second chips include a design chip having the second design chip image and a first test chip having the second test chip image. The second test chip is provided with contacts for connecting to the outside world for circuit testing and an intermediate trace with the same line width and line spacing connecting the two contacts.

[0126] The second leakage test image and the second shear force test image are located on the same second test chip after the step of cutting the second integrated circuit wafer into individual second chips. This is similar to step 106 and will not be described in detail here.

[0127] Reference Figure 6 , further comprising a method for determining whether to continue the steps of coating a third dielectric layer and sputtering a third metal TiCu layer on the redistribution layer, the method comprising:

[0128] Step 300: Execute a preset leakage current detection method and obtain a leakage current detection result.

[0129] The leakage current test method measures the current on the wafer. This method uses the voltammetry method. This involves applying a 5V voltage and setting the current range to 0-100nA. Two probes are placed on the left and right antennas, respectively. A current less than 10nA is considered acceptable, while a current greater than or equal to 10nA is considered unacceptable. A failure indicates that the second metal TiCu layer has not been completely etched. The leakage current test result represents the corresponding current level.

[0130] Step 301: Analyze possible causes of abnormality based on the leakage current detection result.

[0131] Possible causes of abnormality are possible reasons for the leakage current test result. These reasons can be found by looking up a table, for example: insufficient plasma etching volume, etching process defects (short solution life, excessively fast etching rate, too short etching time), Q-time not meeting requirements, or problems with the test equipment. This table was compiled by personnel in this field based on actual conditions and their own experience.

[0132] Step 302: Find a corresponding detection solution from a preset detection database based on the possible cause of the abnormality.

[0133] A detection plan is a method for determining whether the cause of the corresponding abnormality is present. For example, insufficient plasma etching volume can be detected through surface image recognition, while a problem with the test machine can be detected using on-machine detection equipment. For example, temperature can be measured using a thermometer, while light intensity can be measured using a brightness meter. A database stores a mapping between possible abnormality causes and detection plans, which are then determined by field personnel based on the actual cause and the equipment that can detect it.

[0134] Step 303: After executing the detection plan, determine the exact cause of the abnormality.

[0135] The exact cause of the anomaly is the actual cause. This command retrieves a series of information, including images and detection values, and compares them with the standard values ​​to identify any mismatched values. The possible cause of the anomaly corresponding to these values ​​is the exact cause of the anomaly.

[0136] Step 304: Find the corresponding treatment plan from the preset treatment database based on the accurate abnormality cause.

[0137] The solution is a solution to the exact cause of the abnormality. The database stores the mapping relationship between the exact cause of the abnormality and the solution, which is designed by the staff in this field based on their own experience and actual situation.

[0138] Step 305 : When the processing type corresponding to the processing scheme is a preset continuous etching type, execute the processing scheme and re-obtain the leakage current detection result.

[0139] The Continue Etch category indicates insufficient etching and requires continued etching. Possible causes for abnormalities such as insufficient plasma etching volume, defective etching processes (short solution life, excessively fast etching rate, too short etching time), and non-compliant Q-time all correspond to the Continue Etch category. If the solution corresponds to the preset Continue Etch category, the problem is clear and has a simple solution. There's no need to shut down the machine; simply continue etching. Therefore, the solution can be executed.

[0140] Step 306 : When the leakage current detection result is a predetermined normal result, the steps of coating a third dielectric layer and sputtering a third metal TiCu layer on the redistribution layer are continued.

[0141] A normal result means no leakage. If the leakage current test result is normal, it means that the etching is complete and you can proceed to the next step.

[0142] Step 307 : When the processing type corresponding to the processing plan is the machine adjustment type, the processing plan is output and the steps of coating a third dielectric layer and sputtering a third metal TiCu layer on the redistribution layer are not executed.

[0143] The Machine Adjustment category indicates that the machine needs parameter adjustment or is damaged, requiring manual repair. If the solution corresponds to the Machine Adjustment category, it indicates that the machine itself cannot resolve the problem and a solution cannot be determined. Manual repair and machine downtime are required. Therefore, the solution is output and the steps of coating the third dielectric layer on the redistribution layer and sputtering the third metal TiCu layer are not executed.

[0144] Reference Figure 7 , further comprising a method for arranging a second test chip image on a second mask, the method comprising:

[0145] Step 400: Determine the optional chip position and the optional quantity, wherein the optional chip position is a position on the second mask corresponding to the second chip to be formed that falls on the edge line of a preset second effective range and partially exceeds the second effective range.

[0146] The optional chip position is the chip position that can be used as a test chip, such as Figure 3 and Figure 4 As shown, the position on the second mask corresponding to the second chip to be formed falls on the edge line of the second effective range and partially exceeds the second effective range.

[0147] Step 401 : Outputting the selectable chip positions as a second test chip image when the selectable number is greater than a preset detection requirement number.

[0148] The required number of tests is the number of second test chip images required to ensure leakage detection accuracy. If it is greater than , it means that the second test chip image positions can be directly selected on these invalid chips, and the requirements are met, so the optional chip positions can be output as the second test chip images. You can arbitrarily select the number of optional chip positions that corresponds to the required number of tests.

[0149] Step 402 : Analyze the second design chip image to obtain a design image number when the selectable number is less than the detection required number.

[0150] The design image number is the category number corresponding to the second design chip image. To facilitate user identification and differentiation of individual chips, each chip image is distinguished. The analysis method can be a matching method, using a database that stores mappings between chip images and image numbers. Professionals in this field assign numbers to each different type of chip image. When the system receives the second design chip image, it matches it with each chip image in the database. If a match is successful, the corresponding mapping is found and the image number in the mapping is output as the design image number.

[0151] Step 403: Find the corresponding design requirement quantity from a preset requirement database based on the design image number.

[0152] The design requirement quantity is the effective number of design chips corresponding to the design image number that need to be generated on each wafer. The database stores the mapping between design image numbers and design requirement quantities, which are set by the manufacturer's staff based on actual needs and the required product yield.

[0153] Step 404: Count the number of design image numbers and define this number as the actual design number.

[0154] The actual design quantity is the actual number of design chips corresponding to the design image number. Here, this value refers to the number of second design chip images on the corresponding mask. To maintain a certain margin of error and to avoid wafer waste, the number of chips is usually designed to be slightly higher than required.

[0155] Step 405 : When the actual design quantity is greater than the required design quantity, the required quantity difference is calculated based on the optional quantity and the inspection required quantity.

[0156] The required quantity difference is the difference between the selectable quantity and the required test quantity. This means the number of test chip positions remaining after selecting the selectable chip positions corresponding to the selectable quantity. It is calculated by subtracting the required test quantity from the selectable quantity. If the actual design quantity exceeds the required design quantity, it indicates that there are some excess design chips available for use as test chips.

[0157] If it is not greater than, then the alarm can be output directly here.

[0158] Step 406: Determine the actual quantity difference based on the design actual quantity and the design required quantity.

[0159] The actual quantity difference is the difference between the actual design quantity and the required design quantity. This means there are some extra design chips that can be used as test chips. It is calculated by subtracting the required design quantity from the actual design quantity.

[0160] Step 407 : When the required quantity difference is smaller than the actual quantity difference, the statistical image numbers are analyzed to determine the outermost image numbers and the positions of the outer chips.

[0161] The outermost image number is the image number farthest from the center of the second effective range, such as Figure 4 As shown, a circle can be made with the center of the second effective range, and the diameter can be gradually reduced from the diameter of the second effective range. When the chip corresponding to the statistical image number is first contacted, the area where the chip is located is the peripheral chip position, and then the corresponding number is counted. When the number is less than the required number difference, the area is further reduced and a new batch of chips is contacted. The corresponding number is accumulated and these are also defined as peripheral chip positions until the corresponding number is greater than or equal to the required number difference, and the diameter reduction process is terminated. The remaining images defined as peripheral chip positions are all images corresponding to the outermost image number.

[0162] Step 408: arbitrarily select the peripheral chip positions corresponding to the required quantity difference and the optional chip positions corresponding to the optional quantity as the positions of the second test chip image for output.

[0163] Here, when the number of optional chip positions is insufficient, some redundant chip positions can be selected as positions corresponding to the test chip images, thereby ensuring the number of test chips while ensuring the number of design chips.

[0164] The method of steps 400-408 can also be applied to the third test chip image.

[0165] Reference Figure 8, further comprising a method for arranging a second test chip image on a second mask, the method comprising:

[0166] Step 500 : Analyze the second test chip image to obtain a test image number when the selectable number is less than the detection required number.

[0167] The test image number is the number of the image used for testing. Here, only the number of the image used for leakage detection is used. The analysis method is similar to step 402 and will not be described in detail here.

[0168] Step 501: searching for corresponding equivalent replacement possibilities from a preset comparison database based on the outermost image number and the test image number.

[0169] The equivalent replacement possibility is the probability of being able to serve as the chip corresponding to the test image number. This possibility requires a similar layout of the four contacts and the middle trace, as well as similar measured results (current less than 10nA is acceptable, and greater than or equal to 10nA is unacceptable). A database stores a mapping between the outermost image number, test image number, and equivalent replacement possibility. Professionals in this field perform comparative analysis and testing based on the circuit logic corresponding to each image number, then generate a numerical value for the probability and output it. When the system receives the corresponding outermost image number and test image number, it automatically searches the database for the corresponding equivalent replacement possibility and outputs it.

[0170] Step 502: When there is an equivalent replacement possibility greater than a preset no-influence probability, define the outermost image number corresponding to the equivalent replacement possibility as an equivalent design image number, and define the test image number corresponding to the equivalent replacement possibility as an equivalent test image number.

[0171] The probability of no impact is the possibility that the two images can be replaced with each other without affecting the final result. However, if this probability exists, it means that the equivalent design image number and the equivalent test image number can be replaced with each other.

[0172] Step 503 : performing a partial update based on the second test chip image corresponding to the same test image number and the second design chip image corresponding to the same design image number to obtain an updated leakage test image.

[0173] The updated leakage test image is an image that can be used as both a design chip and a test chip after combining the second test chip image corresponding to the same test image number and the second design chip image corresponding to the same design image number. Figure 2 As shown, the special pattern in the center of the second test chip image corresponding to the same test image number is imprinted into the second design chip image.

[0174] Step 504: Count the number of chips corresponding to the same design image number.

[0175] The chip quantity is the number of chips corresponding to the same design image number.

[0176] Step 505: Calculate the sum of the chip quantity and the optional quantity, and define the sum as the total optional quantity.

[0177] Step 506 : When the total number of selectable images is less than the detection requirement number, continue searching for an equivalent test image number and update the total number of selectable images.

[0178] If it is less than, it means that even if the chip corresponding to the equivalent design image number is added, the required number of tests cannot be met, and then it is necessary to continue searching for the corresponding equivalent test image number.

[0179] When there is no equivalent test image number and the total number of options is still less than the detection requirement, an alarm is output.

[0180] Step 507: When the total optional quantity is greater than the preset minimum leakage detection requirement quantity and the sum of the required quantity difference and the optional quantity is greater than the preset minimum shear force requirement quantity, the optional chip position is output as the second leakage test image, and the position on the second mask corresponding to the second design chip image corresponding to the same design image number is output as the position corresponding to the updated leakage test image.

[0181] The minimum leakage detection requirement is the minimum number of chips required for leakage detection. The minimum shear force requirement is the minimum number of chips required for shear force detection. When the total optional quantity is greater than the minimum leakage detection requirement, it means that the design chip corresponding to the equivalent design image number can also be tested as a leakage detection test chip, and this does not affect the use of the design chip in the later stage. When the sum of the required quantity difference and the optional quantity is greater than the minimum shear force requirement, it means that when designing the shear force test chip, the excess design chips and the chips corresponding to the optional chip position can be used as shear force test chips for testing, and it will not affect the remaining design chips.

[0182] Those skilled in the art will clearly understand that for the sake of convenience and brevity, the division of the above-mentioned functional modules is only used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working processes of the above-mentioned systems, devices, and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0183] The above are all preferred embodiments of the present application and are not intended to limit the scope of protection of this application. Unless otherwise stated, any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features. In other words, unless otherwise stated, each feature is merely an example of a series of equivalent or similar features.

Claims

1. A packaging method for a test chip, applied to a chip without a rewiring structure, characterized in that: include: Taking out a first integrated circuit wafer and covering a side of the first integrated circuit wafer where the first electrode is exposed with a first dielectric layer, the first integrated circuit wafer being provided with a first chip to be formed, the first chip to be formed being provided with a first electrode and a first circuit module, the first integrated circuit wafer being covered with a first passivation layer, the first passivation layer being provided with a first opening on a side away from the first integrated circuit wafer where the first electrode is exposed; sputtering a first metal TiCu layer on a side of the first dielectric layer away from the first integrated circuit wafer; Performing photolithography on the image on the preset first mask to form a first photolithography layer on the first metal TiCu layer, wherein the first photolithography layer includes a preset first design chip image and a first test chip image; electroplating a first UBM metal layer on the first photoresist layer; Sequentially removing the first photoresist layer and the first metal TiCu layer to expose the first electroplated metal layer formed into the first design chip image and the first test chip image; forming a first bump on the first electroplated metal layer by a ball planting process or a reflow process; After being inspected, the first integrated circuit wafer is cut into individual first chips, wherein the first chips include a design chip having a first design chip image and a first test chip having a first test chip image.

2. The packaging method of a test chip according to claim 1, characterized in that: The first test chip image includes a first leakage test image and a first shear force test image set on different first test chips. The first shear force test image is set at the edge of the first photolithography layer. The first test chip including the first leakage test image is provided with contacts connected to the outside world for circuit testing and intermediate traces with the same line width and line spacing connecting the two contacts.

3. The packaging method of a test chip according to claim 1, wherein: The first test chip image includes a first leakage test image and a first shear force test image set on the same test chip. The first shear force test image is set at the edge of the first photolithography layer. The first test chip including the first leakage test image is provided with a first contact connected to the outside world for circuit testing and a first intermediate trace with the same line width and line spacing connecting the two first contacts.

4. The packaging method of a test chip according to claim 3, characterized in that: The first test chip provided with the first shear force test image is located on an edge line of a preset first effective range and partially exceeds the first effective range.

5. A packaging method for a test chip, applied to a chip with a rewiring structure, characterized in that: include: Taking out a second integrated circuit wafer and covering a side of the second integrated circuit wafer where the second electrode is exposed with a second dielectric layer, the second integrated circuit wafer being provided with a second chip to be formed, the second chip to be formed being provided with a second electrode and a second circuit module, the second integrated circuit wafer being covered with a second passivation layer, and a side of the second passivation layer being provided with a second opening exposing the second electrode; sputtering a second metal TiCu layer on a side of the second dielectric layer away from the second integrated circuit wafer; Performing photolithography on the image on the preset second mask to form a second photolithography layer on the second metal TiCu layer, wherein the second photolithography layer includes a preset second design chip image and a second test chip image, and the second test chip image includes a second leakage test image; electroplating a redistribution layer on the second photoresist layer; Electroplating a second UBM metal layer on the redistribution layer; removing the second photoresist layer and the second metal TiCu layer in sequence to expose the second electroplated metal layer formed into the second design chip image and the second test chip image; forming a second bump on the second electroplated metal layer by a ball planting process or a reflow process; After testing, the second integrated circuit wafer is cut into single second chips, wherein the second chips include a design chip having a second design chip image and a first test chip having a second test chip image. The second test chip is provided with contacts for connecting to the outside world for circuit testing and an intermediate trace with the same line width and line spacing connecting the two contacts.

6. The packaging method of a test chip according to claim 5, characterized in that: The method further includes the following steps between the step of electroplating a redistribution layer on the second photoresist layer and the step of electroplating a second UBM metal layer on the redistribution layer: Continue coating a third dielectric layer on the redistribution layer and sputtering a third metal TiCu layer; covering the side of the second integrated circuit wafer where the second electrode is exposed with a third dielectric layer; sputtering a third metal TiCu layer on a side of the third dielectric layer away from the second integrated circuit wafer; The image on the preset third mask is photolithographically processed to form a third photolithographic layer on the third metal TiCu layer, wherein the third photolithographic layer includes a preset third test chip image, and the third test chip image includes a second shear force test image.

7. The packaging method of a test chip according to claim 6, characterized in that: The second leakage test image and the second shear force test image are located on the same second test chip after the step of cutting the second integrated circuit wafer into individual second chips.

8. The packaging method of a test chip according to claim 6, characterized in that: The method also includes a method for determining whether to continue the steps of coating a third dielectric layer and sputtering a third metal TiCu layer on the redistribution layer, the method comprising: Executing a preset leakage current detection method and obtaining a leakage current detection result; Analyze possible causes of abnormalities based on leakage current detection results; Find the corresponding detection plan from the preset detection database based on the possible cause of the abnormality; Determine the exact cause of the abnormality after executing the detection plan; Find the corresponding treatment plan from the preset treatment database based on the accurate cause of the abnormality; When the processing type corresponding to the processing scheme is a preset continuous etching category, executing the processing scheme and re-obtaining the leakage current detection result; When the leakage current detection result is a preset normal result, the steps of coating a third dielectric layer on the redistribution layer and sputtering a third metal TiCu layer are performed; When the processing type corresponding to the processing scheme is the machine adjustment category, the processing scheme is output and the steps of coating a third dielectric layer on the redistribution layer and sputtering a third metal TiCu layer are no longer performed.

9. The packaging method of a test chip according to claim 8, characterized in that: The method further includes arranging a second test chip image on a second mask, the method comprising: Determining optional chip positions and optional quantities, wherein the optional chip positions are positions on the second mask corresponding to the second chip to be formed that falls on an edge line of a preset second effective range and partially exceeds the second effective range; When the selectable number is greater than the preset detection requirement number, the selectable chip position is output as a second test chip image; When the selectable number is less than the detection required number, analyzing the second design chip image to obtain a design image number; Find the corresponding design requirement quantity from the preset requirement database based on the design image number; Counting the number of design image numbers, and defining the number as the actual number of designs; When the actual design quantity is greater than the design requirement quantity, the required quantity difference is calculated based on the optional quantity and the inspection requirement quantity; Determine the actual quantity difference based on the actual design quantity and the design requirement quantity; When the required quantity difference is less than the actual quantity difference, the image numbers are analyzed and counted to determine the outermost image numbers and the positions of the peripheral chips; The peripheral chip positions corresponding to the required quantity difference and the optional chip positions corresponding to the optional quantity are arbitrarily selected as the positions of the second test chip image for output.

10. The packaging method of a test chip according to claim 9, characterized in that: Also included is a further arrangement method of a second test chip image on a second mask, the method comprising: analyzing the second test chip image to obtain a test image number when the selectable number is less than the detection required number; Finding corresponding equivalent replacement possibilities from a preset comparison database based on the outermost image number and the test image number; When there is an equivalent replacement possibility greater than a preset non-influence probability, the outermost image number corresponding to the equivalent replacement possibility is defined as the equivalent design image number, and the test image number corresponding to the equivalent replacement possibility is defined as the equivalent test image number; Performing a partial update based on a second test chip image corresponding to an identical test image number and a second design chip image corresponding to an identical design image number to obtain an updated leakage test image; Count the number of chips corresponding to the same design image number; Calculate the sum of the chip quantity and the optional quantity, and define the sum as the total optional quantity; When the total number of options is less than the number required for testing, continue to search for equivalent test image numbers and update the total number of options; When the total optional quantity is greater than the preset minimum leakage detection requirement quantity and the sum of the required quantity difference and the optional quantity is greater than the preset minimum shear force requirement quantity, the optional chip position is output as the second leakage test image, and the position on the second mask corresponding to the second design chip image corresponding to the equivalent design image number is output as the position corresponding to the updated leakage test image.

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